|Numéro de publication||US20060038231 A9|
|Type de publication||Demande|
|Numéro de demande||US 10/653,628|
|Date de publication||23 févr. 2006|
|Date de dépôt||2 sept. 2003|
|Date de priorité||21 déc. 1998|
|Autre référence de publication||EP1199750A2, EP1199750A3, EP2365524A2, EP2365524A3, US6495442, US6605528, US6649509, US6734563, US7265047, US7276422, US7351650, US7382052, US7405150, US7419900, US7439626, US7439627, US7443033, US7443034, US7446031, US7446035, US7449752, US7459791, US7462938, US7466007, US7479450, US7524759, US7534718, US7892965, US7902067, US7915161, US7919865, US7923366, US8004088, US8188603, US8435883, US8461686, US8482127, US8492900, US20030057531, US20040041211, US20060060973, US20060063374, US20060068574, US20060076684, US20080001293, US20080001294, US20080001300, US20080001301, US20080001302, US20080003806, US20080003807, US20080006946, US20080009131, US20080029785, US20080032496, US20080042285, US20080042293, US20080042294, US20080042295, US20080042296, US20080045001, US20080045002, US20080045004, US20080045008, US20080057703, US20080061444, US20080067686, US20080067693, US20080067694, US20080085596, US20080085597|
|Numéro de publication||10653628, 653628, US 2006/0038231 A9, US 2006/038231 A9, US 20060038231 A9, US 20060038231A9, US 2006038231 A9, US 2006038231A9, US-A9-20060038231, US-A9-2006038231, US2006/0038231A9, US2006/038231A9, US20060038231 A9, US20060038231A9, US2006038231 A9, US2006038231A9|
|Inventeurs||Mou-Shiung Lin, Jin-Yuan Lee|
|Cessionnaire d'origine||Megic Corporation|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Citations de brevets (44), Référencé par (28), Classifications (37), Événements juridiques (5)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
This application is related to Ser. No. 09/251,183 filed on Feb. 17, 1999 which is a continuation-in-part of Ser. No. 09/216,791 filed on Dec. 21, 1998 assigned to a common assignee. This application is also related to attorney docket MEG00-008, Ser. No. ______, filing date ______.
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of post-passivation processing for the creation of conductive interconnects.
(2) Description of the Prior Art
Improvements in semiconductor device performance are typically obtained by scaling down the geometric dimensions of the Integrated Circuits, this results in a decrease in the cost per die while at the same time some aspects of semiconductor device performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
To solve this problem, one approach has been is to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Current practice is to create metal interconnection networks under a layer of passivation, this approach however limits the interconnect network to fine line interconnects and the therewith associated how parasitic capacitance and high line resistivity. The latter two parameters, because of their relatively high values, degrade device performance, an effect which becomes even more severe for higher frequency applications and for long interconnect lines that are, for instance, used for clock distribution lines. Also, fine line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.
It has previously been stated that it is of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity. The invention provides such a method. An analogy can be drawn in this respect whereby the currently (prior art) used fine line interconnection schemes, which are created under a layer of passivation, are the streets in a city; in the post-passivation interconnection scheme of the present invention, the interconnections that are created above a layer of passivation can be considered the freeways between cities.
From the above the following can be summarized: circuits are created in or on the surface of a silicon substrate, interconnect lines are created for these circuits for further interconnection to external circuitry, the circuits are, on a per I/O pin basis, provided with an ESD circuit, these circuits with their ESD circuit are connected to a power or ground pin that penetrates a layer of passivation. The layer of passivation is the final layer that overlies the created interconnect line structure, the interconnect line underneath the layer of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistivity and high parasitic capacitance.
Relating to the cross section that is shown in
The same comments apply to the cross section that is shown in
Further applies to the cross section that is shown in
It is therefore of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity.
A principal objective of the invention is to provide a method for the creation of interconnect metal that allows for the use of thick and wide metal.
Another objective of the invention is to provide a method for the creation of interconnect metal that uses the application of thick layer of dielectric such as polymer.
Yet another objective of the invention is to provide a method that allows for the creation of long interconnect lines, whereby these long interconnect lines do not have high resistance or introduce high parasitic capacitance.
A still further objective of the invention is to create interconnect lines that can carry high values of current for the creation of power and ground distribution networks.
A still further objective of the invention is to create interconnect metal that can be created using cost effective methods of manufacturing by creating the interconnect metal on the surface of and after a layer of passivation has been deposited.
In accordance with the objectives of the invention a new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric.
For purposes of reference and for clarity of understanding,
Referring now more specifically to
Layers 14 (two examples are shown) represent all of the metal layers and dielectric layers that are typically created on top of the dielectric layer 12, layers 14 that are shown in
The key steps of the above referenced application begin with the deposition of a thick layer 20 of polyimide that is deposited over the surface of layer 18. Access must be provided to points of electrical contact 16, for this reason a pattern of openings 22, 36 and 38.is etched through the polyimide layer 20 and the passivation layer 18, the pattern of openings 22, 36 and 38 aligns with the pattern of electrical contact points 16. Contact points 16 are, by means of the openings 22/36/38 that are created in the layer 20 of polyimide, electrically extended to the surface of layer 20.
The above referenced material that is used for the deposition of layer 20 is polyimide, the material that can be used for this layer is not limited to polyimide but can contain any of the known polymers (SiClxOy) The indicated polyimide is the preferred material to be used for the processes of the invention for the thick layer 20 of polymer. Examples of polymers that can be used are silicons, carbons, fluoride, chlorides, oxygens, silicone elastomer, parylene or teflon, polycarbonate (PC), polysterene (PS), polyoxide (PO), poly polooxide (PPO), benzocyclobutene (BCB).
Electrical contact with the contact points 16 can now be established by filling the openings 22/36/38 with a conductive material. The top surfaces 24 of these metal conductors that are contained in openings 22/36/38 can now be used for connection of the IC to its environment, and for further integration into the surrounding electrical circuitry. This latter statement is the same as saying the semiconductor devices that have been provided in the surface of substrate 10 can, via the conductive interconnects contained in openings 22/36/38, be further connected to surrounding components and circuitry. Interconnect pads 26 and 28 are formed on top of surfaces 24 of the metal interconnects contained in openings 22, 36 and 38. These pads 26 and 28 can be of any design in width and thickness to accommodate specific circuit design requirements. A pad can, for instance, be used as a flip chip pad. Other pads can be used for power distribution or as a ground or signal bus. The following connections can, for instance, be made to the pads shown in
The following comments relate to the size and the number of the contact points 16,
For higher aspect ratio vias, the vias are filled with via plug before the deposition of the metal layers 26 and 28. However, for vias that have lower aspect ratios (for example less than 2), the via plugs may not be needed in which case the metal of layers 26 and 28 can directly establish contact with the pads 16.
The referenced application does not impose a limitation on the number of contact pads that can be included in the design, this number is not only dependent on package design requirements but is mostly dependent on the internal circuit design requirements of the package. Layer 18 in
The frequently used passivation layer in the present state of the art is plasma enhanced CVD (PECVD) oxide and nitride. In creating layer 18 of passivation, a layer of approximately 0.5 um. PECVD oxide can be deposited first allowed by a layer of approximately 0.7 um. nitride. Passivation layer 18 is very important because it protects the device wafer from moisture and foreign ion contamination. The positioning of this layer between the sub-micron process (of the integrated circuit) and the tens-micron process (of the interconnecting metalization structure) is of critical importance since it allows for a cheaper process that possibly has less stringent clean room requirements for the process of creating the interconnecting metalization structure.
Layer 20 is a thick polymer dielectric layer (for example polyimide) that have a thickness in excess of 2 um (after curing). The range of the polymer thickness can vary from 2 um to 150 um, dependent on electrical design requirements.
For the deposition of layer 20 the Hitachi-Dupont polyimide HD 2732 or 2734 can, for example, be used. The polyimide can be spin-on coated and cured. After spin-on coating, the polyimide will be cured at 400 degrees C. for 1 hour in a vacuum or nitrogen ambient. For thicker polyimide, the polyimide film can be multiple coated and cured.
Another material that can be used to create layer 20 is the polymer benzocyclobutene (BCB). This polymer is at this time commercially produced by for instance Dow Chernicai and has recently gained acceptance to be used instead of typical polyimide application.
The dimensions of openings 22, 36 and 38 have previously been discussed. The dimension of the opening together with the dielectric thickness determine the aspect ratio of the opening. The aspect ratio challenges the via etch process and the metal filling capability. This leads to a diameter for openings 22/36/38 in the range of approximately 0.5 um to 30 um the height for openings 22/36/38 can be in the range of approximately 2 um to 150 um. The aspect ratio of openings 22/36/38 is designed such that filling of the via with metal can be accomplished. The via can be filled with CVD metal such as CVD tungsten or CVD copper, with electro-less nickel, with a damascene metal filling process, with electroplating copper, etc. As previously stated, for low aspect ratio vias, the filling of the vias is not required as an extra processing step. A direct contact can be established between the metal layers 26 and 28 and the contact pads 16.
The referenced application can be further extended by applying multiple layers of polymer (such as polylmide) and can therefore be adapted to a larger variety of applications. The function of the structure that has been described in
This completes the discussion of the construct shown for purposes of reference in
The thick layer 20 of polymer can be coated in liquid form on the surface of the layer 18 of passivation or can be laminated over the surface of layer 18 of passivation by dry film application. Vias that are required for the creation of conductive plugs 21 can be defined by conventional processes of photolithography or can be created using laser (drill) technology.
It is clear from previous discussions that the sequence of layers that is shown in cross section in
With respect to the cross section that is shown in
Referring now specifically to
From the cross section that is shown in
Some points of interest can be listed at this time as they relate to prior art methods and to the invention.
It must, in this respect and related to the above provided comments, be remembered that power and ground pins do not require drivers and/or receiver circuitry.
The method that is used to create the interconnect network that is shown in cross section in
Referring now to
The not previously highlighted features that are shown in
The method that is used to create the interconnect network that is shown in cross section in
The method that is used to create the wide thick line interconnect lines-that is shown in cross section in
It must further be emphasized that, where
It is further of value to briefly discuss the above implemented and addressed distinction between fine-line interconnect lines and wide, thick interconnect lines. The following points apply in this respect:
Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.
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|Classification aux États-Unis||257/361, 257/E23.167, 257/E23.153|
|Classification internationale||H01L21/768, H01L23/60, H01L23/62, H01L23/528, H01L23/532, H01L27/02|
|Classification coopérative||H01L24/05, H01L23/62, H01L23/5286, H01L23/60, H01L23/5223, H01L2924/3011, H01L21/76838, H01L21/768, H01L23/5227, H01L21/76801, H01L2924/12044, H01L23/5329, H01L27/0248, H01L23/5283, H01L23/5222, H01L23/53295|
|Classification européenne||H01L23/522C4, H01L21/768C, H01L23/60, H01L23/528C, H01L21/768, H01L23/532N4, H01L23/522C, H01L21/768B, H01L23/522L, H01L23/528P, H01L23/62, H01L23/532N|
|3 mai 2006||AS||Assignment|
Owner name: MEGICA CORPORATION, TAIWAN
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|23 mars 2012||FPAY||Fee payment|
Year of fee payment: 4
|10 juil. 2013||AS||Assignment|
Owner name: MEGIC CORPORATION, TAIWAN
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Effective date: 20000921
|25 sept. 2013||AS||Assignment|
Owner name: MEGIT ACQUISITION CORP., CALIFORNIA
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|11 juil. 2014||AS||Assignment|
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