US20060076661A1 - Attachment of integrated circuit structures and other substrates to substrates with vias - Google Patents
Attachment of integrated circuit structures and other substrates to substrates with vias Download PDFInfo
- Publication number
- US20060076661A1 US20060076661A1 US11/253,490 US25349005A US2006076661A1 US 20060076661 A1 US20060076661 A1 US 20060076661A1 US 25349005 A US25349005 A US 25349005A US 2006076661 A1 US2006076661 A1 US 2006076661A1
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- US
- United States
- Prior art keywords
- substrate
- integrated circuit
- contact pads
- solder
- circuit structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Definitions
- the present invention relates to attachment of integrated circuits to other substrates.
- FIG. 1 illustrates a chip 124 flip-chip attached to a PCB 130 .
- the chip is attached face down, with its contact pads 137 connected to contact pads 139 of the PCB.
- contact pad metal layer 137 (the layer that provides the contact pads) is deposited and patterned over the chip's silicon substrate 140 .
- a passivation dielectric layer 147 is formed on layer 137 . Openings are formed in dielectric 147 to expose the contact pads 137 .
- contact pads 137 are recessed into the chip's surface.
- protruding metal bumps 150 are formed on the contact pads. Bumps 150 are bonded to PCB contact pads 139 with solder, an adhesive, or by thermal or thermosonic compression.
- Bumps 150 can themselves be made of solder.
- the chip is placed on the PCB with bumps 150 on pads 139 , and solder 150 is reflowed to form solder joints.
- This attachment is mechanically strong and reliable in the presence of thermal stresses, but the solder bumps are difficult to scale down as contact pads 137 become smaller and the pitch between the pads 137 is reduced.
- the solder bump sizes decrease to accommodate the smaller contact pads and pitches, the solder joints become mechanically and thermally weaker.
- the solder ball (solder bump) size defines the standoff distance between the chip 124 and PCB 130 . If the standoff is too small, there will be increased fatigue stresses on the solder joints during thermal cycling. In addition, there is a greater possibility of undesirable residues remaining between the chip 124 and the PCB and causing some degradation.
- Bumps 150 can also be made without solder, e.g. from copper (Cu) or gold (Au), to obtain better scalability.
- solder e.g. from copper (Cu) or gold (Au)
- Cu copper
- Au gold
- cavities 210 increase the mechanical strength of the structure.
- the structure becomes stronger against lateral forces (including lateral stresses caused by thermal expansion).
- the amount of solder or adhesive can be increased by increasing the depth of cavities 210 without increasing the lateral size of the structure. Improved scalability is therefore provided.
- bumps 150 are attached with solder or a conductive or anisotropic adhesive, the size uniformity requirements for bumps 150 are relaxed. If the bumps are not uniform in size, the shorter bumps will still provide a reliable electrical connection to contacts 139 as long as there is a reliable electrical connection between the bumps and the solder or adhesive in cavities 210 .
- an optional conductive film 220 (e.g. metal) is formed on the bottom and sidewalls of each cavity 210 .
- Film 220 is believed to improve the strength and the electrical conductivity of the bond between bumps 150 and contact pads 139 . Film 220 is not necessary however.
- Bumps 150 can be thought of as “contact pads”, and the invention is applicable to any protruding contact pads and not necessarily the protruding pads formed by bumping a die.
- protruding contact pads can be formed on a die by removing the die material to expose metal features, as described in U.S. Pat. No. 6,322,903 issued Nov. 27, 2001 to Siniaguine et al. and incorporated herein by reference.
- layer 220 is absent, and a cavity 210 exposes not only the contact pad 139 but also a surrounding dielectric region in substrate 130 .
- the solder (not shown) wets the contact pad 139 better than the surrounding region, so more solder gathers near the bump 150 , and the solder reaches up higher along the surface of bump 150 . This is believed to provide a stronger solder joint and better electrical conductivity at least in some embodiments.
- the contact pad 139 or layer 220 may include multiple conductive layers, with the top layer being more solder wettable than the bottom layers and the top layer covering only a portion of the bottom layers. The solder will preferentially wet the more solder wettable layer, gathering closer to bump 150 and reaching up higher.
- FIGS. 2, 3 show vertical cross sections of integrated circuits attached to substrates according to embodiments of the present invention.
- FIGS. 4-8 show vertical cross sections of integrated circuits in the process of fabrication for attachment according to embodiments of the present invention.
- FIG. 9 shows a vertical cross section of a BT substrate fabricated according to an embodiment of the present invention.
- FIGS. 10-13 show vertical cross sections of integrated circuits attached to substrates according to embodiments of the present invention.
- FIGS. 14, 15 are flowcharts of an integrated circuit packaging processes according to embodiments of the present invention.
- FIG. 3 illustrates another integrated circuit packaging structure.
- Integrated circuit packaging substrate 310 is an intermediate substrate that provides an interconnection between dies 124 and PCB 130 .
- Substrate 310 includes two intermediate integrated circuit packaging substrates 110 , 120 .
- Substrate 120 is a silicon interposer attached to BT substrate 110 , and thus is itself a semiconductor integrated circuit. The attachment is made as described above in connection with FIG. 2 . More particularly, cavities 210 B (also called vias or openings herein) are formed in the top surface of BT substrate 110 . Protruding contact pads 340 of interposer 120 are inserted into the cavities.
- Dies 124 are attached to interposer 120 as in FIG. 2 . More particularly, cavities 210 are formed in the top surface of the interposer, and the dies' bumps 150 are inserted into these cavities.
- BT substrate 110 is attached to PCB 130 in a conventional manner. More particularly, solder balls 134 are attached to contact pads 360 on the bottom surface of BT substrate 110 , and the solder balls are later reflowed to solder the contact pads 360 to PCB contact pads 139 .
- the cavities are used to attach the dies 124 to interposer 120 but the attachment of interposer 120 to BT substrate 110 is performed without cavities.
- the cavities are used to attach the interposer 120 to BT substrate 110 , but the attachment of dies 124 to interposer 120 is performed without cavities. In other embodiments, the cavities are used to attach one but not both dies 124 to interposer 120 . Also, the cavities can be used to attach some but not all of the a single die's contact pads to the interposer, or some but not all of the interposer's contact pads 340 to BT substrate 110 .
- Silicon interposer 120 includes metal layers 136 formed over silicon substrate 140 .
- Substrate 140 has substantially planar top and bottom surfaces, and is quite thin. In some embodiments, the planarity of substrate 140 is suitable for fine geometry photolithography (finer than possible with BT and FR4 substrates).
- the thickness of substrate 140 can be 100 ⁇ m or less (50 ⁇ m to 35 ⁇ m thickness values believed to be achievable, and smaller values may be possible).
- Layers 136 provide interconnect lines and may also provide power and ground planes, resistors, inductors, capacitor plates for decoupling capacitors and other capacitor types, and possibly other elements, known or to be invented. Layers 136 can be separated from each other, and from the substrate, by dielectric layers 144 .
- Layers 136 contact each other and the silicon substrate through openings in the dielectric layers. Layers 136 can also be formed directly on the silicon substrate if desired. Layers 136 provide contact pads 136 C at the top surface of the interposer. At least a portion of each contact pad 136 C is located in a corresponding cavity 210 .
- silicon substrate 140 can be thicker than described above, and its top and bottom surfaces do not have to be planar.
- silicon substrate 140 includes metalized through-silicon vias 330 that pass between the top and bottom surfaces of substrate 140 .
- Conductive paths are provided from contact pads 136 C at the top of the interposer to contact pads 340 at the bottom of the interposer through the vias 330 .
- Contact pads 340 protrude out of vias 330 .
- Contact pads 340 are attached to contact pads 350 at the top surface of BT substrate 110 .
- Interconnects (not shown) in BT substrate 110 connect the contact pads 350 to contact pads 360 at the bottom surface of substrate 110 .
- Solder balls 134 are formed on pads 360 by conventional techniques for attachment to PCB 130 .
- the size and spacing (pitch) of contact pads 136 C on interposer 120 matches the size and the pitch of the contact pads on dies 124 . If dies 124 are silicon integrated circuits, their CTE (coefficient of thermal expansion) matches the CTE of the interposer, so the pitch of contact pads 136 C can be small because the low thermal stresses at the interface between the dies and the interposer make it unnecessary to use large bumps 150 as would be desirable for a strong mechanical connection.
- the contact pads 340 on the bottom of the interposer match the top contact pads 350 of BT substrate 110 . For some fabrication technologies, the minimum dimensions are as shown in the following Table 1. The dimensions can typically be reduced if more expensive technologies are used.
- Silicon interposer 120 can be manufactured using conventional techniques. See e.g. the aforementioned U.S. Pat. No. 6,322,903. Other techniques are described in U.S. patent application Ser. No. 10/410,929 filed on Apr. 9, 2003 by P. Halahan et al., entitled “Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby”, incorporated herein by reference. Still other techniques can possibly be used, whether known or to be invented.
- DRIE deep reactive ion etching
- the via diameter Dv is 25 ⁇ m to 100 ⁇ m.
- Silicon dioxide layer 410 is thermally grown on the wafer to a thickness of about 1 ⁇ m. A larger thickness can also be used to reduce the capacitance between substrate 140 and the metal features that will be fabricated in vias 330 .
- Barrier layer 420 of titanium-tungsten (TiW) is sputtered on oxide 410 to a thickness of 0.2 ⁇ m.
- a seed copper (Cu) layer 430 . 1 is sputtered on the wafer to a thickness sufficient to ensure a continuous copper coverage in the vias. Thicknesses of 0.5 ⁇ m to 2 ⁇ m are believed to be adequate, depending on the sputter technology.
- a dry photoresist film 440 is deposited on the wafer and patterned to expose the vias 330 .
- gold (Au) layer 444 and nickel (Ni) layer 448 are electroplated, in that order, to an exemplary thickness of 0.2 ⁇ m and 1.0 ⁇ m respectively.
- Copper 430 . 2 is electroplated on nickel 448 to fill the vias 330 and possibly protrude out of the vias.
- the cathode terminal (not shown) of the power source is placed at the periphery of wafer 140 in physical contact with seed layer 430 . 1 .
- nickel (Ni) layer 450 is electroplated on the top surface of copper layer 430 . 2 to an exemplary thickness of 0.5 ⁇ m.
- Resist 440 is removed ( FIG. 5 ).
- a wet copper etch removes the exposed portions of seed copper 430 . 1 , with nickel 450 acting as a mask.
- Nickel 450 protects copper 430 . 2 in vias 330 .
- Copper 430 . 2 , 430 . 1 can be etched laterally during the wet etch, but the lateral etch does not remove the copper over the vias 330 because the copper extends laterally beyond the via edges.
- the copper etch may reduce the thickness of copper 430 . 2 , but this is acceptable if the copper protrusions above the vias are sufficiently thick. In either case, it is desirable for the top surface of copper 430 . 2 to be at or above the top surface of oxide 410 after the copper etch.
- a CMP step (chemical mechanical polishing) is performed to remove copper 430 . 2 , nickel 448 , gold 444 , and TiW 420 off the top surface of substrate 140 ( FIG. 6 ).
- the CMP stops on oxide 410 .
- the structure has a planar top surface.
- the wet etch of copper 430 . 1 is omitted, and copper 430 . 1 is removed by the CMP step.
- the separate wet etch of copper 430 . 1 may be desirable however because it may shorten the more expensive CMP step, thus reducing the total manufacturing cost.
- Oxide 410 can be patterned if desired.
- Metal layers 136 ( FIG. 7 ) and dielectric layers 144 are deposited on the interposer wafer and patterned to provide interconnects and, possibly, other elements as described above.
- metal 136 is copper and dielectric 144 is polyimide, but other materials can also be used.
- dielectric layers 144 can be silicon dioxide, photosensitive benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials.
- a high dielectric constant material such as Ta 2 O 5
- Aluminum, conductive polysilicon, and other materials can be used as layers 136 .
- Cavities 210 are formed in the top dielectric layer 144 to expose the contact pads 136 C provided by the top metal layer 136 .
- Solder wettable materials 710 e.g. Ni and/or Au
- Solder balls 720 are formed on contact pads 136 C, by any suitable technique.
- solder paste can be deposited to cover the interposer wafer 120 , and then wiped off by a squeegee blade to force the solder into cavities 210 and remove it from the top surface of the top layer 144 .
- interconnects 136 are made of copper, and contact pads 136 C are plated with a layer 710 of nickel or gold. Layer 710 does not dissolve in solder 720 and provides a barrier for the copper diffusion from interconnects 136 , so the melting temperature of solder 720 does not change when the solder is reflowed.
- the solder is not placed at this stage to avoid solder melting at high temperatures present in plasma wafer thinning processes described below in connection with FIG. 8 .
- the top dielectric layer 144 is sufficiently thick to accommodate the solder volume needed for a reliable bond to dies 124 ( FIG. 1 ).
- the top dielectric 144 is 50 ⁇ m thick. Cavities 210 are about 50 ⁇ m deep and have a diameter of about 75 ⁇ m.
- the interposer wafer is thinned from the bottom to expose the gold 444 . See FIG. 8 .
- the exposed metal provides the contact pads 340 ( FIG. 3 ) that will be soldered to BT substrate 110 .
- the wafer thinning can be performed with any of the techniques described in the aforementioned U.S. Pat. No. 6,322,903 and U.S. patent application Ser. No. 10/410,929. See also U.S. Pat. No. 6,498,381 issued on Dec. 24, 2002 to Halahan et al. and incorporated herein by reference.
- the wafer thinning includes a CF 4 plasma etch at atmospheric pressure.
- the wafer is held from the top by a vortex wafer holder (not shown) that does not touch the wafer except possibly at the wafer periphery.
- the holder emits gas vortices that create vacuum between the holder and the wafer but do not allow the wafer to touch the top surface of the holder.
- the plasma etch exposes the oxide 410 and then etches the silicon 140 , oxide 410 and TiW 420 selectively to copper 430 . 1 . (Copper 430 . 1 is etched later as explained below.)
- the plasma etch etches silicon 140 faster than oxide 410 , so the oxide protrudes out of the silicon the bottom surface of the wafer after the etch.
- the final thickness “Tsif” (marked in FIG.
- silicon substrate 140 is 100 ⁇ m, and it can be smaller (e.g. 35 ⁇ m).
- Oxide 410 and TiW 420 form 5 ⁇ m protrusions around the copper 430 . 1 below the silicon surface. If the solder 720 melting temperature is low, the solder can melt in this process and be blown away by the wafer holder's gas vortices. Therefore, in some embodiments the solder 720 is placed on the wafer after the wafer thinning and, possibly, after the wafer attachment to BT substrate 110 .
- the plasma etch forms copper oxide (not shown) on the exposed portions of copper 430 . 1 .
- the copper oxide and the copper 430 . 1 are etched by a wet etch to expose gold 444 .
- the gold provides a solderable oxide-free surface.
- Nickel 448 will prevent copper diffusion from layer 430 . 2 into the solder. The copper diffusion may be undesirable because it increases the solder melting temperature. In other embodiments, the copper diffusion is desirable to achieve a certain solder hierarchy (the hierarchy of the melting temperatures of different solders) as explained below. In such embodiments, the etch of copper 430 . 1 can be omitted. Nickel 448 can also be omitted.
- gold 444 can be omitted.
- the etch of copper 430 . 1 will then expose nickel 448 .
- the copper 430 . 1 is not etched away.
- the copper oxide (not shown) on copper 430 . 1 can be removed by a wet etch.
- the copper oxide can also be removed by a solder flux during soldering of the interposer wafer to BT substrate 110 (the soldering operation is described below).
- Layers 444 , 448 can be omitted.
- Metal contact pads 340 are metal protrusions formed by the metal layers 430 . 2 , 448 , 444 , 430 . 1 , 420 below the bottom surface of silicon 140 .
- the height Hd of metal contact pads 340 is 50 ⁇ m.
- a dielectric layer (not shown) can optionally be formed on the bottom surface or the interposer to cover the silicon 140 but not the metal contact pads 340 .
- the dielectric can be formed without photolithography. See the aforementioned U.S. Pat. Nos. 6,322,903 and 6,498,381 and U.S. patent application Ser. No. 10/410,929.
- the interposer wafer can be diced if desired.
- the dicing can be performed at the same time as the interposer wafer thinning if vias were formed along the dicing lines (scribe lines) simultaneously with vias 330 at the stage of FIG. 4 .
- U.S. Pat. No. 6,498,074 issued Dec. 24, 2002 to Siniaguine et al. entitled “THINNING AND DICING OF SEMICONDUCTOR WAFERS . . . ”, incorporated herein by reference.
- the interposer wafer is not diced. ICs 124 will be attached to the undiced interposer wafer.
- metal 430 . 2 does not fill the through-silicon vias.
- Metal 430 . 2 is a thin film deposited over the via sidewalls, and it can be part of a layer 136 . See the aforementioned U.S. Pat. No. 6,498,381. Also, in some embodiments the contact pads 340 do not protrude out of the bottom surface of the interposer.
- BT substrate 110 ( FIGS. 9 and 10 ) is formed from one or more BT layers laminated in a conventional manner. Three layers 110 . 1 , 110 . 2 , 110 . 3 are shown, but any number of layers can be present.
- Thin film metal layers 910 e.g. copper
- Layers 910 are interconnected through vias in the BT layers 110 .i (i.e. 110 . 1 , 110 . 2 , 110 . 3 ) using known techniques to provide conductive paths between contact pads 350 and contact pads 360 .
- the bottom metal layer 910 provides contact pads 360 ( FIG. 3 ) at the bottom surface of BT substrate 110 .
- Top contact pads 350 and the top metal layer 910 , are formed below the top BT layer 110 . 3 .
- the top contact pads 350 and the top metal 910 are formed on BT layer 110 . 2 .
- Layer 110 . 3 has vias 210 B exposing the contact pads 350 .
- Vias 210 B form cavities in the top surface of BT substrate 110 .
- Silicon interposer contact pads 340 will be inserted into these cavities to form a reliable mechanical and electrical contact.
- Dc can be calculated starting with the diameter Dv ( FIG. 4 ) of via 330 , by subtracting double the thickness of the layers 410 , 420 , 430 . 1 , 444 , 448 .
- the depth Hcav of each cavity 210 B (about equal to the thickness of layer 110 . 3 ) is 50 ⁇ m for a 50 ⁇ m height Hd of contact pads 340 (Hcav is measured to the top surface of contact pads 350 ).
- Cavities 210 B are filled with solder paste 930 .
- the solder paste is deposited to cover the BT substrate, and then is wiped off by a squeegee blade to force the solder into cavities 210 B and remove it from the top surface of BT layer 110 . 3 .
- the solder is chosen to have a high melting temperature to provide a desired solder hierarchy for subsequent solder attachment of dies 124 and PCB 130 .
- the solder paste is a no-clean type NC253 available from AIM of Montreal, Canada. This paste incorporates solder flux but there is no need to clean the flux after the solder reflow.
- No-flow underfill 940 (dielectric) is dispensed on BT substrate 110 at the future site of interposer 120 .
- the underfill is type STAYCHIPTM 2078E available from Cookson Electronics, a company having an office in Georgia, the United States of America. This underfill performs both the underfill function and the solder flux function.
- the underfill can be dispensed with a dispensing system of type CAMELOT/SPEEDLINE 1818 available from Cookson Electronics.
- Interposer wafer 120 is placed on BT substrate 110 ( FIG. 10 ).
- Protruding contact pads 340 enter the BT substrate cavities 210 B and contact the solder 930 but do not necessarily reach the metal 910 of contact pads 350 .
- a uniform height of contact pads 340 is not required for a good electrical contact.
- Underfill 940 spreads out under the interposer. In the embodiment shown, the bottom surface of silicon 140 does not reach the BT substrate. Underfill 940 helps insulate the silicon from solder 930 . Therefore, it is unnecessary to form a dielectric layer on the bottom silicon surface.
- the interposer placement can be performed with a placement tool of type SIPLACE F4 available from Siemens corporation of Germany.
- the placement tool picks up the interposer from the top by a vacuum holder 1010 schematically shown in FIG. 10 .
- the vacuum pick-up flattens the interposer if the interposer is warped.
- Dielectric 144 protects the interposer from being damaged by the holder.
- Other placement tools, with vacuum and non-vacuum holders, known or to be invented, can also possibly be used.
- vacuum holder 1010 releases the interposer.
- FIG. 11 illustrates another embodiment.
- the BT substrate 110 is similar to the BT substrate of FIGS. 9 and 10 , but a metal layer 220 is formed on the bottom and sidewalls of each BT substrate cavity 210 B.
- Metal 220 is believed to improve the strength and the electrical conductivity of the solder bond between contact pads 340 and contact pads 350 .
- Metal layer 220 can be copper deposited on the BT substrate and patterned by lift-off or some other process.
- metal 220 extends out of BT substrate cavities 210 B to the top surface of the BT layer 110 . 3 but does not provide any interconnects or other elements on the top surface of layer 110 . 3 .
- Metal 220 is present only in the immediate vicinity of each BT substrate cavity 210 B.
- Each contact pad 350 includes the portions of metal layers 910 , 220 on the bottom and sidewalls of the corresponding BT substrate cavity 210 B.
- metal 220 provides an additional level of interconnects and/or a power or ground plane on layer 110 . 3 .
- solder 720 has a lower melting temperature than solder 930 . Therefore, solder 930 is not melted during the attachment of dies 124 .
- Metal contact pads 136 C can be formed from a material other than copper. This may be desirable if solder 720 is placed on the interposer before the interposer attachment to BT substrate 110 , because copper in pads 136 C could diffuse in solder 720 during the interposer attachment to the BT substrate and increase the solder 720 melting temperature.
- interconnects 136 are made of copper, but contact pads 136 C are plated with a layer 710 of nickel or gold. Layer 710 does not dissolve in solder 720 and provides a barrier for the copper diffusion from interconnects 136 , so the melting temperature of solder 720 does not change. In other embodiments, the melting temperature of solder 720 changes during the attachment of the interposer to substrate 110 , but the melting temperature of solder 720 remains below the melting temperature of solder 930 .
- FIGS. 13-14 illustrate a possible manufacturing sequence with multiple die levels 124 . 1 , 124 . 2 , 124 . 3 attached to the packaging substrate.
- the packaging substrate is manufactured as in FIG. 10, 11 or 12 .
- the interposer vias are marked 330 . 0 (instead of 330 as in FIG. 3 ), the contact pads at the bottom of the interposer are marked 340 . 0 , and the solder at the top is marked 720 . 0 .
- the cavities at the top of the interposer are marked 210 . 0 .
- circuitry in dies 124 . 1 does not have to be identical to the interposer circuitry, and different dies 124 . 1 may differ from each other.
- contact pads 340 . 1 may have smaller dimensions, and may be placed closer to each other, as they do not have to meet the BT substrate dimension requirements.
- Pads 340 . 1 can be copper/nickel/gold structures as in FIG. 12 , or they can be made from other materials.
- the metal in vias 330 . 1 is insulated from substrate 140 . 1 by a dielectric 410 ( FIG. 12 ).
- dies 124 . 1 and interposer 120 have devices (e.g. transistors, diodes, and others) manufactured at the top surface (active surface). Transistor source/drain regions, diodes' cathodes and anodes, and other elements can be formed in semiconductor substrates 140 . 0 , 140 . 1 of interposer 120 and dies 124 . 1 at the top surface of the respective substrates. Cavities 210 . 1 are formed in the top surface of dies 124 . 1 , and solder balls 720 . 1 are formed in the cavities on the dies' top contact pads, possibly before the wafer thinning operation exposing the contact pads 340 . 1 , as in FIGS. 10-12 .
- devices e.g. transistors, diodes, and others
- Transistor source/drain regions, diodes' cathodes and anodes, and other elements can be formed in semiconductor substrates 140 . 0 , 140 . 1 of interposer 120 and dies 124 .
- Dies 124 . 2 may be similar to dies 124 . 1 . Dies 124 . 2 include metalized vias 330 . 2 in semiconductor substrates 140 . 2 , and contact pads 340 . 2 protruding out of the vias on the bottom. Dies 124 . 2 may contain devices (e.g. transistors, diodes, and others) manufactured at the top surface (active surface) of semiconductor substrates 140 . 2 . Transistor source/drain regions and other elements can be formed in semiconductor substrates 140 . 2 at the top surface. Cavities 210 . 2 are formed in the top surface of dies 124 . 2 , and solder balls 720 . 2 are formed in the cavities on the dies' top contact pads, possibly before the wafer thinning operation exposing the contact pads 340 . 2 , as in FIGS. 10-12 .
- devices e.g. transistors, diodes, and others
- Transistor source/drain regions and other elements can be formed in semiconductor substrates 140 . 2 at
- the third level dies 124 . 3 are like dies 124 in FIGS. 2 and 3 .
- the semiconductor substrates of dies 124 . 3 are marked 140 . 3 .
- the dies' active surface is the bottom surface.
- solder 720 . 0 does not present a problem because the dies 124 . 1 have not yet been attached to the interposer. If solder 720 . 0 is placed on the interposer after the attachment to the BT substrate, solder 720 . 0 can be reflowed in a separate step before the attachment of dies 124 . 1 . The solder reflow does not increase the melting temperature of solder 720 . 0 .
- all of solders 720 . 0 , 720 . 1 , 720 . 2 , 930 are initially the same material.
- the solders are eutectic type LF 128 described above, with the initial melting temperature of 218° C.
- the melting temperature of solder 930 increases to about 230° C. in step 1420 .
- dies 124 . 1 are soldered to interposer 120 with solder 720 . 0 , at a temperature of about 218° C. or higher, but below 230° C. not to melt the solder 930 .
- Contact pads 340 . 1 are inserted into cavities 210 . 0 of interposer 120 .
- the copper from contact pads 340 . 1 dissolves in solder 720 . 0 and increases its melting temperature to about 230° C.
- Solder 720 . 1 may be placed on dies 124 . 1 in advance and may melt, but its melting temperature does not increase because the solder 720 . 1 is not in contact with copper or other material that could increase the solder melting temperature (the top surface portions of the top contact pads of die 124 . 1 are made of suitable materials to ensure that the solder melting temperature does not increase).
- dies 124 . 2 are attached to dies 124 . 1 with solder 720 . 1 , at a temperature below 230° C.
- Contact pads 340 . 2 are inserted into cavities 210 . 1 of dies 124 . 1 .
- Solders 720 . 0 and 930 do not melt.
- the melting temperature of solder 720 . 1 is increased to about 230° C. due to the diffusion of copper from contact pads 340 . 2 .
- dies 124 . 3 are flip-chip attached to dies 124 . 2 with solder 720 . 2 , at a temperature below 230° C.
- Bumps 150 are inserted into cavities 210 . 2 of dies 124 . 2 .
- Solders 930 , 720 . 0 , 720 . 1 do not melt.
- bumps 150 may include copper to increase the melting temperature of solder 720 . 2 .
- the higher melting temperature may be desirable to prevent the solder melting during the attachment of BT substrate 110 to PCB 130 ( FIG. 3 ).
- the solder 134 used for the PCB attachment may be the same material (LF128) as the solders 930 , 720 . 0 , 720 . 1 , 720 . 2 .
- any number of dies can be used at each level.
- one or more dies 124 . 2 can be attached directly to interposer 120 , i.e. there may be three levels of dies over one interposer area but only two levels of dies over another interposer area. Any number of die levels can be present in different interposer areas. Dies 124 . 3 may be omitted. Dies 124 . 2 may have no contact pads on the top, or they may have contact pads on the top which can be wire bonded to other substrates.
- solder types and melting temperatures can be used, and materials other than copper can be used to increase the melting temperatures.
- materials and contact pad structures can be used in different dies.
- Different semiconductor substrates can be different semiconductor materials in the same structure.
- Varying the solder melting temperature to achieve a desired solder hierarchy is not limited to the interposer structures, but may be used in other semiconductor packages, known or to be invented, with or without interposers.
- FIG. 15 shows another manufacturing sequence. See also the aforementioned U.S. Pat. No. 6,322,903.
- numerals 124 . 2 , 124 . 1 , 120 denote both the dies as shown in FIG. 13 and the wafers from which the dies are obtained.
- Dies 124 . 3 are attached to wafer 124 . 2 (step 1510 ) before the wafer 124 . 2 is thinned and diced.
- Contacts 340 . 2 are not yet exposed.
- the wafer 124 . 2 is thinned to expose the contact pads 340 . 2 (step 1520 ), and diced (step 1524 ).
- dies 124 . 2 are attached to wafer 124 .
- step 1530 before the wafer is thinned and diced.
- wafer 124 . 1 is thinned to expose contact pads 340 . 1 (step 1540 ), and diced (step 1544 ).
- dies 124 . 1 are attached to interposer wafer 120 (step 1550 ) before the interposer wafer is thinned and diced.
- interposer wafer 120 is thinned to expose the contact pads 340 . 0 (step 1560 ), and diced (step 1564 ).
- the interposer is attached to BT substrate 110 (step 1570 ).
- All the thinning and dicing operations are performed when the wafer or die being thinned has been attached to other dies.
- the structure has therefore a greater mechanical strength and greater thermal dissipation capabilities for the thinning operation.
- Plasma and non-plasma thinning process can be used, and the solder can be protected with suitable underfill or other coatings. All the solders can be initially the same material. The solder attachment increases the melting temperature of each solder being reflowed, so the solder does not melt in the subsequent soldering steps, as in FIG. 14 .
- the invention is not limited to any particular manufacturing sequence however.
- the same dimensions are obtained for the attachment of dies 124 . 1 , 124 . 2 , 124 . 3 as for the attachment between the BT substrate and the interposer. More particularly, the final value of the gap between the silicon 140 . 1 and interposer 120 or between the silicon 140 . 2 and the dies 124 . 1 is 25 ⁇ m (gap values of 5 to 10 ⁇ m and larger are believed to be appropriate to provide sufficient electrical insulation if no dielectric is formed on the bottom surface of silicon 140 . 1 or 140 . 2 ); the portions of contacts 340 . 1 , 340 . 2 , 150 inside the respective cavities 210 . 0 , 210 . 1 , 210 .
- the top dielectric layer on interposer 120 and dies 124 . 1 , 124 . 2 is 50 ⁇ m thick. Other dimensions can also be used.
- Underfill (not shown) can be injected between the interposer and the dies 124 . 1 , between the dies 124 . 1 and 124 . 2 , and between the dies 124 . 2 and 124 . 3 using known techniques. No flow underfill can also be used.
- FIGS. 16A, 16B illustrate an embodiment in which a contact pad 350 (made from metal 910 ) covers only a portion of the bottom surface of opening 210 B in BT substrate 110 .
- FIG. 16B is a top view, and FIG. 16A shows a vertical cross section along the line A-A in FIG. 16B .
- Only portions of interposer 120 and substrate 110 are shown, with only one contact 340 and opening 210 B, though many such contacts and openings can be present.
- the contact 340 at the bottom of interposer 120 is shown to be formed by metal 430 in through silicon via 330 , but the contact 340 may have any structure, including the structures of FIGS. 10-13 , the structures used for contacts 150 of FIGS. 1-2 , and other structures known or to be invented.
- Substrate 110 can be a non-BT substrate, e.g. it can be a PCB or some other integrated circuit packaging substrate, or an integrated circuit die or an integrated circuit wafer (e.g. such as a die 124 . 1 or 124 . 2 in FIG. 13 ).
- Substrate 120 can be a semiconductor integrated circuit or a non-semiconductor packaging substrate.
- the advantage of the contact pad 350 as in FIGS. 16A, 16B is that the solder 930 does not wet the dielectric 110 . 2 on the bottom of opening 210 B. Therefore, more solder will gather closer to contact 340 , and the solder will reach higher up along the contact surface. This is believed to improve the mechanical strength and electrical conductivity of the solder joint. Less solder is needed for good mechanical strength and electrical conductivity, so the diameter of opening 230 B can be reduced (this diameter controls the solder volume by controlling the volume of the solder paste in opening 230 B).
- FIG. 16B only one conductive line 910 extends from contact pad 350 , but many lines 910 can extend from the contact pad.
- the width W 1 (20-30 ⁇ m in some embodiments) of line 910 is shown as smaller than the diameter of pad 350 , but this is not necessary.
- W 1 can be any number, with any relationship between W 1 and pad 350 .
- the invention is not limited to the circular shapes of pad 350 and opening 210 B. Any shapes can be employed.
- contact pad 350 includes two conductive layers 910 . 1 , 910 . 2 .
- the bottom layer 910 . 1 covers the whole bottom of opening 230 B, and the top layer 910 . 2 covers only a portion of the bottom of opening 230 B.
- Bottom layer 910 . 1 is less solder wettable than the top layer 910 . 2 .
- bottom layer 910 . 1 does not cover the whole bottom of opening 230 B, and the top layer 910 . 2 covers a smaller portion of the bottom of opening 230 B than the top layer 910 . 1 .
- FIGS. 18, 19 illustrate possible shapes of solder 930 in the embodiments of FIGS. 16A, 16B , 17 after the solder reflow before the attachment of interposer 120 to the BT substrate.
- the solder shape is an approximation; the solder is assumed to wet only the pad 350 , ignoring the line 910 extending from the pad (see FIG. 16B ). It is assumed that the solder shape is a sphere truncated at the bottom, of some diameter Ds.
- Symbol Hs denotes the solder ball height above contact pad 350 .
- Hc is the depth of cavity 210 B.
- Db is the diameter of pad 350 .
- Dc is the diameter of cavity 210 B (shown as Dcav in FIG. 9 ).
- the interposer may include capacitors having a capacitance of 5.0 pF or higher.
- capacitance values of 10 pF, 100 pF, or higher have been used on circuit boards to decouple the power lines from the ground lines or for other purposes, and such capacitors can be manufactured in the interposer.
- Resistors having resistance values of 10 ⁇ and higher e.g. 50 ⁇ , 100 ⁇ , or 150 ⁇
- Inductors having inductance values of 100 nH or higher are commonly used on circuit boards and can be manufactured in the interposer.
- the invention is not limited to particular capacitance, resistance or inductance values. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
Abstract
Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad (350) in the substrate but also a surrounding region. Solder (930) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (910.1, 910.2), with the top layer (910.2) being more solder wettable than the bottom layer (910.1) and the top layer covering only a portion of the bottom layer.
Description
- The present application is a division of U.S. patent application Ser. No. 10/798,540 filed on Mar. 10, 2004 by S. Savastiouk et al., entitled “ATTACHMENT OF INTEGRATED CIRCUIT STRUCTURES AND OTHER SUBSTRATES TO SUBSTRATES WITH VIAS”, incorporated herein by reference, which is a continuation-in-part of U.S. patent application Ser. No. 10/739,788 filed on Dec. 17, 2003 by S. Savastiouk et al., entitled “INTEGRATED CIRCUITS AND PACKAGING SUBSTRATES WITH CAVITIES, AND ATTACHMENT METHODS INCLUDING INSERTION OF PROTRUDING CONTACT PADS INTO CAVITIES”, incorporated herein by reference.
- The present invention relates to attachment of integrated circuits to other substrates.
- Integrated circuit dies (“chips”) can be attached to a lead frame and then packaged in a ceramic or plastic carrier. The leads of the lead frame can then be soldered to a printed circuit board (PCB). Alternatively, the chip can be soldered directly to the PCB (“flip chip” packaging). The flip chip packaging reduces the package size and shortens the electrical connections between the die and the PCB.
FIG. 1 illustrates achip 124 flip-chip attached to aPCB 130. The chip is attached face down, with itscontact pads 137 connected tocontact pads 139 of the PCB. - In the manufacturing process, contact pad metal layer 137 (the layer that provides the contact pads) is deposited and patterned over the chip's
silicon substrate 140. A passivationdielectric layer 147 is formed onlayer 137. Openings are formed in dielectric 147 to expose thecontact pads 137. As a result,contact pads 137 are recessed into the chip's surface. To connect thecontact pads 137 to the PCB, protrudingmetal bumps 150 are formed on the contact pads.Bumps 150 are bonded toPCB contact pads 139 with solder, an adhesive, or by thermal or thermosonic compression. -
Bumps 150 can themselves be made of solder. The chip is placed on the PCB withbumps 150 onpads 139, andsolder 150 is reflowed to form solder joints. This attachment is mechanically strong and reliable in the presence of thermal stresses, but the solder bumps are difficult to scale down ascontact pads 137 become smaller and the pitch between thepads 137 is reduced. As the solder bump sizes decrease to accommodate the smaller contact pads and pitches, the solder joints become mechanically and thermally weaker. Also, the solder ball (solder bump) size defines the standoff distance between thechip 124 and PCB 130. If the standoff is too small, there will be increased fatigue stresses on the solder joints during thermal cycling. In addition, there is a greater possibility of undesirable residues remaining between thechip 124 and the PCB and causing some degradation. -
Bumps 150 can also be made without solder, e.g. from copper (Cu) or gold (Au), to obtain better scalability. See S. Zama et al., “Flip Chip Interconnect Systems Using Wire Stud Bumps and Lead Free Solder”, 2000 Electronic Components and Technology Conference, pages 1111-1117 (available from IEEE); C. H. Wang et al., “Laser-Assisted Bump Transfer for Flip Chip Assembly”, 2000 International Symposium on Electronic Materials & Packaging, pages 86-90 (available from IEEE), both incorporated herein by reference. A combination of solder and copper has also been used. More particularly, a “copper pillar” can be plated oncontact pads 137, then solder is plated on the copper pillar. See H. Lu et al., “Predicting Optimal Process Conditions for Flip-Chip Assembly Using Copper Column Bumped Dies”, 2002 Electronics Packaging Technology Conference, pages 338-343 (available from IEEE); Tie Wang et al., “Studies on a Novel Flip-Chip Interconnect Structure—Pillar Bump”, 2001 Electronic Components and Technology Conference (available from IEEE), both incorporated herein by reference. - Improved integrated circuit attachment techniques are desirable.
- This section summarizes some features of the invention. Other features are described in the subsequent sections. The invention is defined by the appended claims which are incorporated into this section by reference.
- In some embodiments of the present invention, cavities are formed in the PCB, and the integrated circuit bumps are inserted into the cavities. For example, in
FIG. 2 ,cavities 210 are formed in the top surface ofPCB 130. At least a portion of eachcontact PCB pad 139 is located in the corresponding cavity.Bumps 150 are inserted into the cavities and attached tocontact pads 139.Bumps 150 may be solderless bumps, e.g. they may be copper columns, gold wires, or some other kind of bumps, known or to be invented.Bumps 150 may also include solder.Bumps 150 can be attached toPCB contact pads 139 with solder, a conductive or anisotropic adhesive, by thermal or thermosonic compression, or some other technique, known or to be invented. For example, in some embodiments, solder paste or an adhesive (not shown) are deposited incavities 210, then the die 124 is placed on the PCB with thebumps 150 inserted into the cavities. - In some embodiments,
cavities 210 increase the mechanical strength of the structure. The structure becomes stronger against lateral forces (including lateral stresses caused by thermal expansion). Also, the amount of solder or adhesive can be increased by increasing the depth ofcavities 210 without increasing the lateral size of the structure. Improved scalability is therefore provided. - In addition, if
bumps 150 are attached with solder or a conductive or anisotropic adhesive, the size uniformity requirements forbumps 150 are relaxed. If the bumps are not uniform in size, the shorter bumps will still provide a reliable electrical connection tocontacts 139 as long as there is a reliable electrical connection between the bumps and the solder or adhesive incavities 210. - In
FIG. 2 , an optional conductive film 220 (e.g. metal) is formed on the bottom and sidewalls of eachcavity 210.Film 220 is believed to improve the strength and the electrical conductivity of the bond betweenbumps 150 andcontact pads 139.Film 220 is not necessary however. -
Bumps 150 can be thought of as “contact pads”, and the invention is applicable to any protruding contact pads and not necessarily the protruding pads formed by bumping a die. For example, protruding contact pads can be formed on a die by removing the die material to expose metal features, as described in U.S. Pat. No. 6,322,903 issued Nov. 27, 2001 to Siniaguine et al. and incorporated herein by reference. - In some embodiments,
layer 220 is absent, and acavity 210 exposes not only thecontact pad 139 but also a surrounding dielectric region insubstrate 130. The solder (not shown) wets thecontact pad 139 better than the surrounding region, so more solder gathers near thebump 150, and the solder reaches up higher along the surface ofbump 150. This is believed to provide a stronger solder joint and better electrical conductivity at least in some embodiments. Alternatively, thecontact pad 139 orlayer 220 may include multiple conductive layers, with the top layer being more solder wettable than the bottom layers and the top layer covering only a portion of the bottom layers. The solder will preferentially wet the more solder wettable layer, gathering closer tobump 150 and reaching up higher. - The invention is not limited to the embodiments discussed in this section. For example,
cavities 210 can be replaced by through vias (through holes) that pass through the PCB 130.Contacts 139 can be metal layers on the sidewalls of the through vias. Theintegrated circuit structure 124 can be a wafer rather than a die.PCB 130 can be replaced with a ball grid array substrate (BGA) or some other packaging substrate, e.g. a silicon interposer.PCB 130 can also be replaced with another integrated circuit structure (a die or a wafer). Other features and advantages of the invention are described below. The invention is defined by the appended claims. -
FIG. 1 shows a vertical cross section of an integrated circuit attached to a PCB according to prior art. -
FIGS. 2, 3 show vertical cross sections of integrated circuits attached to substrates according to embodiments of the present invention. -
FIGS. 4-8 show vertical cross sections of integrated circuits in the process of fabrication for attachment according to embodiments of the present invention. -
FIG. 9 shows a vertical cross section of a BT substrate fabricated according to an embodiment of the present invention. -
FIGS. 10-13 show vertical cross sections of integrated circuits attached to substrates according to embodiments of the present invention. -
FIGS. 14, 15 are flowcharts of an integrated circuit packaging processes according to embodiments of the present invention. - The embodiments described in this section illustrate but do not limit the invention. The invention is not limited to particular materials, process steps, or dimensions. The invention is defined by the appended claims.
-
FIG. 3 illustrates another integrated circuit packaging structure. Integratedcircuit packaging substrate 310 is an intermediate substrate that provides an interconnection between dies 124 andPCB 130.Substrate 310 includes two intermediate integratedcircuit packaging substrates Substrate 120 is a silicon interposer attached toBT substrate 110, and thus is itself a semiconductor integrated circuit. The attachment is made as described above in connection withFIG. 2 . More particularly,cavities 210B (also called vias or openings herein) are formed in the top surface ofBT substrate 110.Protruding contact pads 340 ofinterposer 120 are inserted into the cavities. - Dies 124 are attached to interposer 120 as in
FIG. 2 . More particularly,cavities 210 are formed in the top surface of the interposer, and the dies'bumps 150 are inserted into these cavities.BT substrate 110 is attached toPCB 130 in a conventional manner. More particularly,solder balls 134 are attached to contactpads 360 on the bottom surface ofBT substrate 110, and the solder balls are later reflowed to solder thecontact pads 360 toPCB contact pads 139. These features are not limiting. For example, in some embodiments, the cavities are used to attach the dies 124 tointerposer 120 but the attachment ofinterposer 120 toBT substrate 110 is performed without cavities. In other embodiments, the cavities are used to attach theinterposer 120 toBT substrate 110, but the attachment of dies 124 tointerposer 120 is performed without cavities. In other embodiments, the cavities are used to attach one but not both dies 124 tointerposer 120. Also, the cavities can be used to attach some but not all of the a single die's contact pads to the interposer, or some but not all of the interposer'scontact pads 340 toBT substrate 110. -
Silicon interposer 120 includesmetal layers 136 formed oversilicon substrate 140.Substrate 140 has substantially planar top and bottom surfaces, and is quite thin. In some embodiments, the planarity ofsubstrate 140 is suitable for fine geometry photolithography (finer than possible with BT and FR4 substrates). The thickness ofsubstrate 140 can be 100 μm or less (50 μm to 35 μm thickness values believed to be achievable, and smaller values may be possible).Layers 136 provide interconnect lines and may also provide power and ground planes, resistors, inductors, capacitor plates for decoupling capacitors and other capacitor types, and possibly other elements, known or to be invented.Layers 136 can be separated from each other, and from the substrate, bydielectric layers 144.Layers 136 contact each other and the silicon substrate through openings in the dielectric layers.Layers 136 can also be formed directly on the silicon substrate if desired.Layers 136 providecontact pads 136C at the top surface of the interposer. At least a portion of eachcontact pad 136C is located in acorresponding cavity 210. - These features are exemplary and not necessary. For example,
silicon substrate 140 can be thicker than described above, and its top and bottom surfaces do not have to be planar. - In the embodiment of
FIG. 3 ,silicon substrate 140 includes metalized through-silicon vias 330 that pass between the top and bottom surfaces ofsubstrate 140. Conductive paths are provided fromcontact pads 136C at the top of the interposer to contactpads 340 at the bottom of the interposer through thevias 330. Contactpads 340 protrude out ofvias 330. Contactpads 340 are attached to contactpads 350 at the top surface ofBT substrate 110. - Interconnects (not shown) in
BT substrate 110 connect thecontact pads 350 to contactpads 360 at the bottom surface ofsubstrate 110.Solder balls 134 are formed onpads 360 by conventional techniques for attachment toPCB 130. - The size and spacing (pitch) of
contact pads 136C oninterposer 120 matches the size and the pitch of the contact pads on dies 124. If dies 124 are silicon integrated circuits, their CTE (coefficient of thermal expansion) matches the CTE of the interposer, so the pitch ofcontact pads 136C can be small because the low thermal stresses at the interface between the dies and the interposer make it unnecessary to uselarge bumps 150 as would be desirable for a strong mechanical connection. Thecontact pads 340 on the bottom of the interposer match thetop contact pads 350 ofBT substrate 110. For some fabrication technologies, the minimum dimensions are as shown in the following Table 1. The dimensions can typically be reduced if more expensive technologies are used.TABLE 1 Minimum Solder ball Contacts pitch Solder ball diameter height Contact pads 136C 125 μm 75 μm 60 μm Contact pads 340, 350 254 μm 150 μm 120 μm (solder balls, not shown, joining pads 340 to 350)Contact pads 3601.27 mm 0.75 mm 0.60 mm (solder balls 134) -
Silicon interposer 120 can be manufactured using conventional techniques. See e.g. the aforementioned U.S. Pat. No. 6,322,903. Other techniques are described in U.S. patent application Ser. No. 10/410,929 filed on Apr. 9, 2003 by P. Halahan et al., entitled “Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby”, incorporated herein by reference. Still other techniques can possibly be used, whether known or to be invented. An exemplary manufacturing process is as follows. Vias 330 (FIG. 4 ) are etched in the top surface of silicon substrate 140 (e.g. monocrystalline silicon) by DRIE (deep reactive ion etching) to an exemplary depth Hv=150 μm. (The dimensions, etching processes, and other particulars are exemplary and not limiting.) The via diameter Dv is 25 μm to 100 μm. The via diameter DV is one of the parameters defining the diameter of contact pads 340 (FIG. 3 ), and DV is chosen large enough to provide the necessary mechanical strength for the protruding contact pads. Exemplary dimensions below will be given for Dv=65 μm.Silicon dioxide layer 410 is thermally grown on the wafer to a thickness of about 1 μm. A larger thickness can also be used to reduce the capacitance betweensubstrate 140 and the metal features that will be fabricated invias 330.Barrier layer 420 of titanium-tungsten (TiW) is sputtered onoxide 410 to a thickness of 0.2 μm. A seed copper (Cu) layer 430.1 is sputtered on the wafer to a thickness sufficient to ensure a continuous copper coverage in the vias. Thicknesses of 0.5 μm to 2 μm are believed to be adequate, depending on the sputter technology. Adry photoresist film 440 is deposited on the wafer and patterned to expose thevias 330. - Optionally, gold (Au)
layer 444 and nickel (Ni)layer 448 are electroplated, in that order, to an exemplary thickness of 0.2 μm and 1.0 μm respectively. - Copper 430.2 is electroplated on
nickel 448 to fill thevias 330 and possibly protrude out of the vias. In the electroplating oflayers wafer 140 in physical contact with seed layer 430.1. - Optionally, nickel (Ni)
layer 450 is electroplated on the top surface of copper layer 430.2 to an exemplary thickness of 0.5 μm. - Resist 440 is removed (
FIG. 5 ). A wet copper etch removes the exposed portions of seed copper 430.1, withnickel 450 acting as a mask.Nickel 450 protects copper 430.2 invias 330. Copper 430.2, 430.1 can be etched laterally during the wet etch, but the lateral etch does not remove the copper over thevias 330 because the copper extends laterally beyond the via edges. In those embodiments in which thenickel 450 is omitted, the copper etch may reduce the thickness of copper 430.2, but this is acceptable if the copper protrusions above the vias are sufficiently thick. In either case, it is desirable for the top surface of copper 430.2 to be at or above the top surface ofoxide 410 after the copper etch. - Then a CMP step (chemical mechanical polishing) is performed to remove copper 430.2,
nickel 448,gold 444, andTiW 420 off the top surface of substrate 140 (FIG. 6 ). The CMP stops onoxide 410. The structure has a planar top surface. - In an alternative embodiment, the wet etch of copper 430.1 is omitted, and copper 430.1 is removed by the CMP step. The separate wet etch of copper 430.1 may be desirable however because it may shorten the more expensive CMP step, thus reducing the total manufacturing cost.
-
Oxide 410 can be patterned if desired. Metal layers 136 (FIG. 7 ) anddielectric layers 144 are deposited on the interposer wafer and patterned to provide interconnects and, possibly, other elements as described above. In some embodiments,metal 136 is copper anddielectric 144 is polyimide, but other materials can also be used. Some or all ofdielectric layers 144 can be silicon dioxide, photosensitive benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials. For a capacitor, a high dielectric constant material (such as Ta2O5) can be used. Aluminum, conductive polysilicon, and other materials can be used aslayers 136.Cavities 210 are formed in thetop dielectric layer 144 to expose thecontact pads 136C provided by thetop metal layer 136. Solder wettable materials 710 (e.g. Ni and/or Au) can be plated oncontact pads 136C if desired. -
Solder balls 720 are formed oncontact pads 136C, by any suitable technique. For example, solder paste can be deposited to cover theinterposer wafer 120, and then wiped off by a squeegee blade to force the solder intocavities 210 and remove it from the top surface of thetop layer 144. In some embodiments, interconnects 136 are made of copper, andcontact pads 136C are plated with alayer 710 of nickel or gold.Layer 710 does not dissolve insolder 720 and provides a barrier for the copper diffusion frominterconnects 136, so the melting temperature ofsolder 720 does not change when the solder is reflowed. - In some embodiments, the solder is not placed at this stage to avoid solder melting at high temperatures present in plasma wafer thinning processes described below in connection with
FIG. 8 . Whether or not the solder is placed at this stage or after the wafer thinning, thetop dielectric layer 144 is sufficiently thick to accommodate the solder volume needed for a reliable bond to dies 124 (FIG. 1 ). In some embodiments, thetop dielectric 144 is 50 μm thick.Cavities 210 are about 50 μm deep and have a diameter of about 75 μm. - Then the interposer wafer is thinned from the bottom to expose the
gold 444. SeeFIG. 8 . The exposed metal provides the contact pads 340 (FIG. 3 ) that will be soldered toBT substrate 110. The wafer thinning can be performed with any of the techniques described in the aforementioned U.S. Pat. No. 6,322,903 and U.S. patent application Ser. No. 10/410,929. See also U.S. Pat. No. 6,498,381 issued on Dec. 24, 2002 to Halahan et al. and incorporated herein by reference. In one embodiment, the wafer thinning includes a CF4 plasma etch at atmospheric pressure. The wafer is held from the top by a vortex wafer holder (not shown) that does not touch the wafer except possibly at the wafer periphery. The holder emits gas vortices that create vacuum between the holder and the wafer but do not allow the wafer to touch the top surface of the holder. The plasma etch exposes theoxide 410 and then etches thesilicon 140,oxide 410 andTiW 420 selectively to copper 430.1. (Copper 430.1 is etched later as explained below.) The plasma etch etchessilicon 140 faster thanoxide 410, so the oxide protrudes out of the silicon the bottom surface of the wafer after the etch. In one embodiment, the final thickness “Tsif” (marked inFIG. 8 ) ofsilicon substrate 140 is 100 μm, and it can be smaller (e.g. 35 μm).Oxide 410 andTiW 420form 5 μm protrusions around the copper 430.1 below the silicon surface. If thesolder 720 melting temperature is low, the solder can melt in this process and be blown away by the wafer holder's gas vortices. Therefore, in some embodiments thesolder 720 is placed on the wafer after the wafer thinning and, possibly, after the wafer attachment toBT substrate 110. - The plasma etch forms copper oxide (not shown) on the exposed portions of copper 430.1. The copper oxide and the copper 430.1 are etched by a wet etch to expose
gold 444. The gold provides a solderable oxide-free surface.Nickel 448 will prevent copper diffusion from layer 430.2 into the solder. The copper diffusion may be undesirable because it increases the solder melting temperature. In other embodiments, the copper diffusion is desirable to achieve a certain solder hierarchy (the hierarchy of the melting temperatures of different solders) as explained below. In such embodiments, the etch of copper 430.1 can be omitted.Nickel 448 can also be omitted. - As stated above,
gold 444 can be omitted. The etch of copper 430.1 will then exposenickel 448. - In some embodiments, the copper 430.1 is not etched away. The copper oxide (not shown) on copper 430.1 can be removed by a wet etch. The copper oxide can also be removed by a solder flux during soldering of the interposer wafer to BT substrate 110 (the soldering operation is described below).
Layers -
Metal contact pads 340 are metal protrusions formed by the metal layers 430.2, 448, 444, 430.1, 420 below the bottom surface ofsilicon 140. In some embodiments, the height Hd ofmetal contact pads 340 is 50 μm. - A dielectric layer (not shown) can optionally be formed on the bottom surface or the interposer to cover the
silicon 140 but not themetal contact pads 340. The dielectric can be formed without photolithography. See the aforementioned U.S. Pat. Nos. 6,322,903 and 6,498,381 and U.S. patent application Ser. No. 10/410,929. - The interposer wafer can be diced if desired. The dicing can be performed at the same time as the interposer wafer thinning if vias were formed along the dicing lines (scribe lines) simultaneously with
vias 330 at the stage ofFIG. 4 . See U.S. Pat. No. 6,498,074 issued Dec. 24, 2002 to Siniaguine et al., entitled “THINNING AND DICING OF SEMICONDUCTOR WAFERS . . . ”, incorporated herein by reference. - In some embodiments, the interposer wafer is not diced.
ICs 124 will be attached to the undiced interposer wafer. - In some embodiments, metal 430.2 does not fill the through-silicon vias. Metal 430.2 is a thin film deposited over the via sidewalls, and it can be part of a
layer 136. See the aforementioned U.S. Pat. No. 6,498,381. Also, in some embodiments thecontact pads 340 do not protrude out of the bottom surface of the interposer. - BT substrate 110 (
FIGS. 9 and 10 ) is formed from one or more BT layers laminated in a conventional manner. Three layers 110.1, 110.2, 110.3 are shown, but any number of layers can be present. Thin film metal layers 910 (e.g. copper) are formed on top of BT layers 110.i (i=1, 2, 3) and on the bottom side of layer 110.1 in a conventional manner to provide signal routing paths and ground and power planes.Layers 910 are interconnected through vias in the BT layers 110.i (i.e. 110.1, 110.2, 110.3) using known techniques to provide conductive paths betweencontact pads 350 andcontact pads 360. Thebottom metal layer 910 provides contact pads 360 (FIG. 3 ) at the bottom surface ofBT substrate 110. -
Top contact pads 350, and thetop metal layer 910, are formed below the top BT layer 110.3. InFIG. 9 , thetop contact pads 350 and thetop metal 910 are formed on BT layer 110.2. Layer 110.3 hasvias 210B exposing thecontact pads 350.Vias 210B form cavities in the top surface ofBT substrate 110. Siliconinterposer contact pads 340 will be inserted into these cavities to form a reliable mechanical and electrical contact. - In one embodiment, each
BT substrate cavity 210B has a diameter Dcav=150 μm to accommodate a 50 μm to 60 μm diameter Dc of thecontact pads 340. Dc can be calculated starting with the diameter Dv (FIG. 4 ) of via 330, by subtracting double the thickness of thelayers cavity 210B (about equal to the thickness of layer 110.3) is 50 μm for a 50 μm height Hd of contact pads 340 (Hcav is measured to the top surface of contact pads 350). -
Cavities 210B are filled withsolder paste 930. In one embodiment, the solder paste is deposited to cover the BT substrate, and then is wiped off by a squeegee blade to force the solder intocavities 210B and remove it from the top surface of BT layer 110.3. The solder is chosen to have a high melting temperature to provide a desired solder hierarchy for subsequent solder attachment of dies 124 andPCB 130. In some embodiments, the solder paste is a no-clean type NC253 available from AIM of Montreal, Canada. This paste incorporates solder flux but there is no need to clean the flux after the solder reflow. - No-flow underfill 940 (dielectric) is dispensed on
BT substrate 110 at the future site ofinterposer 120. In some embodiments, the underfill is type STAYCHIP™ 2078E available from Cookson Electronics, a company having an office in Georgia, the United States of America. This underfill performs both the underfill function and the solder flux function. The underfill can be dispensed with a dispensing system of type CAMELOT/SPEEDLINE 1818 available from Cookson Electronics. -
Interposer wafer 120 is placed on BT substrate 110 (FIG. 10 ).Protruding contact pads 340 enter theBT substrate cavities 210B and contact thesolder 930 but do not necessarily reach themetal 910 ofcontact pads 350. A uniform height ofcontact pads 340 is not required for a good electrical contact. -
Underfill 940 spreads out under the interposer. In the embodiment shown, the bottom surface ofsilicon 140 does not reach the BT substrate.Underfill 940 helps insulate the silicon fromsolder 930. Therefore, it is unnecessary to form a dielectric layer on the bottom silicon surface. - The interposer placement can be performed with a placement tool of type SIPLACE F4 available from Siemens corporation of Germany. The placement tool picks up the interposer from the top by a
vacuum holder 1010 schematically shown inFIG. 10 . The vacuum pick-up flattens the interposer if the interposer is warped.Dielectric 144 protects the interposer from being damaged by the holder. Other placement tools, with vacuum and non-vacuum holders, known or to be invented, can also possibly be used. - The structure is heated to reflow the
solder paste 930 and cure theunderfill 940. The solder wets the bottom and side surfaces ofcopper contact pads 340. In one embodiment, the final value of the gap G1 between thesilicon 140 and theBT substrate 110 is 25 μm. The gap values of 5 to 10 μm and larger are believed to be appropriate to provide sufficient electrical insulation if no dielectric is formed on the bottom surface ofsilicon 140. Thecontact 340 portion inside thevias 210B is 25 μm high (C1=25 μm inFIG. 10 ). The value C1 is in the range from 10 μm to 451 μm in some embodiments. - If the
solder 720 was placed on the interposer before the interposer attachment toBT substrate 110,solder 720 may or may not be reflowed during this step depending on thesolder 720 melting temperature. - Then
vacuum holder 1010 releases the interposer. - In some embodiments, the vacuum holder releases the interposer before the reflow of
solder paste 930. The interposer stays in place due to a surface tension betweensilicon 140 and theunderfill 940. Multiple interposers can be placed onBT substrate 110, and the solder reflow and underfill curing can be performed in a single heating step for all the interposers, after thevacuum holder 1010 is removed. A similar technique has previously been applied for flip-chip mounting of dies on a BT substrate, as described in M. Painaik and J. Hurtley, “Process Recommendations for Assembly of Flip Chips using No-flow Underfill”, Technical Bulletin, Cookson Semiconductor. -
FIG. 11 illustrates another embodiment. TheBT substrate 110 is similar to the BT substrate ofFIGS. 9 and 10 , but ametal layer 220 is formed on the bottom and sidewalls of eachBT substrate cavity 210B.Metal 220 is believed to improve the strength and the electrical conductivity of the solder bond betweencontact pads 340 andcontact pads 350.Metal layer 220 can be copper deposited on the BT substrate and patterned by lift-off or some other process. InFIG. 11 ,metal 220 extends out ofBT substrate cavities 210B to the top surface of the BT layer 110.3 but does not provide any interconnects or other elements on the top surface of layer 110.3.Metal 220 is present only in the immediate vicinity of eachBT substrate cavity 210B. Eachcontact pad 350 includes the portions ofmetal layers BT substrate cavity 210B. In other embodiments,metal 220 provides an additional level of interconnects and/or a power or ground plane on layer 110.3. - In the BT embodiment described above, the BT layers 110.1, 110.2, 110.3 are laminated on top of each other. Each layer 110.1, 110.2 is a solid sheet placed on the structure in a solid form. In some embodiments, the top layer 110.3 is made from a material different from the material of layers 110.1, 110.2. For example, solder dam materials can be used, such as photoimageable polyimide, Dupont VACREL 8100, Dupont Flexible Photolmageable Coverlay (PIC) 1000 & 2000, Shipley (Dynachem) DynaMASK 5000, Shipley ConforMASK 2500, and possibly others. Some of the solder dam materials (e.g. polyimide) can be deposited in a liquid (possibly viscous) form and then cured.
- In some embodiments,
solder 720 has a lower melting temperature thansolder 930. Therefore,solder 930 is not melted during the attachment of dies 124. - In other embodiments,
solder 720 initially has the same or higher melting temperature thansolder 930, but the melting temperature ofsolder 930 is increased during the attachment ofinterposer 120 toBT substrate 110. The melting temperature ofsolder 930 becomes higher than the melting temperature ofsolder 720. The melting temperature ofsolder 930 is increased because the copper fromlayer 220 and/orlayer 350 dissolves insolder 930. In the embodiment ofFIG. 12 , copper 430.1 was not etched away as inFIG. 8 , so copper 430.1 can also dissolve insolder 930. In some embodiments,solders -
Metal contact pads 136C can be formed from a material other than copper. This may be desirable ifsolder 720 is placed on the interposer before the interposer attachment toBT substrate 110, because copper inpads 136C could diffuse insolder 720 during the interposer attachment to the BT substrate and increase thesolder 720 melting temperature. In some embodiments, interconnects 136 are made of copper, butcontact pads 136C are plated with alayer 710 of nickel or gold.Layer 710 does not dissolve insolder 720 and provides a barrier for the copper diffusion frominterconnects 136, so the melting temperature ofsolder 720 does not change. In other embodiments, the melting temperature ofsolder 720 changes during the attachment of the interposer tosubstrate 110, but the melting temperature ofsolder 720 remains below the melting temperature ofsolder 930. -
FIGS. 13-14 illustrate a possible manufacturing sequence with multiple die levels 124.1, 124.2, 124.3 attached to the packaging substrate. The packaging substrate is manufactured as inFIG. 10, 11 or 12. The interposer vias are marked 330.0 (instead of 330 as inFIG. 3 ), the contact pads at the bottom of the interposer are marked 340.0, and the solder at the top is marked 720.0. The cavities at the top of the interposer are marked 210.0. - Each die 124.1 has one or more metalized through vias 330.1 formed in the die's semiconductor substrate 140.1 (e.g. monocrystalline silicon). Each via 330.1 passes between the top and bottom surfaces of substrate 140.1. Conductive paths are provided from contact pads at the top of each die 124.1 to contact pads 340.1 at the bottom of the die through the vias 330.1. Contact pads 340.1 protrude out of the respective vias 330.1. The dies 124.1 can be manufactured using the same techniques as described above for interposer 120 (involving the wafer thinning to expose the contact pads 340.1). Each die may have the same general structure as
interposer 120 inFIGS. 10-12 . Of course, the circuitry in dies 124.1 does not have to be identical to the interposer circuitry, and different dies 124.1 may differ from each other. Also, contact pads 340.1 may have smaller dimensions, and may be placed closer to each other, as they do not have to meet the BT substrate dimension requirements. Pads 340.1 can be copper/nickel/gold structures as inFIG. 12 , or they can be made from other materials. The metal in vias 330.1 is insulated from substrate 140.1 by a dielectric 410 (FIG. 12 ). - In some embodiments, dies 124.1 and
interposer 120 have devices (e.g. transistors, diodes, and others) manufactured at the top surface (active surface). Transistor source/drain regions, diodes' cathodes and anodes, and other elements can be formed in semiconductor substrates 140.0, 140.1 ofinterposer 120 and dies 124.1 at the top surface of the respective substrates. Cavities 210.1 are formed in the top surface of dies 124.1, and solder balls 720.1 are formed in the cavities on the dies' top contact pads, possibly before the wafer thinning operation exposing the contact pads 340.1, as inFIGS. 10-12 . - Dies 124.2 may be similar to dies 124.1. Dies 124.2 include metalized vias 330.2 in semiconductor substrates 140.2, and contact pads 340.2 protruding out of the vias on the bottom. Dies 124.2 may contain devices (e.g. transistors, diodes, and others) manufactured at the top surface (active surface) of semiconductor substrates 140.2. Transistor source/drain regions and other elements can be formed in semiconductor substrates 140.2 at the top surface. Cavities 210.2 are formed in the top surface of dies 124.2, and solder balls 720.2 are formed in the cavities on the dies' top contact pads, possibly before the wafer thinning operation exposing the contact pads 340.2, as in
FIGS. 10-12 . - The third level dies 124.3 are like dies 124 in
FIGS. 2 and 3 . The semiconductor substrates of dies 124.3 are marked 140.3. The dies' active surface is the bottom surface. - The manufacturing sequence is shown in
FIG. 14 .Interposer 120 is attached toBT substrate 110 as described above with respect toFIGS. 10-12 (step 1420). During this step, the melting temperature of solder 930 (FIGS. 10-12 ) increases and becomes higher than the melting temperature of solders 720.0, 720.1, 720.2. Solder 720.0 can be placed on the interposer after the attachment toBT substrate 110. If solder 720.0 is placed before the attachment, solder 720.0 may or may not be melted during the attachment step, but its melting temperature does not change because this solder is not in contact with copper (there is no copper on the top surface of the top contact pads of the interposer). The melting of solder 720.0 does not present a problem because the dies 124.1 have not yet been attached to the interposer. If solder 720.0 is placed on the interposer after the attachment to the BT substrate, solder 720.0 can be reflowed in a separate step before the attachment of dies 124.1. The solder reflow does not increase the melting temperature of solder 720.0. - In some embodiments, all of solders 720.0, 720.1, 720.2, 930 are initially the same material. In an illustrative example, the solders are eutectic type LF 128 described above, with the initial melting temperature of 218° C. The melting temperature of
solder 930 increases to about 230° C. instep 1420. - At
step 1430, dies 124.1 are soldered to interposer 120 with solder 720.0, at a temperature of about 218° C. or higher, but below 230° C. not to melt thesolder 930. Contact pads 340.1 are inserted into cavities 210.0 ofinterposer 120. The copper from contact pads 340.1 dissolves in solder 720.0 and increases its melting temperature to about 230° C. Solder 720.1 may be placed on dies 124.1 in advance and may melt, but its melting temperature does not increase because the solder 720.1 is not in contact with copper or other material that could increase the solder melting temperature (the top surface portions of the top contact pads of die 124.1 are made of suitable materials to ensure that the solder melting temperature does not increase). - At
step 1440, dies 124.2 are attached to dies 124.1 with solder 720.1, at a temperature below 230° C. Contact pads 340.2 are inserted into cavities 210.1 of dies 124.1. Solders 720.0 and 930 do not melt. The melting temperature of solder 720.1 is increased to about 230° C. due to the diffusion of copper from contact pads 340.2. - At
step 1450, dies 124.3 are flip-chip attached to dies 124.2 with solder 720.2, at a temperature below 230°C. Bumps 150 are inserted into cavities 210.2 of dies 124.2.Solders 930, 720.0, 720.1 do not melt. If desired, bumps 150 may include copper to increase the melting temperature of solder 720.2. The higher melting temperature may be desirable to prevent the solder melting during the attachment ofBT substrate 110 to PCB 130 (FIG. 3 ). For example, thesolder 134 used for the PCB attachment may be the same material (LF128) as thesolders 930, 720.0, 720.1, 720.2. - Many variations are possible. For example, any number of dies can be used at each level. Also, one or more dies 124.2 can be attached directly to
interposer 120, i.e. there may be three levels of dies over one interposer area but only two levels of dies over another interposer area. Any number of die levels can be present in different interposer areas. Dies 124.3 may be omitted. Dies 124.2 may have no contact pads on the top, or they may have contact pads on the top which can be wire bonded to other substrates. - Other solder types and melting temperatures can be used, and materials other than copper can be used to increase the melting temperatures. Different materials and contact pad structures can be used in different dies. Different semiconductor substrates can be different semiconductor materials in the same structure.
- Varying the solder melting temperature to achieve a desired solder hierarchy is not limited to the interposer structures, but may be used in other semiconductor packages, known or to be invented, with or without interposers.
-
FIG. 15 shows another manufacturing sequence. See also the aforementioned U.S. Pat. No. 6,322,903. Below, numerals 124.2, 124.1, 120 denote both the dies as shown inFIG. 13 and the wafers from which the dies are obtained. Dies 124.3 are attached to wafer 124.2 (step 1510) before the wafer 124.2 is thinned and diced. Contacts 340.2 are not yet exposed. Then the wafer 124.2 is thinned to expose the contact pads 340.2 (step 1520), and diced (step 1524). Then dies 124.2 are attached to wafer 124.1 (step 1530) before the wafer is thinned and diced. Then wafer 124.1 is thinned to expose contact pads 340.1 (step 1540), and diced (step 1544). Then dies 124.1 are attached to interposer wafer 120 (step 1550) before the interposer wafer is thinned and diced. Theninterposer wafer 120 is thinned to expose the contact pads 340.0 (step 1560), and diced (step 1564). Then the interposer is attached to BT substrate 110 (step 1570). All the thinning and dicing operations (steps FIG. 14 . - The invention is not limited to any particular manufacturing sequence however.
- In some embodiments, the same dimensions are obtained for the attachment of dies 124.1, 124.2, 124.3 as for the attachment between the BT substrate and the interposer. More particularly, the final value of the gap between the silicon 140.1 and
interposer 120 or between the silicon 140.2 and the dies 124.1 is 25 μm (gap values of 5 to 10 μm and larger are believed to be appropriate to provide sufficient electrical insulation if no dielectric is formed on the bottom surface of silicon 140.1 or 140.2); the portions of contacts 340.1, 340.2, 150 inside the respective cavities 210.0, 210.1, 210.2 are 25 μm high (note dimension C1 inFIG. 10 ). This value is in the range from 10 μm to 45 μm in some embodiments. The top dielectric layer oninterposer 120 and dies 124.1, 124.2 is 50 μm thick. Other dimensions can also be used. - Underfill (not shown) can be injected between the interposer and the dies 124.1, between the dies 124.1 and 124.2, and between the dies 124.2 and 124.3 using known techniques. No flow underfill can also be used.
-
FIGS. 16A, 16B illustrate an embodiment in which a contact pad 350 (made from metal 910) covers only a portion of the bottom surface of opening 210B inBT substrate 110.FIG. 16B is a top view, andFIG. 16A shows a vertical cross section along the line A-A inFIG. 16B . Only portions ofinterposer 120 andsubstrate 110 are shown, with only onecontact 340 andopening 210B, though many such contacts and openings can be present. Thecontact 340 at the bottom ofinterposer 120 is shown to be formed bymetal 430 in through silicon via 330, but thecontact 340 may have any structure, including the structures ofFIGS. 10-13 , the structures used forcontacts 150 ofFIGS. 1-2 , and other structures known or to be invented.Substrate 110 can be a non-BT substrate, e.g. it can be a PCB or some other integrated circuit packaging substrate, or an integrated circuit die or an integrated circuit wafer (e.g. such as a die 124.1 or 124.2 inFIG. 13 ).Substrate 120 can be a semiconductor integrated circuit or a non-semiconductor packaging substrate. - The advantage of the
contact pad 350 as inFIGS. 16A, 16B is that thesolder 930 does not wet the dielectric 110.2 on the bottom ofopening 210B. Therefore, more solder will gather closer to contact 340, and the solder will reach higher up along the contact surface. This is believed to improve the mechanical strength and electrical conductivity of the solder joint. Less solder is needed for good mechanical strength and electrical conductivity, so the diameter of opening 230B can be reduced (this diameter controls the solder volume by controlling the volume of the solder paste in opening 230B). - In
FIG. 16B , only oneconductive line 910 extends fromcontact pad 350, butmany lines 910 can extend from the contact pad. The width W1 (20-30 μm in some embodiments) ofline 910 is shown as smaller than the diameter ofpad 350, but this is not necessary. W1 can be any number, with any relationship between W1 andpad 350. Also, the invention is not limited to the circular shapes ofpad 350 andopening 210B. Any shapes can be employed. - In
FIG. 17 ,contact pad 350 includes two conductive layers 910.1, 910.2. The bottom layer 910.1 covers the whole bottom of opening 230B, and the top layer 910.2 covers only a portion of the bottom of opening 230B. Bottom layer 910.1 is less solder wettable than the top layer 910.2. In still other embodiments, bottom layer 910.1 does not cover the whole bottom of opening 230B, and the top layer 910.2 covers a smaller portion of the bottom of opening 230B than the top layer 910.1. -
FIGS. 18, 19 illustrate possible shapes ofsolder 930 in the embodiments ofFIGS. 16A, 16B , 17 after the solder reflow before the attachment ofinterposer 120 to the BT substrate. The solder shape is an approximation; the solder is assumed to wet only thepad 350, ignoring theline 910 extending from the pad (seeFIG. 16B ). It is assumed that the solder shape is a sphere truncated at the bottom, of some diameter Ds. Symbol Hs denotes the solder ball height abovecontact pad 350. Hc is the depth ofcavity 210B. Db is the diameter ofpad 350. Dc is the diameter ofcavity 210B (shown as Dcav inFIG. 9 ). - Assuming the solder paste filled the cavity before the solder reflow, and ignoring the thickness of
pad 350, the solder paste volume Vc was the cavity volume, i.e.:
Vc=π*Dc 2 *Hc/4 (1) - We will assume that the solder paste was half solder and half flux. After the reflow, the solder volume Vs is therefore one half of Vc, i.e.
Vs=π*Dc 2 *Hc/8 (2) - Also, Vs is the volume of the truncated solder sphere, and therefore:
Vs=π*Ds 3/6−π*(3*Db 2+4*h 2)*h/24 (3)
where h=Ds−Hs. - From (2) and (3) we obtain:
4*Ds 3−(3*Db 2+4*h 2)*h=3*Dc 2 *Hc (4)
where
Ds=(4*h 2 +Db 2)/(4*h) (5)
and, as noted above,
Hs=Ds−h (6) - Example: suppose Dc=150 μm, Hc=50 μm, Db=80 μm. From equation (4):
h=20.57 μm - From equation (5):
Ds=98.35 μm - From equation (6):
Hs=77.78 μm - Other examples are given in the following Table 2 for Dc=150 μm. The dimensions are in micrometers. Tilda (“˜”) denotes approximation.
TABLE 2 Db Ds Hs Solder Profile in FIG. 19 65 ˜96 ˜83 930A 80 ˜98 ˜78 930B 100 ˜105 ˜69 930C 150 ˜170 ˜45 930D - The invention is not limited to the embodiments described above. For example, non-eutectic solders can be used. The “melting temperature” is any temperature as high or higher than the solidus and but not higher than the liquidus. As is known, the solidus is the highest temperature at which 100% of the solder is solid, i.e. the solder is just beginning to melt. The liquidus is the lowest temperature at which 100% of the solder is liquid. For a eutectic solder, the solidus and the liquidus are the same.
- Also, in some embodiments, the
cavities 210B (FIG. 9 ) extend through two or more BT layers, for example, through layers 110.3 and 110.2. Contactpads 350 can thus be formed from themetal layer 910 located between the BT layers 110.1, 110.2. Thelayer 910 on BT layer 110.2 can be used for interconnects, power or ground planes, or other elements as discussed above. The invention is not limited to particular materials, dimensions and processes. For example, anisotropic adhesive, conductive epoxy, and/or thermocompression can be used instead of solder.Bumps 150 orcontacts 340, 340.0, 340.1, 340.2 may include a solder layer. For example, they may include copper pillars with solder thereon, or they can be solder bumps. The invention is applicable to non-silicon semiconductor integrated circuits. The integrated circuits can be entire wafers or dice obtained by dicing the wafers. - The interposer may include capacitors having a capacitance of 5.0 pF or higher. For example, capacitance values of 10 pF, 100 pF, or higher have been used on circuit boards to decouple the power lines from the ground lines or for other purposes, and such capacitors can be manufactured in the interposer. Resistors having resistance values of 10 Ω and higher (e.g. 50 Ω, 100 Ω, or 150 Ω) are used on circuit boards for line termination and other purposes, and they can be manufactured in the interposer. Inductors having inductance values of 100 nH or higher are commonly used on circuit boards and can be manufactured in the interposer. The invention is not limited to particular capacitance, resistance or inductance values. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
Claims (26)
1. A structure comprising:
(1) a first integrated circuit structure comprising:
a semiconductor substrate;
one or more first conductive contact pads protruding out at a surface of the first integrated circuit structure;
(2) a first substrate comprising a circuit which comprises one or more first conductive contact pads, wherein at least a portion of each of the one or more first contact pads of the first substrate is located in a corresponding via in a surface of the first substrate;
wherein the protruding first contact pads of the first integrated circuit structure are inserted into the corresponding vias of the first substrate and attached to the first contact pads of the first substrate;
wherein each first contact pad of the first integrated circuit structure has a non-solder portion inside the corresponding via.
2. The structure of claim 1 wherein the first contact pads of the first integrated circuit structure are attached to the first contact pads of the first substrate with solder.
3. The structure of claim 1 wherein the first contact pads of the first integrated circuit structure are attached to the first contact pads of the first substrate without solder with thermal or thermosonic compression.
4. The structure of claim 1 wherein the non-solder portions of the protruding first contact pads of the first integrated circuit structure are made of copper and/or gold and/or nickel.
5. The structure of claim 1 wherein the first substrate comprises a semiconductor substrate.
6. The structure of claim 1 wherein the first substrate is an integrated circuit packaging substrate which does not comprise a semiconductor substrate.
7. The structure of claim 1 wherein the first substrate is a printed circuit board.
8. The structure of claim 1 wherein a spacing between the bottom surface of the semiconductor substrate and the top surface of the first substrate is at least 5 μm.
9. The structure of claim 1 wherein at least a portion of the bottom surface of the semiconductor substrate is not covered by any dielectric layer in the first integrated circuit structure.
10. The structure of claim 1 wherein at least a portion of the bottom surface of the semiconductor substrate is covered by a dielectric in the first integrated circuit structure.
11. The structure of claim 1 wherein at least 10 μm of each protruding first contact pad is inside the corresponding via.
12. The structure of claim 1 wherein the first integrated circuit structure is an interposer that comprises no transistors and no diodes.
13. The structure of claim 1 wherein the first integrated circuit structure comprises a transistor or a diode, the transistor or the diode having a semiconductor region in the semiconductor substrate.
14. The structure of claim 1 wherein each first contact pad of the first substrate covers a bottom and sidewalls of the corresponding via.
15. The structure of claim 1 further comprising:
(4) a second integrated circuit structure comprising:
a semiconductor substrate;
one or more first conductive contact pads protruding out at a surface of the second integrated circuit structure;
wherein the first integrated circuit structure further comprises one or more second conductive contact pads, wherein at least a portion of each of the one or more second contact pads of the first integrated circuit structure is located in a corresponding via in a surface of the first integrated circuit structure;
wherein the protruding first contact pads of the second integrated circuit structure are inserted into the corresponding vias of the first integrated circuit structure and attached to the second contact pads of the first integrated circuit structure;
wherein each first contact pad of the second integrated circuit structure has a non-solder portion inside the corresponding via of the first integrated circuit structure.
16. The structure of claim 1 wherein the first contact pads of the first integrated circuit structure are located on a first side of the first integrated circuit structure, and the second contact pads of the first integrated circuit structure are located on a second side of the first integrated circuit structure, the first side being opposite to the first side.
17. The structure of claim 1 wherein each first contact pad of the first integrated circuit structure is provided by a conductor formed in a corresponding through via in the semiconductor substrate and protruding out of the through via.
18. The structure of claim 17 wherein the first contact pads of the first integrated circuit structure protrude out at the surface which is opposite to an active surface of the first integrated circuit structure.
19. A first substrate comprising:
one or more conductive contact pads for attachment to circuitry; and
a dielectric having one or more openings over the one or more contact pads;
wherein a surface of at least one of the openings has a first portion which is a surface portion of one of the contact pads, and a second portion made from a different material than the first portion.
20. The first substrate of claim 19 wherein the second portion of the bottom of said one of the openings is less solder wettable than the first portion.
21. The first substrate of claim 19 wherein the second portion is dielectric.
22. The first substrate of claim 19 in combination with solder at least on the first portion.
23. The first substrate of claim 19 in combination with a second substrate having a contact pad soldered to said one of the contact pads of the first substrate with solder on the first portion.
24. The combination of claim 23 wherein the second substrate is a semiconductor integrated circuit.
25. The first substrate of claim 19 wherein the first substrate is a semiconductor integrated circuit packaging substrate that does not include a semiconductor substrate.
26. The first substrate of claim 19 wherein the firs substrate is a semiconductor integrated circuit.
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US11/253,490 US20060076661A1 (en) | 2003-12-17 | 2005-10-19 | Attachment of integrated circuit structures and other substrates to substrates with vias |
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US11/136,799 Abandoned US20050212127A1 (en) | 2003-12-17 | 2005-05-24 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
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US11/253,943 Expired - Lifetime US7186586B2 (en) | 2003-12-17 | 2005-10-19 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
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US10/798,540 Expired - Lifetime US7241675B2 (en) | 2003-12-17 | 2004-03-10 | Attachment of integrated circuit structures and other substrates to substrates with vias |
US11/136,799 Abandoned US20050212127A1 (en) | 2003-12-17 | 2005-05-24 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
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US11/253,943 Expired - Lifetime US7186586B2 (en) | 2003-12-17 | 2005-10-19 | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090035940A1 (en) * | 2007-08-02 | 2009-02-05 | Enthone Inc. | Copper metallization of through silicon via |
US20090065894A1 (en) * | 2004-03-31 | 2009-03-12 | Makoto Ishida | Electronic circuit device having silicon substrate |
US20090278238A1 (en) * | 2008-05-12 | 2009-11-12 | Texas Instruments Inc | Tsvs having chemically exposed tsv tips for integrated circuit devices |
US20110085314A1 (en) * | 2007-08-16 | 2011-04-14 | Michael Franz | Electrical circuit system and method for producing an electrical circuit system |
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Publication number | Priority date | Publication date | Assignee | Title |
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US20070045844A1 (en) | 2005-08-24 | 2007-03-01 | Andry Paul S | Alpha particle shields in chip packaging |
US7863187B2 (en) | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
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US8368165B2 (en) | 2005-10-20 | 2013-02-05 | Siliconix Technology C. V. | Silicon carbide Schottky diode |
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US7462509B2 (en) * | 2006-05-16 | 2008-12-09 | International Business Machines Corporation | Dual-sided chip attached modules |
AT9551U1 (en) * | 2006-05-16 | 2007-11-15 | Austria Tech & System Tech | METHOD FOR FIXING AN ELECTRONIC COMPONENT ON A PCB AND A SYSTEM CONSISTING OF A PCB AND AT LEAST ONE ELECTRONIC COMPONENT |
US8067840B2 (en) * | 2006-06-20 | 2011-11-29 | Nxp B.V. | Power amplifier assembly |
US20080012099A1 (en) * | 2006-07-11 | 2008-01-17 | Shing Yeh | Electronic assembly and manufacturing method having a reduced need for wire bonds |
KR101193453B1 (en) | 2006-07-31 | 2012-10-24 | 비쉐이-실리코닉스 | Molybdenum barrier metal for sic schottky diode and process of manufacture |
US7473577B2 (en) * | 2006-08-11 | 2009-01-06 | International Business Machines Corporation | Integrated chip carrier with compliant interconnect |
US8021981B2 (en) | 2006-08-30 | 2011-09-20 | Micron Technology, Inc. | Redistribution layers for microfeature workpieces, and associated systems and methods |
JP2008084959A (en) * | 2006-09-26 | 2008-04-10 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
US8513789B2 (en) | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
US7829438B2 (en) | 2006-10-10 | 2010-11-09 | Tessera, Inc. | Edge connect wafer level stacking |
US7759166B2 (en) * | 2006-10-17 | 2010-07-20 | Tessera, Inc. | Microelectronic packages fabricated at the wafer level and methods therefor |
US20080131996A1 (en) * | 2006-12-05 | 2008-06-05 | Gene Wu | Reverse build-up process for fine bump pitch approach |
US20080136038A1 (en) * | 2006-12-06 | 2008-06-12 | Sergey Savastiouk | Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate |
US7952195B2 (en) | 2006-12-28 | 2011-05-31 | Tessera, Inc. | Stacked packages with bridging traces |
US20080217183A1 (en) * | 2007-03-09 | 2008-09-11 | Sriram Muthukumar | Electropolishing metal features on a semiconductor wafer |
US20080242003A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Integrated circuit devices with integral heat sinks |
FR2914460B1 (en) * | 2007-03-30 | 2009-08-21 | Oberthur Card Syst Sa | THIN ELECTRONIC MODULE FOR MICROCIRCUIT BOARD. |
US7528492B2 (en) * | 2007-05-24 | 2009-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test patterns for detecting misalignment of through-wafer vias |
US8476735B2 (en) | 2007-05-29 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Programmable semiconductor interposer for electronic package and method of forming |
US7841080B2 (en) * | 2007-05-30 | 2010-11-30 | Intel Corporation | Multi-chip packaging using an interposer with through-vias |
US8067814B2 (en) * | 2007-06-01 | 2011-11-29 | Panasonic Corporation | Semiconductor device and method of manufacturing the same |
US7982137B2 (en) * | 2007-06-27 | 2011-07-19 | Hamilton Sundstrand Corporation | Circuit board with an attached die and intermediate interposer |
US7939941B2 (en) | 2007-06-27 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of through via before contact processing |
US7825517B2 (en) | 2007-07-16 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for packaging semiconductor dies having through-silicon vias |
EP2186134A2 (en) | 2007-07-27 | 2010-05-19 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
WO2009020572A2 (en) | 2007-08-03 | 2009-02-12 | Tessera Technologies Hungary Kft. | Stack packages using reconstituted wafers |
US8455766B2 (en) * | 2007-08-08 | 2013-06-04 | Ibiden Co., Ltd. | Substrate with low-elasticity layer and low-thermal-expansion layer |
US8043895B2 (en) | 2007-08-09 | 2011-10-25 | Tessera, Inc. | Method of fabricating stacked assembly including plurality of stacked microelectronic elements |
US9398453B2 (en) * | 2007-08-17 | 2016-07-19 | Qualcomm Incorporated | Ad hoc service provider's ability to provide service for a wireless network |
US7973413B2 (en) | 2007-08-24 | 2011-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate via for semiconductor device |
US7888257B2 (en) * | 2007-10-10 | 2011-02-15 | Agere Systems Inc. | Integrated circuit package including wire bonds |
US8476769B2 (en) * | 2007-10-17 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon vias and methods for forming the same |
WO2009058143A1 (en) * | 2007-10-31 | 2009-05-07 | Agere Systems Inc. | Bond pad support structure for semiconductor device |
US8227902B2 (en) | 2007-11-26 | 2012-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structures for preventing cross-talk between through-silicon vias and integrated circuits |
US7588993B2 (en) * | 2007-12-06 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment for backside illumination sensor |
US8304909B2 (en) * | 2007-12-19 | 2012-11-06 | Intel Corporation | IC solder reflow method and materials |
US8399973B2 (en) * | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
US7843064B2 (en) | 2007-12-21 | 2010-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and process for the formation of TSVs |
US8671476B2 (en) * | 2008-02-05 | 2014-03-18 | Standard Textile Co., Inc. | Woven contoured bed sheet with elastomeric yarns |
US7898063B2 (en) * | 2008-02-16 | 2011-03-01 | International Business Machines Corporation | Through substrate annular via including plug filler |
US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
US20090212438A1 (en) * | 2008-02-26 | 2009-08-27 | Franz Kreupl | Integrated circuit device comprising conductive vias and method of making the same |
US8247267B2 (en) * | 2008-03-11 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level IC assembly method |
US7880293B2 (en) * | 2008-03-25 | 2011-02-01 | Stats Chippac, Ltd. | Wafer integrated with permanent carrier and method therefor |
KR101052870B1 (en) * | 2008-04-21 | 2011-07-29 | 주식회사 하이닉스반도체 | A laminated semiconductor package having a through electrode, a circuit board having the same, a semiconductor package having the same, and a semiconductor package |
US8853830B2 (en) | 2008-05-14 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | System, structure, and method of manufacturing a semiconductor substrate stack |
US8395902B2 (en) * | 2008-05-21 | 2013-03-12 | International Business Machines Corporation | Modular chip stack and packaging technology with voltage segmentation, regulation, integrated decoupling capacitance and cooling structure and process |
US8018738B2 (en) * | 2008-06-02 | 2011-09-13 | Oracle America, Inc., | Voltage regulator attach for high current chip applications |
US7745920B2 (en) | 2008-06-10 | 2010-06-29 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
WO2009154761A1 (en) | 2008-06-16 | 2009-12-23 | Tessera Research Llc | Stacking of wafer-level chip scale packages having edge contacts |
US8288872B2 (en) * | 2008-08-05 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via layout |
US8399273B2 (en) | 2008-08-18 | 2013-03-19 | Tsmc Solid State Lighting Ltd. | Light-emitting diode with current-spreading region |
US8932906B2 (en) | 2008-08-19 | 2015-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via bonding structure |
US20100062693A1 (en) * | 2008-09-05 | 2010-03-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Two step method and apparatus for polishing metal and other films in semiconductor manufacturing |
US8278152B2 (en) * | 2008-09-08 | 2012-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding process for CMOS image sensor |
US9524945B2 (en) | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
US7820485B2 (en) * | 2008-09-29 | 2010-10-26 | Freescale Semiconductor, Inc. | Method of forming a package with exposed component surfaces |
US8415203B2 (en) * | 2008-09-29 | 2013-04-09 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package including two devices |
KR20100037300A (en) * | 2008-10-01 | 2010-04-09 | 삼성전자주식회사 | Method of forming semiconductor device having embedded interposer |
US8653648B2 (en) * | 2008-10-03 | 2014-02-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Zigzag pattern for TSV copper adhesion |
US7928534B2 (en) | 2008-10-09 | 2011-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad connection to redistribution lines having tapered profiles |
US8030780B2 (en) | 2008-10-16 | 2011-10-04 | Micron Technology, Inc. | Semiconductor substrates with unitary vias and via terminals, and associated systems and methods |
US8097953B2 (en) * | 2008-10-28 | 2012-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit stacking-joint interface structure |
US8624360B2 (en) | 2008-11-13 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling channels in 3DIC stacks |
US8158456B2 (en) * | 2008-12-05 | 2012-04-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming stacked dies |
US7989318B2 (en) | 2008-12-08 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking semiconductor dies |
US8513119B2 (en) * | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
US8736050B2 (en) * | 2009-09-03 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Front side copper post joint structure for temporary bond in TSV application |
TW201025462A (en) | 2008-12-17 | 2010-07-01 | United Test Ct Inc | Semiconductor device and method for fabricating the same |
US8264077B2 (en) * | 2008-12-29 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chips |
US7910473B2 (en) * | 2008-12-31 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with air gap |
US20100171197A1 (en) | 2009-01-05 | 2010-07-08 | Hung-Pin Chang | Isolation Structure for Stacked Dies |
US8749027B2 (en) * | 2009-01-07 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust TSV structure |
US8399354B2 (en) | 2009-01-13 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US8501587B2 (en) | 2009-01-13 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked integrated chips and methods of fabrication thereof |
US8168529B2 (en) | 2009-01-26 | 2012-05-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming seal ring in an integrated circuit die |
US8314483B2 (en) | 2009-01-26 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | On-chip heat spreader |
US8820728B2 (en) * | 2009-02-02 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor wafer carrier |
US8704375B2 (en) * | 2009-02-04 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier structures and methods for through substrate vias |
US7932608B2 (en) * | 2009-02-24 | 2011-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via formed with a post passivation interconnect structure |
US9142586B2 (en) | 2009-02-24 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for backside illuminated image sensor |
US8531565B2 (en) * | 2009-02-24 | 2013-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Front side implanted guard ring structure for backside illuminated image sensor |
JP4833307B2 (en) * | 2009-02-24 | 2011-12-07 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor module, terminal plate, method for manufacturing terminal plate, and method for manufacturing semiconductor module |
US7894230B2 (en) | 2009-02-24 | 2011-02-22 | Mosaid Technologies Incorporated | Stacked semiconductor devices including a master device |
KR20100096879A (en) * | 2009-02-25 | 2010-09-02 | 삼성전자주식회사 | Devices including copper pads, stacked structures thereof and methods of manufacturing the same |
US8643149B2 (en) * | 2009-03-03 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress barrier structures for semiconductor chips |
US9299648B2 (en) * | 2009-03-04 | 2016-03-29 | Stats Chippac Ltd. | Integrated circuit packaging system with patterned substrate and method of manufacture thereof |
US8067306B2 (en) | 2010-02-26 | 2011-11-29 | Stats Chippac Ltd. | Integrated circuit packaging system with exposed conductor and method of manufacture thereof |
US8487444B2 (en) * | 2009-03-06 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional system-in-package architecture |
CN102422412A (en) | 2009-03-13 | 2012-04-18 | 德塞拉股份有限公司 | Stacked microelectronic assemblies having vias extending through bond pads |
US8344513B2 (en) | 2009-03-23 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier for through-silicon via |
US8531015B2 (en) * | 2009-03-26 | 2013-09-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming a thin wafer without a carrier |
US8232140B2 (en) | 2009-03-27 | 2012-07-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for ultra thin wafer handling and processing |
US8329578B2 (en) * | 2009-03-27 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via structure and via etching process of forming the same |
US8829355B2 (en) * | 2009-03-27 | 2014-09-09 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US8552563B2 (en) | 2009-04-07 | 2013-10-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional semiconductor architecture |
US8691664B2 (en) * | 2009-04-20 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside process for a substrate |
US8263492B2 (en) | 2009-04-29 | 2012-09-11 | International Business Machines Corporation | Through substrate vias |
US8759949B2 (en) * | 2009-04-30 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside structures having copper pillars |
US8432038B2 (en) | 2009-06-12 | 2013-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via structure and a process for forming the same |
US8689437B2 (en) * | 2009-06-24 | 2014-04-08 | International Business Machines Corporation | Method for forming integrated circuit assembly |
US8158489B2 (en) * | 2009-06-26 | 2012-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of TSV backside interconnects by modifying carrier wafers |
US9305769B2 (en) | 2009-06-30 | 2016-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thin wafer handling method |
US8871609B2 (en) * | 2009-06-30 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thin wafer handling structure and method |
US8247906B2 (en) | 2009-07-06 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Supplying power to integrated circuits using a grid matrix formed of through-silicon vias |
US8264066B2 (en) * | 2009-07-08 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Liner formation in 3DIC structures |
US8377816B2 (en) * | 2009-07-30 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming electrical connections |
US8841766B2 (en) | 2009-07-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
US8859424B2 (en) | 2009-08-14 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor wafer carrier and method of manufacturing |
US8048794B2 (en) * | 2009-08-18 | 2011-11-01 | International Business Machines Corporation | 3D silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport |
US8344512B2 (en) * | 2009-08-20 | 2013-01-01 | International Business Machines Corporation | Three-dimensional silicon interposer for low voltage low power systems |
US8324738B2 (en) | 2009-09-01 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned protection layer for copper post structure |
US8252665B2 (en) | 2009-09-14 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection layer for adhesive material at wafer edge |
US8791549B2 (en) * | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
CN102033877A (en) * | 2009-09-27 | 2011-04-27 | 阿里巴巴集团控股有限公司 | Search method and device |
US8647925B2 (en) * | 2009-10-01 | 2014-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface modification for handling wafer thinning process |
US8264067B2 (en) * | 2009-10-09 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via (TSV) wire bond architecture |
US7969013B2 (en) * | 2009-10-22 | 2011-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via with dummy structure and method for forming the same |
KR101585216B1 (en) * | 2009-10-28 | 2016-01-13 | 삼성전자주식회사 | Semiconductor chip and wafer stack package using the same and method of manufacturing the same |
US8659155B2 (en) * | 2009-11-05 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps |
US8283745B2 (en) | 2009-11-06 | 2012-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating backside-illuminated image sensor |
US8405201B2 (en) * | 2009-11-09 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via structure |
TWI470749B (en) * | 2009-12-23 | 2015-01-21 | Ind Tech Res Inst | Thermal conductive and electrical insulation complex film and chip package structure utilizing the same |
EP2339627A1 (en) * | 2009-12-24 | 2011-06-29 | Imec | Window interposed die packaging |
US10297550B2 (en) * | 2010-02-05 | 2019-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC architecture with interposer and interconnect structure for bonding dies |
US8610270B2 (en) * | 2010-02-09 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and semiconductor assembly with lead-free solder |
US8252682B2 (en) * | 2010-02-12 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for thinning a wafer |
US8237272B2 (en) * | 2010-02-16 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pillar structure for semiconductor substrate and method of manufacture |
US8390009B2 (en) * | 2010-02-16 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-emitting diode (LED) package systems |
US8466059B2 (en) | 2010-03-30 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer interconnect structure for stacked dies |
US8222139B2 (en) | 2010-03-30 | 2012-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously |
US8507940B2 (en) | 2010-04-05 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat dissipation by through silicon plugs |
US8174124B2 (en) | 2010-04-08 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dummy pattern in wafer backside routing |
US8455995B2 (en) | 2010-04-16 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSVs with different sizes in interposers for bonding dies |
US9293366B2 (en) | 2010-04-28 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias with improved connections |
US8519538B2 (en) | 2010-04-28 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Laser etch via formation |
US8441124B2 (en) | 2010-04-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
US8674513B2 (en) * | 2010-05-13 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures for substrate |
US8866301B2 (en) | 2010-05-18 | 2014-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers with interconnection structures |
TWI572750B (en) | 2010-05-24 | 2017-03-01 | 安頌股份有限公司 | Copper filling of through silicon vias |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8471358B2 (en) | 2010-06-01 | 2013-06-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D inductor and transformer |
US9059026B2 (en) | 2010-06-01 | 2015-06-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3-D inductor and transformer |
US9018758B2 (en) | 2010-06-02 | 2015-04-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall spacer and metal top cap |
US8362591B2 (en) | 2010-06-08 | 2013-01-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuits and methods of forming the same |
KR101078745B1 (en) * | 2010-06-09 | 2011-11-02 | 주식회사 하이닉스반도체 | Semiconductor chip and method for manuafacturing of the same |
US8411459B2 (en) | 2010-06-10 | 2013-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd | Interposer-on-glass package structures |
US8500182B2 (en) | 2010-06-17 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vacuum wafer carriers for strengthening thin wafers |
US8896136B2 (en) | 2010-06-30 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark and method of formation |
US8319336B2 (en) | 2010-07-08 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of etch microloading for through silicon vias |
US8338939B2 (en) | 2010-07-12 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV formation processes using TSV-last approach |
US8999179B2 (en) | 2010-07-13 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive vias in a substrate |
CN102202827A (en) * | 2010-07-20 | 2011-09-28 | 联发软件设计(深圳)有限公司 | A tin pre-coating method used for a multicolumn quad flat no-lead chip and a rework method |
US8722540B2 (en) | 2010-07-22 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling defects in thin wafer handling |
US8598695B2 (en) | 2010-07-23 | 2013-12-03 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
US9299594B2 (en) | 2010-07-27 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate bonding system and method of modifying the same |
US8674510B2 (en) | 2010-07-29 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional integrated circuit structure having improved power and thermal management |
US8846499B2 (en) | 2010-08-17 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite carrier structure |
US8546254B2 (en) | 2010-08-19 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming copper pillar bumps using patterned anodes |
US8507358B2 (en) | 2010-08-27 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite wafer semiconductor |
US8693163B2 (en) | 2010-09-01 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cylindrical embedded capacitors |
US8928159B2 (en) | 2010-09-02 | 2015-01-06 | Taiwan Semiconductor Manufacturing & Company, Ltd. | Alignment marks in substrate having through-substrate via (TSV) |
US8502338B2 (en) | 2010-09-09 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate via waveguides |
US8039385B1 (en) * | 2010-09-13 | 2011-10-18 | Texas Instruments Incorporated | IC devices having TSVS including protruding tips having IMC blocking tip ends |
US8928127B2 (en) | 2010-09-24 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Noise decoupling structure with through-substrate vias |
US8525343B2 (en) | 2010-09-28 | 2013-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device with through-silicon via (TSV) and method of forming the same |
US9190325B2 (en) | 2010-09-30 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV formation |
US8572840B2 (en) * | 2010-09-30 | 2013-11-05 | International Business Machines Corporation | Method of attaching an electronic module power supply |
US8580682B2 (en) | 2010-09-30 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cost-effective TSV formation |
US8466553B2 (en) * | 2010-10-12 | 2013-06-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package having the same |
US8836116B2 (en) | 2010-10-21 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level packaging of micro-electro-mechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) substrates |
US8519409B2 (en) | 2010-11-15 | 2013-08-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light emitting diode components integrated with thermoelectric devices |
US8567837B2 (en) | 2010-11-24 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reconfigurable guide pin design for centering wafers having different sizes |
JP2012119601A (en) * | 2010-12-03 | 2012-06-21 | Nec Corp | Interposer and semiconductor device |
US9153462B2 (en) | 2010-12-09 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spin chuck for thin wafer cleaning |
US8773866B2 (en) | 2010-12-10 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Radio-frequency packaging with reduced RF loss |
TWI445155B (en) * | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | Stacked semiconductor package and method for making the same |
US20120175772A1 (en) * | 2011-01-07 | 2012-07-12 | Leung Andrew K | Alternative surface finishes for flip-chip ball grid arrays |
US8236584B1 (en) | 2011-02-11 | 2012-08-07 | Tsmc Solid State Lighting Ltd. | Method of forming a light emitting diode emitter substrate with highly reflective metal bonding |
US9059262B2 (en) | 2011-02-24 | 2015-06-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits including conductive structures through a substrate and methods of making the same |
KR101780423B1 (en) * | 2011-03-18 | 2017-09-22 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
US8823133B2 (en) | 2011-03-29 | 2014-09-02 | Xilinx, Inc. | Interposer having an inductor |
US8487410B2 (en) | 2011-04-13 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon vias for semicondcutor substrate and method of manufacture |
US8716128B2 (en) | 2011-04-14 | 2014-05-06 | Tsmc Solid State Lighting Ltd. | Methods of forming through silicon via openings |
US8546235B2 (en) | 2011-05-05 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits including metal-insulator-metal capacitors and methods of forming the same |
US8803269B2 (en) | 2011-05-05 | 2014-08-12 | Cisco Technology, Inc. | Wafer scale packaging platform for transceivers |
US8481425B2 (en) | 2011-05-16 | 2013-07-09 | United Microelectronics Corp. | Method for fabricating through-silicon via structure |
US8674883B2 (en) | 2011-05-24 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Antenna using through-silicon via |
US8900994B2 (en) | 2011-06-09 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for producing a protective structure |
US8587127B2 (en) | 2011-06-15 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods of forming the same |
US8552485B2 (en) | 2011-06-15 | 2013-10-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having metal-insulator-metal capacitor structure |
US8822336B2 (en) | 2011-06-16 | 2014-09-02 | United Microelectronics Corp. | Through-silicon via forming method |
JP5808586B2 (en) * | 2011-06-21 | 2015-11-10 | 新光電気工業株式会社 | Manufacturing method of interposer |
US8766409B2 (en) | 2011-06-24 | 2014-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and structure for through-silicon via (TSV) with diffused isolation well |
US8531035B2 (en) | 2011-07-01 | 2013-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect barrier structure and method |
US8828745B2 (en) | 2011-07-06 | 2014-09-09 | United Microelectronics Corp. | Method for manufacturing through-silicon via |
US8872345B2 (en) | 2011-07-07 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming grounded through-silicon vias in a semiconductor substrate |
US8525168B2 (en) * | 2011-07-11 | 2013-09-03 | International Business Machines Corporation | Integrated circuit (IC) test probe |
US9406738B2 (en) | 2011-07-20 | 2016-08-02 | Xilinx, Inc. | Inductive structure formed using through silicon vias |
US8604491B2 (en) | 2011-07-21 | 2013-12-10 | Tsmc Solid State Lighting Ltd. | Wafer level photonic device die structure and method of making the same |
US8445296B2 (en) | 2011-07-22 | 2013-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for end point determination in reactive ion etching |
US8691691B2 (en) | 2011-07-29 | 2014-04-08 | International Business Machines Corporation | TSV pillar as an interconnecting structure |
US8809073B2 (en) | 2011-08-03 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for de-embedding through substrate vias |
US9159907B2 (en) | 2011-08-04 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid film for protecting MTJ stacks of MRAM |
US8748284B2 (en) | 2011-08-12 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing decoupling MIM capacitor designs for interposers |
US8525278B2 (en) | 2011-08-19 | 2013-09-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | MEMS device having chip scale packaging |
US8546886B2 (en) | 2011-08-24 | 2013-10-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling the device performance by forming a stressed backside dielectric layer |
US8604619B2 (en) | 2011-08-31 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via keep out zone formation along different crystal orientations |
KR20130032724A (en) * | 2011-09-23 | 2013-04-02 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
US20130075268A1 (en) * | 2011-09-28 | 2013-03-28 | Micron Technology, Inc. | Methods of Forming Through-Substrate Vias |
KR20130037609A (en) * | 2011-10-06 | 2013-04-16 | 한국전자통신연구원 | Silicon interpower including backside inductor |
US8803322B2 (en) | 2011-10-13 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through substrate via structures and methods of forming the same |
US8659126B2 (en) | 2011-12-07 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit ground shielding structure |
US9087838B2 (en) | 2011-10-25 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for a high-K transformer with capacitive coupling |
US8610247B2 (en) | 2011-12-30 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for a transformer with magnetic features |
US11127664B2 (en) | 2011-10-31 | 2021-09-21 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
US8896089B2 (en) | 2011-11-09 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposers for semiconductor devices and methods of manufacture thereof |
US11264262B2 (en) | 2011-11-29 | 2022-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer debonding and cleaning apparatus |
US9390949B2 (en) | 2011-11-29 | 2016-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer debonding and cleaning apparatus and method of use |
US10381254B2 (en) | 2011-11-29 | 2019-08-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer debonding and cleaning apparatus and method |
US8803316B2 (en) | 2011-12-06 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV structures and methods for forming the same |
US8546953B2 (en) | 2011-12-13 | 2013-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit |
US8890293B2 (en) | 2011-12-16 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Guard ring for through vias |
US9330823B1 (en) * | 2011-12-19 | 2016-05-03 | Xilinx, Inc. | Integrated circuit structure with inductor in silicon interposer |
US8580647B2 (en) | 2011-12-19 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductors with through VIAS |
US9607937B2 (en) | 2011-12-19 | 2017-03-28 | Intel Corporation | Pin grid interposer |
US8518823B2 (en) | 2011-12-23 | 2013-08-27 | United Microelectronics Corp. | Through silicon via and method of forming the same |
US8716859B2 (en) * | 2012-01-10 | 2014-05-06 | Intel Mobile Communications GmbH | Enhanced flip chip package |
US8757897B2 (en) | 2012-01-10 | 2014-06-24 | Invensas Corporation | Optical interposer |
US9323010B2 (en) | 2012-01-10 | 2016-04-26 | Invensas Corporation | Structures formed using monocrystalline silicon and/or other materials for optical and other applications |
US8609529B2 (en) | 2012-02-01 | 2013-12-17 | United Microelectronics Corp. | Fabrication method and structure of through silicon via |
US8618631B2 (en) | 2012-02-14 | 2013-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | On-chip ferrite bead inductor |
US9618712B2 (en) | 2012-02-23 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optical bench on substrate and method of making the same |
US10180547B2 (en) | 2012-02-23 | 2019-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optical bench on substrate |
US9293521B2 (en) | 2012-03-02 | 2016-03-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Concentric capacitor structure |
US8860114B2 (en) | 2012-03-02 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for a fishbone differential capacitor |
US9337138B1 (en) | 2012-03-09 | 2016-05-10 | Xilinx, Inc. | Capacitors within an interposer coupled to supply and ground planes of a substrate |
US9312432B2 (en) | 2012-03-13 | 2016-04-12 | Tsmc Solid State Lighting Ltd. | Growing an improved P-GaN layer of an LED through pressure ramping |
US9105628B1 (en) | 2012-03-29 | 2015-08-11 | Valery Dubin | Through substrate via (TSuV) structures and method of making the same |
US9139420B2 (en) | 2012-04-18 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | MEMS device structure and methods of forming same |
US8691600B2 (en) | 2012-05-02 | 2014-04-08 | United Microelectronics Corp. | Method for testing through-silicon-via (TSV) structures |
US9583365B2 (en) | 2012-05-25 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming interconnects for three dimensional integrated circuit |
US8691688B2 (en) | 2012-06-18 | 2014-04-08 | United Microelectronics Corp. | Method of manufacturing semiconductor structure |
US9275933B2 (en) | 2012-06-19 | 2016-03-01 | United Microelectronics Corp. | Semiconductor device |
US8900996B2 (en) | 2012-06-21 | 2014-12-02 | United Microelectronics Corp. | Through silicon via structure and method of fabricating the same |
US8525296B1 (en) | 2012-06-26 | 2013-09-03 | United Microelectronics Corp. | Capacitor structure and method of forming the same |
US8759210B2 (en) | 2012-07-19 | 2014-06-24 | International Business Machines Corporation | Control of silver in C4 metallurgy with plating process |
US8742578B2 (en) | 2012-07-19 | 2014-06-03 | International Business Machines Corporation | Solder volume compensation with C4 process |
US9006101B2 (en) * | 2012-08-31 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
US9343442B2 (en) | 2012-09-20 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Passive devices in package-on-package structures and methods for forming the same |
KR101366552B1 (en) * | 2012-09-20 | 2014-02-26 | 주식회사 동부하이텍 | A semiconductor device and a method of manufacturing the same |
KR101366554B1 (en) * | 2012-09-20 | 2014-02-26 | 주식회사 동부하이텍 | A semiconductor device and a method of manufacturing the same |
US8912844B2 (en) | 2012-10-09 | 2014-12-16 | United Microelectronics Corp. | Semiconductor structure and method for reducing noise therein |
TWI544599B (en) * | 2012-10-30 | 2016-08-01 | 矽品精密工業股份有限公司 | Fabrication method of package structure |
EP2738827B1 (en) * | 2012-11-29 | 2022-04-06 | IMEC vzw | MIMCAP structure in a semiconductor device package |
US9035457B2 (en) | 2012-11-29 | 2015-05-19 | United Microelectronics Corp. | Substrate with integrated passive devices and method of manufacturing the same |
US9034769B2 (en) * | 2012-12-12 | 2015-05-19 | Micron Technology, Inc. | Methods of selectively removing a substrate material |
US9123780B2 (en) | 2012-12-19 | 2015-09-01 | Invensas Corporation | Method and structures for heat dissipating interposers |
US8716104B1 (en) | 2012-12-20 | 2014-05-06 | United Microelectronics Corp. | Method of fabricating isolation structure |
US10032696B2 (en) | 2012-12-21 | 2018-07-24 | Nvidia Corporation | Chip package using interposer substrate with through-silicon vias |
US9123789B2 (en) | 2013-01-23 | 2015-09-01 | United Microelectronics Corp. | Chip with through silicon via electrode and method of forming the same |
US9484211B2 (en) | 2013-01-24 | 2016-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etchant and etching process |
US9490133B2 (en) | 2013-01-24 | 2016-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etching apparatus |
US9059241B2 (en) * | 2013-01-29 | 2015-06-16 | International Business Machines Corporation | 3D assembly for interposer bow |
US9041152B2 (en) | 2013-03-14 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductor with magnetic material |
US8884398B2 (en) | 2013-04-01 | 2014-11-11 | United Microelectronics Corp. | Anti-fuse structure and programming method thereof |
US9287173B2 (en) | 2013-05-23 | 2016-03-15 | United Microelectronics Corp. | Through silicon via and process thereof |
US9123730B2 (en) | 2013-07-11 | 2015-09-01 | United Microelectronics Corp. | Semiconductor device having through silicon trench shielding structure surrounding RF circuit |
CN104282664B (en) * | 2013-07-12 | 2018-09-04 | 联华电子股份有限公司 | Semiconductor device with shielding construction |
US9449898B2 (en) | 2013-07-31 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having backside interconnect structure through substrate via and method of forming the same |
US9024416B2 (en) | 2013-08-12 | 2015-05-05 | United Microelectronics Corp. | Semiconductor structure |
US8916471B1 (en) | 2013-08-26 | 2014-12-23 | United Microelectronics Corp. | Method for forming semiconductor structure having through silicon via for signal and shielding structure |
US9048223B2 (en) | 2013-09-03 | 2015-06-02 | United Microelectronics Corp. | Package structure having silicon through vias connected to ground potential |
US9117804B2 (en) | 2013-09-13 | 2015-08-25 | United Microelectronics Corporation | Interposer structure and manufacturing method thereof |
US9397051B2 (en) | 2013-12-03 | 2016-07-19 | Invensas Corporation | Warpage reduction in structures with electrical circuitry |
US9343359B2 (en) | 2013-12-25 | 2016-05-17 | United Microelectronics Corp. | Integrated structure and method for fabricating the same |
US20150187714A1 (en) * | 2013-12-26 | 2015-07-02 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits including copper pillar structures and methods for fabricating the same |
US10340203B2 (en) | 2014-02-07 | 2019-07-02 | United Microelectronics Corp. | Semiconductor structure with through silicon via and method for fabricating and testing the same |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US9355997B2 (en) | 2014-03-12 | 2016-05-31 | Invensas Corporation | Integrated circuit assemblies with reinforcement frames, and methods of manufacture |
KR102353651B1 (en) * | 2014-03-24 | 2022-01-21 | 인텔 코포레이션 | A method of forming a through-body via in a semiconductor die and an integrated circuit comprising the through-body via |
US9472518B2 (en) * | 2014-04-04 | 2016-10-18 | Micron Technology, Inc. | Semiconductor structures including carrier wafers and methods of using such semiconductor structures |
WO2015160359A1 (en) * | 2014-04-18 | 2015-10-22 | Halliburton Energy Services, Inc. | High-temperature cycling bga packaging |
US9165793B1 (en) | 2014-05-02 | 2015-10-20 | Invensas Corporation | Making electrical components in handle wafers of integrated circuit packages |
US9741649B2 (en) | 2014-06-04 | 2017-08-22 | Invensas Corporation | Integrated interposer solutions for 2D and 3D IC packaging |
US9412806B2 (en) | 2014-06-13 | 2016-08-09 | Invensas Corporation | Making multilayer 3D capacitors using arrays of upstanding rods or ridges |
US9252127B1 (en) | 2014-07-10 | 2016-02-02 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
TWI660476B (en) * | 2014-07-11 | 2019-05-21 | 矽品精密工業股份有限公司 | Package structure and method of manufacture |
TWI556385B (en) * | 2014-08-07 | 2016-11-01 | 財團法人工業技術研究院 | Semiconductor device, manufacturing method and stacking structure thereof |
US9373564B2 (en) | 2014-08-07 | 2016-06-21 | Industrial Technology Research Institute | Semiconductor device, manufacturing method and stacking structure thereof |
TWI710671B (en) | 2014-09-15 | 2020-11-21 | 美商麥德美樂思公司 | Levelers for copper deposition in microelectronics |
US9496154B2 (en) | 2014-09-16 | 2016-11-15 | Invensas Corporation | Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias |
TWI566305B (en) * | 2014-10-29 | 2017-01-11 | 巨擘科技股份有限公司 | Method for manufacturing three-dimensional integrated circuit |
US9502469B2 (en) * | 2014-10-29 | 2016-11-22 | Qualcomm Incorporated | Electrically reconfigurable interposer with built-in resistive memory |
US9786574B2 (en) * | 2015-05-21 | 2017-10-10 | Globalfoundries Inc. | Thin film based fan out and multi die package platform |
US9478504B1 (en) | 2015-06-19 | 2016-10-25 | Invensas Corporation | Microelectronic assemblies with cavities, and methods of fabrication |
US9780052B2 (en) * | 2015-09-14 | 2017-10-03 | Micron Technology, Inc. | Collars for under-bump metal structures and associated systems and methods |
TWI605544B (en) * | 2015-11-25 | 2017-11-11 | 矽品精密工業股份有限公司 | Substrate structure and method of fabrication |
US9748106B2 (en) * | 2016-01-21 | 2017-08-29 | Micron Technology, Inc. | Method for fabricating semiconductor package |
US9806018B1 (en) * | 2016-06-20 | 2017-10-31 | International Business Machines Corporation | Copper interconnect structures |
US11569176B2 (en) * | 2017-03-21 | 2023-01-31 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and method of manufacturing thereof |
US11101140B2 (en) * | 2017-11-10 | 2021-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
US10381322B1 (en) * | 2018-04-23 | 2019-08-13 | Sandisk Technologies Llc | Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same |
CN108511327B (en) * | 2018-05-09 | 2020-05-22 | 中国电子科技集团公司第三十八研究所 | Manufacturing method of ultrathin silicon adapter plate without temporary bonding |
US10455707B1 (en) | 2018-08-10 | 2019-10-22 | Apple Inc. | Connection pad for embedded components in PCB packaging |
KR102518803B1 (en) * | 2018-10-24 | 2023-04-07 | 삼성전자주식회사 | Semiconductor package |
US11616019B2 (en) * | 2020-12-21 | 2023-03-28 | Nvidia Corp. | Semiconductor assembly |
US11875988B2 (en) | 2021-04-29 | 2024-01-16 | Nxp Usa, Inc. | Substrate pad and die pillar design modifications to enable extreme fine pitch flip chip (FC) joints |
US20230098054A1 (en) * | 2021-09-29 | 2023-03-30 | International Business Machines Corporation | Electronic substrate stacking |
Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4807021A (en) * | 1986-03-10 | 1989-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device having stacking structure |
US5391514A (en) * | 1994-04-19 | 1995-02-21 | International Business Machines Corporation | Low temperature ternary C4 flip chip bonding method |
US5611140A (en) * | 1989-12-18 | 1997-03-18 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
US6163456A (en) * | 1998-01-30 | 2000-12-19 | Taiyo Yuden, Co., Ltd. | Hybrid module and methods for manufacturing and mounting thereof |
US6175158B1 (en) * | 1998-09-08 | 2001-01-16 | Lucent Technologies Inc. | Interposer for recessed flip-chip package |
US20010019178A1 (en) * | 1999-05-18 | 2001-09-06 | International Business Machines Corporation | Method of interconnecting electronic components using a plurality of conductive studs |
US6322903B1 (en) * | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
US20020036340A1 (en) * | 2000-09-27 | 2002-03-28 | Kabushiki Kaisha Toshiba | Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device |
US20020048916A1 (en) * | 1999-03-29 | 2002-04-25 | Toshiharu Yanagida | Thinned, stackable semiconductor device having low profile |
US20020074637A1 (en) * | 2000-12-19 | 2002-06-20 | Intel Corporation | Stacked flip chip assemblies |
US20020175421A1 (en) * | 2001-05-25 | 2002-11-28 | Naoto Kimura | Semiconductor device |
US6498381B2 (en) * | 2001-02-22 | 2002-12-24 | Tru-Si Technologies, Inc. | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same |
US6498074B2 (en) * | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
US20030047798A1 (en) * | 2001-09-13 | 2003-03-13 | Halahan Patrick B. | Semiconductor structures with cavities, and methods of fabrication |
US20030080437A1 (en) * | 2001-10-26 | 2003-05-01 | Intel Corporation | Electronic assembly with filled no-flow underfill and methods of manufacture |
US20030116859A1 (en) * | 1997-03-10 | 2003-06-26 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
US20030199123A1 (en) * | 2002-04-18 | 2003-10-23 | Oleg Siniaguine | Clock distribution networks and conductive lines in semiconductor integrated |
US6661088B1 (en) * | 1999-09-27 | 2003-12-09 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having interposer and method of manufacturing the same |
US20040087057A1 (en) * | 2002-10-30 | 2004-05-06 | Advanpack Solutions Pte. Ltd. | Method for fabricating a flip chip package with pillar bump and no flow underfill |
US6903443B2 (en) * | 1997-12-18 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component and interconnect having conductive members and contacts on opposing sides |
US7161237B2 (en) * | 2002-03-04 | 2007-01-09 | Micron Technology, Inc. | Flip chip packaging using recessed interposer terminals |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61196546A (en) | 1985-02-25 | 1986-08-30 | シーメンス、アクチエンゲゼルシヤフト | Film carrier integrated circuit and manufacture thereof |
JP3024506B2 (en) | 1995-02-28 | 2000-03-21 | 住友金属工業株式会社 | Connection method between Si chip and package |
US5872051A (en) * | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
DE19531158A1 (en) | 1995-08-24 | 1997-02-27 | Daimler Benz Ag | Diffusion soldering method esp. for semiconductor components |
US6399178B1 (en) * | 1998-07-20 | 2002-06-04 | Amerasia International Technology, Inc. | Rigid adhesive underfill preform, as for a flip-chip device |
US6190940B1 (en) * | 1999-01-21 | 2001-02-20 | Lucent Technologies Inc. | Flip chip assembly of semiconductor IC chips |
US6452113B2 (en) * | 1999-07-15 | 2002-09-17 | Incep Technologies, Inc. | Apparatus for providing power to a microprocessor with integrated thermal and EMI management |
US7560779B2 (en) * | 1999-11-30 | 2009-07-14 | Texas Instruments Incorporated | Method for forming a mixed voltage circuit having complementary devices |
SE517921C2 (en) | 1999-12-16 | 2002-08-06 | Strand Interconnect Ab | Module comprising one or more chips |
DE10101359A1 (en) * | 2001-01-13 | 2002-07-25 | Conti Temic Microelectronic | Method of manufacturing an electronic assembly |
US6878608B2 (en) * | 2001-05-31 | 2005-04-12 | International Business Machines Corporation | Method of manufacture of silicon based package |
US6939789B2 (en) | 2002-05-13 | 2005-09-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of wafer level chip scale packaging |
US7059048B2 (en) | 2002-06-07 | 2006-06-13 | Intel Corporation | Wafer-level underfill process making use of sacrificial contact pad protective material |
-
2003
- 2003-12-17 US US10/739,788 patent/US7049170B2/en active Active
-
2004
- 2004-03-10 US US10/798,540 patent/US7241675B2/en not_active Expired - Lifetime
- 2004-12-16 WO PCT/US2004/042228 patent/WO2005059998A1/en active Application Filing
-
2005
- 2005-05-24 US US11/136,799 patent/US20050212127A1/en not_active Abandoned
- 2005-10-19 US US11/253,490 patent/US20060076661A1/en not_active Abandoned
- 2005-10-19 US US11/253,492 patent/US7241641B2/en not_active Expired - Lifetime
- 2005-10-19 US US11/253,943 patent/US7186586B2/en not_active Expired - Lifetime
Patent Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4807021A (en) * | 1986-03-10 | 1989-02-21 | Kabushiki Kaisha Toshiba | Semiconductor device having stacking structure |
US5611140A (en) * | 1989-12-18 | 1997-03-18 | Epoxy Technology, Inc. | Method of forming electrically conductive polymer interconnects on electrical substrates |
US5391514A (en) * | 1994-04-19 | 1995-02-21 | International Business Machines Corporation | Low temperature ternary C4 flip chip bonding method |
US6498074B2 (en) * | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
US20030116859A1 (en) * | 1997-03-10 | 2003-06-26 | Seiko Epson Corporation | Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board |
US6903443B2 (en) * | 1997-12-18 | 2005-06-07 | Micron Technology, Inc. | Semiconductor component and interconnect having conductive members and contacts on opposing sides |
US6163456A (en) * | 1998-01-30 | 2000-12-19 | Taiyo Yuden, Co., Ltd. | Hybrid module and methods for manufacturing and mounting thereof |
US6175158B1 (en) * | 1998-09-08 | 2001-01-16 | Lucent Technologies Inc. | Interposer for recessed flip-chip package |
US20020048916A1 (en) * | 1999-03-29 | 2002-04-25 | Toshiharu Yanagida | Thinned, stackable semiconductor device having low profile |
US20010019178A1 (en) * | 1999-05-18 | 2001-09-06 | International Business Machines Corporation | Method of interconnecting electronic components using a plurality of conductive studs |
US6661088B1 (en) * | 1999-09-27 | 2003-12-09 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having interposer and method of manufacturing the same |
US6322903B1 (en) * | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
US20020036340A1 (en) * | 2000-09-27 | 2002-03-28 | Kabushiki Kaisha Toshiba | Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device |
US20020074637A1 (en) * | 2000-12-19 | 2002-06-20 | Intel Corporation | Stacked flip chip assemblies |
US6498381B2 (en) * | 2001-02-22 | 2002-12-24 | Tru-Si Technologies, Inc. | Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same |
US20020175421A1 (en) * | 2001-05-25 | 2002-11-28 | Naoto Kimura | Semiconductor device |
US20030047798A1 (en) * | 2001-09-13 | 2003-03-13 | Halahan Patrick B. | Semiconductor structures with cavities, and methods of fabrication |
US20030080437A1 (en) * | 2001-10-26 | 2003-05-01 | Intel Corporation | Electronic assembly with filled no-flow underfill and methods of manufacture |
US7161237B2 (en) * | 2002-03-04 | 2007-01-09 | Micron Technology, Inc. | Flip chip packaging using recessed interposer terminals |
US20030199123A1 (en) * | 2002-04-18 | 2003-10-23 | Oleg Siniaguine | Clock distribution networks and conductive lines in semiconductor integrated |
US20040087057A1 (en) * | 2002-10-30 | 2004-05-06 | Advanpack Solutions Pte. Ltd. | Method for fabricating a flip chip package with pillar bump and no flow underfill |
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Also Published As
Publication number | Publication date |
---|---|
US20050136635A1 (en) | 2005-06-23 |
US7049170B2 (en) | 2006-05-23 |
US7241641B2 (en) | 2007-07-10 |
US20050136634A1 (en) | 2005-06-23 |
US20060035416A1 (en) | 2006-02-16 |
US7186586B2 (en) | 2007-03-06 |
US7241675B2 (en) | 2007-07-10 |
US20050212127A1 (en) | 2005-09-29 |
US20060040423A1 (en) | 2006-02-23 |
WO2005059998A1 (en) | 2005-06-30 |
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