US20060077722A1 - Direct memory access interface in integrated circuits - Google Patents
Direct memory access interface in integrated circuits Download PDFInfo
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- US20060077722A1 US20060077722A1 US10/962,293 US96229304A US2006077722A1 US 20060077722 A1 US20060077722 A1 US 20060077722A1 US 96229304 A US96229304 A US 96229304A US 2006077722 A1 US2006077722 A1 US 2006077722A1
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- memory access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1204—Bit line control
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
Definitions
- the invention relates to direct memory bit line access interfaces used to establish a direct electrical connection to an internal memory cell of an integrated circuit.
- a direct memory bit line access interface is important for testing and characterizing memory devices within integrated circuits.
- This interface allows execution of measurement operations by providing access to selected memory bit lines.
- the interface provides access for externally connected instrumentation to have a direct electrical connection to memory cells allowing measurement and characterization operations to be carried out.
- Critical measurements executable by direct electrical connection are bit line leakage measurements, bit line capacitance characterization, bit line to bit line short detection, memory cell current/voltage characterization, and memory cell operation with external voltage levels.
- a direct memory bit line access interface 100 provides connection to a particular set of bit lines within a large array of memory bit lines 110 within an internal memory of an integrated circuit.
- a memory access interface register 120 1 . . . 120 n selects a particular set of bit lines, senses the bit line data values, and retains a plurality of values read.
- the direct memory bit line access interface 100 also manages connection of a retained bit line value to one of several data pads 130 of the integrated circuit.
- the direct memory bit line access interface 100 also provides programming capabilities for the memory cells connected to by the memory bit lines 110 .
- a particular set of memory bit lines 210 associated with a memory access register element 120 connect to the respective inputs of a register of sense amps 220 1 . . . 220 n (i.e., sense amplifiers). Outputs of the sense amps 220 1 . . . 220 n connect to a register of bidirectional storage element 230 1 . . . 230 n .
- the bidirectional storage element 230 1 . . . 230 n connect to a bidirectional data multiplexer 240 .
- the bidirectional data multiplexer 240 has an output bidirectional data line 250 connected to a data pad (not shown).
- the memory bit lines 210 also connect to the inputs of a memory bit line multiplexer 260 .
- the memory bit line multiplexer 260 has an output memory access line 290 connected to a data pad (not shown).
- a memory bit line 310 of a page register element 300 connects to an input of a sense amp 220 .
- An output of the sense amp 220 connects to a bidirectional storage element 230 .
- the bidirectional storage element 230 also connects to a bidirectional data line 350 and a programming driver 360 .
- An output of the programming driver 360 connects to the memory bit line 310 .
- the memory bit line 310 is connected to a memory access line 390 through a memory access gate 370 .
- the memory access gate is enabled by a connection to a select signal at the output of an address select gate 380 .
- the address select gate 380 is activated with an application of address bits at address bit lines 385 that correspond to an address of the page register element 300 or address of a memory bit line.
- the memory access interface register 120 1 . . . 120 n ( FIG. 1 ) includes several memory access register elements 120 ( FIG. 2 ), each of which comprises a page register element 300 ( FIG. 3 ) for each memory bit line 310 to which it is connected.
- the bidirectional data line 350 and the memory access line 390 connect to the bidirectional data multiplexer 240 and the memory bit line multiplexer 260 respectively.
- a memory access gate is activated by connection to an address decoder gate within a memory bit line selection scheme.
- the address decoder is repeated for each page register element.
- An address decoder gate may become large and complex depending upon the number of address selection bits required in the selection scheme.
- the size of each address decoder gate and an instantiation of one decoder gate per bit line selected requires die area. Unless an address decoder scheme becomes additionally complex, only one address and, therefore, only one bit line, is selectable at a time. It is desirable to be able to have access to bit lines and avoid having additional logic incorporating a substantial amount of silicon area at each bit line instance. It is further desirable to be able to select multiple page register elements simultaneously and independently.
- a direct memory access interface incorporates setting bit line selection data into a storage element of a particular page register element.
- the selection data and an access enable signal activate a memory access gate to electrically couple a memory access line with a desired memory bit line.
- Individual bit lines are selectable independently and more than one page register element may be selected at a time.
- Direct access of a memory bit line allows measurement and characterization operations to be carried out electrically with selected memory cells. This direct electrical access allows instrumentation to make voltage and current measurements necessary for characterization operations. Area that would otherwise be incorporated for an address decoder gate at each bit line selector circuit is saved since no on-chip decoding scheme is necessary. Additional area savings are realized since selection data are stored within a bidirectional storage element already present in a page register element.
- FIG. 1 is a block diagram of a prior art direct memory bit line access interface.
- FIG. 2 is a block diagram of a prior art memory access register of the direct memory bit line access interface of FIG. 1 .
- FIG. 3 is a block diagram of a prior art memory page register element of the memory access register of FIG. 2 .
- FIG. 4 is a block diagram of an exemplary embodiment of a memory page register element of the present invention.
- FIG. 5 is a block diagram of an alternate exemplary embodiment of a memory page register element of the present invention.
- a memory bit line 410 of an exemplary page register element 400 connects from a memory device 405 to an input of a sense amp 420 .
- An output of the sense amp 420 connects to a bidirectional storage element 430 and a memory access select gate 480 .
- the bidirectional storage element 430 also connects to a bidirectional data line 450 and an optional programming driver 460 .
- a measurement controller 465 connects to a sense amp enable node (SAEN) of the sense amp 420 , a programming enable node (PGMEN) of the programming driver 460 , and a store enable node (STOREN) of the bidirectional storage element 430 .
- SAEN sense amp enable node
- PGMEN programming enable node
- STOREN store enable node
- An output of the programming driver 460 connects to the memory bit line 410 .
- a data source 455 connects to the bidirectional data line 450 for providing data to either the bidirectional storage element 430 or the programming driver 460 .
- the memory bit line 410 is connected to a memory access line 490 through a memory access gate 470 .
- the memory access line 490 connects to a measurement device 495 for applying and measuring electrical levels from a memory cell within memory device 405 .
- the memory access gate 470 is activated by a select signal from a select output of the memory access select gate 480 .
- a memory access enable input of the memory access select gate 480 is connected to the measurement controller 465 through a memory access enable line 485 .
- a selection input of the memory access select gate 480 is connected to an output of the bi-directional storage element 430 .
- the memory access select gate 480 receives an output logic level determined by selection data retained in the bi-directional storage element 430 .
- the measurement controller 465 connects to all bit lines of the memory device 405 through multiple page register elements (not shown). Communication and control is established by the measurement controller 465 using multiple parallel signals such as SAEN, PGMEN, STOREN, a memory access enable line to each page register element used, and various address selection lines connected to the memory device 405 (not shown).
- a selection data signal is applied at a low logic level from the data source 455 through the corresponding bidirectional data line 450 . This is also true for each of a plurality of bit lines (not shown) to be accessed at a single time.
- the measurement controller 465 may apply enabling signals to all page registers of an integrated circuit (not shown). All page registers of an integrated circuit may be connected in parallel to the measurement controller 465 and the measurement device 495 . Particular memory cells are selected in parallel by the measurement controller 465 applying selection signals to the word lines of interest in the memory device 405 (not shown).
- the measurement controller 465 enables the selection data to be stored from the data source 455 , through the bidirectional data line 450 , and into the bidirectional storage element 430 . Storage is initiated with a store enable signal applied to the store enable node from the measurement controller 465 through the memory access enable line 485 .
- Selection data of a low logic level is fed from an output of the bidirectional storage element 430 to the selection input of the memory access select gate 480 .
- the select gate 480 activates the memory access gate 470 by receiving a low logic level as an access enable signal from the measurement controller 465 .
- selection data from the data source 455 and the access enable signal from the measurement controller 465 replace address decode logic that would otherwise be required at each page register element 400 .
- the activated memory access gate 470 electrically couples the memory access line 490 with the memory bit line 410 .
- This electrical coupling allows a measurement device 495 attached to the memory access line 490 to read or apply electrical signals and voltage levels to write, measure, or characterize a corresponding selected memory cell.
- the measurement device 495 may be located externally or internally to the integrated circuit.
- the bidirectional data line 450 is left free to operate the programming driver 460 , providing a capability of monitoring or testing programming operations through the memory access line 490 .
- selection of a particular memory bit line 410 of the memory device 405 is accomplished by a selection data signal being applied at a high logic level from the data source 455 through the corresponding bidirectional data line 450 .
- the selection data signal is connected to the selection input of the memory access select gate 580 .
- the measurement controller 465 produces a high logic level access enable signal, which is connected to the memory access enable input of the memory access select gate 580 through a memory access enable line 485 .
- the memory access select gate 580 performs a logical AND function and produces a high logic level access selection signal at the select output.
- a high logic level signal applied to the memory access gate 470 produces an electrical connection between the measurement device 495 and the selected memory bit line 410 through the memory access line 490 .
- a direct memory access interface has been shown in terms of a memory access select gate being implemented as a NOR gate or an AND gate, an artisan would recognize that a NAND or an OR gate could also be used for the same access selection control.
- a memory access gate has been shown as an NMOS transistor with a series connected channel, a practitioner in the art would readily recognize that the same switching means may be implemented by alternatives such as a transmission gate or a PMOS transistor.
- memory device means, data sources, and measurement control devices have been shown as managing the supplying and measurement of electrical levels, one skilled in the art would readily realize that various other equipment such as test generators, logic analyzers, voltage sources, signal generators, electrical meters, and controllers may be utilized to achieve similar results.
- a storage element may be implemented in many embodiments such as a latch, a flip-flop, or cross-coupled inverters.
Abstract
A direct memory access interface incorporates setting bit line selection data into a particular storage element of a desired page register element. The selection data and an access enable signal activate a memory access gate to electrically couple a memory access line with a desired memory bit line. Individual bit lines are selectable independently and more than one page register element may be selected at a time. Direct access of a memory bit line allows measurement and characterization operations to be carried out electrically with selected memory cells. This direct electrical access allows instrumentation to make voltage and current measurements necessary for characterization operations. Area that would otherwise be incorporated for an address decoder gate at each bit line selector circuit is saved since no on-chip decoding scheme is necessary. Additional area savings are realized since selection data storage are within a bidirectional storage element already present in a page register element.
Description
- The invention relates to direct memory bit line access interfaces used to establish a direct electrical connection to an internal memory cell of an integrated circuit.
- A direct memory bit line access interface is important for testing and characterizing memory devices within integrated circuits. This interface allows execution of measurement operations by providing access to selected memory bit lines. The interface provides access for externally connected instrumentation to have a direct electrical connection to memory cells allowing measurement and characterization operations to be carried out. Critical measurements executable by direct electrical connection are bit line leakage measurements, bit line capacitance characterization, bit line to bit line short detection, memory cell current/voltage characterization, and memory cell operation with external voltage levels.
- With reference to
FIG. 1 , a direct memory bitline access interface 100 provides connection to a particular set of bit lines within a large array ofmemory bit lines 110 within an internal memory of an integrated circuit. A memoryaccess interface register 120 1 . . . 120 n, selects a particular set of bit lines, senses the bit line data values, and retains a plurality of values read. The direct memory bitline access interface 100 also manages connection of a retained bit line value to one ofseveral data pads 130 of the integrated circuit. The direct memory bitline access interface 100 also provides programming capabilities for the memory cells connected to by thememory bit lines 110. - With reference to
FIG. 2 , a particular set ofmemory bit lines 210 associated with a memoryaccess register element 120, connect to the respective inputs of a register ofsense amps 220 1 . . . 220 n (i.e., sense amplifiers). Outputs of thesense amps 220 1 . . . 220 n connect to a register ofbidirectional storage element 230 1 . . . 230 n. Thebidirectional storage element 230 1 . . . 230 n connect to abidirectional data multiplexer 240. Thebidirectional data multiplexer 240 has an outputbidirectional data line 250 connected to a data pad (not shown). Thememory bit lines 210 also connect to the inputs of a memorybit line multiplexer 260. The memorybit line multiplexer 260 has an outputmemory access line 290 connected to a data pad (not shown). - With reference to
FIG. 3 , amemory bit line 310 of apage register element 300 connects to an input of asense amp 220. An output of thesense amp 220 connects to abidirectional storage element 230. Thebidirectional storage element 230 also connects to abidirectional data line 350 and aprogramming driver 360. An output of theprogramming driver 360 connects to thememory bit line 310. Thememory bit line 310 is connected to amemory access line 390 through amemory access gate 370. The memory access gate is enabled by a connection to a select signal at the output of an addressselect gate 380. The addressselect gate 380 is activated with an application of address bits ataddress bit lines 385 that correspond to an address of thepage register element 300 or address of a memory bit line. - The memory
access interface register 120 1 . . . 120 n (FIG. 1 ) includes several memory access register elements 120 (FIG. 2 ), each of which comprises a page register element 300 (FIG. 3 ) for eachmemory bit line 310 to which it is connected. Thebidirectional data line 350 and thememory access line 390 connect to thebidirectional data multiplexer 240 and the memorybit line multiplexer 260 respectively. - Typically, a memory access gate is activated by connection to an address decoder gate within a memory bit line selection scheme. The address decoder is repeated for each page register element. An address decoder gate may become large and complex depending upon the number of address selection bits required in the selection scheme. The size of each address decoder gate and an instantiation of one decoder gate per bit line selected requires die area. Unless an address decoder scheme becomes additionally complex, only one address and, therefore, only one bit line, is selectable at a time. It is desirable to be able to have access to bit lines and avoid having additional logic incorporating a substantial amount of silicon area at each bit line instance. It is further desirable to be able to select multiple page register elements simultaneously and independently.
- A direct memory access interface incorporates setting bit line selection data into a storage element of a particular page register element. The selection data and an access enable signal activate a memory access gate to electrically couple a memory access line with a desired memory bit line. Individual bit lines are selectable independently and more than one page register element may be selected at a time. Direct access of a memory bit line allows measurement and characterization operations to be carried out electrically with selected memory cells. This direct electrical access allows instrumentation to make voltage and current measurements necessary for characterization operations. Area that would otherwise be incorporated for an address decoder gate at each bit line selector circuit is saved since no on-chip decoding scheme is necessary. Additional area savings are realized since selection data are stored within a bidirectional storage element already present in a page register element.
-
FIG. 1 is a block diagram of a prior art direct memory bit line access interface. -
FIG. 2 is a block diagram of a prior art memory access register of the direct memory bit line access interface ofFIG. 1 . -
FIG. 3 is a block diagram of a prior art memory page register element of the memory access register ofFIG. 2 . -
FIG. 4 is a block diagram of an exemplary embodiment of a memory page register element of the present invention. -
FIG. 5 is a block diagram of an alternate exemplary embodiment of a memory page register element of the present invention. - With reference to
FIG. 4 , amemory bit line 410 of an exemplarypage register element 400 connects from amemory device 405 to an input of asense amp 420. An output of thesense amp 420 connects to abidirectional storage element 430 and a memory accessselect gate 480. Thebidirectional storage element 430 also connects to abidirectional data line 450 and anoptional programming driver 460. Ameasurement controller 465 connects to a sense amp enable node (SAEN) of thesense amp 420, a programming enable node (PGMEN) of theprogramming driver 460, and a store enable node (STOREN) of thebidirectional storage element 430. An output of theprogramming driver 460, if employed, connects to thememory bit line 410. Adata source 455 connects to thebidirectional data line 450 for providing data to either thebidirectional storage element 430 or theprogramming driver 460. Thememory bit line 410 is connected to amemory access line 490 through amemory access gate 470. Thememory access line 490 connects to ameasurement device 495 for applying and measuring electrical levels from a memory cell withinmemory device 405. Thememory access gate 470 is activated by a select signal from a select output of the memory accessselect gate 480. - In one example, to perform a cell current measurement, a memory access enable input of the memory access
select gate 480 is connected to themeasurement controller 465 through a memory access enableline 485. A selection input of the memory accessselect gate 480 is connected to an output of thebi-directional storage element 430. The memory accessselect gate 480 receives an output logic level determined by selection data retained in thebi-directional storage element 430. Themeasurement controller 465 connects to all bit lines of thememory device 405 through multiple page register elements (not shown). Communication and control is established by themeasurement controller 465 using multiple parallel signals such as SAEN, PGMEN, STOREN, a memory access enable line to each page register element used, and various address selection lines connected to the memory device 405 (not shown). - To select a
memory bit line 410 of interest, a selection data signal is applied at a low logic level from thedata source 455 through the correspondingbidirectional data line 450. This is also true for each of a plurality of bit lines (not shown) to be accessed at a single time. Themeasurement controller 465 may apply enabling signals to all page registers of an integrated circuit (not shown). All page registers of an integrated circuit may be connected in parallel to themeasurement controller 465 and themeasurement device 495. Particular memory cells are selected in parallel by themeasurement controller 465 applying selection signals to the word lines of interest in the memory device 405 (not shown). Themeasurement controller 465 enables the selection data to be stored from thedata source 455, through thebidirectional data line 450, and into thebidirectional storage element 430. Storage is initiated with a store enable signal applied to the store enable node from themeasurement controller 465 through the memory access enableline 485. - Selection data of a low logic level is fed from an output of the
bidirectional storage element 430 to the selection input of the memory accessselect gate 480. Theselect gate 480 activates thememory access gate 470 by receiving a low logic level as an access enable signal from themeasurement controller 465. By this selection means, selection data from thedata source 455 and the access enable signal from themeasurement controller 465 replace address decode logic that would otherwise be required at eachpage register element 400. - The activated
memory access gate 470 electrically couples thememory access line 490 with thememory bit line 410. This electrical coupling allows ameasurement device 495 attached to thememory access line 490 to read or apply electrical signals and voltage levels to write, measure, or characterize a corresponding selected memory cell. Themeasurement device 495 may be located externally or internally to the integrated circuit. Additionally, with selection data stored in thebidirectional storage element 430, thebidirectional data line 450 is left free to operate theprogramming driver 460, providing a capability of monitoring or testing programming operations through thememory access line 490. - In an alternate exemplary embodiment of a
page register element 500 ofFIG. 5 , selection of a particularmemory bit line 410 of thememory device 405 is accomplished by a selection data signal being applied at a high logic level from thedata source 455 through the correspondingbidirectional data line 450. The selection data signal is connected to the selection input of the memory accessselect gate 580. Themeasurement controller 465 produces a high logic level access enable signal, which is connected to the memory access enable input of the memory accessselect gate 580 through a memory access enableline 485. The memory accessselect gate 580 performs a logical AND function and produces a high logic level access selection signal at the select output. A high logic level signal applied to thememory access gate 470 produces an electrical connection between themeasurement device 495 and the selectedmemory bit line 410 through thememory access line 490. - Although a direct memory access interface has been shown in terms of a memory access select gate being implemented as a NOR gate or an AND gate, an artisan would recognize that a NAND or an OR gate could also be used for the same access selection control. While a memory access gate has been shown as an NMOS transistor with a series connected channel, a practitioner in the art would readily recognize that the same switching means may be implemented by alternatives such as a transmission gate or a PMOS transistor. While memory device means, data sources, and measurement control devices have been shown as managing the supplying and measurement of electrical levels, one skilled in the art would readily realize that various other equipment such as test generators, logic analyzers, voltage sources, signal generators, electrical meters, and controllers may be utilized to achieve similar results. A skilled practitioner would also recognize that a storage element may be implemented in many embodiments such as a latch, a flip-flop, or cross-coupled inverters.
Claims (11)
1. A direct memory access circuit comprising:
a memory bit line;
a memory access line;
a bidirectional data line capable of receiving selection data; and
a selection circuit comprising:
a storage element coupled to said bidirectional data line;
a memory access gate coupled to said memory bit line and said memory access line; and
a memory access select gate having a selection input, a memory access enable input, and a select output, said select output coupled to said memory access gate, said selection input coupled to said storage element, and said memory access enable input configured to receive an access enable signal.
2. The direct memory access circuit of claim 1 , wherein said memory access gate is configured to electrically couple said memory access line with said memory bit line upon application of said selection data and said access enable signal to said memory access select gate.
3. A direct memory access system comprising:
a memory device containing one or more memory cells;
at least one memory bit line in electrical communication with at least one of said memory cells;
a measurement device;
a data source capable of producing selection data;
a measurement control device configured to produce an access enable signal; and
at least one register element electrically coupled to said at least one memory bit line, said at least one register element each comprising:
a memory access gate coupled to said memory bit line, a memory access line coupled to said memory access gate and said measurement device, a bidirectional data line coupled to said data source, a storage element coupled to said bidirectional data line and said measurement control device, and a memory access select gate coupled to said memory access gate, said storage element, and said measurement control device.
4. The direct memory access circuit of claim 3 , wherein said memory access gate is configured to electrically couple said memory access line with said memory bit line upon application of said selection data and said access enable signal to said memory access select gate.
5. The direct memory access system of claim 3 , wherein said controlled direct memory bit line access allows for testing and characterizing operations by electrical measurement.
6. A method for controlling direct memory access, the method comprising:
selecting a memory cell in a memory array;
writing a selection bit to a storage element, said storage element associated with said selected memory cell;
generating a select signal from said storage element containing said selection bit;
receiving said selection signal at a selection gate to allow access to said selected memory cell, said access providing electrical communication with said memory cell; and
coupling said selected memory cell to an access line, said access line allowing electrical equipment to be coupled to said selected memory cell allowing characterizing of said memory cell.
7. The method for controlling direct memory access of claim 6 , wherein said selecting step includes selecting a plurality of memory cells.
8. The method for controlling direct memory access of claim 6 , wherein said characterizing further comprises performing leakage measurements on said selected memory cell.
9. The method for controlling direct memory access of claim 6 , wherein said characterizing further comprises performing bitline capacitance characterization and bitline-to-bitline short detection.
10. The method for controlling direct memory access of claim 6 , wherein said characterizing further comprises stimulating and measuring current and voltage, thereby characterizing said selected memory cell.
11. The method for controlling direct memory access of claim 6 , wherein said characterizing further comprises programming said memory cell with external voltages.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US10/962,293 US7031211B1 (en) | 2004-10-08 | 2004-10-08 | Direct memory access interface in integrated circuits |
PCT/US2005/031654 WO2006041598A1 (en) | 2004-10-08 | 2005-09-07 | Direct memory access interface in integrated circuits |
TW094132968A TW200627471A (en) | 2004-10-08 | 2005-09-23 | Direct memory access interface in integrated circuits and method therefor |
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US10/962,293 US7031211B1 (en) | 2004-10-08 | 2004-10-08 | Direct memory access interface in integrated circuits |
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US20060077722A1 true US20060077722A1 (en) | 2006-04-13 |
US7031211B1 US7031211B1 (en) | 2006-04-18 |
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US10/962,293 Expired - Fee Related US7031211B1 (en) | 2004-10-08 | 2004-10-08 | Direct memory access interface in integrated circuits |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20120224410A1 (en) * | 2011-03-03 | 2012-09-06 | Tianhong Yan | Three dimensional memory system with intelligent select circuit |
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US8943238B2 (en) | 2012-05-18 | 2015-01-27 | Atmel Corporation | Operations using direct memory access |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6002623A (en) * | 1997-02-12 | 1999-12-14 | Micron Technology, Inc. | Semiconductor memory with test circuit |
US6233191B1 (en) * | 1995-12-20 | 2001-05-15 | International Business Machines Corporation | Field programmable memory array |
US6864738B2 (en) * | 2003-01-06 | 2005-03-08 | Texas Instruments Incorporated | CMOS voltage booster circuits |
-
2004
- 2004-10-08 US US10/962,293 patent/US7031211B1/en not_active Expired - Fee Related
-
2005
- 2005-09-07 WO PCT/US2005/031654 patent/WO2006041598A1/en active Application Filing
- 2005-09-23 TW TW094132968A patent/TW200627471A/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6233191B1 (en) * | 1995-12-20 | 2001-05-15 | International Business Machines Corporation | Field programmable memory array |
US6002623A (en) * | 1997-02-12 | 1999-12-14 | Micron Technology, Inc. | Semiconductor memory with test circuit |
US6864738B2 (en) * | 2003-01-06 | 2005-03-08 | Texas Instruments Incorporated | CMOS voltage booster circuits |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120224410A1 (en) * | 2011-03-03 | 2012-09-06 | Tianhong Yan | Three dimensional memory system with intelligent select circuit |
US9053766B2 (en) * | 2011-03-03 | 2015-06-09 | Sandisk 3D, Llc | Three dimensional memory system with intelligent select circuit |
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Publication number | Publication date |
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TW200627471A (en) | 2006-08-01 |
WO2006041598A1 (en) | 2006-04-20 |
US7031211B1 (en) | 2006-04-18 |
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