CROSSREFERENCE TO OTHER APPLICATIONS

[0001]
This application is a continuation of pending U.S. application Ser. No. 11/015,653, filed Dec. 20, 2004 (Atty. Docket No. 1744.0450004), which is a continuation of U.S. application Ser. No. 09/525,615, filed Mar. 14, 2000, now U.S. Pat. No. 6,853,690, and which claims the benefit of U.S. Provisional Application No. 60/177,381, filed Jan. 24, 2000; U.S. Provisional Application No. 60/171,502, filed Dec. 22, 1999; U.S. Provisional Application No. 60/177,705, filed Jan. 24, 2000; U.S. Provisional Application No. 60/129,839, filed Apr. 16, 1999; U.S. Provisional Application No. 60/158,047, filed Oct. 7, 1999; U.S. Provisional Application No. 60/171,349, filed Dec. 21, 1999; U.S. Provisional Application No. 60/177,702, filed Jan. 24, 2000; U.S. Provisional Application No. 60/180,667, filed Feb. 7, 2000; and U.S. Provisional Application No. 60/171,496, filed Dec. 22, 1999, all of which are incorporated by reference herein in their entireties.
BACKGROUND OF THE INVENTION

[0002]
1. Field of the Invention

[0003]
The present invention is generally related to methods and systems for utilizing universal frequency translators for phase and/or frequency detection.

[0004]
2. Related Art

[0005]
Prior art methods and systems for frequency translation and phase and/or frequency detection exist.
BRIEF SUMMARY OF THE INVENTION

[0006]
Briefly stated, the field of the invention is directed to methods and systems for utilizing universal frequency translators for phase and/or frequency detection.

[0007]
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost character(s) and/or digit(s) in the corresponding reference number.
BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

[0008]
The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention. Generally, in the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, generally, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.

[0009]
FIG. 1 illustrates an example phase difference detector.

[0010]
FIG. 2 illustrates an example phase locked loop.

[0011]
FIG. 3 illustrates an example compensation module of the phase locked loop shown in FIG. 2.

[0012]
FIG. 4 illustrates an example frequency difference detection module.

[0013]
FIG. 5 illustrates an example frequency locked loop.

[0014]
FIG. 6 illustrates an example loop filter of the frequency difference detection module shown in FIG. 5.

[0015]
FIG. 7 illustrates an example carrier acquisition and tracking module with D2D.

[0016]
FIG. 8 illustrates an example baseband symbol clock recovery module with D2D.

[0017]
FIG. 9 illustrates example transversal equalizer demodulator and modulator configurations.

[0018]
FIG. 10 illustrates an example baseband linear transversal equalizer LMS implementation.

[0019]
FIG. 11 illustrates an example baseband linear transversal equalizer zero forcing implementation.

[0020]
FIG. 12 illustrates an example zero forcing D2D implementation.

[0021]
FIG. 13 illustrates an example RF or passband linear transversal equalizer LMS implementation.

[0022]
FIG. 14 illustrates an example RF or passband linear transversal equalizer zero forcing implementation.

[0023]
FIG. 15 illustrates an example zero forcing D2D implementation.

[0024]
FIG. 16 illustrates an example D2D spreader/despreader configuration.

[0025]
FIG. 17 illustrates example waveforms for a D2D spreader/despreader.

[0026]
FIG. 18 illustrates a first example implementation of a D2D spreader/despreader.

[0027]
FIG. 19 illustrates a second example implementation of a D2D spreader/despreader.

[0028]
FIG. 20 illustrates a third example implementation of a D2D spreader/despreader.

[0029]
FIG. 21 illustrates a fourth example implementation of a D2D spreader/despreader.

[0030]
FIG. 22 illustrates a fifth example implementation of a D2D spreader/despreader.

[0031]
FIG. 23 illustrates a block diagram on an example D2D system and modem on a chip.
DETAILED DESCRIPTION OF THE INVENTION

[0032]


Table of Contents 


1. 
Phase Detection 

1.1 
Gating Module as a Phase Difference Detector 

1.2 
Implemented as a Phase Locked Loop (PLL) 


1.2.1 
Controlling the Trigger Point of v(t) 



1.2.1.1 
Controlling the Trigger Point 




of v(t) with Phase Delay 



1.2.1.2 
Controlling the Trigger Point 




of v(t) with Bias Voltage 


1.2.2. 

Automatic Gain Control (AGC) 


1.2.3 
Using a PLL to Simultaneously DownConvert 



and Demodulate a Phase Modulated Signal 
2. 
Frequency Detection 

2.1 
Multiple UFTs for Frequency Detection 

2.2 
Implemented as a Frequency Locked Loop 


2.2.1 
Controlling the Frequency of v(t) with a VCO 


2.2.2 
Automatic Gain Control (AGC) 


2.2.3 
Using a Frequency Locked Loop to 



Simultaneously DownConvert and 



Demodulate a Frequency Modulated Signal 
3. 
Combination PLL and Frequency Locked Loop 
4. 
Carrier Acquisition and Tracking with D2D 

4.1 
Carrier Acquisition and Tracking 

4.2 
Carrier Acquisition and Tracking 

4.3 
Baseband Symbol Clock Recovery with D2D 
5. 
Linear Baseband Transversal Equalizer with D2D 

5.1 
LMS Algorithm for Convergence 

5.2 
LMS Baseband Transversal Equalizer 

5.3 
Zero Forcing Algorithm for Convergence 

5.4 
Zero Forcing Transversal Equalizer 
6. 
Linear RF or Passband Transversal Equalizer with D2D 

6.1 
LMS Algorithm for Convergence 

6.2 
LMS RF or Passband Transversal Equalizer 

6.3 
Zero Forcing Algorithm for Convergence 

6.4 
Zero Forcing RF or Passband Transversal Equalizer 
7. 
D2D as a Spreader/Despreader 

7.1 
Case 1 

7.2 
Case 2 

7.3 
Case 3 

7.4 
Case 4 

7.5 
Case 5 
8. 
Example Implementations of Gated Transfer Unit 
9. 
Conclusion 


[0033]
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are illustrated. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art.
1. PHASE DETECTOR

[0034]
Universal frequency translators (UFTs), as taught and described in U.S. patent application Ser. No. 09/176,022, titled “Method And System For DownConverting Electromagnetic Signals,” filed Oct. 21, 1998, now U.S. Pat. No. 6,061,551, U.S. patent application Ser. No. 09/293,342, titled “Method And Circuit For DownConverting A Signal Using A Complementary FET Structure For Improved Dynamic Range,” filed Apr. 16, 1999, now U.S. Pat. No. 6,687,493, and U.S. patent application Ser. No. 09/293,095, titled “Method And System For DownConverting Electromagnetic Signals Having Optimized Switch Structures,” filed Apr. 16, 1999, now U.S. Pat. No. 6,580,902 (hereinafter referred to collectively as “Related UFT Patents”), all of which are incorporated herein by reference in their entireties, can be utilized as phase and/or frequency difference detectors.

[0000]
1.1 Gating Module as a Phase Difference Detector

[0035]
FIG. 1 illustrates a gating module 102, as described in one or more of the Related UFT Patents. In FIG. 1, the gating module 102 is implemented and referred to herein as a phase difference detector. The phase difference detector 102 is functionally illustrated with a UFT, or switching module 104, a capacitor 106, and a pulse generator 108. FIG. 1 is intended to functionally illustrate aspects of an embodiment of the present invention. As described in one or more of the Related UFT Patents, the phase difference detector 102 can be implemented in a variety of configurations using a variety of components.

[0036]
In operation, the pulse generator 108 controls the UFT 104 according to a control signal v(t) at terminal 112, to transfer energy from a reference signal s(t) at terminal 110, to the capacitor 106, as described in the one or more of the Related UFT Patents. From the energy, or charge, transferred to the capacitor 106, a difference signal d(t) is provided at output terminal 114.

[0037]
The difference signal d(t) includes a downconverted version of the reference signal s(t). The difference signal d(t) is substantially proportional to a frequency and phase difference between s(t) and v(t). More specifically, as described in one or more of the Related UFT Patents, the frequency of d(t) is substantially equal to the frequency of s(t) minus N times the frequency of the control signal v(t). Thus, when the frequency of s(t) is substantially equal to N times the frequency of v(t), d(t) will be substantially constant. But, when the phase difference between s(t) and v(t) changes, the constant voltage level of d(t) will change.

[0038]
The amplitude of d(t) will depend, in part, on the phase of s(t) when the switch 104 is closed. The switch 104 closes when the pulse generator 108 generates a pulse. The pulse generator 108 generates a pulse when a rising edge of v(t) triggers the pulse generator 108 to generate a pulse. This is referred to as the trigger point of v(t). Thus, the switch 104 closes on trigger points of v(t).

[0039]
Generally, when the trigger point of v(t) is aligned with a maximum point of s(t)'s carrier frequency, s(t) and v(t) are said to be phase aligned, and the amplitude of d(t) will be at a relative maximum. But as the phase difference between v(t)'s trigger point and s(t) increases, the amplitude of d(t) decreases.

[0040]
As a result of the above description, when the frequency of s(t) is substantially equal to N times the frequency of v(t), the gating module 102 can be viewed as a phase difference detector. One use for the phase difference detector 102 is in a phase locked loop, as described below.

[0000]
1.2 Implemented as a Phase Locked Loop (PLL)

[0041]
The phase difference detector 102 can be implemented as part of a phase locked loop. In an embodiment, the phase detector 102 is used to simultaneously downconvert the reference signal s(t) and detect phase differences. In this embodiment, phase locking occurs at a lower frequency than the reference signal s(t), which reduces component cost and design complexities. In an example, a UFT is implemented in a phase locked loop.

[0042]
FIG. 2 illustrates the phase difference detector 102 from FIG. 1 implemented in a phase locked loop (PLL) 202. The PLL 202 includes a loop filter 204 and a compensation module 206.

[0043]
The loop filter 204 can be designed for desired stabilization and/or response characteristics. Based on the description herein, one skilled in the relevant art(s) will recognize that the loop filter 204 can be designed and implemented in a variety of configurations using hardware, firmware, software, or any combination thereof. In an embodiment, the loop filter 204 includes an integration function that sums successive values of d(t).

[0044]
The compensation module 206 adjusts the phase and/or frequency of v(t), as necessary, to maintain d(t) at a zero. In an embodiment, when the loop filter 204 includes an integration function that sums successive values of d(t), the output of the loop filter 204 is used by the compensation module 206 to maintain the phase and/or frequency of v(t) at a level that maintains d(t) at zero amplitude.

[0045]
In operation, when the trigger point of v(t) is aligned with a zero crossing of s(t), d(t) will be substantially zero. As a result, there will be no change in the output of the integrator/loop filter 204, and thus, the compensation module 206 will make no changes to v(t). But when the phase of s(t) changes relative to the phase of v(t), d(t) will change away from zero, either positive or negative, depending on which direction the relative phases change. When d(t) changes from zero, positive or negative, the output of the integrator/loop filter 204 increases or decreases respectively, causing the compensation module to increase or decrease the phase and/or frequency of v(t). When the trigger point of v(t) is again aligned with a zero crossing of s(t), d(t) will return to zero. When d(t) returns to zero, the output of the loop filter 204 will hold its previous value until d(t) again changes. So long as the output of the loop filter remains constant at its previous level, the compensation module 206 will maintain the phase and/or frequency of v(t) at its previous level. Thus, any relative phase change between s(t) and v(t) are corrected.

[0046]
One use for phase locked loop as described above is for simultaneously downconverting and demodulating a phase modulated signal, as described below. Before discussing simultaneous downconverting and demodulation, exemplary implementation details of the compensation module will be discussed.

[0000]
1.2.1 Controlling the Trigger Point of v(t)

[0047]
From the description of the v(t) trigger point above, it will be understood that, for phase locking, the relative phase difference between the v(t) trigger point and s(t) is to be controlled. The relative phase difference between the v(t) trigger point and s(t) can be controlled in a variety of ways.

[0000]
1.2.1.1 Controlling the Trigger Point of v(t) with Phase Delay

[0048]
In an embodiment, the relative phase of v(t) is controlled by controlling a delay of v(t). This can be done with, for example, a voltage controlled oscillator (VCO). Phase delay can be implemented independently or as part of a voltage controlled oscillator (VCO). Based on the description herein, one skilled in the relevant art(s) will recognize how a conventional VCO with phase delay control can be incorporated into the compensation module 206, in order to control the relative phase difference between the v(t) trigger point and s(t).

[0000]
1.2.1.2 Controlling the Trigger Point of v(t) with Bias Voltage

[0049]
In another embodiment, the relative phase difference between the v(t) trigger point and s(t) are controlled by controlling a bias voltage on v(t). This can be performed with the circuit illustrated in FIG. 3, or functional equivalents thereof. Changing the bias level of v(t) changes the voltage level for all of v(t) so that, for a given phase of v(t), the bias voltage can be adjusted to meet or exceed the trigger voltage of the pulse generator. In an embodiment, a linear region of v(t) is utilized for bias voltage adjustments.

[0000]
1.2.2. Automatic Gain Control (AGC)

[0050]
Phase difference detection can be affected by unintentional amplitude variations due to, for example, amplitude changes on the reference signal s(t), or DC offset voltages. In an embodiment, an automatic gain control (AGC) system is used to maintain relative amplitude control.

[0000]
1.2.3 Using a PLL to Simultaneously DownConvert and Demodulate a Phase Modulated Signal

[0051]
When the reference signal s(t) is a phase modulated carrier signal, information is encoded, or modulated, on the reference signal s(t) in the form of phase changes about a carrier frequency. In the PLL 202 of FIG. 2, these phase changes will appear as amplitude changes on d(t). When the loop filter 204 includes an integrationtype function, as described above, the output of the loop filter will substantially resemble the information that was phase encoded on the reference signal s(t). Thus, while the PLL 202 maintains the phase relationship between v(t) and s(t), the information is simultaneously available as a demodulated baseband information signal at terminal 208. In an embodiment, the PLL 202 includes an AGC system as described above.
2. FREQUENCY DETECTION

[0052]
Universal frequency translators (UFTs), as taught and described in the Related UFT Patents, can be utilized as phase and/or frequency difference detectors.

[0000]
2.1 Multiple UFTs for Frequency Detection

[0053]
FIG. 4 illustrates a frequency difference detection module 402, including a gating module 404, low pass filters 418 and 420, and loop filter 422. The dualswitch gating modules 404 is functionally illustrated with universal frequency translators (UFTs), or switching modules, 406 and 408, a pulse generator 410, a delay element 412, and capacitors 414 and 416. As described in one or more of the Related UFT Patents, the gating module 404 can be implemented in a variety of configurations using a variety of components, and is not limited to the functional illustration of FIG. 4.

[0054]
In operation, the pulse generator 410 controls the UFTs 406 and 408, according to a control signal v(t) at terminal 426, to transfer energy from a reference signal s(t) at terminal 424, to the capacitors 414 and 416, as described in the one or more of the Related UFT Patents. The delay element 412 causes the UFT 408 to downconvert s(t) 90 degrees out of phase with respect to UFT 406. UFTs 406 and 408 are thus said to generate inphase and quadraturephase (I and Q) information channels 430 and 432, respectively.

[0055]
The I and Q channels 430 and 432 are filtered by LPFs 418 and 420, and then provided to the loop filter 422, which generates the difference signal 428. The difference signal d(t) is substantially proportional to the difference between v(t) and s(t).

[0056]
The loop filter 204 can be designed for desired stabilization and/or response characteristics. Based on the description herein, one skilled in the relevant art(s) will recognize that the loop filter 204 can be designed and implemented in a variety of configurations using hardware, firmware, software, or any combination thereof.

[0057]
In an embodiment, loop filter 422 is implemented so that d(t) is positive when the frequency of s(t) is greater than the frequency of v(t), and negative when the frequency of s(t) is less than the frequency of v(t), with an amplitude that is relative to the difference value. An example implementation of this embodiment is illustrated in FIG. 6, as part of a frequency locked loop, as is described in detail below. The present invention is not limited to the example loop filter 422 illustrated in FIG. 6. The example of the loop filter 422 illustrated in FIG. 6 is not limited to implementations in frequency locked loops. Rather, the loop filter 422 illustrated in FIG. 6 can be implemented in systems other than frequency locked loops.

[0058]
In an embodiment, a frequency difference detector, as described above, is utilized in a frequency locked loop, as described below.

[0000]
2.2 Implemented as a Frequency Locked Loop

[0059]
The frequency difference detector 404 can be implemented as part of a frequency locked loop. In an embodiment, the frequency difference detector 404 is used to simultaneously downconvert the reference signal s(t) and detect frequency differences. In this embodiment, frequency locking occurs at a lower frequency than the reference signal s(t), which reduces component cost and design complexities.

[0060]
FIG. 5 illustrates a frequency locked loop 502, including the frequency difference detector 404 and a compensation module 504. The compensation module 504 controls v(t), based upon d(t).

[0061]
The compensation module 504 adjusts the frequency of v(t), as necessary. In an embodiment, the compensation module 504 adjusts the frequency of v(t), to maintain d(t) substantially at a zero (i.e., to maintain the frequency of v(t), or a harmonic or subharmonic thereof, substantially equal to the frequency of s(t)).

[0062]
In an embodiment, the loop filter 422 or the compensation module 504 includes an integration function, illustrated here as integration module 506, that sums successive values of d(t), the result of which is used by the compensation module 504 to maintain the frequency of v(t), or a harmonic or subharmonic thereof, substantially equal to the frequency of s(t)).

[0063]
FIG. 6 illustrates an example embodiment of the frequency locked loop 502, including an example implementation of the loop filter 422. It can be shown that d(t) is positive when the frequency of s(t) is greater than the frequency of v(t), and d(t) is negative when the frequency of s(t) is less than the frequency of v(t). The amplitude of d(t) is relative to the extent of the difference between the frequency of s(t) and v(t).

[0064]
In FIG. 6, point a can be defined as A sin(θ_{A}), where θ=∫ ω(t)dt. Since the frequency is of interest here, not phase, A sin(θ_{A}) can be written as sin(ω_{A}t).

[0065]
Point b can then be defined as B sin(θ_{B}), where θ_{B}=θ_{A}90°. So B sin(θ_{B}) becomes cos(θ_{A}), which, for frequency detection, becomes cos(ω_{A}t).

[0066]
It follows that:

 point b is ω_{A}cos(ω_{A}t);
 point e is −ω_{Asin}(ω_{A}t);
 point c is ω_{A}cos^{2}(ω_{A}t);
 point f is −ω_{A}sin^{2}(ω_{A}t); and
 point g is ω_{A}cos^{2}(ω_{A}t)−(−ω_{A}Sin^{2}(ω_{A}t))=ω_{A}(cos^{2}(θ_{A}t)+sin^{2}(ω_{A}t)), which equals ω_{A}, since cos^{2}(x)+sin^{2}(x)=1.

[0072]
It can be shown that ω
_{A }is proportional to ω
_{s(t)}Nω
_{v(t)}. Thus, it can be shown that:

 when ω_{s(t) }is greater than N times ω_{v(t)}, ω_{A }is greater than zero; and
 when ω_{s(t) }is less greater than N times ω_{v(t)}, ω_{A }is less than zero.
ω_{A }can thus be used to control v(t) with respect to s(t).
2.2.1 Controlling the Frequency of v(t) with a VCO

[0075]
In an embodiment, the compensation module 504 includes a VCO that controls the frequency of v(t), based on d(t). In alternative embodiments, a frequency synthesizer and/or any other frequency generator with frequency control can be utilized.

[0000]
2.2.2 Automatic Gain Control (AGC)

[0076]
In some electronic systems, it may be desirable or necessary to maintain a constant signal level at some point in the system. To achieve a constant signal level, an AGC may be employed.

[0077]
The signal √{square root over (I^{2}+Q^{2})}, or any reasonable approximation may be used as the control signal to a controlled amplifier. Here, I and Q are the outputs, possibly amplified and filtered, of I and Q UFT devices. As described previously, √{square root over (I^{2}+Q^{2})} is directly proportional to the signal strength, and so provides an adequate control signal.

[0000]
2.2.3 Using a Frequency Locked Loop to Simultaneously DownConvert and Demodulate a Frequency Modulated Signal

[0078]
When the reference signal s(t) is a frequency modulated carrier signal, information is encoded, or modulated, on the reference signal s(t) in the form of frequency changes about a carrier frequency. In the frequency locked loop 502 of FIG. 5, these phase changes will appear as amplitude changes on d(t). When the frequency locked loop 502 includes an integrationtype function, as described above, the output of the integration function will substantially resemble the information that was frequency encoded on the reference signal s(t). Thus, while the frequency locked loop maintains the frequency of v(t) at the frequency of s(t) divided by N, the information is simultaneously available as a demodulated baseband information signal at terminal 508.
3. COMBINATION PLL AND FREQUENCY LOCKED LOOP

[0079]
The phase locked loops and frequency locked loops described herein can be utilized in combination so that a frequency locked loop tracks the frequency of s(t) and a phase locked loop tracks the phase of s(t).
4. CARRIER ACQUISITION AND TRACKING WITH D2D

[0000]
4.1 Carrier Recovery and Tracking

[0080]
The D2D can readily control the phase of a local oscillator (LO) and the dPHI/dt, which is the frequency. If the LO is placed onchip, the phase lock loop can be an onchip analog circuit and this will use less power than a digital signal processing (DSP) solution. Analog solutions are almost always lower power solutions than DSP solutions. Based on classical phase lock loop theory, D2D implementation of the baseband clock recovery will simplify the baseband DSP and lower the power requirements of battery powered telecommunications devices requiring coherent detection schemes. The D2D embodiments described herein can be used to drastically reduce the power and weight and cost over a DSP solution.

[0081]
In the example carrier and acquisition architecture shown in FIG. 7, a D2D circuit is used in three places to perform three different functions. First, the D2D circuit is used as a phase detector to compare the phase of the reference carrier, which is coherent, with the sampling signal. Second, the D2D circuit is used as a control circuit to control the frequency and phase of a sampling LO so as to track the frequency and phase of the incoming signal.

[0082]
Third, the D2D circuit is used to convert a sample of the sampling LO to RF so the D2D at RF can detect the phase difference between the incoming signal and the reference LO.

[0083]
In each of these three implementations, the D2D is configured differently. In the phase detector implementation, the two signals to be compared are input to the RF and the LO (or sampling) inputs. The output that would normally be the demodulated signal (baseband port) is a voltage proportional to the phase and frequency difference of the two signals (note that the average input power of both signals should the same in this case). An automatic gain control (AGC) will probably be required. The output of the phase detector is low pass filtered and the filtered voltage is used to control the second D2D. The control voltage is input to the baseband port and is used to modulate the phase and frequency of the LO. The loop filter transfer function will control the natural frequency of the loop and thus the 2BL. The third D2D takes the output of the phase controlling D2D and upconverts it to RF for phase comparison.

[0000]
4.2 Carrier Acquisition and Tracking

[0084]
The D2D demodulator function requires the subharmonic LO to be coherent with the received RF carrier. If this can be achieved without a residual carrier or a pilot tone, more of the transmitted energy can be committed to the useable signaltonoise ratio (Eb/No). FIG. 7 illustrates a block diagram of such an implementation.

[0085]
Since D2D can translate any baseband signal to RF by appropriately modulating the carrier, D2D can be used to modify the phase or frequency of a LO output. The output of the low frequency LO is RF/m, where m is greater or equal to n. The first D2D translates RF/m to RF/n with a phase and frequency offset determined by the control voltage. The output of the first D2D is split. One signal goes to the quadrature D2D, which performs the direct to data conversion as covered in the Related UFT Patents. The second output is input to the second D2D, which translates the output to RF. At RF, another D2D (or any phase detector), is used to determine the phase error between the reference signal and the received signal.

[0086]
The output of the phase detector is input to a logic and loop filter circuit, which generates the control voltage to adjust the phase and frequency of the reference LO output signal.

[0000]
4.3 Baseband Symbol Clock Recovery with D2D

[0087]
The D2D can readily control the phase of a LO and the dPHI/dt, which is the frequency. If the LO is placed onchip, the phase lock loop can be an onchip analog circuit, which will use less power than a DSP solution. Analog solutions are almost always lower power solutions than DSP solutions. Based on classical phase lock loop theory, D2D implementation of the baseband clock recovery will simplify the baseband DSP and lower the power requirements of battery powered telecommunications devices requiring coherent detection schemes. The D2D embodiments described herein can be used to drastically reduce the power and weight and cost over a DSP solution.

[0088]
In the example baseband symbol clock recovery architecture shown in FIG. 8, a D2D circuit is used in two places to perform two different functions.

[0089]
First, the D2D circuit is used as a phase detector to compare the phase of the baseband signal on either the I or Q channel to that of the baseband clock, which will be used to sample the baseband waveforms. Second, the D2D circuit is used as a control circuit to control the frequency and phase of a baseband clock so as to track the frequency and phase of the incoming baseband signal.

[0090]
In each of these two implementations, the D2D is configured differently. In the phase detector implementation, the two signals to be compared are input to the RF and the LO (or sampling) inputs. The output that would normally be the demodulated signal (baseband port) is a voltage proportional to the phase and frequency difference of the two signals (note that the average input power of both signals should the same). An AGC will probably be required. The output of the phase detector is low pass filtered, and the filtered voltage is used to control the second D2D. The control voltage is input to the baseband port and is used to modulate the phase and frequency of the LO. The loop filter transfer function will control the natural frequency of the loop and thus the 2BL.
5. LINEAR BASEBAND TRANSVERSAL EQUALIZER D2D

[0000]
5.1 LMS Algorithm for Convergence

[0091]
In the modulator configuration, shown in FIG. 9, the baseband signal will modulate (or modify) the input signal of the subharmonic port. By adjusting the voltage on the baseband port, the phase and amplitude of the signal on the subharmonic port can be controlled to create any arbitrary phase and amplitude of the signal input to the subharmonic port on the RF output port.

[0092]
In a transversal equalizer application, the signal on the subharmonic port is at the same frequency as the signal on the RF output port. In this case, the D2D and the equalizer tap are used. For convenience, the subharmonic, baseband, and RF ports are referred to as ports A, B and C, respectively.

[0000]
5.2 LMS Baseband Transversal Equalizer

[0093]
The polyphase filter or transversal equalizer is known to persons of skill in the art. The uniqueness of this embodiment, among other features, is the use of the D2D to facilitate the implementation of the analog equalizer on a chip and as part of a system on a chip. The D2D implementation of the baseband transversal equalizer will be lower cost, lower power and lower weight and volume than the equivalent implementation in either discrete components or a DSP solution. A LMS solution can be implemented in logic (on or off chip) to control the tap weights of the equalizer by analyzing the sampled output from the A/D converters in the DSP portion of the system and minimizing the squared error. Use of D2D in this embodiment results in the benefits realized as described above. A convergence algorithm, such as a constant modulus algorithm (CMA), can be used.

[0094]
Due to the very small size, extremely large dynamic range and signal quality, and low power consumption of the D2D, very long analog equalizers can be realized, which can be used for a wide range of channel bandwidths. If the equalizer is designed for a T/2 implementation at some symbol rate R, the equalizer can be used at any rate of R/m as long as the group delay does not exceed the time length of the entire equalizer. The T/2 will simply become T/n where n is greater than 2. The benefits of a fractional spaced equalizer will be fully realized at all data rates.

[0095]
An example LMS implementation of a baseband linear transversal equalizer is shown in FIG. 10. B(i) are determined by some algorithm, such as LMS. The coefficients B(i) change at a very low rate (e.g., on the order of 10 to 100 Hz). If the equalizer is being used to compensate for multipath, the update must be faster than the time constant for the multipath. If “T” is less than one half of the symbol period, then the implementation shown in FIG. 10 becomes an adaptive matched filter because it is a fractional spaced equalizer.

[0096]
Applications of the LMS implementation of the baseband transversal equalizer include: hand held communications devices and fixed systems, equalizers on satellite transponders to equalize uplink group delay, and any radio channel with linear group delay.

[0000]
5.3 Zero Forcing Algorithm for Convergence

[0097]
In the modulator configuration, shown in FIG. 9, the baseband signal will modulate (or modify) the input signal of the subharmonic port. By adjusting the voltage on the baseband port, the phase and amplitude of the signal on the subharmonic port can be controlled to create any arbitrary phase and amplitude of the signal input to the subharmonic port on the RF output port.

[0098]
In the transversal equalizer application, the signal on the subharmonic port is at the same frequency as the signal on the RF output port. In this case, the D2D and the equalizer tap are used. For convenience, the subharmonic, baseband, and RF ports are referred to as ports A, B and C, respectively.

[0000]
5.4 Zero Forcing Transversal Equalizer

[0099]
The polyphase filter or transversal equalizer is known to persons of skill in the art. The uniqueness of this embodiment, among other features, is the use of the D2D to facilitate the implementation of the analog equalizer on a chip and as part of a system on a chip. As described above, the D2D implementation of the transversal equalizer will be lower cost, lower power and lower weight and volume than the equivalent implementation in either discrete components or a DSP solution. In a zero forcing implementation of the baseband linear transversal equalizer, the sample at each time tap point is sent to a D2D correlator, which determines the correlation with the punctual signal. The output voltage of the D2D is input to a zero forcing function, and the control tap weight “B” is sent to the subject tap, which is done in parallel with all taps simultaneously, independent of modulation. Use of D2D in this application results in the benefits realized as described above.

[0100]
Due to the very small size, extremely large dynamic range and signal quality, and low power consumption of the D2D, very long analog equalizers can be realized, which can be used for a wide range of channel bandwidths.

[0101]
As shown in FIG. 11, if the equalizer is designed for a T/2 implementation at some symbol rate R, the equalizer can be used at any rate of R/m, as long as the group delay does not exceed the time length of the entire equalizer. The T/2 will simply be come T/n where n is greater than 2. The benefits of a fractional spaced equalizer will be fully realized at all data rates.

[0102]
An example zero forcing implementation of the linear baseband transversal equalizer is shown in FIG. 11. B(i) are determined by some algorithm, such as LMS. The coefficients B(i) change at a very low rate (e.g., on the order of 10 to 100 Hz). If the equalizer is being used to compensate for multipath, the update must be faster than the time constant for the multipath.

[0103]
If “T” is less than one half of the symbol period, then the implementation shown in FIG. 11 becomes an adaptive matched filter because it is a fractional spaced equalizer.

[0104]
FIG. 12 shows a zero forcing D2D implementation of the baseband transversal equalizer.

[0105]
Applications of the zero forcing implementation of the baseband transversal equalizer include: hand held communications devices and fixed systems, equalizers on satellite transponders to equalize uplink group delay, and any radio channel with linear group delay.
6. LINEAR RF OR PASSBAND TRANSVERSAL EQUALIZER WITH D2D

[0000]
6.1 LMS Algorithm for Convergence

[0106]
In the modulator configuration, shown in FIG. 9, the baseband signal will modulate (or modify) the input signal of the subharmonic port. By adjusting the voltage on the baseband port, the phase and amplitude of the signal on the subharmonic port can be controlled to create any arbitrary phase and amplitude of the signal input to the subharmonic port on the RF output port.

[0107]
In a transversal equalizer application, the signal on the subharmonic port is at the same frequency as the signal on the RF output port. In this case, the D2D and the equalizer tap are used. For convenience, the subharmonic, baseband, and RF ports are referred to as ports A, B and C, respectively.

[0000]
6.2 LMS RF or Passband Transversal Equalizer

[0108]
The polyphase filter or transversal equalizer is known to persons of skill in the art. The uniqueness of this embodiment, among other features, is the use of the D2D to facilitate the implementation of the analog equalizer on a chip and as part of a system on a chip. As described above, the D2D implementation of the transversal equalizer will be lower cost, lower power and lower weight and volume than the equivalent implementation in either discrete components or a DSP solution. A LMS solution can be implemented in logic (on or off chip), which would control the tap weights of the equalizer by analyzing the sampled output from the A/D converters in the DSP portion of the system and minimizing the squared error. Use of D2D in this embodiment results in the benefits realized as described above. A convergence algorithm, such as a CMA, can be used.

[0109]
This equalizer is implemented at RF or passband and only one delay line equalizer is required since D2D control taps can adjust the tap outputs from zero to maximum amplitude and from 0 to 360 degrees.

[0110]
Due to the very small size, extremely large dynamic range and signal quality, and low power consumption of the D2D, very long analog equalizers can be realized which can be used for a wide range of channel bandwidths. If the equalizer is designed for a T/2 implementation at some symbol rate R, the equalizer can be used at any rate of R/m as long as the group delay does not exceed the time length of the entire equalizer. The T/2 will simply be come T/n where n is greater than 2. The benefits of a fractional spaced equalizer will be fully realized at all data rates.

[0111]
An example LMS implementation of a RF or passband linear transversal equalizer is shown in FIG. 13. B(i) are determined by some algorithm, such as LMS. The coefficients B(i) change at a very low rate (e.g., on the order of 10 to 100 Hz). If the equalizer is being used to compensate for multipath, the update must be faster than the time constant for the multipath. If “T” is less than one half of the symbol period, then the implementation shown in FIG. 13 becomes an adaptive matched filter because it is a fractional spaced equalizer.

[0112]
Applications of the LMS implementation of the RF or passband linear transversal equalizer include: hand held communications devices and fixed systems, equalizers on satellite transponders to equalize uplink group delay, and any radio channel with linear group delay.

[0000]
6.3 Zero Forcing Algorithm for Convergence

[0113]
In the modulator configuration, shown in FIG. 9, the baseband signal will modulate (or modify) the input signal of the subharmonic port. By adjusting the voltage on the baseband port, the phase and amplitude of the signal on the subharmonic port can be controlled to create any arbitrary phase and amplitude of the signal input to the subharmonic port on the RF output port.

[0114]
In a transversal equalizer application, the signal on the subharmonic port is at the same frequency as the signal on the RF output port. In this case, the D2D and the equalizer tap can be used. For convenience, the subharmonic, baseband, and RF ports are referred to as ports A, B and C, respectively.

[0000]
6.4 Zero Forcing RF or Passband Transversal Equalizer

[0115]
The polyphase filter or transversal equalizer is known to persons of skill in the art. The uniqueness of this embodiment, among other features, is the use of the D2D to facilitate the implementation of the analog equalizer on a chip and as part of a system on a chip. The D2D implementation of the transversal equalizer will be lower cost, lower power and lower weight and volume than the equivalent implementation in either discrete components or a DSP solution. In a zero forcing implementation of the RF or passband linear transversal equalizer, the sample at each time tap point is sent to a D2D correlator, which determines the correlation with the punctual signal. The output voltage of the D2D is input to a zero forcing function, and the control tap weight “B” is sent to the subject tap, which is done in parallel with all taps simultaneously, independent of modulation. Use of D2D in this embodiment results in the benefits realized as described above.

[0116]
This equalizer is implemented at RF or passband and only one delay line equalizer is required since D2D control taps can adjust the tap outputs from zero to maximum amplitude and from 0 to 360 degrees.

[0117]
Due to the very small size, extremely large dynamic range and signal quality, and low power consumption of the D2D, very long analog equalizers can be realized which can be used for a wide range of channel bandwidths. If the equalizer is designed for a T/2 implementation at some symbol rate R, the equalizer can be used at any rate of R/m as long as the group delay does not exceed the time length of the entire equalizer. The T/2 will simply be come T/n where n is greater than 2. The benefits of a fractional spaced equalizer will be fully realized at all data rates.

[0118]
An example zero forcing implementation of an RF or passband linear transversal equalizer is shown in FIG. 14. B(i) are determined by some algorithm, such as LMS. The coefficients B(i) change at a very low rate (e.g., on the order of 10 to 100 Hz). If the equalizer is being used to compensate for multipath, the update must be faster than the time constant for the multipath. If “T” is less than one half of the symbol period, then the implementation shown in FIG. 14 becomes an adaptive matched filter because it is a fractional spaced equalizer.

[0119]
FIG. 15 shows an example zero forcing D2D implementation of the RF or passband transversal equalizer.
7. D2D AS A SPREADER/DESPREADER

[0120]
Since D2D transmission/reception is symmetric, we need only describe a spreader/transmitter. FIG. 16 illustrates a block diagram of an example D2D spreader/transmitter.

[0000]
7.1 Case 1

[0121]
If signal {tilde over (s)}(t) is fixed and a local oscillator (LO) contains BPSK or QPSK symbols with spreading information, then

 b_{psk}(i)=PSK symbol in i^{th }bit interval, and
 b_{psk}(i)=e^{iφ} ^{ i }, where φ_{i }is one of the allowed phases (e.g., for BPSK, φ_{i}=+π/2 or φ_{i}=−π/2).

[0124]
FIG. 17 shows a binary waveform σ(t) that has the same out of phases as b_{psk}. Also shown in FIG. 17 is a spread waveform. An example implementation of Case 1 is shown in FIG. 18. In FIG. 18, the LO signal is data modulated and spread.

[0000]
7.2 Case 2

[0125]
In this case, {tilde over (s)}(t) is modulated using any type of modulation and spreading, and the LO is unmodulated. If {tilde over (s)}(t) is any information signal (i.e., analog, digital, etc.) and σ is any spreading sequence (note that while σ is normally binary, σ can include frequency shifts, such as hopping spread spectrum, wavelets, etc.), then Case 2 may be implemented as shown in FIG. 19.

[0000]
7.3 Case 3

[0126]
In this case, {tilde over (s)}(t) is an arbitrary baseband signal and the LO is binary modulated. Case 3 may be implemented as shown in FIG. 20.

[0000]
7.4 Case 4 p In this case, {tilde over (s)}(t) is an arbitrary baseband signal and a reference signal is binary and/or frequency modulated. Case 4 may be implemented as shown in FIG. 21.

[0000]
7.5 Case 5

[0127]
In this case, a reference signal is frequency step controlled and is used in conjunction with binary spreading. Case 5 may be implemented as shown in FIG. 22.
8. EXAMPLE IMPLEMENTATIONS OF GATED TRANSFER UNIT

[0128]
Another embodiment of the present invention is implemented as a combination of the following embodiments: (1) D2D in linear transversal equalizers for pre and post equalizers (transmit and receive), including linear baseband with LMS or CMA algorithm, linear RF/passband with LMS or CMA algorithm, linear baseband with zero forcing circuits, and linear RF/passband with zero forcing circuits; (2) carrier acquisition and tracking loop with D2D; (3) baseband clock recovery loop with D2D; (4) use of D2D as a correlator; (5) use of D2D as a phase detector; (6) use of D2D as a modulator; (7) use of D2D as a demodulator; (8) use of D2D as a phase control in a phase locked loop; (9) use of D2D as an upconverter; and (10) use of D2D as a downconverter.

[0129]
As shown in FIG. 23, this embodiment allows an entire modem to be implemented with D2D circuits. The functions usually done in DSP can be done in analog and combined in a single chip or on a chip with the DSP to drastically cut the power consumption for functions (1)(10) listed above. This embodiment will eliminate a great deal of DSP processing requirements, thus reducing power consumption.
9. CONCLUSION

[0130]
Example implementations of the methods, systems and components of the invention have been described herein. As noted elsewhere, these example implementations have been described for illustrative purposes only, and are not limiting. Other implementation embodiments are possible and covered by the invention, such as but not limited to software and software/hardware implementations of the systems and components of the invention. Such implementation embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.

[0131]
While various application embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the abovedescribed exemplary embodiments.