US20060086954A1 - Multi-layer film stack for extinction of substrate reflections during patterning - Google Patents

Multi-layer film stack for extinction of substrate reflections during patterning Download PDF

Info

Publication number
US20060086954A1
US20060086954A1 US11/297,390 US29739005A US2006086954A1 US 20060086954 A1 US20060086954 A1 US 20060086954A1 US 29739005 A US29739005 A US 29739005A US 2006086954 A1 US2006086954 A1 US 2006086954A1
Authority
US
United States
Prior art keywords
substrate
dielectric
layer
silicon dioxide
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/297,390
Inventor
Sanjay Natarajan
Sean King
Khaled Elamrawi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/297,390 priority Critical patent/US20060086954A1/en
Publication of US20060086954A1 publication Critical patent/US20060086954A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832Multiple layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/902Capping layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/945Special, e.g. metal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/95Multilayer mask including nonradiation sensitive layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/952Utilizing antireflective layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/958Passivation layer

Definitions

  • interconnections Modern integrated circuits use interconnections to connect the individual devices on a chip or to send and/or receive signals external to the chip.
  • Popular types of interconnections include aluminum or copper interconnections (lines) coupled to devices, including other interconnections (lines) by interconnections through vias.
  • the invention relates to integrated circuit fabrication and, more particularly, to the definition and alignment of interconnections in integrated circuit structures.
  • Fabricating an interconnection structure to a device formed on a circuit substrate, such as an interconnection to a transistor device typically involves introducing a photoimageable material (e.g., photoresist) over a dielectric layer insulating the device.
  • the photoimageable material is patterned to have an opening to the dielectric above the desired point of contact for the subsequent interconnection.
  • An etch is then used to form an opening or via through the dielectric layer to the device.
  • FIG. 1 illustrates the light scattering effect according to conventional processing.
  • FIG. 1 shows structure 100 including substrate 110 of, for example, a semiconductor material such as silicon.
  • Substrate 110 has, in this example, transistor devices 120 formed in active areas of the substrate. The active areas are separated from one another by shallow trench isolation (STI) 130 .
  • Dielectric material 135 such as, for example, silicon dioxide (SiO 2 ) overlies devices 120 and substrate 110 .
  • Photoimageable material 140 such as a positive photoresist overlies dielectric material 135 .
  • an opening in photoimageable material is desired over area 150 which will be an opening for a via to transistor device 120 .
  • FIG. 1 shows that light directed through opening area 150 in the process of developing the photoimageable material may scatter within structure 110 and reflect off structures on substrate 110 (i.e., substrate reflections). Certain structures, such as gate electrodes and STI 130 are sufficiently reflective to reflect the scattered light and create undesired developed areas in photoimageable material 140 .
  • FIG. 1 shows undesired opening area 180 formed by reflective light 160 off a gate electrode and reflective light 170 off STI 130 .
  • the undesired opening area 180 may be developed in such a way to create an opening to photoimageable material to dielectric material 135 .
  • FIG. 1 shows a schematic, cross-sectional view of a portion of a prior art integrated circuit substrate and illustrates light reflections through a photoimageable material opening.
  • FIG. 2 shows a cross-sectional view of a portion of an integrated circuit structure including a substrate having circuit devices formed thereon, an etch stop layer overlying the substrate followed by a base dielectric material and two alternating layers of dielectric material according to an embodiment of the invention.
  • FIG. 3 shows the structure of FIG. 2 after the introduction of two additional alternating layers of dielectric material.
  • FIG. 4 shows the structure of FIG. 3 after the introduction of two additional alternating layers.
  • FIG. 5 shows the structure of FIG. 4 after the introduction of three additional alternating layers.
  • FIG. 6 shows the structure of FIG. 5 after the introduction and patterning of a photoimageable material having openings to devices in the substrate.
  • FIG. 7 shows the structure of FIG. 6 after introducing an interconnection to a contact point on the substrate.
  • FIG. 8 is a graphical representation of the peak reflectance through a prior art substrate structure and a structure according to FIG. 5 .
  • a method includes introducing a dielectric layer over a substrate between an interconnection line and a contact point, the dielectric layer comprising a plurality of different material layers, and patterning an interconnection to the contact point.
  • An embodiment of the apparatus includes a substrate comprising a plurality of devices formed thereon and a dielectric layer comprising a plurality of alternating material layers overlying the substrate.
  • the apparatus also includes an interconnection line overlying the dielectric layer and coupled to at least one of the plurality of devices.
  • FIGS. 2-7 illustrate an example of a dielectric layer that suppresses substrate reflections.
  • substrate refers to the device substrate, such as a silicon semiconductor substrate as well as a substrate having one or more interconnection lines formed thereon.
  • the dielectric layer described herein is an interlayer dielectric material(s) between interconnection lines. It is recognized that the majority of substrate reflection problems occur through the primary dielectric material over the device substrate (e.g., primary dielectric material between the device substrate and the first interlayer dielectric layer). Accordingly, with reference to FIG. 2 through FIG. 7 , a technique is shown of forming an interlayer dielectric over the device substrate. It is appreciated that subsequent dielectric material layers (i.e., subsequent interlayer dielectric material layers) may optionally be formed according to technique described herein, depending in part on the extent of reflections seen at the various higher levels.
  • FIG. 2 shows structure 200 including device substrate 210 of, for example, a semiconductor such as silicon.
  • Device substrate 210 includes a plurality of devices 220 formed in active areas thereon. Such active areas are defined, in one sense, by isolation structures such as shallow trench isolation (STI) structures 230 .
  • STI shallow trench isolation
  • etch stop layer 240 Overlying substrate 210 and any devices formed thereon is etch stop layer 240 .
  • etch stop layer 240 is, for example, silicon nitride material deposited by chemical vapor deposition to a thickness on the order of about 500 angstroms ( ⁇ ). In one sense, etch stop layer 240 protects substrate 210 and devices formed thereon from a subsequent etching operation.
  • Base layer 250 is, for example, silicon dioxide (SiO 2 ) formed by tetraethyl orthosilicate (TEOS) or a plasma enhanced chemical vapor deposition (PECVD) source.
  • TEOS tetraethyl orthosilicate
  • PECVD plasma enhanced chemical vapor deposition
  • base layer 250 is doped with phosphorous or boron (e.g., by adding PH 3 or B 2 H 6 during deposition) so that base layer 250 may serve as a getter (collector) of metallic contaminants.
  • base layer 250 over the substrate may proceed in a conformal manner leaving a non-planar substrate surface.
  • structure 200 is planarized by, for example, the use of a chemical-mechanical polish.
  • a representative thickness of planarized base layer 250 of, for example, silicon dioxide, is on the order of 1900 angstroms ( ⁇ ).
  • dielectric cap 255 includes a plurality of alternating material layers.
  • FIG. 2 shows dielectric cap 255 of a first dielectric material 260 A and a different second dielectric material 270 A.
  • dielectric material 260 A is silicon oxynitride deposited to a thickness on the order of 50 ⁇ .
  • Dielectric material 270 A is, in one embodiment, silicon dioxide deposited to a thickness on the order of about 283 ⁇ .
  • One objective of introducing dielectric cap 255 over base layer 250 is to yield a uniform interlayer dielectric film.
  • One way to target a uniform film of dielectric cap 255 is by introducing the cap layers on a multi-station tool such as a Concept 2 SequelTM, commercially available from Novellus Systems, Inc. of San Jose, Calif. Through the use of a multi-station tool, it is possible to introduce multiple alternating layers or films of dielectric material as dielectric cap 255 .
  • FIG. 3 shows two layers or films 260 A and 260 B of silicon oxynitride deposited to approximately 50 ⁇ each.
  • each silicon oxynitride layer or film Disposed between each silicon oxynitride layer or film (i.e., between layer or film 260 A and 260 B) are dielectric layers or films 270 A and 270 B of silicon dioxide introduced to a thickness on the order of about 283 ⁇ .
  • FIG. 4 shows three alternating layers or films of silicon oxynitride ( 260 A, 260 B, and 260 C) and three layers or films of silicon dioxide ( 270 A, 270 B, and 270 C).
  • FIG. 5 shows six layers or films of silicon oxynitride ( 260 A- 260 F) and six layers or films of silicon dioxide ( 270 A- 270 F).
  • dielectric cap 255 By using a multi-station tool to introduce dielectric cap 255 , multiple alternating layers or films of different dielectric materials may be introduced efficiently. By selecting thicknesses of the alternating materials and the number of alternating films, cap layer 255 may be maintained within a suitable thickness range consistent with prior art structures. For example, in one embodiment, it is-desired that a dielectric cap 255 has a thickness on the order of about 2,000 ⁇ for the structure described (i.e., an overall dielectric thickness (cap+base layer+etch stop) of approximately 4,000 ⁇ ).
  • the structure represented in each of FIG. 2 through FIG. 5 has silicon dioxide as the ultimate layer or film and for each film thickness of the alternating layers or films, the silicon dioxide film is more than five times thicker than the silicon oxynitride film.
  • the alternating cap materials as silicon dioxide and silicon oxynitride
  • silicon dioxide is generally a much harder material than silicon oxynitride. Accordingly, any subsequent polishing steps associated with the introduction of, for example, interconnection material over dielectric cap 255 allows for planarization (e.g., polishing) of silicon dioxide rather than silicon oxynitride.
  • Silicon dioxide also provides better adherence to a subsequent interconnection structure such as an interconnection line of aluminum or copper.
  • silicon oxynitride has a higher dielectric constant than silicon dioxide.
  • Measurably increasing the dielectric constant of dielectric cap 255 may impair circuit performance by, for example, introducing undesired capacitance, such as metal to metal capacitance within the structure.
  • FIG. 6 shows the structure of FIG. 5 after the introduction and patterning of photoimageable material 280 .
  • photoimageable material 280 is a positive photoresist.
  • Photoimageable material 280 is patterned to have opening areas 290 over the dielectric structure, the opening areas formed in this example to devices 220 on substrate 210 .
  • FIG. 5 also illustrates minimal undesired developed areas (none) in photoimageable material 280 as a result of undesired reflections in forming opening areas 290 .
  • FIG. 7 shows the structure of FIG. 6 after the etching of openings to devices 220 on substrate 210 and the removal of photoimageable material 280 .
  • FIG. 7 also shows the structure after the introduction of interconnection material 295 to devices 220 and interconnection material 297 over the dielectric layer. Such etching, removal of photoimageable material, and introduction of interconnection material may proceed by techniques as known in the art.
  • the embodiment shown in FIG. 6 illustrates no undesired opening areas due to substrate reflection
  • the total inhibition of substrate reflection depends also on the light that is reflected.
  • light of possibly many wavelengths is introduced into the substrate.
  • the path length that the light travels is also significant in determining substrate reflections. For example, where the path length dictates that the wavelength will be modified by one-half, it is possible that such wavelength difference will be destructive and not contribute to a noticeable reflection.
  • the reflected light differs from the introduced light by a full wavelength, it is possible that such reflective light will be constructive and lead to undesired developing of photoimageable material.
  • FIG. 8 shows the simulated peak reflectance of a prior art dielectric material configuration such as described with respect to FIG. 1 and the accompanying text yielding a peak reflectance of approximately 66 percent.
  • the structure shown in FIG. 6 has a peak reflectance of 24 percent.
  • dielectric cap of interweaved layers or films of dielectric materials of silicon dioxide and silicon oxynitride is presented. It is appreciated that there may be other materials besides silicon dioxide and silicon oxynitride that may suitably substituted. Other materials may likewise be substituted for the base layer material as well. These dielectric materials include materials having a dielectric constant lower than silicon dioxide (“low k” dielectrics).

Abstract

A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional of co-pending U.S. patent application Ser. No. 09/750,734, filed Dec. 27, 2000.
  • BACKGROUND
  • 1. Background
  • Modern integrated circuits use interconnections to connect the individual devices on a chip or to send and/or receive signals external to the chip. Popular types of interconnections include aluminum or copper interconnections (lines) coupled to devices, including other interconnections (lines) by interconnections through vias.
  • 2. Field of the Invention
  • The invention relates to integrated circuit fabrication and, more particularly, to the definition and alignment of interconnections in integrated circuit structures.
  • Fabricating an interconnection structure to a device formed on a circuit substrate, such as an interconnection to a transistor device, typically involves introducing a photoimageable material (e.g., photoresist) over a dielectric layer insulating the device. The photoimageable material is patterned to have an opening to the dielectric above the desired point of contact for the subsequent interconnection. An etch is then used to form an opening or via through the dielectric layer to the device.
  • One problem with the current state of the art photoimaging technique is the formation of undesired openings in the photoimageable material due to substrate reflections of light. FIG. 1 illustrates the light scattering effect according to conventional processing. FIG. 1 shows structure 100 including substrate 110 of, for example, a semiconductor material such as silicon. Substrate 110 has, in this example, transistor devices 120 formed in active areas of the substrate. The active areas are separated from one another by shallow trench isolation (STI) 130. Dielectric material 135 such as, for example, silicon dioxide (SiO2) overlies devices 120 and substrate 110. Photoimageable material 140 such as a positive photoresist overlies dielectric material 135. In this example, an opening in photoimageable material is desired over area 150 which will be an opening for a via to transistor device 120.
  • Referring to FIG. 1, it is shown that light directed through opening area 150 in the process of developing the photoimageable material may scatter within structure 110 and reflect off structures on substrate 110 (i.e., substrate reflections). Certain structures, such as gate electrodes and STI 130 are sufficiently reflective to reflect the scattered light and create undesired developed areas in photoimageable material 140. FIG. 1 shows undesired opening area 180 formed by reflective light 160 off a gate electrode and reflective light 170 off STI 130. Upon developing the photoimageable material, the undesired opening area 180 may be developed in such a way to create an opening to photoimageable material to dielectric material 135.
  • By creating undesired openings in the photoimageable material, failure modes are introduced into the circuit device processing. When these openings are later filled with interconnection material, electrical shorts may be introduced either between metal lines or on the silicon structure. Further, undesired interconnects coupled to silicon surface introduce a capacitive element in the structure.
  • Attempts to remedy the problem of creating undesired opening areas include placing an anti-reflective coating over the structure. Such technique, however, involves introducing an additional film which adds process cost and complexity and possibly additional defects in the process flow. Reduction of the light intensity is not a workable solution at this point as it requires approximately 27 milliJoules (mJ) to develop positive photoresist with only one to two milliJoules margin. Therefore, reducing the light intensity may result in the loss of the desired opening area, such as opening area 150.
  • What is needed are improved processing techniques and an improved structure that suppresses undesired reflections.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a schematic, cross-sectional view of a portion of a prior art integrated circuit substrate and illustrates light reflections through a photoimageable material opening.
  • FIG. 2 shows a cross-sectional view of a portion of an integrated circuit structure including a substrate having circuit devices formed thereon, an etch stop layer overlying the substrate followed by a base dielectric material and two alternating layers of dielectric material according to an embodiment of the invention.
  • FIG. 3 shows the structure of FIG. 2 after the introduction of two additional alternating layers of dielectric material.
  • FIG. 4 shows the structure of FIG. 3 after the introduction of two additional alternating layers.
  • FIG. 5 shows the structure of FIG. 4 after the introduction of three additional alternating layers.
  • FIG. 6 shows the structure of FIG. 5 after the introduction and patterning of a photoimageable material having openings to devices in the substrate.
  • FIG. 7 shows the structure of FIG. 6 after introducing an interconnection to a contact point on the substrate.
  • FIG. 8 is a graphical representation of the peak reflectance through a prior art substrate structure and a structure according to FIG. 5.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The invention relates to techniques and an apparatus for forming interlayer dielectric material layers that suppress undesired substrate reflections. In one embodiment, a method includes introducing a dielectric layer over a substrate between an interconnection line and a contact point, the dielectric layer comprising a plurality of different material layers, and patterning an interconnection to the contact point. An embodiment of the apparatus includes a substrate comprising a plurality of devices formed thereon and a dielectric layer comprising a plurality of alternating material layers overlying the substrate. The apparatus also includes an interconnection line overlying the dielectric layer and coupled to at least one of the plurality of devices.
  • FIGS. 2-7 illustrate an example of a dielectric layer that suppresses substrate reflections. Unless otherwise specified, substrate refers to the device substrate, such as a silicon semiconductor substrate as well as a substrate having one or more interconnection lines formed thereon. In the latter case, the dielectric layer described herein is an interlayer dielectric material(s) between interconnection lines. It is recognized that the majority of substrate reflection problems occur through the primary dielectric material over the device substrate (e.g., primary dielectric material between the device substrate and the first interlayer dielectric layer). Accordingly, with reference to FIG. 2 through FIG. 7, a technique is shown of forming an interlayer dielectric over the device substrate. It is appreciated that subsequent dielectric material layers (i.e., subsequent interlayer dielectric material layers) may optionally be formed according to technique described herein, depending in part on the extent of reflections seen at the various higher levels.
  • FIG. 2 shows structure 200 including device substrate 210 of, for example, a semiconductor such as silicon. Device substrate 210 includes a plurality of devices 220 formed in active areas thereon. Such active areas are defined, in one sense, by isolation structures such as shallow trench isolation (STI) structures 230.
  • Overlying substrate 210 and any devices formed thereon is etch stop layer 240. In one embodiment, etch stop layer 240 is, for example, silicon nitride material deposited by chemical vapor deposition to a thickness on the order of about 500 angstroms (Å). In one sense, etch stop layer 240 protects substrate 210 and devices formed thereon from a subsequent etching operation.
  • Referring to FIG. 2 overlying etch stop layer 240 is base layer 250. Base layer 250 is, for example, silicon dioxide (SiO2) formed by tetraethyl orthosilicate (TEOS) or a plasma enhanced chemical vapor deposition (PECVD) source. In one embodiment, base layer 250 is doped with phosphorous or boron (e.g., by adding PH3 or B2H6 during deposition) so that base layer 250 may serve as a getter (collector) of metallic contaminants.
  • It is appreciated that the introduction of base layer 250 over the substrate may proceed in a conformal manner leaving a non-planar substrate surface. In such cases, following the introduction and possible doping of base layer 250, structure 200 is planarized by, for example, the use of a chemical-mechanical polish. A representative thickness of planarized base layer 250 of, for example, silicon dioxide, is on the order of 1900 angstroms (Å).
  • It is generally desirable at this point to introduce a dielectric cap over planarized base layer 250. The dielectric cap is included, in one sense, to mask any microdefects caused by the planarization. Referring to FIG. 2, in this embodiment, dielectric cap 255 includes a plurality of alternating material layers. FIG. 2 shows dielectric cap 255 of a first dielectric material 260A and a different second dielectric material 270A. In one embodiment, dielectric material 260A is silicon oxynitride deposited to a thickness on the order of 50 Å. Dielectric material 270A is, in one embodiment, silicon dioxide deposited to a thickness on the order of about 283 Å.
  • One objective of introducing dielectric cap 255 over base layer 250 is to yield a uniform interlayer dielectric film. One way to target a uniform film of dielectric cap 255 is by introducing the cap layers on a multi-station tool such as a Concept 2 Sequel™, commercially available from Novellus Systems, Inc. of San Jose, Calif. Through the use of a multi-station tool, it is possible to introduce multiple alternating layers or films of dielectric material as dielectric cap 255. FIG. 3 shows two layers or films 260A and 260B of silicon oxynitride deposited to approximately 50 Å each. Disposed between each silicon oxynitride layer or film (i.e., between layer or film 260A and 260B) are dielectric layers or films 270A and 270B of silicon dioxide introduced to a thickness on the order of about 283 Å. FIG. 4 shows three alternating layers or films of silicon oxynitride (260A, 260B, and 260C) and three layers or films of silicon dioxide (270A, 270B, and 270C). FIG. 5 shows six layers or films of silicon oxynitride (260A-260F) and six layers or films of silicon dioxide (270A-270F).
  • By using a multi-station tool to introduce dielectric cap 255, multiple alternating layers or films of different dielectric materials may be introduced efficiently. By selecting thicknesses of the alternating materials and the number of alternating films, cap layer 255 may be maintained within a suitable thickness range consistent with prior art structures. For example, in one embodiment, it is-desired that a dielectric cap 255 has a thickness on the order of about 2,000 Å for the structure described (i.e., an overall dielectric thickness (cap+base layer+etch stop) of approximately 4,000 Å).
  • The structure represented in each of FIG. 2 through FIG. 5 has silicon dioxide as the ultimate layer or film and for each film thickness of the alternating layers or films, the silicon dioxide film is more than five times thicker than the silicon oxynitride film. With the selection of the alternating cap materials as silicon dioxide and silicon oxynitride, one reason it is desired to have silicon dioxide as the ultimate layer or film in the multi-layer stack is that silicon dioxide is generally a much harder material than silicon oxynitride. Accordingly, any subsequent polishing steps associated with the introduction of, for example, interconnection material over dielectric cap 255 allows for planarization (e.g., polishing) of silicon dioxide rather than silicon oxynitride. Silicon dioxide also provides better adherence to a subsequent interconnection structure such as an interconnection line of aluminum or copper.
  • One reason for selecting films of silicon dioxide that are more than five times thicker than the silicon oxynitride counterparts is that silicon oxynitride has a higher dielectric constant than silicon dioxide. Measurably increasing the dielectric constant of dielectric cap 255 may impair circuit performance by, for example, introducing undesired capacitance, such as metal to metal capacitance within the structure.
  • It has been observed that with a dielectric cap that is a two layer or film of 1,000 Å of silicon oxynitride and 1,000 Å of silicon dioxide (one to one relationship) with undesired substrate reflections from, for example, STI 231, are inhibited. Reduction of the amount of silicon oxynitride to silicon dioxide from one to one, to one to five or one to six inhibits some undesired reflections but is not as effective as the inhibiting reflectance of the one to one relationship. It has also been observed by interweaving or alternating the silicon oxynitride and silicon dioxide films as described above using significantly less silicon oxynitride, similar reflection inhibition to the one to one relationship is seen. Therefore, interweaving or alternating as described the structure shown, for example, in FIG. 5, is suitably effective at inhibiting light reflection while minimizing device performance issues while using silicon oxynitride as a portion of dielectric cap 255.
  • FIG. 6 shows the structure of FIG. 5 after the introduction and patterning of photoimageable material 280. In one embodiment, photoimageable material 280 is a positive photoresist. Photoimageable material 280 is patterned to have opening areas 290 over the dielectric structure, the opening areas formed in this example to devices 220 on substrate 210. FIG. 5 also illustrates minimal undesired developed areas (none) in photoimageable material 280 as a result of undesired reflections in forming opening areas 290. FIG. 7 shows the structure of FIG. 6 after the etching of openings to devices 220 on substrate 210 and the removal of photoimageable material 280. FIG. 7 also shows the structure after the introduction of interconnection material 295 to devices 220 and interconnection material 297 over the dielectric layer. Such etching, removal of photoimageable material, and introduction of interconnection material may proceed by techniques as known in the art.
  • Although the embodiment shown in FIG. 6 illustrates no undesired opening areas due to substrate reflection, it is appreciated that the total inhibition of substrate reflection depends also on the light that is reflected. It is appreciated that in forming an opening area in, for example, photoresist material, light of possibly many wavelengths is introduced into the substrate. In this sense, the path length that the light travels is also significant in determining substrate reflections. For example, where the path length dictates that the wavelength will be modified by one-half, it is possible that such wavelength difference will be destructive and not contribute to a noticeable reflection. On the other hand, if the reflected light differs from the introduced light by a full wavelength, it is possible that such reflective light will be constructive and lead to undesired developing of photoimageable material. Thus, a complete inhibition of substrate reflections according to the techniques described herein is difficult to achieve in every case. Nevertheless, the structure described herein and the techniques of forming such structure offer an improvement over prior art techniques. FIG. 8 shows the simulated peak reflectance of a prior art dielectric material configuration such as described with respect to FIG. 1 and the accompanying text yielding a peak reflectance of approximately 66 percent. The structure shown in FIG. 6, on the other hand, has a peak reflectance of 24 percent.
  • In the above embodiment, a dielectric cap of interweaved layers or films of dielectric materials of silicon dioxide and silicon oxynitride is presented. It is appreciated that there may be other materials besides silicon dioxide and silicon oxynitride that may suitably substituted. Other materials may likewise be substituted for the base layer material as well. These dielectric materials include materials having a dielectric constant lower than silicon dioxide (“low k” dielectrics).
  • In the preceding detailed description, an improved interlayer dielectric is presented that inhibits substrate reflections. The invention is described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (4)

1. An apparatus comprising:
a substrate comprising a plurality of devices formed thereon; and
an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.
2. The apparatus of claim 1, wherein the cap layer comprises silicon dioxide as the ultimate material layer.
3. The apparatus of claim 1, wherein the cap layer comprises a plurality of silicon dioxide layers alternated with at least one other material layers.
4. The apparatus of claim 3, wherein the number of alternating silicon dioxide layers comprises at least six.
US11/297,390 2000-12-27 2005-12-07 Multi-layer film stack for extinction of substrate reflections during patterning Abandoned US20060086954A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/297,390 US20060086954A1 (en) 2000-12-27 2005-12-07 Multi-layer film stack for extinction of substrate reflections during patterning

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/750,734 US7172960B2 (en) 2000-12-27 2000-12-27 Multi-layer film stack for extinction of substrate reflections during patterning
US11/297,390 US20060086954A1 (en) 2000-12-27 2005-12-07 Multi-layer film stack for extinction of substrate reflections during patterning

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/750,734 Division US7172960B2 (en) 2000-12-27 2000-12-27 Multi-layer film stack for extinction of substrate reflections during patterning

Publications (1)

Publication Number Publication Date
US20060086954A1 true US20060086954A1 (en) 2006-04-27

Family

ID=25018971

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/750,734 Expired - Fee Related US7172960B2 (en) 2000-12-27 2000-12-27 Multi-layer film stack for extinction of substrate reflections during patterning
US11/297,390 Abandoned US20060086954A1 (en) 2000-12-27 2005-12-07 Multi-layer film stack for extinction of substrate reflections during patterning
US11/300,023 Expired - Fee Related US7291552B2 (en) 2000-12-27 2005-12-13 Multi-layer film stack for extinction of substrate reflections during patterning

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/750,734 Expired - Fee Related US7172960B2 (en) 2000-12-27 2000-12-27 Multi-layer film stack for extinction of substrate reflections during patterning

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/300,023 Expired - Fee Related US7291552B2 (en) 2000-12-27 2005-12-13 Multi-layer film stack for extinction of substrate reflections during patterning

Country Status (1)

Country Link
US (3) US7172960B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7470505B2 (en) * 2005-09-23 2008-12-30 Lexmark International, Inc. Methods for making micro-fluid ejection head structures
US7784917B2 (en) 2007-10-03 2010-08-31 Lexmark International, Inc. Process for making a micro-fluid ejection head structure
JP5517848B2 (en) * 2010-09-08 2014-06-11 キヤノン株式会社 Method for manufacturing liquid discharge head
US10529552B2 (en) 2017-11-29 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing a semiconductor device and a coating material
US11004612B2 (en) * 2019-03-14 2021-05-11 MicroSol Technologies Inc. Low temperature sub-nanometer periodic stack dielectrics

Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468342A (en) * 1994-04-28 1995-11-21 Cypress Semiconductor Corp. Method of etching an oxide layer
US5565384A (en) * 1994-04-28 1996-10-15 Texas Instruments Inc Self-aligned via using low permittivity dielectric
US5639687A (en) * 1993-07-06 1997-06-17 Motorola Inc. Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride
US5792703A (en) * 1996-03-20 1998-08-11 International Business Machines Corporation Self-aligned contact wiring process for SI devices
US5840624A (en) * 1996-03-15 1998-11-24 Taiwan Semiconductor Manufacturing Company, Ltd Reduction of via over etching for borderless contacts
US5893752A (en) * 1997-12-22 1999-04-13 Motorola, Inc. Process for forming a semiconductor device
US6037276A (en) * 1997-10-27 2000-03-14 Vanguard International Semiconductor Corporation Method for improving patterning of a conductive layer in an integrated circuit
US6042999A (en) * 1998-05-07 2000-03-28 Taiwan Semiconductor Manufacturing Company Robust dual damascene process
US6060380A (en) * 1998-11-06 2000-05-09 Advanced Micro Devices, Inc. Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication
US6127089A (en) * 1998-08-28 2000-10-03 Advanced Micro Devices, Inc. Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques
US6174810B1 (en) * 1998-04-06 2001-01-16 Motorola, Inc. Copper interconnect structure and method of formation
US6214721B1 (en) * 1999-05-27 2001-04-10 National Semiconductor Corp. Method and structure for suppressing light reflections during photolithography exposure steps in processing integrated circuit structures
US6222241B1 (en) * 1999-10-29 2001-04-24 Advanced Micro Devices, Inc. Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer
US20010012689A1 (en) * 1998-12-03 2001-08-09 Uzodinma Okoroanyanwu Interconnect structure with silicon containing alicyclic polymers and low-k dieletric materials and method of making same with single and dual damascene techniques
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
US6350679B1 (en) * 1999-08-03 2002-02-26 Micron Technology, Inc. Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry
US6350700B1 (en) * 2000-06-28 2002-02-26 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6362091B1 (en) * 2000-03-14 2002-03-26 Intel Corporation Method for making a semiconductor device having a low-k dielectric layer
US6383950B1 (en) * 2000-02-23 2002-05-07 Advanced Micro Devices, Inc. Insulating and capping structure with preservation of the low dielectric constant of the insulating layer
US6383918B1 (en) * 1999-03-15 2002-05-07 Philips Electronics Method for reducing semiconductor contact resistance
US6399480B1 (en) * 1997-05-22 2002-06-04 Advanced Micro Devices, Inc. Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction
US20020155698A1 (en) * 1997-08-22 2002-10-24 Micron Technologies, Inc. Isolation using an antireflective coating
US6475925B1 (en) * 2000-04-10 2002-11-05 Motorola, Inc. Reduced water adsorption for interlayer dielectric
US6562544B1 (en) * 1996-11-04 2003-05-13 Applied Materials, Inc. Method and apparatus for improving accuracy in photolithographic processing of substrates
US6627554B1 (en) * 1999-07-15 2003-09-30 Fujitsu Limited Semiconductor device manufacturing method
US6635583B2 (en) * 1998-10-01 2003-10-21 Applied Materials, Inc. Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating
US6664177B1 (en) * 2002-02-01 2003-12-16 Taiwan Semiconductor Manufacturing Company Dielectric ARC scheme to improve photo window in dual damascene process
US6682996B1 (en) * 2002-06-28 2004-01-27 Cypress Semiconductor Corp. Method for forming a semiconductor structure using a disposable hardmask
US6787907B2 (en) * 2000-07-21 2004-09-07 Fujitsu Limited Semiconductor device with dual damascene wiring
US6869879B1 (en) * 2000-11-03 2005-03-22 Advancedmicro Devices, Inc. Method for forming conductive interconnects
US20050093161A1 (en) * 2002-04-12 2005-05-05 Renesas Technology Corp. Semiconductor device

Patent Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5639687A (en) * 1993-07-06 1997-06-17 Motorola Inc. Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride
US5565384A (en) * 1994-04-28 1996-10-15 Texas Instruments Inc Self-aligned via using low permittivity dielectric
US5468342A (en) * 1994-04-28 1995-11-21 Cypress Semiconductor Corp. Method of etching an oxide layer
US6072237A (en) * 1996-03-15 2000-06-06 Taiwan Semiconductor Manufacturing Company Borderless contact structure
US5840624A (en) * 1996-03-15 1998-11-24 Taiwan Semiconductor Manufacturing Company, Ltd Reduction of via over etching for borderless contacts
US5792703A (en) * 1996-03-20 1998-08-11 International Business Machines Corporation Self-aligned contact wiring process for SI devices
US6562544B1 (en) * 1996-11-04 2003-05-13 Applied Materials, Inc. Method and apparatus for improving accuracy in photolithographic processing of substrates
US6399480B1 (en) * 1997-05-22 2002-06-04 Advanced Micro Devices, Inc. Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction
US6333255B1 (en) * 1997-08-21 2001-12-25 Matsushita Electronics Corporation Method for making semiconductor device containing low carbon film for interconnect structures
US20020155698A1 (en) * 1997-08-22 2002-10-24 Micron Technologies, Inc. Isolation using an antireflective coating
US6037276A (en) * 1997-10-27 2000-03-14 Vanguard International Semiconductor Corporation Method for improving patterning of a conductive layer in an integrated circuit
US5893752A (en) * 1997-12-22 1999-04-13 Motorola, Inc. Process for forming a semiconductor device
US6174810B1 (en) * 1998-04-06 2001-01-16 Motorola, Inc. Copper interconnect structure and method of formation
US6042999A (en) * 1998-05-07 2000-03-28 Taiwan Semiconductor Manufacturing Company Robust dual damascene process
US6127089A (en) * 1998-08-28 2000-10-03 Advanced Micro Devices, Inc. Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques
US6635583B2 (en) * 1998-10-01 2003-10-21 Applied Materials, Inc. Silicon carbide deposition for use as a low-dielectric constant anti-reflective coating
US6060380A (en) * 1998-11-06 2000-05-09 Advanced Micro Devices, Inc. Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication
US20010012689A1 (en) * 1998-12-03 2001-08-09 Uzodinma Okoroanyanwu Interconnect structure with silicon containing alicyclic polymers and low-k dieletric materials and method of making same with single and dual damascene techniques
US6383918B1 (en) * 1999-03-15 2002-05-07 Philips Electronics Method for reducing semiconductor contact resistance
US6214721B1 (en) * 1999-05-27 2001-04-10 National Semiconductor Corp. Method and structure for suppressing light reflections during photolithography exposure steps in processing integrated circuit structures
US6627554B1 (en) * 1999-07-15 2003-09-30 Fujitsu Limited Semiconductor device manufacturing method
US6350679B1 (en) * 1999-08-03 2002-02-26 Micron Technology, Inc. Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry
US20010010976A1 (en) * 1999-10-29 2001-08-02 Advanced Micro Devices, Inc. Method and system for reducing ARC layer removal bamd providing a capping layer for the ARC layer
US6420280B2 (en) * 1999-10-29 2002-07-16 Advanced Micro Devices, Inc. Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer
US6222241B1 (en) * 1999-10-29 2001-04-24 Advanced Micro Devices, Inc. Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer
US6383950B1 (en) * 2000-02-23 2002-05-07 Advanced Micro Devices, Inc. Insulating and capping structure with preservation of the low dielectric constant of the insulating layer
US6362091B1 (en) * 2000-03-14 2002-03-26 Intel Corporation Method for making a semiconductor device having a low-k dielectric layer
US6475925B1 (en) * 2000-04-10 2002-11-05 Motorola, Inc. Reduced water adsorption for interlayer dielectric
US6350700B1 (en) * 2000-06-28 2002-02-26 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6787907B2 (en) * 2000-07-21 2004-09-07 Fujitsu Limited Semiconductor device with dual damascene wiring
US6869879B1 (en) * 2000-11-03 2005-03-22 Advancedmicro Devices, Inc. Method for forming conductive interconnects
US6664177B1 (en) * 2002-02-01 2003-12-16 Taiwan Semiconductor Manufacturing Company Dielectric ARC scheme to improve photo window in dual damascene process
US20050093161A1 (en) * 2002-04-12 2005-05-05 Renesas Technology Corp. Semiconductor device
US6682996B1 (en) * 2002-06-28 2004-01-27 Cypress Semiconductor Corp. Method for forming a semiconductor structure using a disposable hardmask

Also Published As

Publication number Publication date
US20020079558A1 (en) 2002-06-27
US7172960B2 (en) 2007-02-06
US20060094251A1 (en) 2006-05-04
US7291552B2 (en) 2007-11-06

Similar Documents

Publication Publication Date Title
US7544602B2 (en) Method and structure for ultra narrow crack stop for multilevel semiconductor device
US20010000034A1 (en) Damascene process with anti-reflection coating
JP2003023069A (en) Metal wiring layer formation method for semiconductor element
US6593223B1 (en) Method of forming dual damascene structure
US7064044B2 (en) Contact etching utilizing multi-layer hard mask
US7291552B2 (en) Multi-layer film stack for extinction of substrate reflections during patterning
KR20030024551A (en) Semiconductor device and manufacturing method thereof
US6734116B2 (en) Damascene method employing multi-layer etch stop layer
US6100158A (en) Method of manufacturing an alignment mark with an etched back dielectric layer and a transparent dielectric layer and a device region on a higher plane with a wiring layer and an isolation region
US20070018341A1 (en) Contact etching utilizing partially recessed hard mask
US6214721B1 (en) Method and structure for suppressing light reflections during photolithography exposure steps in processing integrated circuit structures
US7183202B2 (en) Method of forming metal wiring in a semiconductor device
US6680248B2 (en) Method of forming dual damascene structure
JP2002319619A (en) Semiconductor device and etching method
KR20020051715A (en) Manufacturing method of semiconductor device
US7687394B2 (en) Method for forming inter-layer dielectric of low dielectric constant and method for forming copper wiring using the same
US20090160070A1 (en) Metal line in a semiconductor device
US20030044726A1 (en) Method for reducing light reflectance in a photolithographic process
US20070049005A1 (en) Method for forming dual damascene pattern in semiconductor manufacturing process
US6780763B2 (en) Method for fabricating semiconductor device capable of improving gap-fill property
US7704820B2 (en) Fabricating method of metal line
US7314813B2 (en) Methods of forming planarized multilevel metallization in an integrated circuit
US7112537B2 (en) Method of fabricating interconnection structure of semiconductor device
KR100613384B1 (en) Method of forming interconnection line for semiconductor device
US20050142872A1 (en) Method of forming fine pattern for semiconductor device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION