US 20060097341 A1
A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.
1. A phase change memory comprising:
an insulating material;
a trench formed in said insulating material, said trench having inclined sidewalls; and
a phase change material in said trench.
2. The memory of
3. The memory of
4. The memory of
5. The memory of
6. The memory of
7. The memory of
8. The memory of
9. The memory of
10. The memory of
11. A method comprising:
forming a dielectric layer;
forming a trench in said dielectric layer having inclined sidewalls; and
forming a phase change material in said trench.
12. The method of
13. The method of
14. The method of
15. The method of
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17. The method of
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The present invention relates to phase change memories.
Phase change memories use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated with two different crystallographic structures of the material and variations thereof, such as an amorphous, disordered phase and a crystalline or polycrystalline, ordered phase. The two phases are hence associated to resistivities of considerably different values where the more disordered phases are higher in resistivity and the crystalline are lower in resistivity.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. The currently most promising chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks and has also been proposed for mass storage.
In the chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
Phase change can be obtained by locally increasing the temperature. Below 150° C., both the phases are stable. Starting from an amorphous state, and raising the temperature above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the chalcogenide. Memory devices exploiting the properties of chalcogenic material are called phase change memories.
For the understanding of the present invention, preferred embodiments thereof are now described, purely as non-limitative examples, with reference to the enclosed drawings, wherein:
In a phase change memory including chalcogenic elements as storage elements, memory cells form an array and can be arranged in rows and columns, as shown in
In each memory cell 2, the memory element 3 has a first terminal connected to a bitline 5 and a second terminal connected to a first terminal of a selection element 4. The selection element 4 has a second terminal connected to a row 6.
The selection element 4 may be implemented by any switching device, such as a PN diode, a bipolar junction transistor or a MOS transistor, or by another thin film device such as an Ovonic Threshold Switch (OTS).
A binary memory may be formed by an array of cells including a selection element called “ovonic threshold switch” (also referred to as an OTS hereinafter), connected in series with a memory element called “ovonic memory switch” (OMS). The OTS and the OMS may be formed adjacent to each other on an insulating substrate and may be connected to each other through a conducting strip. Each cell is coupled between a row and a column of a memory array and the OTS has the same function as the selection element 4 in
An ovonic threshold switch may have the characteristics shown in
The OTS and the OMS may have substantially different high resistances. The OTS may have a higher resistance than the amorphous OMS. In such case, when a memory cell is to be read, a voltage drop is applied to the cell voltage. That drop is not sufficient to trigger both the OTS and the OMS when the latter is in its high resistance condition (associated with a digital “0” state), but is sufficient to drive the OTS in its (dynamic) low resistance condition when the OMS is already in its (stable) low resistance condition (associated with a digital “1” state).
From an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the memory element and resistive electrode in contact or close proximity with the chalcogenic material, thus heating the chalcogenic material by Joule effect in the electrode and by power in the chalcogenic material iteself.
In particular, a voltage/current pulse of a suitable length (corresponding to the crystallization time) and amplitude (corresponding to the crystallization temperature) may be applied in order to make the chalcogenic material crystallize. In this condition, the chalcogenic material changes its state and switches to a low resistivity state (also called the set state).
Vice versa, in order to bring the material to the high resistivity state (also called reset state), a voltage/current pulse of suitable duration and amplitude (corresponding to the melting temperature) may be applied to cause the chalcogenic material to melt, followed by terminating the pulse with a fast terminating edge rate, thus cooling it down rapidly and quenching it in the amorphous phase.
To reduce the amount of current needed to cause the chalcogenic material to change its state, a heater may be formed by a wall structure obtained by depositing a suitable resistive material. Furthermore, the chalcogenic material may include a thin portion extending transversely to the wall structure to obtain a small contact area. Here, the selection element is implemented by a junction diode formed in a semiconductor substrate just below the memory element.
Thereafter, as shown in
Then, a spacer layer, e.g. of silicon nitride, is deposited and etched back to remove the horizontal portions of the spacer layer, leaving vertical spacers 21 extending along the vertical surfaces of the openings 20. These spacers 21 join the first nitride layer 18 at the bottom and form, with the first nitride layer 18, a protective region 22. Thus, the structure of
Thereafter, as shown in
Here, the sheath layer 24 and the protective region 22 isolate the resistive layer 23 from the silicon oxide of the first and second oxide layers 19, 25 and prevent oxidation of the resistive layer 23.
The structure is then planarized by CMP, thus removing all portions of the second oxide layer 25, of the sheath layer 24 and of the resistive layer 23 above the openings 20, as shown in
Then, as shown in
Subsequently, the adhesion layer 28 and the mold layer 27 are etched through the apertures 30, so as to open microtrenches 31. The exposed portion of the adhesion layer 28 is preliminarily removed and then the mold layer 27 is etched using a combined chemical and physical plasma etch. In particular, an etchant mixture of a boron halide, preferably BCl3, and chlorine Cl2 may be supplied to the wafer 10. The etchant mixture may comprise also a small amount of CHF3, to increase the etching rate. For example, a suitable etchant mixture comprises 90% to 40% of BCl3 (preferably 58%), 49% to 10% of Cl2 (preferably 38%), and less than 10% of CHF3 (preferably 4%).
Plasma containing BCl3 is highly sputtering. Bonding inside the mold layer 27 (Si—N bonding, in this case) is weak enough to break up under ion bombarding with boron ions. Also, possible metallic residues of the adhesion layer 28 may be removed by sputtering. Moreover, the sputtering yield of BCl3 depends on the impinging angle of the boron ions and is maximum at around 70°. So, under the prevailing sputtering regime of BCl3, the etched portions of the mold layer 27 slope and tend to converge to that angle which maximizes the sputtering yield. In this condition, the greatest energy gain is achieved. Accordingly, the inclined walls 32 of the mold layer 27 and the wafer surface form an angle A which is close to the angle of maximum sputtering yield. More precisely, the angle A is about 60°-70° and also accounts for chemical etching, as explained hereinafter.
In fact, BCl3 etches the mold layer 27 chemically as well. In particular, chemical etching rate of BCl3 is rather low, however, enough to increase overall etching rate. Moreover, BCl3 has a negligible polymerization rate, so that polymer deposition on the walls is substantially prevented. Cl2 and CHF3 further increase chemical etching rate.
The slope of the walls 32 of the microtrench 31 depends on both physical (sputtering) and chemical etching, as already explained; however, the profile of the microtrench 31 may be controlled primarily through the physical effect and secondarily through the chemical effect, since sputtering prevails. One advantageous slope of the walls 32 is about 65°.
Thereby, the microtrench 31 has a sublithographic bottom width W1 (
After removing the mask 29, an Ovonic Memory Switch/Ovonic Threshold Switch stack is deposited. A first first chalcogenic layer 35, for example of Ge2Sb2Te5 with a thickness of 60 nm, is deposited conformally as shown in
Then, a barrier layer 37 (e.g., Ti/TiN) and a planarizing layer 38 (e.g., a metal layer, such as CVD TiN, TiSiN or other metal layer having planarizing features) are deposited. Deposition of the planarizing layer 38 may give rise to the formation of submerged keyholes 38 a, as shown in the figures, however, these keyholes are not detrimental to the operation of the completed device.
The stack of layers 42-40, 38, 37, 35, 28 and 27 is then patterned to form “dots” 44 (
Then, a second insulating layer 45 (e.g. of silicon dioxide) is deposited, as shown in
As shown in
The first elongated wall element 23 a (on the left, in the cross-section of
As visible in
Even if the microtrench 31 is not exactly perpendicular to the first elongated wall element 23 a, and the contact area 36 is no more rectangular, it still has sublithographic dimensions.
The volume of the thin portion 35 a of the first chalcogenic layer 35 that extends above the contact area 36 forms a phase change region intended to store information.
By virtue of the mold region 27, the memory region 35 has a bottom portion forming the thin portion 35 a and a top portion extending on the mold region 27. An annular inclined portion of the memory region 35 extends along the tapered walls of the mold region 27 and connects the bottom and the top portion of the memory region 35.
Furthermore, each stack 44 comprises an adhesion layer 28 on the mold region 27, a first chalcogenic region 35, a barrier region 37, a planarizing region 38, a bottom electrode 40, a switching region 41 and a top electrode 42.
In some embodiments, the decoding elements may be accommodated in the substrate below the array, thus resulting in a considerable saving in the occupied area.
The described structure may be repeated more times on different levels, thus allowing the formation of stacked arrays, with a further reduction in the memory bulk.
This solution may, in some embodiments, afford an improved thermal isolation of the first chalcogenic regions 35, and in particular, the phase change portion thereof, from the respective row lines 13.
Reference is made to
Then, analogously to the embodiment of
Thereafter, the barrier layer 37 (
Afterwards, the layers 42-40, 38, 37, 35, 28 and 27 is defined to form the stacks 44, whose shape is visible in
According to this embodiment, after defining the stacks 44, each microtrench 31 extends for the whole width of the stack 44 (wherein the term width here denotes the dimension perpendicular to the row lines 13) so that in the cross-section of
With the alternative structure of
Then, the wafer 10 is planarized by CMP and planarization stops when reaching the metal material of the planarizing layer 38 (
According to still another embodiment, the second wall element 23 b (on the right in
The chalcogenic materials used may be varied from those disclosed herein which are only exemplary, and any chalcogenic material or mixture of materials, including multiple layers known in the art and suitable to store information depending on its physical state (for first chalcogenic layer 35) and to operate as a switch (for second chalcogenic layer 341) may be used. Moreover any barrier layer or mixture of barrier layers suitable to separate and seal chalcogenic materials may be used, such as carbon, which may provide better endurance and more stable operating characteristics such as threshold current, voltage, and leakage.
The microtrenches 31 a with sloped walls create a small contact area 36. However, it is possible to form trenches in the mold layer 27 with substantially vertical walls. If desired, it is also possible to remove the top portion of the first chalcogenic layer 35, leaving only the thin portion 35 a.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.