US20060108069A1

US20060108069A1 - Plasma reaction chamber and captive silicon electrode plate for processing semiconductor wafers

Info

Publication number: US20060108069A1
Application number: US10/993,136
Authority: US
Inventors: James Gernert
Original assignee: Samsung Electronics Co Ltd; Samsung Austin Semiconductor LLC
Current assignee: Samsung Electronics Co Ltd; Samsung Austin Semiconductor LLC
Priority date: 2004-11-19
Filing date: 2004-11-19
Publication date: 2006-05-25
Also published as: KR20060056216A

Abstract

A plasma processing system for etching a semiconductor wafer comprises: 1) a plasma chamber in which the semiconductor wafer may be mounted; 2) an upper ring capable of being mounted on an upper opening of the plasma chamber, wherein a central portion of the upper ring forms a hole; and 3) an electrode plate having a plurality of vias therethrough. The electrode plate is disposed in the hole in the upper ring, wherein the central portion of the upper ring further forms a shelf for supporting the electrode plate in the hole.

Description

TECHNICAL FIELD OF THE INVENTION

The present invention generally relates to plasma processing systems and, more specifically, to a plasma reaction chamber with a captive silicon electrode for dry plasma etching of semiconductor wafers.

BACKGROUND OF THE INVENTION

Plasma processing techniques, such as dry plasma etching, reactive ion etching, and ion milling techniques, provide numerous advantages over traditional chemical etching of semiconductor wafers. For example, plasma etching has a vertical etch rate that is much greater than the horizontal etch rate. This provides good control over the resulting aspect ratio (i.e., the height to width ratio of the resulting notch) of the etched features. Thus, plasma etching forms very fine features with high aspect ratios in very thin films.
During the plasma etching process, large amounts of energy are added to a gas at relatively low pressure, thereby ionizing the gas. This forms plasma above the masked surface of the substrate (i.e., the semiconductor wafer). An electrical field is established between an electrode at the top of the etching chamber and the semiconductor wafer at the bottom of the etching chamber. The electrical potential of the substrate is adjusted so that charged particles in the plasma are propelled towards the substrate and collide substantially perpendicularly upon the wafer surface. The energy of the impact removes materials in the unmasked regions of the wafer surface. Reactive ion etching improves this process by using gases that are chemically reactive with the material being etched. Reactive ion etching combines the kinetic etching effects of the plasma particles with the chemical etching effect of the gas.
The effectiveness of the etching process is greatly affected by the components of the etching chamber. Uniform etching rates may be achieved across the surface of the wafer by evenly distributing the plasma over the wafer surface. U.S. Pat. Nos. 4,595,484, 4,792,378, 4,820,371, and 4,960,488 disclose showerhead electrodes for distributing gas through holes in the electrodes. These patents generally describe gas dispersion disks having an arrangement of apertures tailored to provide a uniform flow of gas vapor to a semiconductor wafer.
However, the showerhead electrodes that are commonly used in the industry are prohibitively expensive. For example, LAM Research Corporation provides a one-piece showerhead assembly comprising an electrode and a retaining ring. The showerhead assembly is inserted into the top of the etching chamber and costs about $4500. This is a consumable item that greatly increases the cost of using a dry plasma etching system.
Therefore, there is a need in the art for an improved dry plasma etching system that costs less to operate than conventional dry plasma etching systems. In particular, there is a need in the art for an improved dry plasma etching system that uses a less expensive showerhead electrode.

SUMMARY OF THE INVENTION

To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a plasma processing system for etching a semiconductor wafer. According to an advantageous embodiment of the present invention, the plasma processing system comprises: 1) a plasma chamber in which the semiconductor wafer may be mounted; 2) an upper ring capable of being mounted on an upper opening of the plasma chamber, wherein a central portion of the upper ring forms a hole; and 3) an electrode plate having a plurality of vias therethrough. The electrode plate is disposed in the hole in the upper ring, wherein the central portion of the upper ring further forms a shelf for supporting the electrode plate in the hole.
According to one embodiment of the present invention, the shelf is formed below the hole on the side of the upper ring towards the interior of the plasma chamber.
According to another embodiment of the present invention, the shelf encircles the hole and projects inward towards a center of the hole.
According to still another embodiment of the present invention, the shelf has an upper surface capable of supporting a perimeter region of a lower surface of the electrode plate when the electrode plate is inserted into the hole.
According to yet another embodiment of the present invention, the plasma processing system further comprises a retaining ring disposed on an upper surface of the upper ring, wherein the retaining ring encircles and overlaps the hole and holds the electrode plate in place in the hole.
According to a further embodiment of the present invention, the retaining ring is made of aluminum.
According to a still further embodiment of the present invention, the electrode plate is made of a semiconductor material.
According to a yet further embodiment of the present invention, the plasma processing system further comprises an O-ring capable of forming a gas-tight seal between the retaining ring and the electrode plate.
In one embodiment of the present invention, the O-ring is disposed in a groove formed in the retaining ring.
In another embodiment of the present invention, the O-ring is disposed in a groove formed in the electrode plate.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:
FIG. 1 illustrates a cross-sectional view of selected portions of a conventional dry plasma etching system according to an exemplary embodiment of the prior art;
FIG. 2 illustrates a cross-sectional view of selected portions of an improved dry plasma etching system and an improved showerhead electrode assembly according to an exemplary embodiment of the present invention;
FIG. 3 illustrates in greater detail the cross-sectional view of selected portions of the dry plasma etching system and the improved showerhead electrode assembly in FIG. 2 according to a first exemplary embodiment of the present invention; and
FIG. 4 illustrates in greater detail the cross-sectional view of selected portions of the dry plasma etching system and the improved showerhead electrode assembly according to a second exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 4, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged plasma processing system.
FIG. 1 illustrates a cross-sectional view of selected portions of conventional plasma etching system 100 according to an exemplary embodiment of the prior art. Plasma etching system 100 comprises plasma chamber 105, which encloses empty space 106. Semiconductor wafer 115 is mounted on support 120 on the bottom wall (floor) of plasma chamber 105. Plasma etching system 100 further comprises showerhead electrode assembly 130 and housing 110. Showerhead electrode assembly 130 comprises electrode plate 131 (diagonal line shading) and graphite ring 132 (lattice shading), which are bonded together to form showerhead electrode assembly 130 as a single unit. Showerhead electrode assemblies similar to showerhead electrode assembly 130 are well-known to those skilled in the art and may include, for example, the showerhead electrode assemblies provided by LAM Research Corporation as part of the 2300 Exelan® dielectric etch system.
Upper ring 107 of plasma chamber 105 comprises inner (or lower) surface 108 and outer (or upper) surface 109. Upper ring 107 may comprise, for example a ring assembly of quartz and/or silicon carbide and/or ceramic. Upper ring 107 may be removably mounted on the top of plasma chamber 105 to thereby close the chamber. A portion of the center of upper ring 107 forms a circular opening into which showerhead electrode assembly 130 is inserted. The circular opening in upper ring 107 is encircled by retaining ring 135 (dotted shading). When showerhead electrode assembly 130 is inserted into the circular opening, graphite ring 132 is pressed between retaining ring 135 and housing 110. Graphite ring 132 and retaining ring 135 are mounted on, and held in place by, a plurality of threaded bolts 136, including exemplary bolts 136 a and 136 b, mounted up to housing 110. Bolts 136 hold showerhead electrode assembly 130 in place in the circular opening in upper ring 107 and provide a gas-tight seal between housing 110 and graphite ring 132. Screws 142, including exemplary screws 142 a and 142 b hold upper ring 107 to housing 110.
Multiple baffle plates (dotted shading) are disposed on top of electrode plate 131, including exemplary baffle plate 140. Holes or vias 141 are formed in baffle plate 140. Similarly, holes or vias 133 are formed in electrode plate 131. Vias 133 and 141 enable ionizing gas, enclosed in space 111 above baffle plate 140 by housing 110, to flow through the baffle plates and electrode plate 131 into space 106 enclosed by plasma chamber 105. The movement of the ionizing gas from space 111 to space 106 is indicated by the dotted arrows pointing downward in FIG. 1.
Vias 141 in baffle plate 140 are not aligned with the vias in the baffle plate below baffle plate 140. Similarly, the vias in the lower baffle plate are not aligned with vias 133 in electrode plate 131. This misalignment forces the ionizing gas to disperse evenly as the gas flows through the two baffle plates and electrode plate 131. The ionized gas forms plasma in the region above semiconductor wafer 115 in space 106. An electrical potential is introduced between electrode plate 131 and semiconductor wafer 115. This electrical potential is adjusted so that charged particles in the plasma are propelled towards the upper surface of semiconductor wafer 115 and collide substantially perpendicularly upon the upper surface of semiconductor wafer 115. The energy of the impact removes materials in the unmasked regions of the upper surface of semiconductor wafer 115.
For convenience, the upper components of plasma etching system 100 may be assembled in an upside down position prior to being placed on top of plasma chamber 105. Initially, housing 110 may be placed upside down and the baffle plates are put in place. Next, showerhead electrode assembly 130 is placed on top of the baffle plates. Retaining ring 135 is then placed on top of showerhead electrode assembly 130 and is bolted into housing 110 by bolts 136. Finally, upper ring 107 is placed on top of retaining ring 135 and is bolted to housing 110 by bolts 142. The assembled upper components are then flipped over and mounted on top of plasma chamber 105. In that position, upper ring 107 and retaining ring 135 prevent showerhead assembly 130 from dropping into plasma chamber 105.
Electrode plate 131 is worn away throughout the process, thereby requiring replacement. Showerhead electrode assembly 130 is therefore a consumable that increases the cost of operating plasma etching system 100. The present invention improves upon plasma etching system 100 by reducing the cost of showerhead electrode assembly 130.
FIG. 2 illustrates a cross-sectional view of selected portions of improved dry plasma etching system 200 and an improved showerhead electrode assembly according to an exemplary embodiment of the present invention. Plasma etching system 200 comprises plasma chamber 205, which encloses empty space 206. Semiconductor wafer 115 is mounted on support 120 on the bottom wall (floor) of plasma chamber 205. Plasma etching system 200 further comprises a two-piece showerhead electrode assembly and housing 210. The two-piece showerhead electrode assembly comprises electrode plate 231 (diagonal line shading) and retaining ring 235 (dotted shading) Retaining ring 235 is preferably made from aluminum.
Upper ring 207 of plasma chamber 205 comprises inner (or lower) surface 208 and outer (or upper) surface 209. A portion of the center of upper ring 207 forms a circular opening into which electrode plate 231 is lowered. However, upper ring 207 also forms circular shelf 250, which encircles, and projects into, the circular opening in upper ring 207. The outer perimeter region of the bottom surface of electrode plate 231 rests upon, and is supported by, the upper surface of shelf 250.
Retaining ring 235 (dotted shading) is mounted on housing 210 and is held in place by a plurality of threaded bolts 236, including exemplary bolts 236 a and 236 b. Electrode plate 231 is then placed in upper ring 207 and upper ring 207 is bolted to housing 210 by a plurality of threaded bolts 242, including exemplary bolts 242 a and 242 b. Bolts 242 tighten electrode plate 231 between retaining ring 235 and upper ring 207, providing a gas-tight seal between retaining ring 235 and electrode plate 231.
As in FIG. 1, baffle plates are disposed on top of electrode plate 231, including exemplary baffle plate 140. Holes or vias 141 are formed in baffle plate 140. Similarly, holes or vias 233 are formed in electrode plate 231. Vias 233 and 141 enable ionizing gas, enclosed in space 211 above baffle plate 140 by housing 210, to flow through the two baffle plates and electrode plate 231 into space 206 enclosed by plasma chamber 205. The movement of the ionizing gas from space 211 to space 206 is indicated by the dotted arrows pointing downward in FIG. 2.
As before, vias 141 in baffle plate 140 are not aligned with the vias in the baffle plate below baffle plate 140. Similarly, the vias in the lower baffle plate are not aligned with vias 233 in electrode plate 231. This misalignment forces the ionizing gas to disperse evenly as the gas flows through the baffle plates and electrode plate 231. The ionized gas forms plasma in the region above semiconductor wafer 115 in space 206. As in FIG. 1, an electrical potential is introduced between electrode plate 231 and semiconductor wafer 115. This electrical potential is adjusted so that charged particles in the plasma are propelled towards the upper surface of semiconductor wafer 115 and collide substantially perpendicularly upon the upper surface of semiconductor wafer 115. The energy of the impact removes materials in the unmasked regions of the upper surface of semiconductor wafer 115.
FIG. 3 illustrates in greater detail the cross-sectional view of selected portions of dry plasma etching system 200 and the improved showerhead electrode assembly according to a first exemplary embodiment of the present invention. O-ring 305 is placed in a groove formed in retaining ring 235. When retaining ring 235 is pressed down on silicon electrode plate 231, O-ring 305 forms a seal that captures any process gas and channels the captured gas through vias 233 in silicon electrode plate 231. The groove in which O-ring 305 is disposed is recessed so that, when compressed, silicon electrode plate 231 contacts retaining ring 235, which is grounded. Retaining ring 235 is anodized in such a way that silicon electrode plate 231 conducts to a ground plane.
FIG. 4 illustrates in greater detail the cross-sectional view of selected portions of dry plasma etching system 200 and the improved showerhead electrode assembly according to a second exemplary embodiment of the present invention. FIG. 4 is identical in most respect to FIG. 3, except that O-ring 405 is placed in a groove formed in silicon electrode plate 231. When retaining ring 235 is pressed down on silicon electrode plate 231, O-ring 405 forms a seal that captures any process gas and channels the captured gas through vias 233 in silicon electrode plate 231. As in FIG. 3, the groove in which O-ring 405 is disposed is recessed so that, when compressed, silicon electrode plate 231 contacts retaining ring 235, which is grounded.
Although the present invention has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.

Claims

1. A plasma processing system for etching a semiconductor wafer comprising:

a plasma chamber in which said semiconductor wafer may be mounted;

an upper ring capable of being mounted on an upper opening of said plasma chamber, wherein a central portion of said upper ring forms a hole; and

an electrode plate having a plurality of vias therethrough, wherein said electrode plate is disposed in said hole in said upper ring, wherein said central portion of said upper ring further forms a shelf for supporting said electrode plate in said hole.

2. The plasma processing system as set forth in claim 1, wherein said shelf is formed on an interior side in said hole in said upper ring.

3. The plasma processing system as set forth in claim 2, wherein said shelf encircles said hole and projects inward towards a center of said hole.

4. The plasma processing system as set forth in claim 3, wherein said shelf has an upper surface capable of supporting a perimeter region of a lower surface of said electrode plate when said electrode plate is inserted into said hole.

5. The plasma processing system as set forth in claim 4, further comprising a retaining ring disposed on an upper surface of said upper ring, wherein said retaining ring encircles and overlaps said hole and holds said electrode plate in place in said hole.

6. The plasma processing system as set forth in claim 5, wherein said retaining ring is made of aluminum.

7. The plasma processing system as set forth in claim 5, wherein said electrode plate is made of a semiconductor material.

8. The plasma processing system as set forth in claim 5, further comprising an O-ring capable of forming a gas-tight seal between said retaining ring and said electrode plate.

9. The plasma processing system as set forth in claim 8, wherein said O-ring is disposed in a groove formed in said retaining ring.

10. The plasma processing system as set forth in claim 8, wherein said O-ring is disposed in a groove formed in said electrode plate.

11. The plasma processing system as set forth in claim 5, wherein said electrode plate and said hole in said upper ring are circular.