Recherche Images Maps Play YouTube Actualités Gmail Drive Plus »
Les utilisateurs de lecteurs d'écran peuvent cliquer sur ce lien pour activer le mode d'accessibilité. Celui-ci propose les mêmes fonctionnalités principales, mais il est optimisé pour votre lecteur d'écran.


  1. Recherche avancée dans les brevets
Numéro de publicationUS20060113583 A1
Type de publicationDemande
Numéro de demandeUS 11/332,908
Date de publication1 juin 2006
Date de dépôt17 janv. 2006
Date de priorité25 avr. 2003
Autre référence de publicationCN1947251A, EP1721336A2, US6998670, US20040212005, US20060118856, WO2005081798A2, WO2005081798A3
Numéro de publication11332908, 332908, US 2006/0113583 A1, US 2006/113583 A1, US 20060113583 A1, US 20060113583A1, US 2006113583 A1, US 2006113583A1, US-A1-20060113583, US-A1-2006113583, US2006/0113583A1, US2006/113583A1, US20060113583 A1, US20060113583A1, US2006113583 A1, US2006113583A1
InventeursBohumil Lojek
Cessionnaire d'origineAtmel Corporation
Exporter la citationBiBTeX, EndNote, RefMan
Liens externes: USPTO, Cession USPTO, Espacenet
Twin EEPROM memory transistors with subsurface stepped floating gates
US 20060113583 A1
A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word lines. The twin EEPROMs share a common subsurface electrode by having diffused control lines and a diffused bit line. The two EEPROMs are symmetric across the common electrode.
Previous page
Next page
1. In an EEPROM transistor in a memory array of the EEPROM type fabricated in a silicon wafer with an oxide coating on the wafer surface, with a source, drain and floating gate, the improvement comprising a step in floating gate extending at least partially below the wafer surface and a first capacitor control element with first and second capacitor plates, the first plate connected to the floating gate.
2. The transistor of claim 1 having a second capacitor connected to a source or drain electrode.
3. The transistor of claim 1 wherein said second capacitor has plates associated with a word line and a bit line of the memory array.
4. The transistor of claim 1 wherein said step has top and bottom corners.
  • [0001]
    This is a divisional of pending U.S. patent application Ser. No. 10/785,160 filed Feb. 23, 2004 which is a continuation-in-part of prior application Ser. No. 10/423,637 filed Apr. 25, 2003, a continuation-in-part of prior application Ser. No. 10/465,718 filed Jun. 18, 2003, and a continuation-in-part of prior application Ser. No. 10/680,355, filed Oct. 6, 2003. All four applications are herewith incorporated by reference in their entirety.
  • [0002]
    The invention relates to non-volatile memory transistors and, in particular, to a compact arrangement of such memory cells for an array and a method of making them.
  • [0003]
    In prior application Ser. No. 10/423,637 entitled “Mirror Image Memory Cell Transistor Pairs Featuring Poly Floating Spacers,” as well as in prior application Ser. No. 10/465,718 entitled “Mirror Image Non-Volatile Memory Cell Transistor Pairs with Single Poly Layer,” both assigned to the assignee of the present invention, B. Lojek described an arrangement of non-volatile MOS memory transistors for a memory array wherein symmetric pairs of transistors were built in a memory array. Transistor pairs shared an electrode in a common well, such as a drain electrode, but were otherwise completely independent. The pair was manufactured between a pair of isolation regions and sharing the same substrate region, almost as if a single transistor were constructed there.
  • [0004]
    In the prior art, single MOS floating gate transistors that stored two data bits have been devised as a way to achieve compactness. Since millions of data bits are frequently stored in non-volatile memory arrays, small savings of space are multiplied significantly over the array. In prior application Ser. No. 10/327,336 entitled “Multi-Level Memory Cell with Lateral Floating Spacers,” assigned to the assignee of the present invention, B. Lojek described how two spacers, on opposite sides of a conductive gate, behave as independent charge storage regions for separate binary data, thereby allowing a single non-volatile MOS transistor to store two binary bits. Each memory cell is connected to two bit lines and one word line. The bit lines are phased so that during a single clock cycle, first one bit line is active and then the other while a word line is active for the entire cycle. In this manner, both storage areas may be accessed for a read or write operation in a single clock cycle.
  • [0005]
    In U.S. Pat. No. 6,043,530 to M. Chang, a MOS memory transistor construction is shown employing band-to-band tunneling. In U.S. Pat. No. 6,323,088 to F. Gonzalez et al., a multibit charge storage transistor addressing scheme is shown with phased bit lines.
  • [0006]
    In the prior art, multibit charge storage structures are known that achieve good data density in a memory array without giving up valuable chip space. One of the problems that is encountered as density increases is that the amount of crosstalk between storage sites increases. Because the charge storage structures are so small, one charge storage location can sometimes influence another. On the other hand, separation of charge storage sites gives up chip space. The ultimate separation is one dedicated transistor for each data bit. Accordingly, an object of the invention is to provide good separation for data bits afforded by dedicated transistors yet achieve the compactness of multibit charge storage structures for a non-volatile memory array.
  • [0007]
    The above object has been achieved with a memory array having cells with twin EEPROM memory transistors that occupy a space almost the same size as a single EEPROM memory transistor. The twin transistors of each cell are symmetrically arranged in a common substrate and feature a single poly layer, with portions used as floating gates that are stepped below the level of the substrate surface, yet insulated from the substrate by thin oxide. The floating gate electrically communicates with a subsurface electrode that participates in charge transfer to the floating gate. The usual EEPROM control gate is replaced by a first capacitor wherein the same poly portion used to form the floating gate extends to form a second plate of the first capacitor. The first plate of the first capacitor is a control line connected to a phased signal source whereby phasing of plates of the twin cells allows each transistor to act independently. The drain of each transistor is connected to one plate of a second capacitor and to a bit line while the second plate is connected to a word line.
  • [0008]
    By stepping the floating gate into the substrate and forming a floating gate corner in the substrate, the intensity of electric field from a subsurface electrode will increase and enhance tunneling action.
  • [0009]
    FIG. 1 is an electrical schematic drawing of memory cells forming the core of a memory array of the present invention.
  • [0010]
    FIG. 2 is a side sectional view of an early manufacturing step for a memory transistor in the memory cells of FIG. 1.
  • [0011]
    FIG. 3 is a top view of a mask for making a substrate step shown in the sectional view of FIG. 2.
  • [0012]
    FIG. 4 is a top view of a layout in an early manufacturing stage of twin memory cells shown in FIG. 1.
  • [0013]
    FIG. 5 is a side sectional view taken along lines 5-5 in FIG. 4.
  • [0014]
    FIG. 6 is a side sectional view taken along lines 6-6 in FIG. 4.
  • [0015]
    FIG. 7 is a top view of a layout in an intermediate manufacturing stage of twin memory cells shown in FIG. 1.
  • [0016]
    FIG. 8 is a side sectional view taken along lines 8-8 in FIG. 7.
  • [0017]
    FIG. 9 is a side sectional view following FIG. 8 at a later stage in manufacturing.
  • [0018]
    FIG. 10 is a top view of a contact mask superposed on the top view of FIG. 7, with conductor shading for the single polysilicon layer.
  • [0019]
    FIG. 11 is an electrical schematic drawing of twin symmetric memory cells shown in FIG. 1 redrawn for comparison with FIG. 10, including locations of contacts shown in FIG. 10.
  • [0020]
    With reference to FIG. 1, a memory cell 13 in a memory array 10 is seen to have first and second non-volatile memory transistors 15 and 115, respectively. The first memory transistor 15 has a drain 21 connected to select capacitor 19, a floating gate 23 connected to control capacitor 29 and a source 25 connected to the source contact 27.
  • [0021]
    Select capacitor 19 has a first electrode 31 connected to drain 21 of first memory transistor 15 and also connected to the first bit line, BL1. The second electrode 33 of select capacitor 19 is connected to word line WL1. The word line WL1 is extended from first electrode 31 along line 35 into another cell. The floating gate 23 of memory transistor 15 is connected to a first electrode 37 of control capacitor 29, while second electrode 39 is connected to a first control line terminal 41. A pulse on terminal 41 charges the second electrode 39, causing induced charge to appear on first electrode 37 which forms a floating gate together with electrode 23. This is one of two ways in which charge appears on the floating gate 23. Another way for charge to appear is by tunneling or electron injection from source or drain electrode 21 and 25. When one voltage is applied to bit line BL1 and another voltage is applied at source contact 27 charge may be transferred onto the floating gate 23 by tunneling charge transfer mechanisms. Just as the word line WL1 extends into another memory cell in the same column along line 35, bit line BL1 is also extended into a memory cell in the same row along line 43.
  • [0022]
    The second memory transistor 115 is symmetric with first memory transistor 115 relative to source contact 27. The second memory transistor 115 has a floating gate 123 which may be charged by control capacitor 129. Memory transistor 115 has a drain electrode 121 connected to a first plate 131 of select capacitor 119 and a source electrode 125 connected to source contact 27. The first plate 131 is also connected to the bit line BL1. The second plate of capacitor 119 is connected to the word line WL2. The word line WL2 is extended from the first electrode 131 along line 135 to a control capacitor (not shown) into a neighboring cell in the same column. The bit line 43 similarly extends from the first electrode of select capacitor 119 into a neighboring cell in the same row.
  • [0023]
    Memory cell 13 is typical of the memory cells in the memory array 10. Each cell is seen to have twin non-volatile memory transistors that are symmetric about a source contact, such as source contact 27. The two memory transistors have floating gates associated with two control capacitors on the one hand and have drain or source electrodes associated with two select capacitors on the other hand. The two control line terminals 41 and 141 associated with the control capacitors allow programming of the two memory transistors so that each transistor is independent of the other, even though they share a common source electrode at source contact 27 and also share bit line BL1. Memory cell 13 is associated with two word lines, WL1 and WL2, as well as one bit line, BL1.
  • [0024]
    With reference to FIG. 2, a silicon p-type wafer provides a substrate doped to have a p-well with a surface 56, upon which a thin layer of oxide 57 is grown. The oxide layer has a thickness of approximately 100 angstroms. The oxide is covered with a thick photoresist layer 51 and then patterned with a mask 52, shown in FIG. 3. The mask is approximately square with a dimension near the lower limit of resolution of photolithography. The photoresist is then etched so that well-defined steps 53 and 54 form a depression 58 with upper and lower corners to a depth of approximately 500 angstroms below the substrate surface 56. The facing corners of steps 53 and 54 will enhance the electric field near the floating gates of twin memory transistors extending into the planar surface of the wafer. Corners at the top and bottom of each step are important for increasing electric field intensity to enhance tunneling. The floating gates are built upon the steps but insulated from the substrate by gate oxide 57.
  • [0025]
    With reference to FIG. 4, a mask set is shown defining the active regions of two memory cells. The mask set includes masks 52 and 55 for defining common source electrodes of twin EEPROMs and masks 62 and 64, as well as masks 66 and 68 for defining control lines. Two linear masks define parallel bit lines BL1 and BL2. The areas surrounding the masks are isolated by a shallow trench isolation, as shown in FIG. 5. Trenches in p-well or p-substrate 50 (FIG. 6) of a p-type silicon wafer substrate are filled with dielectric insulator material 72, 74, 76, 78, and 80 (FIG. 5), typically silicon dioxide. The areas that are not dielectric material are subject to doping either by diffusion or implantation. This allows the memory cells to have diffused bit lines BL1 and BL2.
  • [0026]
    Turning to FIG. 6, when doping of subsurface regions is complete, the substrate is coated with oxide, previously described in FIG. 2 but not shown in FIG. 6, and the depression 58 is formed below the surface 56 of substrate p-well substrate 50. The depression 58 has steps or corners 53 and 54 that will form part of floating gates of memory transistors. The steps or corners 53 and 54 may be seen in FIG. 4 also.
  • [0027]
    With reference to FIG. 7, the diffused regions previously described with reference to FIG. 4 may be seen. The diffused regions include the areas where source masks 52 and 55 as well as the control line diffusions 62, 64, 66, and 68. The diffused bit lines BL1 and BL2 are also seen. All of these structures lie below the surface of the p-well, or p-substrate, including steps or corners 53 and 54.
  • [0028]
    A layer of poly is deposited over the substrate surface and then etched leaving floating members 82, 84, 86, and 88. Portions of these floating members will become floating gates of twin EEPROM transistors. The floating members have portions extending over the control line diffusions 62 and 64, as well as control line diffusions 66 and 68. Portions of the floating members also extend over the source mask regions 52 and 55. The poly layer is also used to define word lines WL1 and WL2, spaced apart and lying outwardly of the cell core.
  • [0029]
    In FIG. 8, the p-well substrate 50 is seen with gate oxide layer 57 over the substrate surface including the depression 58. The poly layer deposited over the substrate has portions which define floating gates 82 and 84 that follow the contour of steps or corners 53 and 54. Outwardly of the floating gate regions 82 and 84 are poly word lines WL1 and WL2.
  • [0030]
    FIG. 9 follows FIG. 8 at a further point in the manufacturing process. Subsurface implants have been made in p-well substrate 50, particularly source implant 92, as well as drain implants 94 and 96. The subsurface bit line diffusions BL1 are also seen. The poly floating gates 82 and 84 have sidewall spacers, such as sidewall spacers 83 and 85 surrounding floating gate 82. Similarly, word lines WL1 and WL2 have sidewall spacers such as spacers 87 and 89 associated with word line WL1. After the spacers have been constructed, a layer of interlayer dielectric, ILD layer 101, is deposited over the poly one layer. The ILD layer 101 is masked and etched to create. holes that allow insertion of metal contacts 102, 104, and 106. These conductive metal contacts make contact with subsurface regions. Metal contacts 102 and 106 contact the diffused bit line BL1. Metal contact 104 contacts a common subsurface electrode 92. The relation of the metal contacts with the top view of FIG. 7 may be seen in FIG. 10.
  • [0031]
    In FIG. 10, the position of metal contacts 102, 104, and 106 may be seen. Also, contacts 112 and 114, associated with the control line diffusions 62 and 64, may be seen. Contact 104 is located in the center of mask 52 that defines a common electrode for twin side-by-side memory transistors. In other words, contact 104 is located at a plane of symmetry for the twin EEPROM transistors. In FIG. 10, the single poly layer has been shaded, with portions of the layer forming poly members 82 and 84, defining the contoured floating gates associated with the subsurface steps toward the common source electrode. Other portions of the poly one layer define the word lines WL1 and WL2, as indicated by shading. Note that the poly members 82 and 84 extend over the control line diffusions 62 and 64. These control line diffusions have metal contacts 112 and 114, respectively.
  • [0032]
    In FIG. 11 positions of the contacts of the memory cell in the top view of FIG. 10 are indicated relative to an electrical schematic of a memory cell as shown in FIG. 1. A total of five contacts is used for each cell with two contacts, 102 and 106, being on the bit line BL1. The contact 104 is associated with the common source between the twin symmetric memory transistors. The contacts 112 and 114 are associated with capacitors 29 and 129. FIG. 11 may be projected upwardly, towards FIG. 10, where a rough comparison can be made of the various circuit elements. In FIG. 10, the word line WL1 is seen to overlie the bit line BL1 but spaced apart by insulator thereby forming capacitor 19 in FIG. 11. Similarly, a portion of poly member 82 is seen to overlie control line diffusion 62 thereby forming capacitor 29 in FIG. 11.
Citations de brevets
Brevet cité Date de dépôt Date de publication Déposant Titre
US4649520 *7 nov. 198410 mars 1987Waferscale Integration Inc.Single layer polycrystalline floating gate
US4807188 *26 mai 198821 févr. 1989Sgs-Thomson Microelectronics S.P.A.Nonvolatile memory device with a high number of cycle programming endurance
US4814594 *7 juil. 198721 mars 1989Drexler Technology CorporationUpdatable micrographic pocket data card
US4931847 *14 juil. 19895 juin 1990Sgs-Thomson Microelectronics S.P.A.Floating gate memory with sidewall tunnelling area
US5021848 *13 mars 19904 juin 1991Chiu Te LongElectrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5026663 *21 juil. 198925 juin 1991Motorola, Inc.Method of fabricating a structure having self-aligned diffused junctions
US5067002 *31 janv. 198919 nov. 1991Motorola, Inc.Integrated circuit structures having polycrystalline electrode contacts
US5108939 *16 oct. 199028 avr. 1992National Semiconductor Corp.Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region
US5130267 *28 oct. 199114 juil. 1992Texas Instruments IncorporatedSplit metal plate capacitor and method for making the same
US5196722 *12 mars 199223 mars 1993International Business Machines CorporationShadow ram cell having a shallow trench eeprom
US5210597 *4 mars 199111 mai 1993Matsushita Electronics CorporationNon-volatile semiconductor memory device and a method for fabricating the same
US5301150 *22 juin 19925 avr. 1994Intel CorporationFlash erasable single poly EPROM device
US5402002 *24 juil. 199128 mars 1995Siemens AktiengesellschaftBipolar transistor with reduced base/collector capacitance
US5406521 *1 nov. 199311 avr. 1995Nec CorporationSemiconductor memory device and data erase method for it
US5424233 *6 mai 199413 juin 1995United Microflectronics CorporationMethod of making electrically programmable and erasable memory device with a depression
US5487034 *19 sept. 199423 janv. 1996Nec CorporationSemiconductor memory device and method for writing data therein
US5512785 *30 nov. 199430 avr. 1996Motorola, Inc.Semiconducter device having an emitter terminal separated from a base terminal by a composite nitride/oxide layer
US5599724 *24 août 19954 févr. 1997Kabushiki Kaisha ToshibaFET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same
US5761126 *7 févr. 19972 juin 1998National Semiconductor CorporationSingle-poly EPROM cell that utilizes a reduced programming voltage to program the cell
US5780341 *6 déc. 199614 juil. 1998Halo Lsi Design & Device Technology, Inc.Low voltage EEPROM/NVRAM transistors and making method
US5808338 *8 mai 199715 sept. 1998Nkk CorporationNonvolatile semiconductor memory
US5812452 *30 juin 199722 sept. 1998Winbond Memory LaboratoryElectrically byte-selectable and byte-alterable memory arrays
US5821143 *22 avr. 199613 oct. 1998Samsung Electronics Co., Ltd.Fabrication methods for nonvolatile memory devices including extended sidewall electrode
US5917215 *4 sept. 199829 juin 1999Taiwan Semiconductor Manufacturing Company Ltd.Stepped edge structure of an EEPROM tunneling window
US5942780 *9 août 199624 août 1999Advanced Micro Devices, Inc.Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate
US5999456 *3 oct. 19977 déc. 1999Stmicroelectronics S.R.L.Flash EEPROM with controlled discharge time of the word lines and source potentials after erase
US6043530 *15 avr. 199828 mars 2000Chang; Ming-BingFlash EEPROM device employing polysilicon sidewall spacer as an erase gate
US6051465 *30 juil. 199818 avr. 2000Matsushita Electronics CorporationMethod for fabricating nonvolatile semiconductor memory device
US6160287 *8 déc. 199812 déc. 2000United Microelectronics Corp.Flash memory
US6240021 *12 févr. 199929 mai 2001Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device improved in readout operation
US6323088 *29 août 200027 nov. 2001Micron Technology, Inc.Dual floating gate programmable read only memory cell structure and method for its fabrication an operation
US6343031 *26 janv. 200129 janv. 2002Oki Electric Industry Co., Ltd.Semiconductor memory device
US6413802 *23 oct. 20002 juil. 2002The Regents Of The University Of CaliforniaFinfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6420753 *30 juin 199716 juil. 2002Winbond Memory LaboratoryElectrically selectable and alterable memory cells
US6468863 *16 janv. 200122 oct. 2002Taiwan Semiconductor Manufacturing Co., LtdSplit gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof
US6479351 *30 nov. 200012 nov. 2002Atmel CorporationMethod of fabricating a self-aligned non-volatile memory cell
US6486032 *18 juin 200226 nov. 2002Nanya Technology CorporationMethod for fabricating control gate and floating gate of a flash memory cell
US6525403 *24 sept. 200125 févr. 2003Kabushiki Kaisha ToshibaSemiconductor device having MIS field effect transistors or three-dimensional structure
US6538275 *12 juil. 200125 mars 2003Matsushita Electric Industrial Co., Ltd.Nonvolatile semiconductor memory device and method for fabricating the same
US6541816 *27 juin 20011 avr. 2003Advanced Micro Devices, Inc.Planar structure for non-volatile memory devices
US6563733 *24 mai 200113 mai 2003Winbond Electronics CorporationMemory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell
US6580116 *30 nov. 200017 juin 2003Halo Lsi, Inc.Double sidewall short channel split gate flash memory
US6597047 *21 mars 200122 juil. 2003Matsushita Electric Industrial Co., Ltd.Method for fabricating a nonvolatile semiconductor device
US6818936 *5 nov. 200216 nov. 2004Taiwan Semiconductor Manufacturing CompanyScaled EEPROM cell by metal-insulator-metal (MIM) coupling
US6846709 *21 janv. 200425 janv. 2005Atmel CorporationVertical gate CMOS with lithography-independent gate length
US6888192 *18 juin 20033 mai 2005Atmel CorporationMirror image non-volatile memory cell transistor pairs with single poly layer
US6919242 *25 avr. 200319 juil. 2005Atmel CorporationMirror image memory cell transistor pairs featuring poly floating spacers
US6998670 *23 févr. 200414 févr. 2006Atmel CorporationTwin EEPROM memory transistors with subsurface stepped floating gates
US7169660 *28 oct. 200430 janv. 2007Atmel CorporationLithography-independent fabrication of small openings for forming vertical mos transistor
US7232732 *6 oct. 200319 juin 2007Atmel CorporationSemiconductor device with a toroidal-like junction
US7338875 *9 oct. 20064 mars 2008Atmel CorporationMethod of fabricating a semiconductor device having a toroidal-like junction
US20010000153 *30 nov. 20005 avr. 2001Seiki OguraDouble sidewall short channel split gate flash memory
US20010017392 *22 mars 200130 août 2001International Business Machines Corporation.Vertical transport MOSFETs and method for making the same
US20020019097 *21 mars 200114 févr. 2002Masatoshi AraiNonvolatile semiconductor memory device and method for fabricating the device
US20020060338 *6 nov. 200123 mai 2002Zhibo ZhangMethods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls and vertical field effect transistors fabricated thereby
US20020074583 *6 déc. 200120 juin 2002Matsushita Electric Industrial Co., Ltd.Nonvolatile semiconductor memory device and manufacturing method thereof
US20020098657 *20 mars 200225 juil. 2002Mohsen AlaviStructure and process flow for fabrication of dual gate floating body integrated MOS transistors
US20030199143 *2 mai 200223 oct. 2003Hung-Sui LinMethod for fabricating non-volatile memory having P-type floating gate
US20050104119 *9 août 200419 mai 2005California Institute Of Technology, A California Non-Profit CorporationFloating-gate semiconductor structures
US20060118856 *17 janv. 20068 juin 2006Atmel CorporationTwin EEPROM memory transistors with subsurface stepped floating gates
US20070075400 *9 oct. 20065 avr. 2007Atmel CorporationSemiconductor device with a toroidal-like junction
US20070087557 *9 oct. 200619 avr. 2007Atmel CorporationSemiconductor device with a toroidal-like junction
Classification aux États-Unis257/315, 257/E21.694, 257/E29.307, 257/E27.103
Classification internationaleH01L21/28, H01L29/423, H01L27/108, H01L21/8247, G11C11/34, G11C11/22, H01L29/786, H01L21/336, H01L27/115, H01L29/788
Classification coopérativeH01L29/7887, H01L27/11553, H01L29/42324, H01L27/11582, H01L29/66772, H01L29/66742, H01L27/11521, H01L29/7886, H01L27/115, H01L21/28123, H01L29/42384, H01L29/66825, H01L27/11558, G11C16/0433, H01L29/42336, H01L29/78642, G11C2216/10
Classification européenneH01L27/115F12, H01L29/423D2B2, H01L21/28E2B30, H01L29/788C, H01L27/115F10C, H01L29/66M6T6F15, H01L29/66M6T6F15C, H01L29/66M6T6F17, H01L27/115G10C2, H01L29/786C, H01L29/423D2B8, G11C16/04F3, H01L29/788B6C, H01L29/423D2B2D, H01L27/115, H01L27/115F4