US20060113583A1 - Twin EEPROM memory transistors with subsurface stepped floating gates - Google Patents

Twin EEPROM memory transistors with subsurface stepped floating gates Download PDF

Info

Publication number
US20060113583A1
US20060113583A1 US11/332,908 US33290806A US2006113583A1 US 20060113583 A1 US20060113583 A1 US 20060113583A1 US 33290806 A US33290806 A US 33290806A US 2006113583 A1 US2006113583 A1 US 2006113583A1
Authority
US
United States
Prior art keywords
twin
subsurface
transistor
memory
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/332,908
Inventor
Bohumil Lojek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/423,637 external-priority patent/US6919242B2/en
Priority claimed from US10/465,718 external-priority patent/US6888192B2/en
Priority claimed from US10/680,355 external-priority patent/US7232732B2/en
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to US11/332,908 priority Critical patent/US20060113583A1/en
Publication of US20060113583A1 publication Critical patent/US20060113583A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/10—Floating gate memory cells with a single polysilicon layer

Definitions

  • the invention relates to non-volatile memory transistors and, in particular, to a compact arrangement of such memory cells for an array and a method of making them.
  • an object of the invention is to provide good separation for data bits afforded by dedicated transistors yet achieve the compactness of multibit charge storage structures for a non-volatile memory array.
  • the above object has been achieved with a memory array having cells with twin EEPROM memory transistors that occupy a space almost the same size as a single EEPROM memory transistor.
  • the twin transistors of each cell are symmetrically arranged in a common substrate and feature a single poly layer, with portions used as floating gates that are stepped below the level of the substrate surface, yet insulated from the substrate by thin oxide.
  • the floating gate electrically communicates with a subsurface electrode that participates in charge transfer to the floating gate.
  • the usual EEPROM control gate is replaced by a first capacitor wherein the same poly portion used to form the floating gate extends to form a second plate of the first capacitor.
  • the first plate of the first capacitor is a control line connected to a phased signal source whereby phasing of plates of the twin cells allows each transistor to act independently.
  • the drain of each transistor is connected to one plate of a second capacitor and to a bit line while the second plate is connected to a word line.
  • the intensity of electric field from a subsurface electrode will increase and enhance tunneling action.
  • FIG. 1 is an electrical schematic drawing of memory cells forming the core of a memory array of the present invention.
  • FIG. 2 is a side sectional view of an early manufacturing step for a memory transistor in the memory cells of FIG. 1 .
  • FIG. 3 is a top view of a mask for making a substrate step shown in the sectional view of FIG. 2 .
  • FIG. 4 is a top view of a layout in an early manufacturing stage of twin memory cells shown in FIG. 1 .
  • FIG. 5 is a side sectional view taken along lines 5 - 5 in FIG. 4 .
  • FIG. 6 is a side sectional view taken along lines 6 - 6 in FIG. 4 .
  • FIG. 7 is a top view of a layout in an intermediate manufacturing stage of twin memory cells shown in FIG. 1 .
  • FIG. 8 is a side sectional view taken along lines 8 - 8 in FIG. 7 .
  • FIG. 9 is a side sectional view following FIG. 8 at a later stage in manufacturing.
  • FIG. 10 is a top view of a contact mask superposed on the top view of FIG. 7 , with conductor shading for the single polysilicon layer.
  • FIG. 11 is an electrical schematic drawing of twin symmetric memory cells shown in FIG. 1 redrawn for comparison with FIG. 10 , including locations of contacts shown in FIG. 10 .
  • a memory cell 13 in a memory array 10 is seen to have first and second non-volatile memory transistors 15 and 115 , respectively.
  • the first memory transistor 15 has a drain 21 connected to select capacitor 19 , a floating gate 23 connected to control capacitor 29 and a source 25 connected to the source contact 27 .
  • Select capacitor 19 has a first electrode 31 connected to drain 21 of first memory transistor 15 and also connected to the first bit line, BL 1 .
  • the second electrode 33 of select capacitor 19 is connected to word line WL 1 .
  • the word line WL 1 is extended from first electrode 31 along line 35 into another cell.
  • the floating gate 23 of memory transistor 15 is connected to a first electrode 37 of control capacitor 29 , while second electrode 39 is connected to a first control line terminal 41 .
  • a pulse on terminal 41 charges the second electrode 39 , causing induced charge to appear on first electrode 37 which forms a floating gate together with electrode 23 . This is one of two ways in which charge appears on the floating gate 23 . Another way for charge to appear is by tunneling or electron injection from source or drain electrode 21 and 25 .
  • bit line BL 1 When one voltage is applied to bit line BL 1 and another voltage is applied at source contact 27 charge may be transferred onto the floating gate 23 by tunneling charge transfer mechanisms. Just as the word line WL 1 extends into another memory cell in the same column along line 35 , bit line BL 1 is also extended into a memory cell in the same row along line 43 .
  • the second memory transistor 115 is symmetric with first memory transistor 115 relative to source contact 27 .
  • the second memory transistor 115 has a floating gate 123 which may be charged by control capacitor 129 .
  • Memory transistor 115 has a drain electrode 121 connected to a first plate 131 of select capacitor 119 and a source electrode 125 connected to source contact 27 .
  • the first plate 131 is also connected to the bit line BL 1 .
  • the second plate of capacitor 119 is connected to the word line WL 2 .
  • the word line WL 2 is extended from the first electrode 131 along line 135 to a control capacitor (not shown) into a neighboring cell in the same column.
  • the bit line 43 similarly extends from the first electrode of select capacitor 119 into a neighboring cell in the same row.
  • Memory cell 13 is typical of the memory cells in the memory array 10 . Each cell is seen to have twin non-volatile memory transistors that are symmetric about a source contact, such as source contact 27 .
  • the two memory transistors have floating gates associated with two control capacitors on the one hand and have drain or source electrodes associated with two select capacitors on the other hand.
  • the two control line terminals 41 and 141 associated with the control capacitors allow programming of the two memory transistors so that each transistor is independent of the other, even though they share a common source electrode at source contact 27 and also share bit line BL 1 .
  • Memory cell 13 is associated with two word lines, WL 1 and WL 2 , as well as one bit line, BL 1 .
  • a silicon p-type wafer provides a substrate doped to have a p-well with a surface 56 , upon which a thin layer of oxide 57 is grown.
  • the oxide layer has a thickness of approximately 100 angstroms.
  • the oxide is covered with a thick photoresist layer 51 and then patterned with a mask 52 , shown in FIG. 3 .
  • the mask is approximately square with a dimension near the lower limit of resolution of photolithography.
  • the photoresist is then etched so that well-defined steps 53 and 54 form a depression 58 with upper and lower corners to a depth of approximately 500 angstroms below the substrate surface 56 .
  • steps 53 and 54 will enhance the electric field near the floating gates of twin memory transistors extending into the planar surface of the wafer. Corners at the top and bottom of each step are important for increasing electric field intensity to enhance tunneling.
  • the floating gates are built upon the steps but insulated from the substrate by gate oxide 57 .
  • a mask set is shown defining the active regions of two memory cells.
  • the mask set includes masks 52 and 55 for defining common source electrodes of twin EEPROMs and masks 62 and 64 , as well as masks 66 and 68 for defining control lines.
  • Two linear masks define parallel bit lines BL 1 and BL 2 .
  • the areas surrounding the masks are isolated by a shallow trench isolation, as shown in FIG. 5 .
  • Trenches in p-well or p-substrate 50 ( FIG. 6 ) of a p-type silicon wafer substrate are filled with dielectric insulator material 72 , 74 , 76 , 78 , and 80 ( FIG. 5 ), typically silicon dioxide.
  • the areas that are not dielectric material are subject to doping either by diffusion or implantation. This allows the memory cells to have diffused bit lines BL 1 and BL 2 .
  • the substrate is coated with oxide, previously described in FIG. 2 but not shown in FIG. 6 , and the depression 58 is formed below the surface 56 of substrate p-well substrate 50 .
  • the depression 58 has steps or corners 53 and 54 that will form part of floating gates of memory transistors. The steps or corners 53 and 54 may be seen in FIG. 4 also.
  • the diffused regions include the areas where source masks 52 and 55 as well as the control line diffusions 62 , 64 , 66 , and 68 .
  • the diffused bit lines BL 1 and BL 2 are also seen. All of these structures lie below the surface of the p-well, or p-substrate, including steps or corners 53 and 54 .
  • a layer of poly is deposited over the substrate surface and then etched leaving floating members 82 , 84 , 86 , and 88 . Portions of these floating members will become floating gates of twin EEPROM transistors.
  • the floating members have portions extending over the control line diffusions 62 and 64 , as well as control line diffusions 66 and 68 . Portions of the floating members also extend over the source mask regions 52 and 55 .
  • the poly layer is also used to define word lines WL 1 and WL 2 , spaced apart and lying outwardly of the cell core.
  • the p-well substrate 50 is seen with gate oxide layer 57 over the substrate surface including the depression 58 .
  • the poly layer deposited over the substrate has portions which define floating gates 82 and 84 that follow the contour of steps or corners 53 and 54 .
  • Outwardly of the floating gate regions 82 and 84 are poly word lines WL 1 and WL 2 .
  • FIG. 9 follows FIG. 8 at a further point in the manufacturing process.
  • Subsurface implants have been made in p-well substrate 50 , particularly source implant 92 , as well as drain implants 94 and 96 .
  • the subsurface bit line diffusions BL 1 are also seen.
  • the poly floating gates 82 and 84 have sidewall spacers, such as sidewall spacers 83 and 85 surrounding floating gate 82 .
  • word lines WL 1 and WL 2 have sidewall spacers such as spacers 87 and 89 associated with word line WL 1 .
  • a layer of interlayer dielectric, ILD layer 101 is deposited over the poly one layer.
  • the ILD layer 101 is masked and etched to create.
  • metal contacts 102 , 104 , and 106 make contact with subsurface regions.
  • Metal contacts 102 and 106 contact the diffused bit line BL 1 .
  • Metal contact 104 contacts a common subsurface electrode 92 . The relation of the metal contacts with the top view of FIG. 7 may be seen in FIG. 10 .
  • FIG. 10 the position of metal contacts 102 , 104 , and 106 may be seen. Also, contacts 112 and 114 , associated with the control line diffusions 62 and 64 , may be seen. Contact 104 is located in the center of mask 52 that defines a common electrode for twin side-by-side memory transistors. In other words, contact 104 is located at a plane of symmetry for the twin EEPROM transistors.
  • the single poly layer has been shaded, with portions of the layer forming poly members 82 and 84 , defining the contoured floating gates associated with the subsurface steps toward the common source electrode. Other portions of the poly one layer define the word lines WL 1 and WL 2 , as indicated by shading. Note that the poly members 82 and 84 extend over the control line diffusions 62 and 64 . These control line diffusions have metal contacts 112 and 114 , respectively.
  • FIG. 11 positions of the contacts of the memory cell in the top view of FIG. 10 are indicated relative to an electrical schematic of a memory cell as shown in FIG. 1 .
  • a total of five contacts is used for each cell with two contacts, 102 and 106 , being on the bit line BL 1 .
  • the contact 104 is associated with the common source between the twin symmetric memory transistors.
  • the contacts 112 and 114 are associated with capacitors 29 and 129 .
  • FIG. 11 may be projected upwardly, towards FIG. 10 , where a rough comparison can be made of the various circuit elements.
  • the word line WL 1 is seen to overlie the bit line BL 1 but spaced apart by insulator thereby forming capacitor 19 in FIG. 11 .
  • a portion of poly member 82 is seen to overlie control line diffusion 62 thereby forming capacitor 29 in FIG. 11 .

Abstract

A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word lines. The twin EEPROMs share a common subsurface electrode by having diffused control lines and a diffused bit line. The two EEPROMs are symmetric across the common electrode.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This is a divisional of pending U.S. patent application Ser. No. 10/785,160 filed Feb. 23, 2004 which is a continuation-in-part of prior application Ser. No. 10/423,637 filed Apr. 25, 2003, a continuation-in-part of prior application Ser. No. 10/465,718 filed Jun. 18, 2003, and a continuation-in-part of prior application Ser. No. 10/680,355, filed Oct. 6, 2003. All four applications are herewith incorporated by reference in their entirety.
    • TECHNICAL FIELD
  • The invention relates to non-volatile memory transistors and, in particular, to a compact arrangement of such memory cells for an array and a method of making them.
    • BACKGROUND ART
  • In prior application Ser. No. 10/423,637 entitled “Mirror Image Memory Cell Transistor Pairs Featuring Poly Floating Spacers,” as well as in prior application Ser. No. 10/465,718 entitled “Mirror Image Non-Volatile Memory Cell Transistor Pairs with Single Poly Layer,” both assigned to the assignee of the present invention, B. Lojek described an arrangement of non-volatile MOS memory transistors for a memory array wherein symmetric pairs of transistors were built in a memory array. Transistor pairs shared an electrode in a common well, such as a drain electrode, but were otherwise completely independent. The pair was manufactured between a pair of isolation regions and sharing the same substrate region, almost as if a single transistor were constructed there.
  • In the prior art, single MOS floating gate transistors that stored two data bits have been devised as a way to achieve compactness. Since millions of data bits are frequently stored in non-volatile memory arrays, small savings of space are multiplied significantly over the array. In prior application Ser. No. 10/327,336 entitled “Multi-Level Memory Cell with Lateral Floating Spacers,” assigned to the assignee of the present invention, B. Lojek described how two spacers, on opposite sides of a conductive gate, behave as independent charge storage regions for separate binary data, thereby allowing a single non-volatile MOS transistor to store two binary bits. Each memory cell is connected to two bit lines and one word line. The bit lines are phased so that during a single clock cycle, first one bit line is active and then the other while a word line is active for the entire cycle. In this manner, both storage areas may be accessed for a read or write operation in a single clock cycle.
  • In U.S. Pat. No. 6,043,530 to M. Chang, a MOS memory transistor construction is shown employing band-to-band tunneling. In U.S. Pat. No. 6,323,088 to F. Gonzalez et al., a multibit charge storage transistor addressing scheme is shown with phased bit lines.
  • In the prior art, multibit charge storage structures are known that achieve good data density in a memory array without giving up valuable chip space. One of the problems that is encountered as density increases is that the amount of crosstalk between storage sites increases. Because the charge storage structures are so small, one charge storage location can sometimes influence another. On the other hand, separation of charge storage sites gives up chip space. The ultimate separation is one dedicated transistor for each data bit. Accordingly, an object of the invention is to provide good separation for data bits afforded by dedicated transistors yet achieve the compactness of multibit charge storage structures for a non-volatile memory array.
    • SUMMARY OF THE INVENTION
  • The above object has been achieved with a memory array having cells with twin EEPROM memory transistors that occupy a space almost the same size as a single EEPROM memory transistor. The twin transistors of each cell are symmetrically arranged in a common substrate and feature a single poly layer, with portions used as floating gates that are stepped below the level of the substrate surface, yet insulated from the substrate by thin oxide. The floating gate electrically communicates with a subsurface electrode that participates in charge transfer to the floating gate. The usual EEPROM control gate is replaced by a first capacitor wherein the same poly portion used to form the floating gate extends to form a second plate of the first capacitor. The first plate of the first capacitor is a control line connected to a phased signal source whereby phasing of plates of the twin cells allows each transistor to act independently. The drain of each transistor is connected to one plate of a second capacitor and to a bit line while the second plate is connected to a word line.
  • By stepping the floating gate into the substrate and forming a floating gate corner in the substrate, the intensity of electric field from a subsurface electrode will increase and enhance tunneling action.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an electrical schematic drawing of memory cells forming the core of a memory array of the present invention.
  • FIG. 2 is a side sectional view of an early manufacturing step for a memory transistor in the memory cells of FIG. 1.
  • FIG. 3 is a top view of a mask for making a substrate step shown in the sectional view of FIG. 2.
  • FIG. 4 is a top view of a layout in an early manufacturing stage of twin memory cells shown in FIG. 1.
  • FIG. 5 is a side sectional view taken along lines 5-5 in FIG. 4.
  • FIG. 6 is a side sectional view taken along lines 6-6 in FIG. 4.
  • FIG. 7 is a top view of a layout in an intermediate manufacturing stage of twin memory cells shown in FIG. 1.
  • FIG. 8 is a side sectional view taken along lines 8-8 in FIG. 7.
  • FIG. 9 is a side sectional view following FIG. 8 at a later stage in manufacturing.
  • FIG. 10 is a top view of a contact mask superposed on the top view of FIG. 7, with conductor shading for the single polysilicon layer.
  • FIG. 11 is an electrical schematic drawing of twin symmetric memory cells shown in FIG. 1 redrawn for comparison with FIG. 10, including locations of contacts shown in FIG. 10.
    • BEST MODE FOR CARRYING OUT THE INVENTION
  • With reference to FIG. 1, a memory cell 13 in a memory array 10 is seen to have first and second non-volatile memory transistors 15 and 115, respectively. The first memory transistor 15 has a drain 21 connected to select capacitor 19, a floating gate 23 connected to control capacitor 29 and a source 25 connected to the source contact 27.
  • Select capacitor 19 has a first electrode 31 connected to drain 21 of first memory transistor 15 and also connected to the first bit line, BL1. The second electrode 33 of select capacitor 19 is connected to word line WL1. The word line WL1 is extended from first electrode 31 along line 35 into another cell. The floating gate 23 of memory transistor 15 is connected to a first electrode 37 of control capacitor 29, while second electrode 39 is connected to a first control line terminal 41. A pulse on terminal 41 charges the second electrode 39, causing induced charge to appear on first electrode 37 which forms a floating gate together with electrode 23. This is one of two ways in which charge appears on the floating gate 23. Another way for charge to appear is by tunneling or electron injection from source or drain electrode 21 and 25. When one voltage is applied to bit line BL1 and another voltage is applied at source contact 27 charge may be transferred onto the floating gate 23 by tunneling charge transfer mechanisms. Just as the word line WL1 extends into another memory cell in the same column along line 35, bit line BL1 is also extended into a memory cell in the same row along line 43.
  • The second memory transistor 115 is symmetric with first memory transistor 115 relative to source contact 27. The second memory transistor 115 has a floating gate 123 which may be charged by control capacitor 129. Memory transistor 115 has a drain electrode 121 connected to a first plate 131 of select capacitor 119 and a source electrode 125 connected to source contact 27. The first plate 131 is also connected to the bit line BL1. The second plate of capacitor 119 is connected to the word line WL2. The word line WL2 is extended from the first electrode 131 along line 135 to a control capacitor (not shown) into a neighboring cell in the same column. The bit line 43 similarly extends from the first electrode of select capacitor 119 into a neighboring cell in the same row.
  • Memory cell 13 is typical of the memory cells in the memory array 10. Each cell is seen to have twin non-volatile memory transistors that are symmetric about a source contact, such as source contact 27. The two memory transistors have floating gates associated with two control capacitors on the one hand and have drain or source electrodes associated with two select capacitors on the other hand. The two control line terminals 41 and 141 associated with the control capacitors allow programming of the two memory transistors so that each transistor is independent of the other, even though they share a common source electrode at source contact 27 and also share bit line BL1. Memory cell 13 is associated with two word lines, WL1 and WL2, as well as one bit line, BL1.
  • With reference to FIG. 2, a silicon p-type wafer provides a substrate doped to have a p-well with a surface 56, upon which a thin layer of oxide 57 is grown. The oxide layer has a thickness of approximately 100 angstroms. The oxide is covered with a thick photoresist layer 51 and then patterned with a mask 52, shown in FIG. 3. The mask is approximately square with a dimension near the lower limit of resolution of photolithography. The photoresist is then etched so that well-defined steps 53 and 54 form a depression 58 with upper and lower corners to a depth of approximately 500 angstroms below the substrate surface 56. The facing corners of steps 53 and 54 will enhance the electric field near the floating gates of twin memory transistors extending into the planar surface of the wafer. Corners at the top and bottom of each step are important for increasing electric field intensity to enhance tunneling. The floating gates are built upon the steps but insulated from the substrate by gate oxide 57.
  • With reference to FIG. 4, a mask set is shown defining the active regions of two memory cells. The mask set includes masks 52 and 55 for defining common source electrodes of twin EEPROMs and masks 62 and 64, as well as masks 66 and 68 for defining control lines. Two linear masks define parallel bit lines BL1 and BL2. The areas surrounding the masks are isolated by a shallow trench isolation, as shown in FIG. 5. Trenches in p-well or p-substrate 50 (FIG. 6) of a p-type silicon wafer substrate are filled with dielectric insulator material 72, 74, 76, 78, and 80 (FIG. 5), typically silicon dioxide. The areas that are not dielectric material are subject to doping either by diffusion or implantation. This allows the memory cells to have diffused bit lines BL1 and BL2.
  • Turning to FIG. 6, when doping of subsurface regions is complete, the substrate is coated with oxide, previously described in FIG. 2 but not shown in FIG. 6, and the depression 58 is formed below the surface 56 of substrate p-well substrate 50. The depression 58 has steps or corners 53 and 54 that will form part of floating gates of memory transistors. The steps or corners 53 and 54 may be seen in FIG. 4 also.
  • With reference to FIG. 7, the diffused regions previously described with reference to FIG. 4 may be seen. The diffused regions include the areas where source masks 52 and 55 as well as the control line diffusions 62, 64, 66, and 68. The diffused bit lines BL1 and BL2 are also seen. All of these structures lie below the surface of the p-well, or p-substrate, including steps or corners 53 and 54.
  • A layer of poly is deposited over the substrate surface and then etched leaving floating members 82, 84, 86, and 88. Portions of these floating members will become floating gates of twin EEPROM transistors. The floating members have portions extending over the control line diffusions 62 and 64, as well as control line diffusions 66 and 68. Portions of the floating members also extend over the source mask regions 52 and 55. The poly layer is also used to define word lines WL1 and WL2, spaced apart and lying outwardly of the cell core.
  • In FIG. 8, the p-well substrate 50 is seen with gate oxide layer 57 over the substrate surface including the depression 58. The poly layer deposited over the substrate has portions which define floating gates 82 and 84 that follow the contour of steps or corners 53 and 54. Outwardly of the floating gate regions 82 and 84 are poly word lines WL1 and WL2.
  • FIG. 9 follows FIG. 8 at a further point in the manufacturing process. Subsurface implants have been made in p-well substrate 50, particularly source implant 92, as well as drain implants 94 and 96. The subsurface bit line diffusions BL1 are also seen. The poly floating gates 82 and 84 have sidewall spacers, such as sidewall spacers 83 and 85 surrounding floating gate 82. Similarly, word lines WL1 and WL2 have sidewall spacers such as spacers 87 and 89 associated with word line WL1. After the spacers have been constructed, a layer of interlayer dielectric, ILD layer 101, is deposited over the poly one layer. The ILD layer 101 is masked and etched to create. holes that allow insertion of metal contacts 102, 104, and 106. These conductive metal contacts make contact with subsurface regions. Metal contacts 102 and 106 contact the diffused bit line BL1. Metal contact 104 contacts a common subsurface electrode 92. The relation of the metal contacts with the top view of FIG. 7 may be seen in FIG. 10.
  • In FIG. 10, the position of metal contacts 102, 104, and 106 may be seen. Also, contacts 112 and 114, associated with the control line diffusions 62 and 64, may be seen. Contact 104 is located in the center of mask 52 that defines a common electrode for twin side-by-side memory transistors. In other words, contact 104 is located at a plane of symmetry for the twin EEPROM transistors. In FIG. 10, the single poly layer has been shaded, with portions of the layer forming poly members 82 and 84, defining the contoured floating gates associated with the subsurface steps toward the common source electrode. Other portions of the poly one layer define the word lines WL1 and WL2, as indicated by shading. Note that the poly members 82 and 84 extend over the control line diffusions 62 and 64. These control line diffusions have metal contacts 112 and 114, respectively.
  • In FIG. 11 positions of the contacts of the memory cell in the top view of FIG. 10 are indicated relative to an electrical schematic of a memory cell as shown in FIG. 1. A total of five contacts is used for each cell with two contacts, 102 and 106, being on the bit line BL1. The contact 104 is associated with the common source between the twin symmetric memory transistors. The contacts 112 and 114 are associated with capacitors 29 and 129. FIG. 11 may be projected upwardly, towards FIG. 10, where a rough comparison can be made of the various circuit elements. In FIG. 10, the word line WL1 is seen to overlie the bit line BL1 but spaced apart by insulator thereby forming capacitor 19 in FIG. 11. Similarly, a portion of poly member 82 is seen to overlie control line diffusion 62 thereby forming capacitor 29 in FIG. 11.

Claims (4)

1. In an EEPROM transistor in a memory array of the EEPROM type fabricated in a silicon wafer with an oxide coating on the wafer surface, with a source, drain and floating gate, the improvement comprising a step in floating gate extending at least partially below the wafer surface and a first capacitor control element with first and second capacitor plates, the first plate connected to the floating gate.
2. The transistor of claim 1 having a second capacitor connected to a source or drain electrode.
3. The transistor of claim 1 wherein said second capacitor has plates associated with a word line and a bit line of the memory array.
4. The transistor of claim 1 wherein said step has top and bottom corners.
US11/332,908 2003-04-25 2006-01-17 Twin EEPROM memory transistors with subsurface stepped floating gates Abandoned US20060113583A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/332,908 US20060113583A1 (en) 2003-04-25 2006-01-17 Twin EEPROM memory transistors with subsurface stepped floating gates

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/423,637 US6919242B2 (en) 2003-04-25 2003-04-25 Mirror image memory cell transistor pairs featuring poly floating spacers
US10/465,718 US6888192B2 (en) 2003-04-25 2003-06-18 Mirror image non-volatile memory cell transistor pairs with single poly layer
US10/680,355 US7232732B2 (en) 2003-10-06 2003-10-06 Semiconductor device with a toroidal-like junction
US10/785,160 US6998670B2 (en) 2003-04-25 2004-02-23 Twin EEPROM memory transistors with subsurface stepped floating gates
US11/332,908 US20060113583A1 (en) 2003-04-25 2006-01-17 Twin EEPROM memory transistors with subsurface stepped floating gates

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/785,160 Division US6998670B2 (en) 2003-04-25 2004-02-23 Twin EEPROM memory transistors with subsurface stepped floating gates

Publications (1)

Publication Number Publication Date
US20060113583A1 true US20060113583A1 (en) 2006-06-01

Family

ID=34911439

Family Applications (3)

Application Number Title Priority Date Filing Date
US10/785,160 Expired - Lifetime US6998670B2 (en) 2003-04-25 2004-02-23 Twin EEPROM memory transistors with subsurface stepped floating gates
US11/332,908 Abandoned US20060113583A1 (en) 2003-04-25 2006-01-17 Twin EEPROM memory transistors with subsurface stepped floating gates
US11/333,627 Abandoned US20060118856A1 (en) 2003-04-25 2006-01-17 Twin EEPROM memory transistors with subsurface stepped floating gates

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/785,160 Expired - Lifetime US6998670B2 (en) 2003-04-25 2004-02-23 Twin EEPROM memory transistors with subsurface stepped floating gates

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/333,627 Abandoned US20060118856A1 (en) 2003-04-25 2006-01-17 Twin EEPROM memory transistors with subsurface stepped floating gates

Country Status (5)

Country Link
US (3) US6998670B2 (en)
EP (1) EP1721336A2 (en)
CN (1) CN1947251A (en)
TW (1) TW200532758A (en)
WO (1) WO2005081798A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US6888192B2 (en) * 2003-04-25 2005-05-03 Atmel Corporation Mirror image non-volatile memory cell transistor pairs with single poly layer
KR100468787B1 (en) * 2003-05-02 2005-01-29 삼성전자주식회사 Semiconductor device capable of preventing current flow of Latch-up
US7102188B1 (en) * 2005-04-05 2006-09-05 Ami Semiconductor, Inc. High reliability electrically erasable and programmable read-only memory (EEPROM)
US8997255B2 (en) 2006-07-31 2015-03-31 Inside Secure Verifying data integrity in a data storage device
US7439567B2 (en) * 2006-08-09 2008-10-21 Atmel Corporation Contactless nonvolatile memory array
US8352752B2 (en) * 2006-09-01 2013-01-08 Inside Secure Detecting radiation-based attacks
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7868370B2 (en) * 2008-04-14 2011-01-11 Macronix International Co., Ltd. Single gate nonvolatile memory cell with transistor and capacitor
US7999296B2 (en) 2008-04-14 2011-08-16 Macronix International Co., Ltd. Single gate nonvolatile memory cell with transistor and capacitor
KR102142155B1 (en) * 2014-03-21 2020-08-10 에스케이하이닉스 주식회사 Non-volatile memory device with single layered floating gate and fabricating method for the same
CN116114394A (en) * 2020-09-17 2023-05-12 铠侠股份有限公司 Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell
CN114464526B (en) * 2022-04-12 2022-06-17 晶芯成(北京)科技有限公司 Multi-time programmable memory and preparation method thereof

Citations (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4649520A (en) * 1984-11-07 1987-03-10 Waferscale Integration Inc. Single layer polycrystalline floating gate
US4807188A (en) * 1987-05-27 1989-02-21 Sgs-Thomson Microelectronics S.P.A. Nonvolatile memory device with a high number of cycle programming endurance
US4814594A (en) * 1982-11-22 1989-03-21 Drexler Technology Corporation Updatable micrographic pocket data card
US4931847A (en) * 1986-06-27 1990-06-05 Sgs-Thomson Microelectronics S.P.A. Floating gate memory with sidewall tunnelling area
US5021848A (en) * 1990-03-13 1991-06-04 Chiu Te Long Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5026663A (en) * 1989-07-21 1991-06-25 Motorola, Inc. Method of fabricating a structure having self-aligned diffused junctions
US5067002A (en) * 1987-01-30 1991-11-19 Motorola, Inc. Integrated circuit structures having polycrystalline electrode contacts
US5108939A (en) * 1990-10-16 1992-04-28 National Semiconductor Corp. Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region
US5130267A (en) * 1989-05-23 1992-07-14 Texas Instruments Incorporated Split metal plate capacitor and method for making the same
US5196722A (en) * 1992-03-12 1993-03-23 International Business Machines Corporation Shadow ram cell having a shallow trench eeprom
US5210597A (en) * 1990-03-08 1993-05-11 Matsushita Electronics Corporation Non-volatile semiconductor memory device and a method for fabricating the same
US5301150A (en) * 1992-06-22 1994-04-05 Intel Corporation Flash erasable single poly EPROM device
US5402002A (en) * 1989-09-22 1995-03-28 Siemens Aktiengesellschaft Bipolar transistor with reduced base/collector capacitance
US5406521A (en) * 1992-10-30 1995-04-11 Nec Corporation Semiconductor memory device and data erase method for it
US5424233A (en) * 1994-05-06 1995-06-13 United Microflectronics Corporation Method of making electrically programmable and erasable memory device with a depression
US5487034A (en) * 1993-09-27 1996-01-23 Nec Corporation Semiconductor memory device and method for writing data therein
US5512785A (en) * 1994-11-30 1996-04-30 Motorola, Inc. Semiconducter device having an emitter terminal separated from a base terminal by a composite nitride/oxide layer
US5599724A (en) * 1992-05-21 1997-02-04 Kabushiki Kaisha Toshiba FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same
US5761126A (en) * 1997-02-07 1998-06-02 National Semiconductor Corporation Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US5808338A (en) * 1994-11-11 1998-09-15 Nkk Corporation Nonvolatile semiconductor memory
US5812452A (en) * 1997-06-30 1998-09-22 Winbond Memory Laboratory Electrically byte-selectable and byte-alterable memory arrays
US5821143A (en) * 1995-04-27 1998-10-13 Samsung Electronics Co., Ltd. Fabrication methods for nonvolatile memory devices including extended sidewall electrode
US5917215A (en) * 1997-06-30 1999-06-29 Taiwan Semiconductor Manufacturing Company Ltd. Stepped edge structure of an EEPROM tunneling window
US5942780A (en) * 1996-08-09 1999-08-24 Advanced Micro Devices, Inc. Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate
US5999456A (en) * 1995-07-31 1999-12-07 Stmicroelectronics S.R.L. Flash EEPROM with controlled discharge time of the word lines and source potentials after erase
US6043530A (en) * 1998-04-15 2000-03-28 Chang; Ming-Bing Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
US6051465A (en) * 1997-07-30 2000-04-18 Matsushita Electronics Corporation Method for fabricating nonvolatile semiconductor memory device
US6160287A (en) * 1998-12-08 2000-12-12 United Microelectronics Corp. Flash memory
US20010000153A1 (en) * 1998-08-03 2001-04-05 Seiki Ogura Double sidewall short channel split gate flash memory
US6240021B1 (en) * 1998-02-16 2001-05-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device improved in readout operation
US20010017392A1 (en) * 1997-05-19 2001-08-30 International Business Machines Corporation. Vertical transport MOSFETs and method for making the same
US6323088B1 (en) * 1998-04-08 2001-11-27 Micron Technology, Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication an operation
US6343031B1 (en) * 2000-07-14 2002-01-29 Oki Electric Industry Co., Ltd. Semiconductor memory device
US20020019097A1 (en) * 2000-03-22 2002-02-14 Masatoshi Arai Nonvolatile semiconductor memory device and method for fabricating the device
US20020060338A1 (en) * 2000-11-22 2002-05-23 Zhibo Zhang Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls and vertical field effect transistors fabricated thereby
US20020074583A1 (en) * 2000-12-15 2002-06-20 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and manufacturing method thereof
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6420753B1 (en) * 1997-06-30 2002-07-16 Winbond Memory Laboratory Electrically selectable and alterable memory cells
US20020098657A1 (en) * 1999-06-28 2002-07-25 Mohsen Alavi Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6468863B2 (en) * 2001-01-16 2002-10-22 Taiwan Semiconductor Manufacturing Co., Ltd Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof
US6479351B1 (en) * 2000-11-30 2002-11-12 Atmel Corporation Method of fabricating a self-aligned non-volatile memory cell
US6486032B1 (en) * 2001-12-28 2002-11-26 Nanya Technology Corporation Method for fabricating control gate and floating gate of a flash memory cell
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US6538275B2 (en) * 2000-07-12 2003-03-25 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same
US6541816B2 (en) * 2000-11-28 2003-04-01 Advanced Micro Devices, Inc. Planar structure for non-volatile memory devices
US6563733B2 (en) * 2001-05-24 2003-05-13 Winbond Electronics Corporation Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell
US20030199143A1 (en) * 2002-04-16 2003-10-23 Hung-Sui Lin Method for fabricating non-volatile memory having P-type floating gate
US6818936B2 (en) * 2002-11-05 2004-11-16 Taiwan Semiconductor Manufacturing Company Scaled EEPROM cell by metal-insulator-metal (MIM) coupling
US6846709B1 (en) * 2003-10-06 2005-01-25 Atmel Corporation Vertical gate CMOS with lithography-independent gate length
US6888192B2 (en) * 2003-04-25 2005-05-03 Atmel Corporation Mirror image non-volatile memory cell transistor pairs with single poly layer
US20050104119A1 (en) * 1995-03-07 2005-05-19 California Institute Of Technology, A California Non-Profit Corporation Floating-gate semiconductor structures
US6919242B2 (en) * 2003-04-25 2005-07-19 Atmel Corporation Mirror image memory cell transistor pairs featuring poly floating spacers
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US7169660B2 (en) * 2003-10-06 2007-01-30 Atmel Corporation Lithography-independent fabrication of small openings for forming vertical mos transistor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100243294B1 (en) * 1997-06-09 2000-02-01 윤종용 Ferroelectric memory cell &array in semiconductor device
US6757196B1 (en) * 2001-03-22 2004-06-29 Aplus Flash Technology, Inc. Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device
US6661705B1 (en) * 2001-09-20 2003-12-09 Agere Systems Inc. Low voltage flash EEPROM memory cell with improved data retention

Patent Citations (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814594A (en) * 1982-11-22 1989-03-21 Drexler Technology Corporation Updatable micrographic pocket data card
US4649520A (en) * 1984-11-07 1987-03-10 Waferscale Integration Inc. Single layer polycrystalline floating gate
US4931847A (en) * 1986-06-27 1990-06-05 Sgs-Thomson Microelectronics S.P.A. Floating gate memory with sidewall tunnelling area
US5067002A (en) * 1987-01-30 1991-11-19 Motorola, Inc. Integrated circuit structures having polycrystalline electrode contacts
US4807188A (en) * 1987-05-27 1989-02-21 Sgs-Thomson Microelectronics S.P.A. Nonvolatile memory device with a high number of cycle programming endurance
US5130267A (en) * 1989-05-23 1992-07-14 Texas Instruments Incorporated Split metal plate capacitor and method for making the same
US5026663A (en) * 1989-07-21 1991-06-25 Motorola, Inc. Method of fabricating a structure having self-aligned diffused junctions
US5402002A (en) * 1989-09-22 1995-03-28 Siemens Aktiengesellschaft Bipolar transistor with reduced base/collector capacitance
US5210597A (en) * 1990-03-08 1993-05-11 Matsushita Electronics Corporation Non-volatile semiconductor memory device and a method for fabricating the same
US5021848A (en) * 1990-03-13 1991-06-04 Chiu Te Long Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5108939A (en) * 1990-10-16 1992-04-28 National Semiconductor Corp. Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region
US5196722A (en) * 1992-03-12 1993-03-23 International Business Machines Corporation Shadow ram cell having a shallow trench eeprom
US5599724A (en) * 1992-05-21 1997-02-04 Kabushiki Kaisha Toshiba FET having part of active region formed in semiconductor layer in through hole formed in gate electrode and method for manufacturing the same
US5301150A (en) * 1992-06-22 1994-04-05 Intel Corporation Flash erasable single poly EPROM device
US5406521A (en) * 1992-10-30 1995-04-11 Nec Corporation Semiconductor memory device and data erase method for it
US5487034A (en) * 1993-09-27 1996-01-23 Nec Corporation Semiconductor memory device and method for writing data therein
US5424233A (en) * 1994-05-06 1995-06-13 United Microflectronics Corporation Method of making electrically programmable and erasable memory device with a depression
US5808338A (en) * 1994-11-11 1998-09-15 Nkk Corporation Nonvolatile semiconductor memory
US5512785A (en) * 1994-11-30 1996-04-30 Motorola, Inc. Semiconducter device having an emitter terminal separated from a base terminal by a composite nitride/oxide layer
US20050104119A1 (en) * 1995-03-07 2005-05-19 California Institute Of Technology, A California Non-Profit Corporation Floating-gate semiconductor structures
US5821143A (en) * 1995-04-27 1998-10-13 Samsung Electronics Co., Ltd. Fabrication methods for nonvolatile memory devices including extended sidewall electrode
US5999456A (en) * 1995-07-31 1999-12-07 Stmicroelectronics S.R.L. Flash EEPROM with controlled discharge time of the word lines and source potentials after erase
US5942780A (en) * 1996-08-09 1999-08-24 Advanced Micro Devices, Inc. Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate
US5780341A (en) * 1996-12-06 1998-07-14 Halo Lsi Design & Device Technology, Inc. Low voltage EEPROM/NVRAM transistors and making method
US5761126A (en) * 1997-02-07 1998-06-02 National Semiconductor Corporation Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell
US20010017392A1 (en) * 1997-05-19 2001-08-30 International Business Machines Corporation. Vertical transport MOSFETs and method for making the same
US5812452A (en) * 1997-06-30 1998-09-22 Winbond Memory Laboratory Electrically byte-selectable and byte-alterable memory arrays
US5917215A (en) * 1997-06-30 1999-06-29 Taiwan Semiconductor Manufacturing Company Ltd. Stepped edge structure of an EEPROM tunneling window
US6420753B1 (en) * 1997-06-30 2002-07-16 Winbond Memory Laboratory Electrically selectable and alterable memory cells
US6051465A (en) * 1997-07-30 2000-04-18 Matsushita Electronics Corporation Method for fabricating nonvolatile semiconductor memory device
US6240021B1 (en) * 1998-02-16 2001-05-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device improved in readout operation
US6323088B1 (en) * 1998-04-08 2001-11-27 Micron Technology, Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication an operation
US6043530A (en) * 1998-04-15 2000-03-28 Chang; Ming-Bing Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
US20010000153A1 (en) * 1998-08-03 2001-04-05 Seiki Ogura Double sidewall short channel split gate flash memory
US6580116B2 (en) * 1998-08-03 2003-06-17 Halo Lsi, Inc. Double sidewall short channel split gate flash memory
US6160287A (en) * 1998-12-08 2000-12-12 United Microelectronics Corp. Flash memory
US20020098657A1 (en) * 1999-06-28 2002-07-25 Mohsen Alavi Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6597047B2 (en) * 2000-03-22 2003-07-22 Matsushita Electric Industrial Co., Ltd. Method for fabricating a nonvolatile semiconductor device
US20020019097A1 (en) * 2000-03-22 2002-02-14 Masatoshi Arai Nonvolatile semiconductor memory device and method for fabricating the device
US6538275B2 (en) * 2000-07-12 2003-03-25 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same
US6343031B1 (en) * 2000-07-14 2002-01-29 Oki Electric Industry Co., Ltd. Semiconductor memory device
US6525403B2 (en) * 2000-09-28 2003-02-25 Kabushiki Kaisha Toshiba Semiconductor device having MIS field effect transistors or three-dimensional structure
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US20020060338A1 (en) * 2000-11-22 2002-05-23 Zhibo Zhang Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls and vertical field effect transistors fabricated thereby
US6541816B2 (en) * 2000-11-28 2003-04-01 Advanced Micro Devices, Inc. Planar structure for non-volatile memory devices
US6479351B1 (en) * 2000-11-30 2002-11-12 Atmel Corporation Method of fabricating a self-aligned non-volatile memory cell
US20020074583A1 (en) * 2000-12-15 2002-06-20 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and manufacturing method thereof
US6468863B2 (en) * 2001-01-16 2002-10-22 Taiwan Semiconductor Manufacturing Co., Ltd Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof
US6563733B2 (en) * 2001-05-24 2003-05-13 Winbond Electronics Corporation Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell
US6486032B1 (en) * 2001-12-28 2002-11-26 Nanya Technology Corporation Method for fabricating control gate and floating gate of a flash memory cell
US20030199143A1 (en) * 2002-04-16 2003-10-23 Hung-Sui Lin Method for fabricating non-volatile memory having P-type floating gate
US6818936B2 (en) * 2002-11-05 2004-11-16 Taiwan Semiconductor Manufacturing Company Scaled EEPROM cell by metal-insulator-metal (MIM) coupling
US6888192B2 (en) * 2003-04-25 2005-05-03 Atmel Corporation Mirror image non-volatile memory cell transistor pairs with single poly layer
US6919242B2 (en) * 2003-04-25 2005-07-19 Atmel Corporation Mirror image memory cell transistor pairs featuring poly floating spacers
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US20060118856A1 (en) * 2003-04-25 2006-06-08 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US6846709B1 (en) * 2003-10-06 2005-01-25 Atmel Corporation Vertical gate CMOS with lithography-independent gate length
US7169660B2 (en) * 2003-10-06 2007-01-30 Atmel Corporation Lithography-independent fabrication of small openings for forming vertical mos transistor
US20070075400A1 (en) * 2003-10-06 2007-04-05 Atmel Corporation Semiconductor device with a toroidal-like junction
US20070087557A1 (en) * 2003-10-06 2007-04-19 Atmel Corporation Semiconductor device with a toroidal-like junction
US7232732B2 (en) * 2003-10-06 2007-06-19 Atmel Corporation Semiconductor device with a toroidal-like junction
US7338875B2 (en) * 2003-10-06 2008-03-04 Atmel Corporation Method of fabricating a semiconductor device having a toroidal-like junction

Also Published As

Publication number Publication date
US6998670B2 (en) 2006-02-14
EP1721336A2 (en) 2006-11-15
CN1947251A (en) 2007-04-11
WO2005081798A2 (en) 2005-09-09
TW200532758A (en) 2005-10-01
US20040212005A1 (en) 2004-10-28
WO2005081798A3 (en) 2005-11-24
US20060118856A1 (en) 2006-06-08

Similar Documents

Publication Publication Date Title
US20060113583A1 (en) Twin EEPROM memory transistors with subsurface stepped floating gates
US5504028A (en) Method of forming a dynamic random memory device
US5399891A (en) Floating gate or flash EPROM transistor array having contactless source and drain diffusions
JP3065577B2 (en) Semiconductor device and method of forming the same
US20070134875A1 (en) Multi-level memory cell array with lateral floating spacers
US8114737B2 (en) Methods of forming memory cells on pillars and memories with memory cells on pillars
US6004844A (en) Unit cell layout and transfer gate design for high density DRAMs
US20070029603A1 (en) Method of fabricating cell of nonvolatile memory device with floating gate
US20050164452A1 (en) Mirror image non-volatile memory cell transistor pairs with single poly layer
US5414286A (en) Nonvolatile memory, method of fabricating the same, and method of reading information from the same
US20080169500A1 (en) Low voltage non-volatile memory cell with shared injector for floating gate
US5830791A (en) Manufacturing process for a DRAM with a buried region
KR19980055726A (en) Flash memory device and program, erase and read method using same
US5663585A (en) DRAM having a buried region contacted through a field region
US20020089010A1 (en) Semiconductor device comprising a non-volatile memory cell
US20050270864A1 (en) Memory cell arrangement having dual memory cells
JPH1084050A (en) Field-effect transistor and its manufacturing method

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION