US20060114152A1 - Method to eliminate PLL lock-up during power up for high frequency synthesizer - Google Patents
Method to eliminate PLL lock-up during power up for high frequency synthesizer Download PDFInfo
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- US20060114152A1 US20060114152A1 US11/271,343 US27134305A US2006114152A1 US 20060114152 A1 US20060114152 A1 US 20060114152A1 US 27134305 A US27134305 A US 27134305A US 2006114152 A1 US2006114152 A1 US 2006114152A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/0607—Offset or drift compensation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/23—Testing, monitoring, correcting or calibrating of receiver elements
- G01S19/235—Calibration of receiver components
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/34—Power consumption
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/35—Constructional details or hardware or software details of the signal processing chain
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
Definitions
- the present invention relates generally to Global Positioning System (GPS) receivers, and in particular, to a method and apparatus to eliminate Phase-Lock Loop (PLL) lock-up for high frequency synthesizers used in GPS receivers.
- GPS Global Positioning System
- PLL Phase-Lock Loop
- GPS Global System for Mobile communications
- GPS technology is being combined with these devices, the GPS chips are being placed in widely ranging applications. Some of these applications require that the GPS receiver function at low power levels, where GPS receiver manufacturers utilize techniques to shut off portions of the GPS receiver to conserve power consumption.
- frequency synthesizer When the power is turned on and off to portions of the GPS receiver, some of the components of the GPS receiver must be reset when powered up, which may place them in a condition that would provide errors for the GPS receiver.
- One of these components is a frequency synthesizer.
- frequency synthesizers are placed in a condition called a “lock-up” condition, where the frequency output of the synthesizer cannot be changed as in normal operation. This prevents the frequency synthesizer from performing required functions in the GPS receiver.
- the present invention discloses a method and apparatus for eliminating PLL lock-up during power up for high frequency synthesizers.
- a method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with an optimum signal.
- VCO Voltage Controlled Oscillator
- Such a method further optionally forces the VCO to high amplitude and high frequency during power up, the feedback loop being a phase-locked loop, the divider being operated in a preferred region of operation.
- a Global Positioning System (GPS) Receiver in accordance with the present invention comprises a radio frequency section, a baseband section, and a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency and high amplitude when the feedback loop is at a low voltage at power-up of the GPS receiver.
- GPS Global Positioning System
- Such a GPS receiver further optionally includes the frequency source being a Voltage Controlled Oscillator (VCO), the feedback loop being a phase-locked loop (PLL), a divider, coupled to the frequency source within the phase-locked loop, the VCO forced to a high amplitude and high frequency when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.
- VCO Voltage Controlled Oscillator
- PLL phase-locked loop
- divider coupled to the frequency source within the phase-locked loop, the VCO forced to a high amplitude and high frequency when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.
- FIG. 1A illustrates a block diagram of the related art
- FIGS. 1B and 1C illustrate transfer functions for a VCO as performed in the related art
- FIG. 2 illustrates divider operation regions of a divider of the present invention
- FIG. 3A illustrates a circuit with transfer functions in accordance with the present invention
- FIGS. 3B and 3C illustrate transfer functions for a VCO as performed in the present invention
- FIG. 4 illustrates an application of the PLL of the present invention
- FIG. 5 illustrates a process chart for performing the present invention.
- the present invention helps to solve the problem of lock-up when the power supply used to power the frequency synthesizer, and the associated PLL's with that synthesizer, by inverting the control voltage used to control the synthesizer itself.
- FIG. 1A illustrates a block diagram of the related art.
- Phase lock loop 100 is shown, with reference clock (refclk) 102 entering a phase detector 104 .
- the output of the phase detector 104 is then coupled to a filter 106 , which provides a control voltage 108 to a voltage controlled oscillator (VCO) 110 .
- VCO voltage controlled oscillator
- the output 112 frequency of the VCO 110 is used as an output of the PLL 100 , and is also used as a feedback loop to a frequency divider 114 , which, after division, is used as an input 116 to phase detector 104 .
- Phase detector then detects the phase difference between the reference clock 102 and the output 112 of the VCO 110 .
- the phase detector 104 output 118 changes as the difference in phase changes, as does signal 108 .
- FIGS. 1B and 1C illustrate transfer functions for a VCO as performed in the related art.
- the control voltage signal 108 is at a low voltage. This forces the VCO 110 to a low amplitude and low frequency condition.
- the divider 114 operates very poorly, especially for high frequency VCOs 110 .
- CML Current Mode Logic
- FIG. 2 illustrates the operation regions of a divider of the present invention.
- Graph 200 shows a correct divider operation region 202 , an undesired operation region 204 , and the minimum voltage point 206 and maximum voltage point 208 .
- the divider does not continue to force the VCO frequency lower and lower as in the PLL 100 shown in FIG. 1 .
- the region 202 , and, specifically, point 206 will be where the divider will start up in the present invention, which is the highest frequency that the VCO can put out. This condition remains until a corrective voltage is applied, i.e., signal 108 , to lower the frequency, rather than having the system run to a low frequency all by itself.
- a divider in accordance with the design of FIG. 2 which is the design of the present invention will provide the correct frequency division at lower voltages, allowing for a wider range of uses for the divider.
- FIG. 3A illustrates a circuit with transfer functions in accordance with the present invention.
- Phase lock loop 300 is shown, with reference clock (refclk) 302 entering a phase detector 304 .
- the output of the phase detector 304 is then coupled to a filter 306 , which provides a control voltage 308 to a voltage controlled oscillator (VCO) 310 .
- VCO voltage controlled oscillator
- the output 312 frequency of the VCO is used as an output of the PLL 300 , and is also used as a feedback loop to a frequency divider 314 , which, after division, is used as an input 316 to phase detector 304 .
- Phase detector then detects the phase difference between the reference clock 302 and the output 312 of the VCO 310 .
- the phase detector 304 output 318 changes as the difference in phase changes, as does signal 308 .
- FIGS. 3B and 3C illustrate transfer functions for a VCO as performed in the present invention.
- FIGS. 3B and 3C show that when signal 308 is low in voltage, as shown on point 320 of graph 322 in FIG. 3B , the output of VCO 310 is at a high frequency. Conversely, when signal 308 is high in voltage, point 324 on graph 322 shows that the output of the VCO 310 is low in frequency.
- the control voltage signal 308 is at a low voltage, namely, at point 320 .
- divider 314 operates in the proper way, namely, in region 202 , and, as such, does not drive the VCO 310 into a lock-up condition. Since the divider 310 is operating properly, the PLL 300 is properly moved by the divider 314 , and lock-up is avoided.
- FIG. 4 illustrates an application of the PLL of the present invention.
- GPS receiver 400 is shown, with PLL 300 shown providing output 312 to other parts of the circuitry within the radio frequency (RF) section 402 and the baseband section 404 of GPS receiver 400 .
- RF radio frequency
- FIG. 5 illustrates a process chart for performing the present invention.
- Box 500 illustrates coupling a divider to a Voltage Controlled Oscillator (VCO) to create a feedback loop.
- VCO Voltage Controlled Oscillator
- Box 502 illustrates driving the divider with a signal, wherein the signal from the VCO is at high frequency when a control signal voltage is at a low voltage.
- the present invention describes a method and apparatus to eliminate PLL lock-up during power-up for a VCO.
- PLLs the techniques and devices described herein would work for other feedback loops, and such other feedback loops are considered within the scope of the present invention.
- VCOs other types of oscillators or controllable frequency sources can be used without departing from the scope of the present invention.
- the present invention would operate within the scope of the invention if the VCO would provide only the response of FIG. 3B , or FIG. 3C , and does not require both.
- the VCO could only provide a high frequency and low amplitude or low frequency and high amplitude while the divider will operate in the preferred region 202 of FIG. 2 .
- the present invention is useful in many devices, wherever a feedback loop is used to control frequency output.
- a method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with an optimum signal.
- VCO Voltage Controlled Oscillator
- Such a method further optionally forces the VCO to high frequency and high amplitude during power up, the feedback loop being a phase-locked loop, the divider being operated in a preferred region of operation.
- a Global Positioning System (GPS) Receiver in accordance with the present invention comprises a radio frequency section, a baseband section, and a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency when the feedback loop is at a low voltage at power-up of the GPS receiver.
- GPS Global Positioning System
- Such a GPS receiver further optionally includes the frequency source being a Voltage Controlled Oscillator (VCO), the feedback loop being a phase-locked loop (PLL), a divider, coupled to the frequency source within the phase-locked loop, the VCO forced to a high frequency and high amplitude when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.
- VCO Voltage Controlled Oscillator
- PLL phase-locked loop
- divider coupled to the frequency source within the phase-locked loop, the VCO forced to a high frequency and high amplitude when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.
Abstract
Description
- This application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. provisional patent application Ser. No. 60/627,595, filed Nov. 12, 2004, entitled “RF CHIP FOR GLOBAL POSITIONING SYSTEM RECEIVER,” by Lloyd Jian-Le Jiang et al., which application is incorporated by reference herein.
- 1. Field of the Invention
- The present invention relates generally to Global Positioning System (GPS) receivers, and in particular, to a method and apparatus to eliminate Phase-Lock Loop (PLL) lock-up for high frequency synthesizers used in GPS receivers.
- 2. Description of the Related Art
- The use of GPS in consumer products has become commonplace. Hand-held devices used for mountaineering, automobile navigation systems, and GPS for use with cellular telephones are just a few examples of consumer products using GPS technology.
- As GPS technology is being combined with these devices, the GPS chips are being placed in widely ranging applications. Some of these applications require that the GPS receiver function at low power levels, where GPS receiver manufacturers utilize techniques to shut off portions of the GPS receiver to conserve power consumption.
- However, when the power is turned on and off to portions of the GPS receiver, some of the components of the GPS receiver must be reset when powered up, which may place them in a condition that would provide errors for the GPS receiver. One of these components is a frequency synthesizer. At times, frequency synthesizers are placed in a condition called a “lock-up” condition, where the frequency output of the synthesizer cannot be changed as in normal operation. This prevents the frequency synthesizer from performing required functions in the GPS receiver.
- It can be seen, then, that there is a need in the art to provide a method and apparatus for eliminating PLL lock-up during power up in GPS receivers.
- To minimize the limitations in the prior art, and to minimize other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for eliminating PLL lock-up during power up for high frequency synthesizers.
- A method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with an optimum signal.
- Such a method further optionally forces the VCO to high amplitude and high frequency during power up, the feedback loop being a phase-locked loop, the divider being operated in a preferred region of operation.
- A Global Positioning System (GPS) Receiver in accordance with the present invention comprises a radio frequency section, a baseband section, and a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency and high amplitude when the feedback loop is at a low voltage at power-up of the GPS receiver.
- Such a GPS receiver further optionally includes the frequency source being a Voltage Controlled Oscillator (VCO), the feedback loop being a phase-locked loop (PLL), a divider, coupled to the frequency source within the phase-locked loop, the VCO forced to a high amplitude and high frequency when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.
- Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
-
FIG. 1A illustrates a block diagram of the related art; -
FIGS. 1B and 1C illustrate transfer functions for a VCO as performed in the related art; -
FIG. 2 illustrates divider operation regions of a divider of the present invention; -
FIG. 3A illustrates a circuit with transfer functions in accordance with the present invention; -
FIGS. 3B and 3C illustrate transfer functions for a VCO as performed in the present invention; -
FIG. 4 illustrates an application of the PLL of the present invention; and -
FIG. 5 illustrates a process chart for performing the present invention. - In the following description, reference is made to the accompanying drawings which form a part hereof, and which is shown, by way of illustration, several embodiments of the present invention. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
- Overview
- The present invention helps to solve the problem of lock-up when the power supply used to power the frequency synthesizer, and the associated PLL's with that synthesizer, by inverting the control voltage used to control the synthesizer itself.
-
FIG. 1A illustrates a block diagram of the related art. -
Phase lock loop 100 is shown, with reference clock (refclk) 102 entering aphase detector 104. The output of thephase detector 104 is then coupled to afilter 106, which provides acontrol voltage 108 to a voltage controlled oscillator (VCO) 110. Theoutput 112 frequency of the VCO 110 is used as an output of thePLL 100, and is also used as a feedback loop to afrequency divider 114, which, after division, is used as aninput 116 tophase detector 104. - Phase detector then detects the phase difference between the
reference clock 102 and theoutput 112 of theVCO 110. Thephase detector 104output 118 changes as the difference in phase changes, as doessignal 108. -
FIGS. 1B and 1C illustrate transfer functions for a VCO as performed in the related art. - Typically, as shown in
FIGS. 1B and 1C , whensignal 108 is low in voltage, as shown onpoint 120 ofgraph 122 inFIG. 1B , the output ofVCO 110 is at a low frequency. Conversely, whensignal 108 is high in voltage,point 124 ongraph 122 shows that the output of theVCO 110 is high in frequency. - Similarly, when
signal 108 is low in voltage, as shown onpoint 126 ofgraph 128 inFIG. 1C , the output ofVCO 110 is at a low amplitude. Conversely, whensignal 108 is high in voltage,point 130 ongraph 128 shows that the output of theVCO 110 is high in frequency. - During a power up condition, the
control voltage signal 108 is at a low voltage. This forces the VCO 110 to a low amplitude and low frequency condition. At low amplitudes, thedivider 114 operates very poorly, especially forhigh frequency VCOs 110. The reason for this is that thedivider 114 typically uses Current Mode Logic (CML), which is highly dependent on both amplitude and frequency. At thelow frequency point 120 andlow amplitude point 126, thedivider 114 generates the wrong divide ratio, which generatessignal 116 at a higher frequency than it should, which keeps forcing the VCO to lower and lower frequencies. Changing thereference clock signal 102 does not remedy this situation, because the feedback loop is stuck in this “lock-up” condition before thereference clock signal 102 can ever get through the phase detector. As such, theoutput 112 is at an incorrect frequency, and any circuitry using thisoutput 112 will generate incorrect results. -
FIG. 2 illustrates the operation regions of a divider of the present invention. -
Graph 200 shows a correctdivider operation region 202, anundesired operation region 204, and theminimum voltage point 206 andmaximum voltage point 208. By changing the divider to operate at a frequency other than a minimum frequency when the voltage is low, the divider does not continue to force the VCO frequency lower and lower as in thePLL 100 shown inFIG. 1 . Instead, theregion 202, and, specifically,point 206, will be where the divider will start up in the present invention, which is the highest frequency that the VCO can put out. This condition remains until a corrective voltage is applied, i.e., signal 108, to lower the frequency, rather than having the system run to a low frequency all by itself. Further, a divider in accordance with the design ofFIG. 2 , which is the design of the present invention will provide the correct frequency division at lower voltages, allowing for a wider range of uses for the divider. -
FIG. 3A illustrates a circuit with transfer functions in accordance with the present invention. -
Phase lock loop 300 is shown, with reference clock (refclk) 302 entering aphase detector 304. The output of thephase detector 304 is then coupled to afilter 306, which provides acontrol voltage 308 to a voltage controlled oscillator (VCO) 310. Theoutput 312 frequency of the VCO is used as an output of thePLL 300, and is also used as a feedback loop to afrequency divider 314, which, after division, is used as aninput 316 tophase detector 304. - Phase detector then detects the phase difference between the
reference clock 302 and theoutput 312 of theVCO 310. Thephase detector 304output 318 changes as the difference in phase changes, as does signal 308. -
FIGS. 3B and 3C illustrate transfer functions for a VCO as performed in the present invention. - Unlike
FIGS. 1B and 1C ,FIGS. 3B and 3C show that whensignal 308 is low in voltage, as shown onpoint 320 ofgraph 322 inFIG. 3B , the output ofVCO 310 is at a high frequency. Conversely, whensignal 308 is high in voltage,point 324 ongraph 322 shows that the output of theVCO 310 is low in frequency. - Similarly, when
signal 308 is low in voltage, as shown onpoint 326 ofgraph 328 inFIG. 3C , the output ofVCO 310 is at a high amplitude. Conversely, whensignal 308 is high in voltage,point 330 ongraph 328 shows that the output of theVCO 310 is low in amplitude. - During a power up condition using the
PLL 300 of the present invention, thecontrol voltage signal 308 is at a low voltage, namely, atpoint 320. This forces theVCO 310 to a high amplitude and high frequency condition. At thesepoints divider 314 operates in the proper way, namely, inregion 202, and, as such, does not drive theVCO 310 into a lock-up condition. Since thedivider 310 is operating properly, thePLL 300 is properly moved by thedivider 314, and lock-up is avoided. - Application of PLL
-
FIG. 4 illustrates an application of the PLL of the present invention. -
GPS receiver 400 is shown, withPLL 300 shown providingoutput 312 to other parts of the circuitry within the radio frequency (RF)section 402 and thebaseband section 404 ofGPS receiver 400. - Process Chart
-
FIG. 5 illustrates a process chart for performing the present invention. -
Box 500 illustrates coupling a divider to a Voltage Controlled Oscillator (VCO) to create a feedback loop. -
Box 502 illustrates driving the divider with a signal, wherein the signal from the VCO is at high frequency when a control signal voltage is at a low voltage. - In summary, the present invention describes a method and apparatus to eliminate PLL lock-up during power-up for a VCO. Although described with respect to PLLs, the techniques and devices described herein would work for other feedback loops, and such other feedback loops are considered within the scope of the present invention. Also, although described with respect to VCOs, other types of oscillators or controllable frequency sources can be used without departing from the scope of the present invention. Further, the present invention would operate within the scope of the invention if the VCO would provide only the response of
FIG. 3B , orFIG. 3C , and does not require both. For example, the VCO could only provide a high frequency and low amplitude or low frequency and high amplitude while the divider will operate in thepreferred region 202 ofFIG. 2 . Although described with respect to a GPS receiver herein, the present invention is useful in many devices, wherever a feedback loop is used to control frequency output. - A method in accordance with the present invention comprises coupling a divider to a Voltage Controlled Oscillator (VCO) to create the feedback loop, and driving the divider with an optimum signal.
- Such a method further optionally forces the VCO to high frequency and high amplitude during power up, the feedback loop being a phase-locked loop, the divider being operated in a preferred region of operation.
- A Global Positioning System (GPS) Receiver in accordance with the present invention comprises a radio frequency section, a baseband section, and a feedback loop controlled frequency source, coupled to at least one of the baseband section and the radio frequency section, wherein the frequency source is driven to a high frequency when the feedback loop is at a low voltage at power-up of the GPS receiver.
- Such a GPS receiver further optionally includes the frequency source being a Voltage Controlled Oscillator (VCO), the feedback loop being a phase-locked loop (PLL), a divider, coupled to the frequency source within the phase-locked loop, the VCO forced to a high frequency and high amplitude when the control signal is at a low voltage, and the divider being operated in a preferred region of operation when powered-up.
- The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but by the claims appended hereto and the equivalents thereof.
Claims (10)
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US11/271,343 US20060114152A1 (en) | 2004-11-12 | 2005-11-10 | Method to eliminate PLL lock-up during power up for high frequency synthesizer |
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US62759504P | 2004-11-12 | 2004-11-12 | |
US11/271,343 US20060114152A1 (en) | 2004-11-12 | 2005-11-10 | Method to eliminate PLL lock-up during power up for high frequency synthesizer |
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---|---|---|---|
US11/271,343 Abandoned US20060114152A1 (en) | 2004-11-12 | 2005-11-10 | Method to eliminate PLL lock-up during power up for high frequency synthesizer |
US11/271,342 Active 2027-03-10 US7505739B2 (en) | 2004-11-12 | 2005-11-10 | Automatic mode setting and power ramp compensator for system power on conditions |
US11/271,729 Expired - Fee Related US7170437B2 (en) | 2004-11-12 | 2005-11-10 | Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity |
US11/271,121 Active 2029-11-21 US8350600B2 (en) | 2004-11-12 | 2005-11-10 | Glitchless clock multiplexer controlled by an asynchronous select signal |
US11/273,376 Expired - Fee Related US7471152B2 (en) | 2004-11-12 | 2005-11-14 | Automatic gain control and tuned low noise amplifier for process-independent gain systems |
US11/611,276 Active US7379008B2 (en) | 2004-11-12 | 2006-12-15 | Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity |
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Application Number | Title | Priority Date | Filing Date |
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US11/271,342 Active 2027-03-10 US7505739B2 (en) | 2004-11-12 | 2005-11-10 | Automatic mode setting and power ramp compensator for system power on conditions |
US11/271,729 Expired - Fee Related US7170437B2 (en) | 2004-11-12 | 2005-11-10 | Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity |
US11/271,121 Active 2029-11-21 US8350600B2 (en) | 2004-11-12 | 2005-11-10 | Glitchless clock multiplexer controlled by an asynchronous select signal |
US11/273,376 Expired - Fee Related US7471152B2 (en) | 2004-11-12 | 2005-11-14 | Automatic gain control and tuned low noise amplifier for process-independent gain systems |
US11/611,276 Active US7379008B2 (en) | 2004-11-12 | 2006-12-15 | Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity |
Country Status (5)
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US (6) | US20060114152A1 (en) |
EP (2) | EP1815597B1 (en) |
AT (1) | ATE426948T1 (en) |
DE (1) | DE602005013565D1 (en) |
WO (3) | WO2006053204A1 (en) |
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EP1815597B1 (en) | 2009-03-25 |
WO2006053202A1 (en) | 2006-05-18 |
WO2006053204B1 (en) | 2006-07-13 |
WO2006053203B1 (en) | 2007-04-26 |
US7170437B2 (en) | 2007-01-30 |
US7505739B2 (en) | 2009-03-17 |
US20060103565A1 (en) | 2006-05-18 |
EP1815265A2 (en) | 2007-08-08 |
US8350600B2 (en) | 2013-01-08 |
US7471152B2 (en) | 2008-12-30 |
ATE426948T1 (en) | 2009-04-15 |
DE602005013565D1 (en) | 2009-05-07 |
US7379008B2 (en) | 2008-05-27 |
US20080094108A1 (en) | 2008-04-24 |
WO2006053204A1 (en) | 2006-05-18 |
US20070080839A1 (en) | 2007-04-12 |
WO2006053203A2 (en) | 2006-05-18 |
US20060114014A1 (en) | 2006-06-01 |
EP1815597A1 (en) | 2007-08-08 |
WO2006053203A3 (en) | 2007-02-01 |
US20060103465A1 (en) | 2006-05-18 |
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