US20060118856A1 - Twin EEPROM memory transistors with subsurface stepped floating gates - Google Patents
Twin EEPROM memory transistors with subsurface stepped floating gates Download PDFInfo
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- US20060118856A1 US20060118856A1 US11/333,627 US33362706A US2006118856A1 US 20060118856 A1 US20060118856 A1 US 20060118856A1 US 33362706 A US33362706 A US 33362706A US 2006118856 A1 US2006118856 A1 US 2006118856A1
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
A memory array with memory cells arranged in rows and columns with each cell having twin EEPROMs featuring subsurface stepped floating gates for electric field concentration. The twin EEPROMs employ only a single layer of poly, one portion being a floating gate of each EEPROM and another portion being word lines. The twin EEPROMs share a common subsurface electrode by having diffused control lines and a diffused bit line. The two EEPROMs are symmetric across the common electrode.
Description
- This is a divisional of pending U.S. patent application Ser. No. 10/785,160 filed Feb. 23, 2004 which is a continuation-in-part of prior application Ser. No. 10/423,637 filed Apr. 25, 2003, a continuation-in-part of prior application Ser. No. 10/465,718 filed Jun. 18, 2003, and a continuation-in-part of prior application Ser. No. 10/680,355, filed Oct. 6, 2003. All four applications are herewith incorporated by reference in their entirety.
- The invention relates to non-volatile memory transistors and, in particular, to a compact arrangement of such memory cells for an array and a method of making them.
- In prior application Ser. No. 10/423,637 entitled “Mirror Image Memory Cell Transistor Pairs Featuring Poly Floating Spacers,” as well as in prior application Ser. No. 10/465,718 entitled “Mirror Image Non-Volatile Memory Cell Transistor Pairs with Single Poly Layer,” both assigned to the assignee of the present invention, B. Lojek described an arrangement of non-volatile MOS memory transistors for a memory array wherein symmetric pairs of transistors were built in a memory array. Transistor pairs shared an electrode in a common well, such as a drain electrode, but were otherwise completely independent. The pair was manufactured between a pair of isolation regions and sharing the same substrate region, almost as if a single transistor were constructed there.
- In the prior art, single MOS floating gate transistors that stored two data bits have been devised as a way to achieve compactness. Since millions of data bits are frequently stored in non-volatile memory arrays, small savings of space are multiplied significantly over the array. In prior application Ser. No. 10/327,336 entitled “Multi-Level Memory Cell with Lateral Floating Spacers,” assigned to the assignee of the present invention, B. Lojek described how two spacers, on opposite sides of a conductive gate, behave as independent charge storage regions for separate binary data, thereby allowing a single non-volatile MOS transistor to store two binary bits. Each memory cell is connected to two bit lines and one word line. The bit lines are phased so that during a single clock cycle, first one bit line is active and then the other while a word line is active for the entire cycle. In this manner, both storage areas may be accessed for a read or write operation in a single clock cycle.
- In U.S. Pat. No. 6,043,530 to M. Chang, a MOS memory transistor construction is shown employing band-to-band tunneling. In U.S. Pat. No. 6,323,088 to F. Gonzalez et al., a multibit charge storage transistor addressing scheme is shown with phased bit lines.
- In the prior art, multibit charge storage structures are known that achieve good data density in a memory array without giving up valuable chip space. One of the problems that is encountered as density increases is that the amount of crosstalk between storage sites increases. Because the charge storage structures are so small, one charge storage location can sometimes influence another. On the other hand, separation of charge storage sites gives up chip space. The ultimate separation is one dedicated transistor for each data bit. Accordingly, an object of the invention is to provide good separation for data bits afforded by dedicated transistors yet achieve the compactness of multibit charge storage structures for a non-volatile memory array.
- The above object has been achieved with a memory array having cells with twin EEPROM memory transistors that occupy a space almost the same size as a single EEPROM memory transistor. The twin transistors of each cell are symmetrically arranged in a common substrate and feature a single poly layer, with portions used as floating gates that are stepped below the level of the substrate surface, yet insulated from the substrate by thin oxide. The floating gate electrically communicates with a subsurface electrode that participates in charge transfer to the floating gate. The usual EEPROM control gate is replaced by a first capacitor wherein the same poly portion used to form the floating gate extends to form a second plate of the first capacitor. The first plate of the first capacitor is a control line connected to a phased signal source whereby phasing of plates of the twin cells allows each transistor to act independently. The drain of each transistor is connected to one plate of a second capacitor and to a bit line while the second plate is connected to a word line.
- By stepping the floating gate into the substrate and forming a floating gate corner in the substrate, the intensity of electric field from a subsurface electrode will increase and enhance tunneling action.
-
FIG. 1 is an electrical schematic drawing of memory cells forming the core of a memory array of the present invention. -
FIG. 2 is a side sectional view of an early manufacturing step for a memory transistor in the memory cells ofFIG. 1 . -
FIG. 3 is a top view of a mask for making a substrate step shown in the sectional view ofFIG. 2 . -
FIG. 4 is a top view of a layout in an early manufacturing stage of twin memory cells shown inFIG. 1 . -
FIG. 5 is a side sectional view taken along lines 5-5 inFIG. 4 . -
FIG. 6 is a side sectional view taken along lines 6-6 inFIG. 4 . -
FIG. 7 is a top view of a layout in an intermediate manufacturing stage of twin memory cells shown inFIG. 1 . -
FIG. 8 is a side sectional view taken along lines 8-8 inFIG. 7 . -
FIG. 9 is a side sectional view followingFIG. 8 at a later stage in manufacturing. -
FIG. 10 is a top view of a contact mask superposed on the top view ofFIG. 7 , with conductor shading for the single polysilicon layer. -
FIG. 11 is an electrical schematic drawing of twin symmetric memory cells shown inFIG. 1 redrawn for comparison withFIG. 10 , including locations of contacts shown inFIG. 10 . - With reference to
FIG. 1 , amemory cell 13 in amemory array 10 is seen to have first and secondnon-volatile memory transistors first memory transistor 15 has adrain 21 connected toselect capacitor 19, a floating gate 23 connected tocontrol capacitor 29 and asource 25 connected to thesource contact 27. - Select
capacitor 19 has afirst electrode 31 connected todrain 21 offirst memory transistor 15 and also connected to the first bit line, BL1. Thesecond electrode 33 ofselect capacitor 19 is connected to word line WL1. The word line WL1 is extended fromfirst electrode 31 alongline 35 into another cell. The floating gate 23 ofmemory transistor 15 is connected to afirst electrode 37 ofcontrol capacitor 29, whilesecond electrode 39 is connected to a firstcontrol line terminal 41. A pulse onterminal 41 charges thesecond electrode 39, causing induced charge to appear onfirst electrode 37 which forms a floating gate together with electrode 23. This is one of two ways in which charge appears on the floating gate 23. Another way for charge to appear is by tunneling or electron injection from source ordrain electrode source contact 27 charge may be transferred onto the floating gate 23 by tunneling charge transfer mechanisms. Just as the word line WL1 extends into another memory cell in the same column alongline 35, bit line BL1 is also extended into a memory cell in the same row alongline 43. - The
second memory transistor 115 is symmetric withfirst memory transistor 115 relative tosource contact 27. Thesecond memory transistor 115 has a floatinggate 123 which may be charged bycontrol capacitor 129.Memory transistor 115 has adrain electrode 121 connected to afirst plate 131 ofselect capacitor 119 and asource electrode 125 connected to sourcecontact 27. Thefirst plate 131 is also connected to the bit line BL1. The second plate ofcapacitor 119 is connected to the word line WL2. The word line WL2 is extended from thefirst electrode 131 alongline 135 to a control capacitor (not shown) into a neighboring cell in the same column. Thebit line 43 similarly extends from the first electrode ofselect capacitor 119 into a neighboring cell in the same row. -
Memory cell 13 is typical of the memory cells in thememory array 10. Each cell is seen to have twin non-volatile memory transistors that are symmetric about a source contact, such assource contact 27. The two memory transistors have floating gates associated with two control capacitors on the one hand and have drain or source electrodes associated with two select capacitors on the other hand. The twocontrol line terminals source contact 27 and also share bit line BL1.Memory cell 13 is associated with two word lines, WL1 and WL2, as well as one bit line, BL1. - With reference to
FIG. 2 , a silicon p-type wafer provides a substrate doped to have a p-well with asurface 56, upon which a thin layer ofoxide 57 is grown. The oxide layer has a thickness of approximately 100 angstroms. The oxide is covered with athick photoresist layer 51 and then patterned with amask 52, shown inFIG. 3 . The mask is approximately square with a dimension near the lower limit of resolution of photolithography. The photoresist is then etched so that well-definedsteps depression 58 with upper and lower corners to a depth of approximately 500 angstroms below thesubstrate surface 56. The facing corners ofsteps gate oxide 57. - With reference to
FIG. 4 , a mask set is shown defining the active regions of two memory cells. The mask set includesmasks masks FIG. 5 . Trenches in p-well or p-substrate 50 (FIG. 6 ) of a p-type silicon wafer substrate are filled withdielectric insulator material FIG. 5 ), typically silicon dioxide. The areas that are not dielectric material are subject to doping either by diffusion or implantation. This allows the memory cells to have diffused bit lines BL1 and BL2. - Turning to
FIG. 6 , when doping of subsurface regions is complete, the substrate is coated with oxide, previously described inFIG. 2 but not shown inFIG. 6 , and thedepression 58 is formed below thesurface 56 of substrate p-well substrate 50. Thedepression 58 has steps orcorners corners FIG. 4 also. - With reference to
FIG. 7 , the diffused regions previously described with reference toFIG. 4 may be seen. The diffused regions include the areas where source masks 52 and 55 as well as the control line diffusions 62, 64, 66, and 68. The diffused bit lines BL1 and BL2 are also seen. All of these structures lie below the surface of the p-well, or p-substrate, including steps orcorners - A layer of poly is deposited over the substrate surface and then etched leaving floating
members source mask regions - In
FIG. 8 , the p-well substrate 50 is seen withgate oxide layer 57 over the substrate surface including thedepression 58. The poly layer deposited over the substrate has portions which define floatinggates corners gate regions -
FIG. 9 followsFIG. 8 at a further point in the manufacturing process. Subsurface implants have been made in p-well substrate 50, particularlysource implant 92, as well asdrain implants poly floating gates sidewall spacers gate 82. Similarly, word lines WL1 and WL2 have sidewall spacers such asspacers ILD layer 101, is deposited over the poly one layer. TheILD layer 101 is masked and etched to create holes that allow insertion ofmetal contacts Metal contacts Metal contact 104 contacts acommon subsurface electrode 92. The relation of the metal contacts with the top view ofFIG. 7 may be seen inFIG. 10 . - In
FIG. 10 , the position ofmetal contacts contacts mask 52 that defines a common electrode for twin side-by-side memory transistors. In other words, contact 104 is located at a plane of symmetry for the twin EEPROM transistors. InFIG. 10 , the single poly layer has been shaded, with portions of the layer formingpoly members poly members line diffusions metal contacts - In
FIG. 11 positions of the contacts of the memory cell in the top view ofFIG. 10 are indicated relative to an electrical schematic of a memory cell as shown inFIG. 1 . A total of five contacts is used for each cell with two contacts, 102 and 106, being on the bit line BL1. Thecontact 104 is associated with the common source between the twin symmetric memory transistors. Thecontacts capacitors FIG. 11 may be projected upwardly, towardsFIG. 10 , where a rough comparison can be made of the various circuit elements. InFIG. 10 , the word line WL1 is seen to overlie the bit line BL1 but spaced apart by insulator thereby formingcapacitor 19 inFIG. 11 . Similarly, a portion ofpoly member 82 is seen to overliecontrol line diffusion 62 thereby formingcapacitor 29 inFIG. 11 .
Claims (7)
1. A memory array having a plurality of memory cells, each cell comprising:
a pair of parallel word lines, each word line having a pair of first capacitors in series therewith, each first capacitor having a pair of plates;
a bit line associated with one capacitor plate of each first capacitor;
a pair of EEPROM memory transistors each having a drain, source and gate, the drain of each memory transistor connected to the one capacitor plate of each respective first capacitor, the sources of the pair of transistors mutually joined in a common electrode, and the gate of each transistor being a floating gate having a step therein for electric field concentration; and
a pair of second capacitors each having one plate associated with a control line input terminal and another plate connected to the floating gate of an EEPROM transistor.
2. The memory array of claim 1 wherein the step in each floating gate is at least partially below a silicon surface of a silicon wafer, said step having top and bottom corners.
3. The memory array of claim 1 wherein said EEPROM transistors have first portions of a single layer of poly as floating gates.
4. The memory array of claim 3 wherein said memory cells have a second portion of said single layer of poly functioning as said word lines.
5. The memory array of claim 2 wherein said bit line is diffused below the surface of said silicon wafer.
6. The memory array of claim 1 wherein said first capacitors are formed by an intersection of said word lines with said bit line.
7. The memory array of claim 1 wherein said pair of word lines, the pair of second capacitors, and the pair of EEPROM transistors are symmetrically disposed about the common electrode.
Priority Applications (1)
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US11/333,627 US20060118856A1 (en) | 2003-04-25 | 2006-01-17 | Twin EEPROM memory transistors with subsurface stepped floating gates |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US10/423,637 US6919242B2 (en) | 2003-04-25 | 2003-04-25 | Mirror image memory cell transistor pairs featuring poly floating spacers |
US10/465,718 US6888192B2 (en) | 2003-04-25 | 2003-06-18 | Mirror image non-volatile memory cell transistor pairs with single poly layer |
US10/680,355 US7232732B2 (en) | 2003-10-06 | 2003-10-06 | Semiconductor device with a toroidal-like junction |
US10/785,160 US6998670B2 (en) | 2003-04-25 | 2004-02-23 | Twin EEPROM memory transistors with subsurface stepped floating gates |
US11/333,627 US20060118856A1 (en) | 2003-04-25 | 2006-01-17 | Twin EEPROM memory transistors with subsurface stepped floating gates |
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US10/785,160 Division US6998670B2 (en) | 2003-04-25 | 2004-02-23 | Twin EEPROM memory transistors with subsurface stepped floating gates |
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US20060118856A1 true US20060118856A1 (en) | 2006-06-08 |
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US10/785,160 Expired - Lifetime US6998670B2 (en) | 2003-04-25 | 2004-02-23 | Twin EEPROM memory transistors with subsurface stepped floating gates |
US11/333,627 Abandoned US20060118856A1 (en) | 2003-04-25 | 2006-01-17 | Twin EEPROM memory transistors with subsurface stepped floating gates |
US11/332,908 Abandoned US20060113583A1 (en) | 2003-04-25 | 2006-01-17 | Twin EEPROM memory transistors with subsurface stepped floating gates |
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US10/785,160 Expired - Lifetime US6998670B2 (en) | 2003-04-25 | 2004-02-23 | Twin EEPROM memory transistors with subsurface stepped floating gates |
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US (3) | US6998670B2 (en) |
EP (1) | EP1721336A2 (en) |
CN (1) | CN1947251A (en) |
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WO (1) | WO2005081798A2 (en) |
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US20090256183A1 (en) * | 2008-04-14 | 2009-10-15 | Macronix International Co., Ltd | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor |
US20090256184A1 (en) * | 2008-04-14 | 2009-10-15 | Macronix International Co., Ltd. | Single Gate Nonvolatile Memory Cell With Transistor and Capacitor |
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
US9318497B2 (en) | 2014-03-21 | 2016-04-19 | SK Hynix Inc. | Nonvolatile memory devices having single-layered floating gates |
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US7102188B1 (en) * | 2005-04-05 | 2006-09-05 | Ami Semiconductor, Inc. | High reliability electrically erasable and programmable read-only memory (EEPROM) |
US8997255B2 (en) | 2006-07-31 | 2015-03-31 | Inside Secure | Verifying data integrity in a data storage device |
US7439567B2 (en) * | 2006-08-09 | 2008-10-21 | Atmel Corporation | Contactless nonvolatile memory array |
US8352752B2 (en) * | 2006-09-01 | 2013-01-08 | Inside Secure | Detecting radiation-based attacks |
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Also Published As
Publication number | Publication date |
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US20060113583A1 (en) | 2006-06-01 |
US20040212005A1 (en) | 2004-10-28 |
WO2005081798A3 (en) | 2005-11-24 |
WO2005081798A2 (en) | 2005-09-09 |
US6998670B2 (en) | 2006-02-14 |
TW200532758A (en) | 2005-10-01 |
CN1947251A (en) | 2007-04-11 |
EP1721336A2 (en) | 2006-11-15 |
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