US20060121650A1 - Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device - Google Patents

Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device Download PDF

Info

Publication number
US20060121650A1
US20060121650A1 US11/345,027 US34502706A US2006121650A1 US 20060121650 A1 US20060121650 A1 US 20060121650A1 US 34502706 A US34502706 A US 34502706A US 2006121650 A1 US2006121650 A1 US 2006121650A1
Authority
US
United States
Prior art keywords
electrically
pad
pads
conductive
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/345,027
Inventor
Rich Fogal
Tracy Reynolds
Timothy Cowles
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/345,027 priority Critical patent/US20060121650A1/en
Publication of US20060121650A1 publication Critical patent/US20060121650A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G11C29/883—Masking faults in memories by using spares or by reconfiguring with partially good memories using a single defective memory device with reduced capacity, e.g. half capacity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/05578—Plural external layers being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/1613—Disposition the bump connector connecting within a semiconductor or solid-state body, i.e. connecting two bonding areas on the same semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • This invention relates to the field of semiconductor manufacture and, more particularly, to a method for customizing the functionality of a semiconductor device after probe and before assembly through the use of a ball bond, wire bond, or other electrical connection.
  • DRAM dynamic random access memories
  • SRAM static random access memories
  • microprocessors and logic devices
  • each die is measured at probe. This testing occurs at the wafer level subsequent to wafer processing and before the wafer is diced to separate each die prior to packaging. During wafer testing various semiconductor dice are found to be fully functional, some are not functional and not repairable, while others are not functional but may be repairable, depending on their failure mode. For example, if one or more storage elements of a row or column of storage capacitors is nonfunctional, a row or column of functional storage capacitors may be substituted through the use of fuse or antifuse (fusible link) devices.
  • fuse or antifuse fuusible link
  • Antifuses are commonly fabricated with a structure similar to that of a capacitor. Two conductive electrical terminals are separated by a dielectric layer. An unprogrammed “off” state, in which the antifuse is fabricated, presents a high resistance between the antifuse terminals (i.e. the terminals are electrically isolated from each other). The antifuse may also be programmed to an “on” state in which a low resistance connection between the antifuse terminals is provided (i.e. the terminals are electrically coupled or connected). To program or “blow” an antifuse to the “on” state, a large programming voltage is applied across the antifuse terminals, breaking down the interposed dielectric and forming a conductive link between the antifuse terminals. When an antifuse device is programmed “on,” it is selected to replace a nonfunctional storage capacitor row or column with a functional row or column.
  • FIG. 1 depicts a simplified diagram of a conventional arrangement of antifuse devices and other supporting circuitry.
  • an antifuse device for example device AF( 0 ) (antifuse 0 )
  • the proper fuse address is output to FA( 0 ) (fuse address 0 ), which typically comprises 8 or more address bits. This activates the transistor coupled with FA( 0 ).
  • the bank comprising AF( 0 ) is selected by activating BSEL( 0 ) (bank select 0 ) which activates all transistors associated with the BSEL( 0 ) signal.
  • a column decoder (not depicted) redirects the address from the nonfunctional column (not depicted) to the redundant column RC( 0 ) associated with AF( 0 ).
  • antifuse latch AFUSE LATCH ( 0 ) associated with AF( 0 ) is activated during operation of the memory device on powerup, and the redundant column RC( 0 ) associated with AF( 0 ) replaces a nonfunctional column.
  • a similar arrangement is implemented to replace a nonfunctioning row with a redundant row.
  • the Program Circuitry when the device is in program mode (PROG high), the Program Circuitry outputs a low to transistor T 1 and a program voltage is applied to CGND. When the device is in normal operational mode, the Program Circuitry outputs a high to transistor T 1 to tie CGND to ground for proper operation.
  • a semiconductor device such as a DRAM comprises various default configurations which may be altered before encapsulation using bond options.
  • devices are typically manufactured for a “by 1” ( ⁇ 1) data width, such that only one data out line (DQ) is active to supply one data bit for each read cycle.
  • the data width for the device can be changed by wire bonding together a “bond option pad” to a lead frame lead finger which is also electrically coupled with V CC or GND to modify its configuration.
  • the device data width may be modified to a ⁇ 8 configuration, a ⁇ 16 configuration, a ⁇ 32 configuration, etc.
  • the device is manufactured to function in one manner if no bond options are selected, and will function in another manner if one or more bond options are selected.
  • the ball bond is a first end of a bond wire and is attached to a bond pad of the die.
  • a second end of the bond wire is attached to a lead finger of the lead frame, then the lead finger and die are encapsulated or otherwise packaged.
  • the lead is electrically coupled with power or ground, which determines how the die functions.
  • the functionality of the die therefore, is determined by a source external to the die, as the die will function one way if the lead is coupled with power, and another way if it is coupled with ground. Whether the lead will be coupled with power or ground is determined before the wire bond is connected, but the actual functionality depends on whether the lead is connected with power or ground.
  • the present invention provides a new method which, among other advantages, allows for the selection of semiconductor device parameters prior to encapsulation using one or more ball bond, wire bond, or other connection approaches.
  • a semiconductor device is manufactured having a circuit which is separated into two or more segments.
  • the circuit may be designed in a number of different embodiments to control various and diverse device parameters, for example including device latency, aspects of antifuse operation, device density (such as selecting a device to operate as a 64 megabit or 128 megabit device), and various power functions.
  • the circuit further includes at least first and second adjacent conductive pad portions which may be electrically coupled using a ball bond or wire bond. These conductive pad portions are not accessible through the final package lead fingers.
  • the semiconductor device will not function unless two or more of the adjacent conductive pads are shorted together. In other embodiments of the invention the semiconductor device will function in one manner if the adjacent pads are not shorted together, and will function in another manner if the pads are shorted together.
  • FIG. 1 is a block diagram depicting conventional antifuse circuitry
  • FIGS. 2A-7 depict various arrangements for conductive pads which provide circuit segment terminations
  • FIG. 8 is a block diagram depicting an antifuse circuit comprising segmented circuit portions which terminate in conductive pads
  • FIGS. 9A and 9B together comprise a block diagram depicting circuitry associated with an antifuse circuit implementing an embodiment of the invention
  • FIG. 10 is a conventional circuit associated with user-programmable device column address strobe (CAS) latency
  • FIG. 11 is a table listing the latency selected by various combinations of addresses A 4 -A 6 during mode register definition
  • FIG. 12 depicts a circuit in accordance with an embodiment of the invention for hard wiring device latency during device manufacture
  • FIG. 13 is a block diagram depicting an embodiment of the invention to short V SS to V SSQ ( 13 B) or to leave an open between V SS and V SSQ ( 13 A);
  • FIG. 14 depicts a circuit in accordance with an embodiment of the invention for selecting a semiconductor device to function as a 128 megabit device or as a 64 megabit device.
  • a semiconductor device manufactured in accordance with one embodiment of the invention comprises a semiconductor wafer substrate assembly which may be an entire undiced semiconductor wafer or other large scale semiconductor substrate, two or more unsegmented semiconductor dice, or a single semiconductor die. Any of the foregoing may be hereinafter referenced as a “wafer section.”
  • the substrate assembly comprises an electrical circuit segmented into two or more separate parts or portions, with each circuit portion electrically isolated from the other. Each circuit segment terminates in a conductive pad or “mini-pad” which is physically located near the mini-pad of the other circuit segment. The pads are arranged to facilitate their electrical attachment, which shorts together the two separate circuit parts and facilitates completion of the circuit.
  • circuits portions may each be complete circuits which function in one manner if the mini-pads are not electrically connected, and will function in another manner if the mini-pads are electrically connected.
  • FIGS. 2A-7 depict several pad layouts which terminate each of at least two unconnected portions of a circuit.
  • a ball bond may be used to electrically couple adjacent pads, although a wire bond, screen printed conductive paste such as a conductive epoxy, and tape automated bonding assemblies comprising electrical traces on flexible dielectric substrates may also function sufficiently.
  • FIG. 2A depicts two adjacent unconnected pads (mini-pads) 2 , 4 which are in close proximity to each other to facilitate their connection using a ball bond.
  • FIG. 2B depicts two additional pads 6 , 8 , which are unrelated to pads 2 , 4 , electrically coupled to each other using a ball bond 10 .
  • Each pad 2 , 4 , 6 , 8 has associated therewith a unique conductive runner 11 , 12 , 13 , 14 which electrically couples each pad with a respective circuit portion 15 , 16 , 17 , 18 depicted in block form for simplicity of explanation.
  • a ball bond 10 which electrically connects pad 6 with pad 8 , two halves of the circuit are electrically connected and the circuit is completed.
  • connection will typically be manufactured after probe, after dicing of the wafer, and before encapsulation or other assembly of the semiconductor die.
  • Various processes may require connection prior to dicing the wafer prior to encapsulation.
  • each pad is two mils in length and 0.95 mils in width, with a 0.1 mil spacing between each pad.
  • the perimeter of the two pads combined measures two mils square.
  • FIG. 3A depicts a second embodiment comprising a pad arrangement wherein the pads 20 , 22 are of unequal size. This may be an advantage in uses where contact to one of the pads by a probe tip or other temporary connection is used to access the circuit portion connected therewith before electrically coupling the pads. By making pad 22 larger than pad 20 , contact to pad 22 using a probe tip is facilitated while maintaining the outside perimeter of pads 20 and 22 and keeping the space required for the pads to a minimum.
  • FIG. 3B depicts pads 24 , 26 electrically coupled with a ball bond 10 . Pads 24 , 26 are electrically coupled via conductive runners 13 , 14 to circuit portions 17 and 18 . Thus by electrically coupling pads 24 , 26 , the circuit comprising circuit portions 17 , 18 is completed.
  • FIG. 4A depicts another embodiment comprising three pads 30 , 31 , 32 . Each pad provides access to a portion of a single circuit, for a total of three circuit portions 33 , 34 , 35 .
  • FIG. 4B depicts a second similar structure comprising pads 36 , 37 , 38 electrically coupled to three circuit portions 39 , 40 , 41 . Once ball bond 10 is attached to pads 36 , 37 , 38 , the three portions of the circuit are electrically coupled and the circuit is completed and functional.
  • FIG. 5 depicts another arrangement of pads 42 , 43 , 44 which allows connection of three circuit parts 45 , 46 , 47 through the use of a ball bond 10 or another sufficient electrical connection.
  • FIG. 6 depicts another arrangement of pads 50 , 51 , 52 , 53 which facilitates selective connection of circuit portions 54 , 55 , 56 , 57 .
  • circuit portions 54 , 55 , 56 are electrically coupled through ball bonds 58 , 59 while pad 53 and thus circuit portion 57 remain electrically isolated from the other three circuit portions.
  • This arrangement of pads is useful for customizing a circuit to operate in a particular way, rather than a two-pad embodiment which is either functional or not functional.
  • FIG. 7 depicts an arrangement of six pads 60 - 65 and six circuit portions 66 - 71 which may be connected with a single ball bond 10 .
  • antifuse devices may be used to replace malfunctioning rows or columns of DRAM storage capacitors with functional redundant rows or columns.
  • the voltage required to program the antifuses may eventually exceed the junction breakdown voltage of transistor T 1 .
  • CGND and thus the top antifuse plate could not be brought to a level which would program the antifuse in an acceptable period of time without damaging other transistors which may be connected to CGND for normal operation of the semiconductor device.
  • FIG. 8 depicts one antifuse circuit implementation using the pad arrangement as depicted in FIG. 3 for use with antifuse devices. This implementation overcomes the breakdown voltage problem described for the FIG. 1 structure.
  • FIG. 8 depicts an antifuse structure in which the antifuse circuit is segmented into two parts 80 and 82 . Segment 80 terminates at pad 84 , and segment 82 terminates at pad 86 .
  • a voltage source available through a physical connection such as a probe tip (not depicted) is electrically coupled with pad 86 , for example by physical contact with pad 86 in a manner typical of probe tips.
  • pad 86 is larger than pad 84 to provide a larger contact area for the probe tip while maintaining a small combined perimeter of pads 84 , 86 .
  • This embodiment may also allow for the formation of fewer circuit devices on the circuit portion coupled with pad 84 .
  • fuses are programmed after encapsulation of the die, and in these devices the circuitry depicted would be required.
  • programming fuses after encapsulating the semiconductor die is not enabled, some circuitry may not be necessary.
  • the program circuitry and transistor T 1 are not necessary with the FIG. 8 structure, but rather pad 84 could be coupled directly with ground.
  • bonding pad 84 to pad 86 would tie CGND directly to ground. This would free up space for additional device circuitry, or allow for the formation of a smaller die.
  • circuit of FIG. 8 would not allow proper operation of the semiconductor device without coupling of the two circuit portions. While the antifuse devices may be programmed without coupling the two pads 84 , 86 , proper functional replacement of nonfunctioning rows and columns with redundant rows and columns is not possible until coupling the two circuit portions to form a complete circuit.
  • FIG. 9 is a block diagram depicting additional details of an antifuse circuit comprising an embodiment of the instant invention which overcomes problems of conventional antifuse circuitry.
  • Electronic devices using memory such as synchronous dynamic random access memory (SDRAM) are typically manufactured such that device latency is programmable by the user during device powerup.
  • FIG. 10 depicts a conventional circuit which allows user-selectable latency using addresses A 4 -A 6 .
  • FIG. 11 is a table listing the three addresses available for output on A 4 -A 6 to set latency to 1, 2, or 3. All other latency addresses which are not depicted are reserved.
  • FIG. 12 depicts an embodiment of the invention for selecting CAS latency after the wafer has been manufactured but before encapsulation.
  • Pads 120 , 130 , and 140 are coupled with V CC , while pads 124 , 134 , and 144 are coupled with ground.
  • pads 122 , 132 , and 142 are coupled to either their associated V CC or ground pad, the latency may be set before the semiconductor die is encapsulated.
  • Pads 122 , 132 , and 142 are coupled to the nor gate inputs A 6 , A 5 , and A 4 respectively.
  • FIG. 12 further depicts a ball bond 128 coupling mini-pad 122 with mini-pad 124 (A 6 to ground), and thus a low or “0” is output to each A 6 nor gate input.
  • three pads 130 , 132 , 134 are used to select the A 5 address input to each nor gate input.
  • pads 130 and 132 are electrically coupled with a ball bond 138 , and thus a high or “1” is output to each A 5 nor gate inputs.
  • pads 140 , 142 , 144 are used to select the A 4 nor gate inputs.
  • pads 142 and 144 are electrically coupled with a ball bond 148 , and thus a low or “0” is output to the A 4 inputs.
  • a “0 1 0” is output on A 6 , A 5 , and A 4 respectively.
  • Factoring in the inverters located between pads 122 , 132 , 142 and each nor gate a “high” is output only on LAT 2 while a low is output on LAT 1 and LAT 3 . Thus a latency of “2” is selected.
  • any other testing of the device is completed, the wafer is diced, and each die is encapsulated or otherwise packaged.
  • the FIG. 12 structure may be modified for the selection of any device latency.
  • the A 6 output 122 could be coupled directly with ground (i.e. hardwired directly to ground) as the state of A 6 according to the table of FIG. 11 is always low (i.e. a latency of 1, 2, or 3 is determined using only addresses A 5 and A 4 since A 6 is always “low”). Hardwiring the A 6 output to ground would likely require less space than forming the three mini-pads 120 , 122 , 124 and forming ball bond 128 .
  • the ball bonds will be attached after dicing the wafer and prior to encapsulation. However, the ball bonds may also be attached prior to dicing the wafer.
  • FIGS. 13A and 13B Another use and embodiment of the invention is depicted in FIGS. 13A and 13B to selectively alter internal power busing connections and, therefore, to selectively alter power operating characteristics.
  • This exemplary embodiment comprises the selective coupling of V SS and V SSQ , however the invention could be used equally well to selectively couple other internal power busing features.
  • these power busing configurations may be customized for a particular use of the semiconductor die after manufacturing the die but before encapsulation.
  • optimizing the configuration for a specific use of the die is desirable but has previously required different photolithography masks for each particular attachment configuration. This use of the invention eliminates the requirement for different masks and process flows to accomplish this optimization.
  • V SSQ synchronous DRAM
  • Improving the performance of the device by internally tying together the V SS bus with the V SSQ bus is particularly useful in synchronous DRAM (SDRAM) manufacturing. This is especially true with devices which do not generate sufficient noise on the V SSQ to adversely affect the device by transferring excessive V SSQ noise to the V SS bus.
  • devices which are configured to have a ⁇ 8 data width or less generate minimal noise and allow direct connection of the V SSQ bus to the V SS bus.
  • Devices having a ⁇ 32 data width produce excessive noise on the V SSQ bus and therefore require separate, noncoupled V SSQ (or multiple V SSQ ) and V SS busses.
  • V SS and V SSQ In conventional manufacturing technology, tying V SS and V SSQ together in some devices but not in others requires two different masks, one which ties V SS and V SSQ together in devices having a ⁇ 8 data width or less, for example through the use of a metal 2 mask feature, and one which does not tie the two together in devices having a data width greater than ⁇ 8.
  • additional masks are expensive, add greatly to manufacturing costs, and also increase logistical complexity due to an increased number of process flows.
  • FIG. 13 depicts an inventive embodiment which allows electrical coupling of V SS and V SSQ in devices having a data with which allows coupling, and also allows electrical separation of V SS and V SSQ in devices which require their separation. This is accomplished using a single mask.
  • the V SS circuit device comprises a pad 160 electrically coupled therewith through an interconnect 162 .
  • V SSQ comprises a pad 164 electrically coupled therewith through an interconnect 166 .
  • pads 160 and 164 are not physically connected, as depicted in FIG. 13A .
  • a ball bond 168 or other connection means electrically couples pad 160 to pad 164 .
  • Another embodiment of the invention comprises the selection of a device to operate as a fully-functional device or as a partially-functional device.
  • a 64 megabit device may be configured internally as four 16 megabit arrays, eight 8 megabit arrays, etc.
  • 64 megabit SDRAM device (Micron part number MT48LC16M4A2, described in Micron's 64 megabit Synchronous DRAM data sheet 64MSDRAM_D, incorporated herein by reference) is configured as four 16 megabit arrays. Each 16 megabit array of this particular device is accessed using 4,096 (4K) rows and 1,024 (1K) columns, with four bits of data being written to or read from with each address.
  • Each of the four individual banks is selected using a two-bit bank select.
  • one of Micron's 128 megabit SDRAM devices (Micron part number MT48LC32M4A2, described in Micron's 128 megabit Synchronous DRAM data sheet 128MSDRAM_E, incorporated herein by reference) is configured as four 32 megabit arrays. Each 32 megabit array is accessed using 4K rows and 2K columns, with four bits of data being written to or read from with each address.
  • FIG. 14 depicts another inventive embodiment to configure a partial memory device using a pad arrangement similar to the one depicted in FIG. 2 .
  • one pad 170 is electrically coupled with V CC and one is coupled with ground 172 .
  • a ball bond 178 or other connection means couples pad 176 with ground to output a low which is inverted by inverter 180 to output a “high” on 182 and to enable storage elements 174 .
  • pad 176 is coupled with pad 170 to produce a low on 182 and to disable storage elements 174 .
  • a 128 megabit device may be configured with four arrays and four FIG. 14 circuits, thereby allowing the 128 megabit device to supply 32 megabits, 64 megabits, 96 megabits, or 128 megabits, depending on the functionality of each array.
  • each FIG. 14 circuit in the case of four circuits could selectively enable or disable 512 columns of the 2,048 columns described. It is likely that other circuits would function sufficiently using the ball bonds (or other connection means) described herein to selectively enable or disable only a portion of the memory elements of a memory device.
  • the functionality of the die with various embodiments of the present invention is not determined by an external controlled source, such as by whether a lead is coupled with power or ground. Functionality of a die with various embodiments of the present invention is instead determined by whether a ball bond is present and, if a ball bond is present, by which pads are physically connected by the ball bond or by the plurality of ball bonds. The functionality of the die is determined by the configuration of ball bonds, and cannot typically be altered once the pads have been shorted or left unconnected.
  • the ball bonds of the invention do not connect the mini-pads with lead fingers of the lead frame or to other pads or traces external to the die, but rather connect the pads to other mini-pads on the die itself and to other circuitry on the die.
  • wire bonds may be used to electrically couple the pads rather than the ball bonds previously described and depicted.
  • a semiconductor device comprising the invention may be attached along with other devices to a printed circuit board, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe.
  • the inventive device may also be useful in other electronic devices related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, or virtually any piece of consumer or industrial electronic equipment.

Abstract

A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit. Various inventive embodiments and implementations are described.

Description

  • This is a continuation of U.S. Ser. No. 09/945,084 filed Aug. 30, 2001 and issued Jan. 31, 2006 as U.S. Pat. No. 6,991,970.
    • FIELD OF THE INVENTION
  • This invention relates to the field of semiconductor manufacture and, more particularly, to a method for customizing the functionality of a semiconductor device after probe and before assembly through the use of a ball bond, wire bond, or other electrical connection.
    • BACKGROUND OF THE INVENTION
  • The manufacture of semiconductor devices such as dynamic random access memories (DRAM), static random access memories (SRAM), microprocessors, and logic devices involves a number of complex processing steps. While great care is taken during processing to ensure the steps are identical between each manufacturing lot of wafers, variability between lots, between wafers within a lot, and between dice on a single wafer commonly occurs. This processing variability results in differences in electrical performance of completed semiconductor dice.
  • The functionality and electrical performance of each die is measured at probe. This testing occurs at the wafer level subsequent to wafer processing and before the wafer is diced to separate each die prior to packaging. During wafer testing various semiconductor dice are found to be fully functional, some are not functional and not repairable, while others are not functional but may be repairable, depending on their failure mode. For example, if one or more storage elements of a row or column of storage capacitors is nonfunctional, a row or column of functional storage capacitors may be substituted through the use of fuse or antifuse (fusible link) devices. The following US patents, each assigned to Micron Technology, Inc. and incorporated herein as if set forth in their entirety, describe the formation and use of antifuse devices: U.S. Pat. No. 6,108,260 issued Aug. 22, 2000; U.S. Pat. No. 6,088,282 issued Jul. 11, 2000; U.S. Pat. No. 6,087,707 issued Jul. 11, 2000; U.S. Pat. No. 5,345,110 issued Sep. 6, 1994; U.S. Pat. No. 5,331,196 issued Jul. 19, 1994; U.S. Pat. No. 5,324,681 issued Jun. 28, 1994; U.S. Pat. No. 5,241,496 issued Aug. 31, 1993; U.S. Pat. No. 5,110,754 issued May 5, 1992.
  • Antifuses are commonly fabricated with a structure similar to that of a capacitor. Two conductive electrical terminals are separated by a dielectric layer. An unprogrammed “off” state, in which the antifuse is fabricated, presents a high resistance between the antifuse terminals (i.e. the terminals are electrically isolated from each other). The antifuse may also be programmed to an “on” state in which a low resistance connection between the antifuse terminals is provided (i.e. the terminals are electrically coupled or connected). To program or “blow” an antifuse to the “on” state, a large programming voltage is applied across the antifuse terminals, breaking down the interposed dielectric and forming a conductive link between the antifuse terminals. When an antifuse device is programmed “on,” it is selected to replace a nonfunctional storage capacitor row or column with a functional row or column.
  • FIG. 1 depicts a simplified diagram of a conventional arrangement of antifuse devices and other supporting circuitry. To program an antifuse device, for example device AF(0) (antifuse 0), the proper fuse address is output to FA(0) (fuse address 0), which typically comprises 8 or more address bits. This activates the transistor coupled with FA(0). The bank comprising AF(0) is selected by activating BSEL(0) (bank select 0) which activates all transistors associated with the BSEL(0) signal. With both FA(0) and BSEL(0) activated, the lower plate of AF(0), depicted as a curved line, is tied to ground while the lower plates of the remaining antifuses, which likely number in the thousands, are not tied to ground. Finally, to program AF(0), PROG is taken to a “high” state which, through program circuitry, ties CGND to a selected high voltage, for example 7 volts, and sends a “low” state to transistor T1. The high voltage on CGND is maintained for a period of time required to blow the fuse, which is dependent on the voltage applied to CGND. The upper plate of AF(0), depicted as a straight line, as well as the upper plates of the remaining antifuses, therefore, have the programming voltage applied thereto. With a high voltage applied to the upper plate of AF(0) and the lower plate tied to ground, the dielectric interposed between the two plates breaks down and the resistance between two plates is decreased such that the plates, in effect, are shorted together. A column decoder (not depicted) redirects the address from the nonfunctional column (not depicted) to the redundant column RC(0) associated with AF(0). Thus the antifuse latch AFUSE LATCH (0) associated with AF(0) is activated during operation of the memory device on powerup, and the redundant column RC(0) associated with AF(0) replaces a nonfunctional column. A similar arrangement is implemented to replace a nonfunctioning row with a redundant row.
  • As stated above, when the device is in program mode (PROG high), the Program Circuitry outputs a low to transistor T1 and a program voltage is applied to CGND. When the device is in normal operational mode, the Program Circuitry outputs a high to transistor T1 to tie CGND to ground for proper operation.
  • As semiconductor device manufacturing technology improves and storage capacitors continue to decrease in size, problems may result from the use of antifuse devices. One problem which may occur results from the voltage required to program the antifuse. The voltage must be high enough to break down the dielectric between the antifuse plates in a reasonable amount of time. With the large number of antifuse devices which must be programmed with conventional memory devices, often numbering in the thousands, the voltage must be maintained at a fairly high level. As the feature size of semiconductor devices decreases with future device generations, the voltage required to program the antifuse may exceed the junction breakdown voltage of transistor T1. Thus the optimum voltage applied to CGND to program the antifuse will not be obtained because any voltage above the breakdown voltage of T1 can bleed to the substrate and pull down the CGND network of devices. Further, a high voltage over an extended period of time may adversely affect other devices which have a common active area which need to be connected to the CGND node for normal operation.
  • After functional testing and device repair using row and/or column redundancy in a conventional device, fully functional devices are speed graded and otherwise tested. After wafer-level testing is completed, the semiconductor wafer is diced to singularize each semiconductor die from other dice. Each functional die is assembled, for example including attachment to a lead frame and encapsulation in plastic, while nonfunctional dice are discarded.
  • A semiconductor device such as a DRAM comprises various default configurations which may be altered before encapsulation using bond options. For example, devices are typically manufactured for a “by 1” (×1) data width, such that only one data out line (DQ) is active to supply one data bit for each read cycle. Before encapsulation, the data width for the device can be changed by wire bonding together a “bond option pad” to a lead frame lead finger which is also electrically coupled with VCC or GND to modify its configuration. By using these “bond options” the device data width may be modified to a ×8 configuration, a ×16 configuration, a ×32 configuration, etc. Thus the device is manufactured to function in one manner if no bond options are selected, and will function in another manner if one or more bond options are selected.
  • Thus with conventional devices the ball bond is a first end of a bond wire and is attached to a bond pad of the die. A second end of the bond wire is attached to a lead finger of the lead frame, then the lead finger and die are encapsulated or otherwise packaged. In use, the lead is electrically coupled with power or ground, which determines how the die functions. The functionality of the die, therefore, is determined by a source external to the die, as the die will function one way if the lead is coupled with power, and another way if it is coupled with ground. Whether the lead will be coupled with power or ground is determined before the wire bond is connected, but the actual functionality depends on whether the lead is connected with power or ground.
  • Various other device parameters are a function of their processing and cannot typically be modified. These include internal power bus configurations or connecting/disconnecting internal circuitry. In such cases different photolithography masks would typically be required to modify circuit behavior or to modify power busing architecture. Mask sets can be expensive, require several weeks to manufacture, and add to semiconductor device manufacturing costs.
  • A method and structure which overcomes the problems described above and which allows for the modification of semiconductor device parameters not previously selectable in a manner not previously available would be desirable.
    • SUMMARY OF THE INVENTION
  • The present invention provides a new method which, among other advantages, allows for the selection of semiconductor device parameters prior to encapsulation using one or more ball bond, wire bond, or other connection approaches. In accordance with one embodiment of the invention a semiconductor device is manufactured having a circuit which is separated into two or more segments. The circuit may be designed in a number of different embodiments to control various and diverse device parameters, for example including device latency, aspects of antifuse operation, device density (such as selecting a device to operate as a 64 megabit or 128 megabit device), and various power functions. The circuit further includes at least first and second adjacent conductive pad portions which may be electrically coupled using a ball bond or wire bond. These conductive pad portions are not accessible through the final package lead fingers.
  • In various embodiments of the invention, the semiconductor device will not function unless two or more of the adjacent conductive pads are shorted together. In other embodiments of the invention the semiconductor device will function in one manner if the adjacent pads are not shorted together, and will function in another manner if the pads are shorted together.
  • Additional advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram depicting conventional antifuse circuitry;
  • FIGS. 2A-7 depict various arrangements for conductive pads which provide circuit segment terminations;
  • FIG. 8 is a block diagram depicting an antifuse circuit comprising segmented circuit portions which terminate in conductive pads;
  • FIGS. 9A and 9B together comprise a block diagram depicting circuitry associated with an antifuse circuit implementing an embodiment of the invention;
  • FIG. 10 is a conventional circuit associated with user-programmable device column address strobe (CAS) latency;
  • FIG. 11 is a table listing the latency selected by various combinations of addresses A4-A6 during mode register definition;
  • FIG. 12 depicts a circuit in accordance with an embodiment of the invention for hard wiring device latency during device manufacture;
  • FIG. 13 is a block diagram depicting an embodiment of the invention to short VSS to VSSQ (13B) or to leave an open between VSS and VSSQ (13A); and
  • FIG. 14 depicts a circuit in accordance with an embodiment of the invention for selecting a semiconductor device to function as a 128 megabit device or as a 64 megabit device.
  • It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which may be determined by one of skill in the art by examination of the information herein.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • A semiconductor device manufactured in accordance with one embodiment of the invention comprises a semiconductor wafer substrate assembly which may be an entire undiced semiconductor wafer or other large scale semiconductor substrate, two or more unsegmented semiconductor dice, or a single semiconductor die. Any of the foregoing may be hereinafter referenced as a “wafer section.” The substrate assembly comprises an electrical circuit segmented into two or more separate parts or portions, with each circuit portion electrically isolated from the other. Each circuit segment terminates in a conductive pad or “mini-pad” which is physically located near the mini-pad of the other circuit segment. The pads are arranged to facilitate their electrical attachment, which shorts together the two separate circuit parts and facilitates completion of the circuit.
  • In various other embodiments more than two circuit portions and corresponding mini-pads may be used. Further, the circuits portions may each be complete circuits which function in one manner if the mini-pads are not electrically connected, and will function in another manner if the mini-pads are electrically connected.
  • FIGS. 2A-7 depict several pad layouts which terminate each of at least two unconnected portions of a circuit. As depicted in FIGS. 2A-7, a ball bond may be used to electrically couple adjacent pads, although a wire bond, screen printed conductive paste such as a conductive epoxy, and tape automated bonding assemblies comprising electrical traces on flexible dielectric substrates may also function sufficiently.
  • FIG. 2A depicts two adjacent unconnected pads (mini-pads) 2, 4 which are in close proximity to each other to facilitate their connection using a ball bond. FIG. 2B depicts two additional pads 6, 8, which are unrelated to pads 2, 4, electrically coupled to each other using a ball bond 10. Each pad 2, 4, 6, 8 has associated therewith a unique conductive runner 11, 12, 13, 14 which electrically couples each pad with a respective circuit portion 15, 16, 17, 18 depicted in block form for simplicity of explanation. Thus by providing a ball bond 10 which electrically connects pad 6 with pad 8, two halves of the circuit are electrically connected and the circuit is completed. Various circuit embodiments are described below, however this connection will typically be manufactured after probe, after dicing of the wafer, and before encapsulation or other assembly of the semiconductor die. Various processes, however, may require connection prior to dicing the wafer prior to encapsulation.
  • With current technology, gold, copper, palladium, aluminum, platinum, or tin-lead ball bonds as small as two mils in diameter may be manufactured, and the technology will likely improve to allow for ball bonds having even smaller diameters in the future. In the embodiment of FIGS. 2A and 2B, each pad is two mils in length and 0.95 mils in width, with a 0.1 mil spacing between each pad. Thus the perimeter of the two pads combined measures two mils square. Such a structure can easily be manufactured according to means known in the art by one of ordinary skill using conventional photolithography techniques similar to those used to manufacture conventional bond pads.
  • FIG. 3A depicts a second embodiment comprising a pad arrangement wherein the pads 20, 22 are of unequal size. This may be an advantage in uses where contact to one of the pads by a probe tip or other temporary connection is used to access the circuit portion connected therewith before electrically coupling the pads. By making pad 22 larger than pad 20, contact to pad 22 using a probe tip is facilitated while maintaining the outside perimeter of pads 20 and 22 and keeping the space required for the pads to a minimum. FIG. 3B depicts pads 24, 26 electrically coupled with a ball bond 10. Pads 24, 26 are electrically coupled via conductive runners 13, 14 to circuit portions 17 and 18. Thus by electrically coupling pads 24, 26, the circuit comprising circuit portions 17, 18 is completed.
  • FIG. 4A depicts another embodiment comprising three pads 30, 31, 32. Each pad provides access to a portion of a single circuit, for a total of three circuit portions 33, 34, 35. FIG. 4B depicts a second similar structure comprising pads 36, 37, 38 electrically coupled to three circuit portions 39, 40, 41. Once ball bond 10 is attached to pads 36, 37, 38, the three portions of the circuit are electrically coupled and the circuit is completed and functional.
  • FIG. 5 depicts another arrangement of pads 42, 43, 44 which allows connection of three circuit parts 45, 46, 47 through the use of a ball bond 10 or another sufficient electrical connection.
  • FIG. 6 depicts another arrangement of pads 50, 51, 52, 53 which facilitates selective connection of circuit portions 54, 55, 56, 57. In this embodiment, only circuit portions 54, 55, 56 are electrically coupled through ball bonds 58, 59 while pad 53 and thus circuit portion 57 remain electrically isolated from the other three circuit portions. This arrangement of pads is useful for customizing a circuit to operate in a particular way, rather than a two-pad embodiment which is either functional or not functional.
  • FIG. 7 depicts an arrangement of six pads 60-65 and six circuit portions 66-71 which may be connected with a single ball bond 10.
  • As discussed above in the “Background of the Invention” with reference to FIG. 1, antifuse devices may be used to replace malfunctioning rows or columns of DRAM storage capacitors with functional redundant rows or columns. With conventional antifuse device circuitry as depicted in FIG. 1, the voltage required to program the antifuses may eventually exceed the junction breakdown voltage of transistor T1. As such, CGND and thus the top antifuse plate could not be brought to a level which would program the antifuse in an acceptable period of time without damaging other transistors which may be connected to CGND for normal operation of the semiconductor device.
  • FIG. 8 depicts one antifuse circuit implementation using the pad arrangement as depicted in FIG. 3 for use with antifuse devices. This implementation overcomes the breakdown voltage problem described for the FIG. 1 structure. FIG. 8 depicts an antifuse structure in which the antifuse circuit is segmented into two parts 80 and 82. Segment 80 terminates at pad 84, and segment 82 terminates at pad 86. To program the antifuse devices a voltage source available through a physical connection such as a probe tip (not depicted) is electrically coupled with pad 86, for example by physical contact with pad 86 in a manner typical of probe tips. In this embodiment, pad 86 is larger than pad 84 to provide a larger contact area for the probe tip while maintaining a small combined perimeter of pads 84, 86. To program antifuse AF(0), each of FA(0) and BSEL(0) are activated, thus grounding the lower plate of the antifuse, and a program voltage is applied to pad 86 through the probe tip or other connection. Because transistor T1 is electrically isolated from CGND, voltage breakdown of transistor T1 does not occur. Thus a voltage applied to CGND which is above the junction breakdown voltage of T1 does not bleed to the substrate as with the conventional circuit of FIG. 1 as described in the “Background of the Invention.” After the antifuses are programmed a ball bond is formed which electrically couples pad 84 with pad 86 to complete the circuit.
  • This embodiment may also allow for the formation of fewer circuit devices on the circuit portion coupled with pad 84. In some devices fuses are programmed after encapsulation of the die, and in these devices the circuitry depicted would be required. In devices where programming fuses after encapsulating the semiconductor die is not enabled, some circuitry may not be necessary. For example, where fuse programming after die encapsulation is not enabled the program circuitry and transistor T1 are not necessary with the FIG. 8 structure, but rather pad 84 could be coupled directly with ground. Thus bonding pad 84 to pad 86 would tie CGND directly to ground. This would free up space for additional device circuitry, or allow for the formation of a smaller die.
  • It should be noted that the circuit of FIG. 8 would not allow proper operation of the semiconductor device without coupling of the two circuit portions. While the antifuse devices may be programmed without coupling the two pads 84, 86, proper functional replacement of nonfunctioning rows and columns with redundant rows and columns is not possible until coupling the two circuit portions to form a complete circuit.
  • FIG. 9 is a block diagram depicting additional details of an antifuse circuit comprising an embodiment of the instant invention which overcomes problems of conventional antifuse circuitry.
  • Another inventive embodiment is described using FIGS. 10-12. Column Address Strobe (CAS) latency is the delay, in clock cycles, between the registration of a READ command and the availability of the fist piece of output data. For latency=2, two clock cycles from a data request until data is available on the data bus, and for latency=3, three clock cycles required until data is available. Electronic devices using memory such as synchronous dynamic random access memory (SDRAM) are typically manufactured such that device latency is programmable by the user during device powerup. FIG. 10 depicts a conventional circuit which allows user-selectable latency using addresses A4-A6. After Powerup, if LDMODE and OPCODE are both true, an address output on each of A4-A6 is used to set the latency. (Circuit portion 100 associated with address A4 is repeated in 102 and 104 for addresses A5 and A6 respectively, but have not been depicted in FIG. 10 for simplicity of explanation.) A “low” on all three inputs A4-A6 to one of the three nor gates is inverted to a “high” to set latency at either 1, 2, or 3. FIG. 11 is a table listing the three addresses available for output on A4-A6 to set latency to 1, 2, or 3. All other latency addresses which are not depicted are reserved.
  • To manufacture a device with which latency is not programmable by the user, different photolithography masks would typically be required for each latency. Mask sets can be expensive, require several weeks to manufacture, and add greatly to semiconductor device manufacturing costs.
  • An application and embodiment of the instant invention may be used to reduce or eliminate the need for separate masks for each device latency for devices which do not have user-programmable latency. FIG. 12 depicts an embodiment of the invention for selecting CAS latency after the wafer has been manufactured but before encapsulation.
  • Pads 120, 130, and 140 are coupled with VCC, while pads 124, 134, and 144 are coupled with ground. By coupling pads 122, 132, and 142 to either their associated VCC or ground pad, the latency may be set before the semiconductor die is encapsulated. Pads 122, 132, and 142 are coupled to the nor gate inputs A6, A5, and A4 respectively. FIG. 12 further depicts a ball bond 128 coupling mini-pad 122 with mini-pad 124 (A6 to ground), and thus a low or “0” is output to each A6 nor gate input. Similarly, three pads 130, 132, 134 are used to select the A5 address input to each nor gate input. In this embodiment, pads 130 and 132 are electrically coupled with a ball bond 138, and thus a high or “1” is output to each A5 nor gate inputs. Similarly, pads 140, 142, 144 are used to select the A4 nor gate inputs. In this embodiment, pads 142 and 144 are electrically coupled with a ball bond 148, and thus a low or “0” is output to the A4 inputs. With the FIG. 12 embodiment a “0 1 0” is output on A6, A5, and A4 respectively. Factoring in the inverters located between pads 122, 132, 142 and each nor gate, a “high” is output only on LAT2 while a low is output on LAT1 and LAT3. Thus a latency of “2” is selected.
  • Once the ball bonds are formed, for example as depicted in the FIG. 12 embodiment to select a latency of “2,” any other testing of the device is completed, the wafer is diced, and each die is encapsulated or otherwise packaged. The FIG. 12 structure may be modified for the selection of any device latency.
  • In the particular embodiment of FIG. 12, the A6 output 122 could be coupled directly with ground (i.e. hardwired directly to ground) as the state of A6 according to the table of FIG. 11 is always low (i.e. a latency of 1, 2, or 3 is determined using only addresses A5 and A4 since A6 is always “low”). Hardwiring the A6 output to ground would likely require less space than forming the three mini-pads 120, 122, 124 and forming ball bond 128.
  • In many process flows the ball bonds will be attached after dicing the wafer and prior to encapsulation. However, the ball bonds may also be attached prior to dicing the wafer.
  • Another use and embodiment of the invention is depicted in FIGS. 13A and 13B to selectively alter internal power busing connections and, therefore, to selectively alter power operating characteristics. This exemplary embodiment comprises the selective coupling of VSS and VSSQ, however the invention could be used equally well to selectively couple other internal power busing features. Further, as the connections are easily performed using ball bonds or other similar attachment means, these power busing configurations may be customized for a particular use of the semiconductor die after manufacturing the die but before encapsulation. As different internal power busing attachment configurations work with varying degrees of success with a particular use of the invention, optimizing the configuration for a specific use of the die is desirable but has previously required different photolithography masks for each particular attachment configuration. This use of the invention eliminates the requirement for different masks and process flows to accomplish this optimization.
  • Improving the performance of the device by internally tying together the VSS bus with the VSSQ bus is particularly useful in synchronous DRAM (SDRAM) manufacturing. This is especially true with devices which do not generate sufficient noise on the VSSQ to adversely affect the device by transferring excessive VSSQ noise to the VSS bus. Typically, devices which are configured to have a ×8 data width or less generate minimal noise and allow direct connection of the VSSQ bus to the VSS bus. Devices having a ×32 data width, however, produce excessive noise on the VSSQ bus and therefore require separate, noncoupled VSSQ (or multiple VSSQ) and VSS busses. In conventional manufacturing technology, tying VSS and VSSQ together in some devices but not in others requires two different masks, one which ties VSS and VSSQ together in devices having a ×8 data width or less, for example through the use of a metal 2 mask feature, and one which does not tie the two together in devices having a data width greater than ×8. As previously stated, additional masks are expensive, add greatly to manufacturing costs, and also increase logistical complexity due to an increased number of process flows.
  • FIG. 13 depicts an inventive embodiment which allows electrical coupling of VSS and VSSQ in devices having a data with which allows coupling, and also allows electrical separation of VSS and VSSQ in devices which require their separation. This is accomplished using a single mask. In FIG. 13, the VSS circuit device comprises a pad 160 electrically coupled therewith through an interconnect 162. Further, VSSQ comprises a pad 164 electrically coupled therewith through an interconnect 166. In devices requiring separation of VSS and VSSQ, pads 160 and 164 are not physically connected, as depicted in FIG. 13A. In devices where noise from electrically coupling VSS and VSSQ is not a concern, as depicted in FIG. 13B, a ball bond 168 or other connection means electrically couples pad 160 to pad 164.
  • Another embodiment of the invention comprises the selection of a device to operate as a fully-functional device or as a partially-functional device. It is well known in the art that, for example, a 64 megabit device may be configured internally as four 16 megabit arrays, eight 8 megabit arrays, etc. For example, one particular Micron Technology, Inc. 64 megabit SDRAM device (Micron part number MT48LC16M4A2, described in Micron's 64 megabit Synchronous DRAM data sheet 64MSDRAM_D, incorporated herein by reference) is configured as four 16 megabit arrays. Each 16 megabit array of this particular device is accessed using 4,096 (4K) rows and 1,024 (1K) columns, with four bits of data being written to or read from with each address. Each of the four individual banks is selected using a two-bit bank select. Additionally, one of Micron's 128 megabit SDRAM devices (Micron part number MT48LC32M4A2, described in Micron's 128 megabit Synchronous DRAM data sheet 128MSDRAM_E, incorporated herein by reference) is configured as four 32 megabit arrays. Each 32 megabit array is accessed using 4K rows and 2K columns, with four bits of data being written to or read from with each address.
  • Some array defects are so severe that the array cannot be repaired. These defective devices are often discarded or reworked and sold as “partial” (partially functional) devices devoted to special uses which do not require fully functional devices. With a conventional device, for example one having its storage capacitors configured as four arrays, a nonfunctioning quarter or half array is disabled, typically through the use of fuse or antifuse devices. A 128 megabit device having two of four arrays disabled would therefore supply 64 megabits of memory.
  • FIG. 14 depicts another inventive embodiment to configure a partial memory device using a pad arrangement similar to the one depicted in FIG. 2. With this embodiment, one pad 170 is electrically coupled with VCC and one is coupled with ground 172. If the storage elements 174 associated with pad 176 are determined to be functional or repairable, a ball bond 178 or other connection means couples pad 176 with ground to output a low which is inverted by inverter 180 to output a “high” on 182 and to enable storage elements 174. If the elements 174 are determined to be less than fully functional and not repairable, pad 176 is coupled with pad 170 to produce a low on 182 and to disable storage elements 174. There would likely be two or more circuits similar to the circuit of FIG. 14 for a storage array analogous to an array controlled by the interconnect storage array. For example, a 128 megabit device may be configured with four arrays and four FIG. 14 circuits, thereby allowing the 128 megabit device to supply 32 megabits, 64 megabits, 96 megabits, or 128 megabits, depending on the functionality of each array. In the case of Micron's 128 megabit device described above (Micron part number MT48LC32M4A2), each FIG. 14 circuit (in the case of four circuits) could selectively enable or disable 512 columns of the 2,048 columns described. It is likely that other circuits would function sufficiently using the ball bonds (or other connection means) described herein to selectively enable or disable only a portion of the memory elements of a memory device.
  • In contrast with conventional ball bonds and bond options discussed in the Background of the Invention, the functionality of the die with various embodiments of the present invention is not determined by an external controlled source, such as by whether a lead is coupled with power or ground. Functionality of a die with various embodiments of the present invention is instead determined by whether a ball bond is present and, if a ball bond is present, by which pads are physically connected by the ball bond or by the plurality of ball bonds. The functionality of the die is determined by the configuration of ball bonds, and cannot typically be altered once the pads have been shorted or left unconnected. Further, in contrast with conventional devices, the ball bonds of the invention do not connect the mini-pads with lead fingers of the lead frame or to other pads or traces external to the die, but rather connect the pads to other mini-pads on the die itself and to other circuitry on the die.
  • Further, wire bonds may be used to electrically couple the pads rather than the ball bonds previously described and depicted. In these embodiments it may be preferable to attach the wire bonds during a conventional wire bonding process during which bond pads are wire bonded to leads of a lead frame. In most process flows this wire bonding will occur subsequent to dicing of the wafer and prior to encapsulation or other assembly of the semiconductor die.
  • A semiconductor device comprising the invention may be attached along with other devices to a printed circuit board, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe. The inventive device may also be useful in other electronic devices related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, or virtually any piece of consumer or industrial electronic equipment.
  • While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims (25)

1. A method used during fabrication of a semiconductor device comprising:
forming a semiconductor wafer section comprising first, second, and third pads thereon which are electrically separated from each other;
forming a first circuit portion electrically coupled with the first pad;
forming a second circuit portion electrically coupled with the second pad and electrically isolated from the first circuit portion;
forming a third circuit portion electrically coupled with the third pad and electrically isolated from the first and second circuit portions;
enabling the semiconductor device to function in only one of a first operational mode and a second operational mode by selectively electrically connecting together either the first and second pads to enable the first operational mode or the second and third pads to enable the second operational mode; and
encapsulating the semiconductor wafer section such that selectively electrically connecting together either the first and second pads or the second and third pads is not possible when the semiconductor wafer section is encapsulated.
2. The method of claim 1 further comprising attaching a single ball bond to two of the pads during the selective electrical connection.
3. The method of claim 1 further comprising attaching a wire bond to two of the pads during the selective electrical connection.
4. The method of claim 1 further comprising screen printing a conductive epoxy to two of the pads during the selective electrical connection.
5. The method of claim 1 further comprising:
providing a transistor during the providing of the first circuit portion and providing one of a fuse and antifuse array during the providing of the second circuit portion; and
selectively electrically connecting the first pad with the second pad thereby electrically coupling the one of the fuse and antifuse array to the transistor during the selective electrical connection of the first and second pads.
6. The method of claim 1 further comprising:
providing a lead frame;
attaching the wafer section to the lead frame; then
encapsulating the lead frame during the encapsulation of the semiconductor wafer section.
7. A method used during fabrication of a semiconductor device, comprising:
providing first and second conductive pad portions electrically isolated from each other;
providing a transistor electrically coupled with the first conductive pad portion;
providing one of a fuse array and an antifuse array electrically coupled with the second conductive pad portion;
electrically coupling the second pad portion to a voltage source;
with the second pad portion electrically coupled to the voltage source, programming the array; and
subsequent to programming the array, electrically coupling the first pad portion with the second pad portion.
8. The method of claim 7 further comprising electrically coupling the second pad portion to the voltage source through a probe tip during the electrical coupling of the second pad portion with the voltage source.
9. The method of claim 7 further comprising:
providing a CGND node during the providing of the second pad portion;
electrically coupling the CGND node to the transistor during the electrical coupling of the first pad portion with the second pad portion; and
tying the CGND node to ground through the transistor during an operational mode of the semiconductor device subsequent to programming the array.
10. A method used during fabrication of a semiconductor device comprising:
providing a semiconductor wafer substrate assembly;
providing a bond pad comprising at least three separate sections electrically isolated from each other, wherein the three sections of the bond pad each overlie the wafer substrate assembly;
providing at least three circuit portions with one circuit portion electrically connected with only one of the bond pad portions;
electrically interconnecting the at least three bond pad sections to electrically connect the at least three circuit portions.
11. The method of claim 10 further comprising:
providing a lead frame; and
subsequent to electrically interconnecting the at least three bond pad sections, attaching the semiconductor wafer substrate assembly to the lead frame.
12. The method of claim 10 further comprising attaching a ball bond to the at least three bond pad sections during the interconnection of the at least three bond pad sections.
13. The method of claim 10 further comprising screen printing a conductive material to contact the at least three bond pad sections during the interconnection of the at least three bond pad sections.
14. A method used during fabrication of a semiconductor device comprising:
providing a semiconductor wafer substrate assembly;
providing a plurality of conductive pads electrically isolated from each other;
providing a plurality of circuits wherein each circuit is electrically connected with one of the bond pads;
selecting an operational mode of the semiconductor device by selectively connecting at least two of the plurality of conductive pads to each other to selectively connect at least two of the plurality of circuits; and
packaging the semiconductor wafer substrate assembly such that selecting the operational mode of the semiconductor device cannot be performed when the semiconductor wafer substrate assembly is packaged.
15. A method used during fabrication of a semiconductor device comprising:
providing a semiconductor wafer section;
forming first and second spaced conductive pads on the semiconductor wafer section; and
forming first and second internal power buses on the semiconductor wafer section, wherein the first power bus is electrically connected to the first conductive pad and the second power bus is electrically connected to the second conductive pad,
wherein the first and second conductive pads are adapted to be electrically coupled to each other to electrically connect the first power bus with the second power bus.
16. The method of claim 15 further comprising forming a VSS power bus and a VSSQ power bus during the formation of the first and second internal power buses.
17. The method of claim 15 further comprising electrically connecting the first conductive pad with the second conductive pad to electrically connect the VSS power bus with the VSSQ power bus.
18. A method used during fabrication of a semiconductor device having a hardwired and selectable column address strobe (CAS) latency, comprising:
providing at least one CAS latency select line;
forming at least a first conductive pad electrically coupled with a high potential, a second conductive pad electrically coupled with the CAS latency select line, and a third conductive pad electrically coupled with a low potential; and
selecting a CAS latency by either:
forming a conductor to electrically connect the first pad portion with the second pad portion to select a first CAS latency; or
forming a conductor to electrically connect the second pad portion with the third pad portion to select a second CAS latency which is different from the first CAS latency.
19. The method of claim 18 further comprising forming a ball bond during the formation of the conductor which electrically connects only two of the first, second, and third conductive pads together.
20. The method of claim 18 further comprising forming a bond wire during the formation of the conductor which electrically connects only two of the first, second, and third conductive pads together.
21. The method of claim 18 further comprising encapsulating the CAS select line and the first, second, and third conductive pads subsequent to forming the conductor.
22. A method used during fabrication of a semiconductor device, comprising:
selectively electrically connecting conductive pads located on a surface of an integrated circuit die to provide an electrically conductive path between the conductive pads, wherein the conductive path determines an operational mode of the semiconductor device; then
encapsulating the semiconductor die in a dielectric material such that the electrically conductive path is not directly accessible from outside the dielectric material.
23. A method used during fabrication of a semiconductor device, comprising:
selecting a desired operational mode for the semiconductor device from two or more operational modes;
selectively electrically connecting two or more conductive pads located on a surface of an integrated circuit die to provide an electrically conductive path between the two or more conductive pads, wherein the conductive path enables the desired operational mode of the semiconductor device; then
packaging the integrated semiconductor die in a dielectric material such that the electrically conductive path is not directly accessible by an end user of the semiconductor device.
24. A method used during fabrication of a semiconductor device, comprising:
forming a semiconductor die comprising:
a first conductive pad electrically connected to a first circuit portion;
a second conductive pad electrically connected to a second circuit portion;
a third conductive pad electrically connected to a third circuit portion,
wherein the first, second, and third circuit portions are incomplete circuits;
selectively electrically connecting either the first and second conductive pads to electrically connect the first and second incomplete circuit portions to provide a first complete circuit and a first device operational mode, or the second and third conductive pads to electrically connect the second and third incomplete circuit portions to provide a second complete circuit and a second device operational mode,
wherein the semiconductor device is nonfunctional during operation if two of the conductive pads are not electrically connected.
25. The method of claim 24 wherein the first, second, and third conductive pads are adjacently located to each other and the method further comprises placing a single ball bond on either the first and second pads or on the second and third pads during the selective electrical connection.
US11/345,027 2001-08-30 2006-01-31 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device Abandoned US20060121650A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/345,027 US20060121650A1 (en) 2001-08-30 2006-01-31 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/945,084 US6991970B2 (en) 2001-08-30 2001-08-30 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device
US11/345,027 US20060121650A1 (en) 2001-08-30 2006-01-31 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/945,084 Continuation US6991970B2 (en) 2001-08-30 2001-08-30 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device

Publications (1)

Publication Number Publication Date
US20060121650A1 true US20060121650A1 (en) 2006-06-08

Family

ID=25482595

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/945,084 Expired - Lifetime US6991970B2 (en) 2001-08-30 2001-08-30 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device
US11/345,027 Abandoned US20060121650A1 (en) 2001-08-30 2006-01-31 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/945,084 Expired - Lifetime US6991970B2 (en) 2001-08-30 2001-08-30 Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of semiconductor device

Country Status (1)

Country Link
US (2) US6991970B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267137A1 (en) * 2005-05-24 2006-11-30 International Business Machines Corporation Method and structure to prevent circuit network charging during fabrication of integrated circuits
US20070267755A1 (en) * 2006-05-16 2007-11-22 Vo Nhat D Integrated circuit having pads and input/output (i/o) cells
US20070267748A1 (en) * 2006-05-16 2007-11-22 Tran Tu-Anh N Integrated circuit having pads and input/output (i/o) cells
US20090097332A1 (en) * 2007-10-10 2009-04-16 Samsung Electronics Co., Ltd. Semiconductor memory device
CN109243991A (en) * 2017-07-10 2019-01-18 中芯国际集成电路制造(上海)有限公司 A kind of the test structure and test method, electronic device of electrochemical metal reaction
US11107549B2 (en) 2019-12-16 2021-08-31 Microsoft Technology Licensing, Llc At-risk memory location identification and management

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525982B1 (en) * 2001-09-11 2003-02-25 Micron Technology, Inc. Methods of programming and circuitry for a programmable element
DE10349749B3 (en) * 2003-10-23 2005-05-25 Infineon Technologies Ag Anti-fuse connection for integrated circuits and method for producing anti-fuse connections
ITMI20042073A1 (en) * 2004-10-29 2005-01-29 St Microelectronics Srl CONFIGURATION TERMINAL FOR INTEGRATED DEVICES AND METHOD OF CONFIGURATION OF AN INTEGRATED DEVICE
US7241646B2 (en) * 2005-03-03 2007-07-10 Texas Instruments Incorporated Semiconductor device having voltage output function trim circuitry and method for same
US7586199B1 (en) 2005-03-23 2009-09-08 Marvell International Ltd. Structures, architectures, systems, methods, algorithms and software for configuring and integrated circuit for multiple packaging types
US8405220B1 (en) * 2005-03-23 2013-03-26 Marvell International Ltd. Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types
WO2008001248A2 (en) * 2006-06-28 2008-01-03 Nxp B.V. Integrated circuit
JP5579610B2 (en) * 2007-10-12 2014-08-27 エイジャックス トッコ マグネサーミック コーポレーション Semi-liquid metal processing / detection device, and processing / detection method using the device
US20120061796A1 (en) * 2010-09-14 2012-03-15 Power Gold LLC Programmable anti-fuse wire bond pads
US9574826B2 (en) 2012-09-27 2017-02-21 Ajax Tocco Magnethermic Corporation Crucible and dual frequency control method for semi-liquid metal processing
US9236363B2 (en) 2014-03-11 2016-01-12 Freescale Semiconductor, Inc. Wedge bond foot jumper connections
EP3285294B1 (en) * 2016-08-17 2019-04-10 EM Microelectronic-Marin SA Integrated circuit die having a split solder pad
US10249587B1 (en) * 2017-12-15 2019-04-02 Western Digital Technologies, Inc. Semiconductor device including optional pad interconnect
DE102019103730B4 (en) * 2019-02-14 2021-02-04 Infineon Technologies Austria Ag CIRCUIT ARRANGEMENT WITH GALVANIC ISOLATION BETWEEN ELECTRONIC CIRCUITS

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5110754A (en) * 1991-10-04 1992-05-05 Micron Technology, Inc. Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM
US5241496A (en) * 1991-08-19 1993-08-31 Micron Technology, Inc. Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells
US5838625A (en) * 1996-10-29 1998-11-17 Micron Technology, Inc. Anti-fuse programming path
US5858149A (en) * 1995-11-21 1999-01-12 Anam Semiconductor Inc. Process for bonding semiconductor chip
US5898217A (en) * 1998-01-05 1999-04-27 Motorola, Inc. Semiconductor device including a substrate having clustered interconnects
US6078100A (en) * 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
US6088282A (en) * 1996-09-06 2000-07-11 Micron Technology, Inc. System and method for an antifuse bank
US6087707A (en) * 1996-04-16 2000-07-11 Micron Technology, Inc. Structure for an antifuse cell
US6094388A (en) * 1999-07-01 2000-07-25 Micron Technology, Inc. Methods of identifying defects in an array of memory cells and related integrated circuitry
US6097098A (en) * 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
US6100118A (en) * 1998-06-11 2000-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of metal fuse design for redundancy technology having a guard ring
US6154851A (en) * 1997-08-05 2000-11-28 Micron Technology, Inc. Memory repair
US6169331B1 (en) * 1998-08-28 2001-01-02 Micron Technology, Inc. Apparatus for electrically coupling bond pads of a microelectronic device
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6271574B1 (en) * 1998-05-14 2001-08-07 Stmicroelectronics S.A. Integrated circuit fuse with localized fusing point
US6320242B1 (en) * 1997-10-22 2001-11-20 Seiko Instruments Inc. Semiconductor device having trimmable fuses and position alignment marker formed of thin film
US20020017729A1 (en) * 1999-01-25 2002-02-14 Macpherson John Sacrificial bond pads for laser configured integrated circuits
US20020020058A1 (en) * 2000-08-18 2002-02-21 Yuji Saito Method of mounting a BGA
US6423582B1 (en) * 1999-02-25 2002-07-23 Micron Technology, Inc. Use of DAR coating to modulate the efficiency of laser fuse blows
US6555458B1 (en) * 2002-01-14 2003-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Fabricating an electrical metal fuse
US6607945B2 (en) * 2001-05-24 2003-08-19 Advanced Micro Devices, Inc. Laser-assisted silicide fuse programming
US20040012071A1 (en) * 2002-07-22 2004-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, and method for manufacturing semiconductor device
US6753210B2 (en) * 2002-09-17 2004-06-22 Taiwan Semiconductor Manufacturing Company Metal fuse for semiconductor devices
US6774456B2 (en) * 1999-06-10 2004-08-10 Infineon Technologies Ag Configuration of fuses in semiconductor structures with Cu metallization
US20040209404A1 (en) * 1998-10-02 2004-10-21 Zhongze Wang Semiconductor fuses, methods of using and making the same, and semiconductor devices containing the same
US6809398B2 (en) * 2000-12-14 2004-10-26 Actel Corporation Metal-to-metal antifuse structure and fabrication method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US78100A (en) * 1868-05-19 To all whom it mat concern
JPH06232537A (en) * 1993-02-02 1994-08-19 Murata Mfg Co Ltd Short-circuiting method for closed circuit forming electrode
US5345110A (en) * 1993-04-13 1994-09-06 Micron Semiconductor, Inc. Low-power fuse detect and latch circuit
US5831923A (en) * 1996-08-01 1998-11-03 Micron Technology, Inc. Antifuse detect circuit
US5825202A (en) * 1996-09-26 1998-10-20 Xilinx, Inc. Integrated circuit with field programmable and application specific logic areas

Patent Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241496A (en) * 1991-08-19 1993-08-31 Micron Technology, Inc. Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells
US5331196A (en) * 1991-08-19 1994-07-19 Micron Technology, Inc. One-time, voltage-programmable, logic element
US5324681A (en) * 1991-10-04 1994-06-28 Micron Technology, Inc. Method of making a 3-dimensional programmable antifuse for integrated circuits
US5110754A (en) * 1991-10-04 1992-05-05 Micron Technology, Inc. Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM
US5858149A (en) * 1995-11-21 1999-01-12 Anam Semiconductor Inc. Process for bonding semiconductor chip
US6169329B1 (en) * 1996-04-02 2001-01-02 Micron Technology, Inc. Semiconductor devices having interconnections using standardized bonding locations and methods of designing
US6087707A (en) * 1996-04-16 2000-07-11 Micron Technology, Inc. Structure for an antifuse cell
US6088282A (en) * 1996-09-06 2000-07-11 Micron Technology, Inc. System and method for an antifuse bank
US5838625A (en) * 1996-10-29 1998-11-17 Micron Technology, Inc. Anti-fuse programming path
US5973978A (en) * 1996-10-29 1999-10-26 Micron Technology, Inc. Anti-fuse programming path
US6097098A (en) * 1997-02-14 2000-08-01 Micron Technology, Inc. Die interconnections using intermediate connection elements secured to the die face
US6154851A (en) * 1997-08-05 2000-11-28 Micron Technology, Inc. Memory repair
US6320242B1 (en) * 1997-10-22 2001-11-20 Seiko Instruments Inc. Semiconductor device having trimmable fuses and position alignment marker formed of thin film
US5898217A (en) * 1998-01-05 1999-04-27 Motorola, Inc. Semiconductor device including a substrate having clustered interconnects
US6271574B1 (en) * 1998-05-14 2001-08-07 Stmicroelectronics S.A. Integrated circuit fuse with localized fusing point
US6100118A (en) * 1998-06-11 2000-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of metal fuse design for redundancy technology having a guard ring
US6169331B1 (en) * 1998-08-28 2001-01-02 Micron Technology, Inc. Apparatus for electrically coupling bond pads of a microelectronic device
US20040209404A1 (en) * 1998-10-02 2004-10-21 Zhongze Wang Semiconductor fuses, methods of using and making the same, and semiconductor devices containing the same
US6078100A (en) * 1999-01-13 2000-06-20 Micron Technology, Inc. Utilization of die repattern layers for die internal connections
US20020017729A1 (en) * 1999-01-25 2002-02-14 Macpherson John Sacrificial bond pads for laser configured integrated circuits
US6423582B1 (en) * 1999-02-25 2002-07-23 Micron Technology, Inc. Use of DAR coating to modulate the efficiency of laser fuse blows
US6774456B2 (en) * 1999-06-10 2004-08-10 Infineon Technologies Ag Configuration of fuses in semiconductor structures with Cu metallization
US6094388A (en) * 1999-07-01 2000-07-25 Micron Technology, Inc. Methods of identifying defects in an array of memory cells and related integrated circuitry
US20020020058A1 (en) * 2000-08-18 2002-02-21 Yuji Saito Method of mounting a BGA
US6809398B2 (en) * 2000-12-14 2004-10-26 Actel Corporation Metal-to-metal antifuse structure and fabrication method
US6607945B2 (en) * 2001-05-24 2003-08-19 Advanced Micro Devices, Inc. Laser-assisted silicide fuse programming
US6555458B1 (en) * 2002-01-14 2003-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Fabricating an electrical metal fuse
US20040012071A1 (en) * 2002-07-22 2004-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, and method for manufacturing semiconductor device
US6753210B2 (en) * 2002-09-17 2004-06-22 Taiwan Semiconductor Manufacturing Company Metal fuse for semiconductor devices

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267137A1 (en) * 2005-05-24 2006-11-30 International Business Machines Corporation Method and structure to prevent circuit network charging during fabrication of integrated circuits
US7232711B2 (en) * 2005-05-24 2007-06-19 International Business Machines Corporation Method and structure to prevent circuit network charging during fabrication of integrated circuits
US20070166848A1 (en) * 2005-05-24 2007-07-19 Gambino Jeffrey P Method and structure to prevent circuit network charging during fabrication of integrated circuits
US8120141B2 (en) 2005-05-24 2012-02-21 International Business Machines Corporation Method and structure to prevent circuit network charging during fabrication of integrated circuits
US20070267755A1 (en) * 2006-05-16 2007-11-22 Vo Nhat D Integrated circuit having pads and input/output (i/o) cells
US20070267748A1 (en) * 2006-05-16 2007-11-22 Tran Tu-Anh N Integrated circuit having pads and input/output (i/o) cells
US7808117B2 (en) * 2006-05-16 2010-10-05 Freescale Semiconductor, Inc. Integrated circuit having pads and input/output (I/O) cells
US20090097332A1 (en) * 2007-10-10 2009-04-16 Samsung Electronics Co., Ltd. Semiconductor memory device
CN109243991A (en) * 2017-07-10 2019-01-18 中芯国际集成电路制造(上海)有限公司 A kind of the test structure and test method, electronic device of electrochemical metal reaction
CN109243991B (en) * 2017-07-10 2020-12-15 中芯国际集成电路制造(上海)有限公司 Test structure and test method for metal electrochemical reaction and electronic device
US11107549B2 (en) 2019-12-16 2021-08-31 Microsoft Technology Licensing, Llc At-risk memory location identification and management

Also Published As

Publication number Publication date
US6991970B2 (en) 2006-01-31
US20030045026A1 (en) 2003-03-06

Similar Documents

Publication Publication Date Title
US20060121650A1 (en) Method and apparatus for circuit completion through the use of ball bonds or other connections during the formation of a semiconductor device
US5294776A (en) Method of burning in a semiconductor device
US6246615B1 (en) Redundancy mapping in a multichip semiconductor package
US5973978A (en) Anti-fuse programming path
US6946327B2 (en) Semiconductor device and manufacturing method of that
KR100817343B1 (en) Semiconductor integrated circuit device
JP2793427B2 (en) Semiconductor device
US6858472B2 (en) Method for implementing selected functionality on an integrated circuit device
US20040184344A1 (en) Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device
WO2002050898A1 (en) Semiconductor integrated circuit device
JPH0254500A (en) Semiconductor memory cell and semiconductor memory device
US20080073789A1 (en) Method Of Identifying And/Or Programming An Integrated Circuit
US7450450B2 (en) Circuitry for a programmable element
US5896040A (en) Configurable probe pads to facilitate parallel testing of integrated circuit devices
JP3294811B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
US7131033B1 (en) Substrate configurable JTAG ID scheme
US5032889A (en) Wiring structure in a wafer-scale integrated circuit
US5349219A (en) Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device
JP2002093199A (en) Integrated circuit with test mode and test device for testing integrated circuit
JP2597828B2 (en) Semiconductor memory device
JP2003270302A (en) Semiconductor device
KR100426989B1 (en) Control signal providing method using package power pins and IC package structure therefore
JPS58202547A (en) Integrated circuit device
JP3557773B2 (en) Semiconductor device
WO1994008356A1 (en) Semiconductor memory device

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION