US20060158361A1 - Digital-to-analog converter - Google Patents
Digital-to-analog converter Download PDFInfo
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- US20060158361A1 US20060158361A1 US10/907,861 US90786105A US2006158361A1 US 20060158361 A1 US20060158361 A1 US 20060158361A1 US 90786105 A US90786105 A US 90786105A US 2006158361 A1 US2006158361 A1 US 2006158361A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M1/682—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals
Definitions
- the present invention relates to a digital-to-analog converter (DAC), more particularly, to a digital-to-analog converter providing the MSB (most significant bit) portion and the LSB (least significant bit) portion with different bias voltages, wherein these two bias voltages would be adjusted according to the match of current source cells.
- DAC digital-to-analog converter
- the digital-to-analog converter has been widely used for data transforming in electronic devices.
- the DAC mainly converts the digital signals to corresponding analog signals, which are used in electronic devices.
- the application of the DACs is very wide.
- the DACs with high resolution and high speed for example, can be applied to mobile phones or base stations of communication systems, cordless communication networks, image processing and display systems, or audio/video systems, and so on.
- a conventional DAC can be, for example, a binary-weighted DAC.
- Such a DAC comprises various current sources and the corresponding switches.
- a conventional binary-weighted DAC is shown in FIG. 1A , a schematic circuit block drawing.
- a 3-bit DAC is taken as an example.
- the 3-bit DAC comprises three current sources 102 , 104 and 106 , and three corresponding switches S 1 , S 2 and S 3 .
- the current source 102 is connected to the switch S 1 via the line 112 , and passes through the output line 118 for output.
- the current source 104 is connected to the switch S 2 via the line 114 , and passes through the output line 118 for output.
- the current source 106 is connected to the switch S 3 via the line 116 , and passes through the output line 118 for output.
- the proportion of currents provided by these three current sources 102 , 104 and 106 is 4:2:1. That is, if one amp of current is provided by the current source 106 , then the current source 104 and 102 would provide two amps and four amps of current, respectively.
- an input-code IN controls the turning-on and turning-off of switches S 1 , S 2 and S 3 and the corresponding output currents would reach the output end OUT via the line 118 .
- the magnitude of the output current is proportional to the value of input code IN.
- a conventional output circuit (not shown), such as an operation amplifier, can be connected in series thereto for converting the output current to a corresponding voltage value, or to an output voltage with low impedance.
- the control circuit for the kind of binary-weighted DAC is simpler.
- the actual output analog signal value is not an ideal value.
- the DNL error would affect the accuracy of output in the DAC. What is more, the DNL error will lead to a serious non-monotonic problem. That is, the output analog value converted from a smaller digital input-code is larger than that from a larger digital input-code, leading to serious error. It can be seen from FIG. 1C , during data transformation process, an unpredictable transient glitch could occur.
- a binary-weighted DAC has more bits, and each received digital bit controls 2 (n ⁇ 1) current source cells, where n ranges from 1 to 10, then, transient glitch would be more serious.
- the DNL error could be caused by characteristic discrepancy among the formed transistors in the array of current source cells.
- the characteristic discrepancy among the formed transistors can be traced back to the inconsistency in semiconductor manufacturing process, such as inconsistent thickness of oxide layer, poor poly-silicon etching, or shift in ion implant, and so on.
- the binary-weighted DAC needs a substantial chip layout area as well.
- thermometer-code a DAC with so-called thermometer-code was introduced to control output of current source.
- FIG. 2 a schematic circuit drawing of an 8-bit DAC with thermometer-codes is shown.
- the DAC 200 comprises two four-to-fifteen bit converters 210 and 220 .
- the four-to-fifteen bit converter 210 is used for converting the four MSBs (most significant bits) in the input-code IN 1 , IN 2 , IN 3 and IN 4 to the corresponding fifteen pieces of data, M 1 , M 2 , M 3 , . . . , M 15 (M 1 ⁇ M 15 ).
- thermometer-code outputs are referred to as thermometer-code outputs.
- thermometer-code outputs When the above-mentioned input-codes are on the increase, these thermometer-codes can avoid the transient glitch when switching all the switches, and consequently, suddenly changing the currents.
- the DAC 200 further comprises fifteen current source cells CSM 1 ⁇ CSM 15 corresponding to MSBs and fifteen current source cells CSL 1 ⁇ CSL 15 corresponding to LSBs.
- the current source cells CSM 1 ⁇ CSM 15 are connected to the outputs M 1 ⁇ M 15 of the four-to-fifteen bit converter 210 via the corresponding switches SWM 1 ⁇ SWM 15 .
- the current source cells CSL 1 ⁇ CSL 15 are connected to the outputs L 1 ⁇ L 15 of the four-to-fifteen bit converter 220 via the corresponding switches SWL 1 ⁇ SWL 15 .
- the outputs M 1 ⁇ M 15 of the four-to-fifteen bit converter 210 are used to control the turning-on and turning-off of the switches SWM 1 ⁇ SWM 15 .
- the outputs L 1 ⁇ L 15 of the four-to-fifteen bit converter 220 are used to control the turning-on and turning-off of switches SWL 1 ⁇ SWL 15 .
- the arrangement of the current source cells CSL 1 ⁇ CSL 15 corresponding to LSBs and the arrangement of the current source cells CSM 1 ⁇ CSM 15 corresponding to MSBs in the above-described configuration can be seen with reference to FIG. 3 .
- the current source cells for LSBs and MSBs comprise 255 MOS transistors in an array.
- the array is formed by 16 columns and 16 rows.
- Each of all transistors is labeled with Tij where i and j represent the column number and the row number, respectively.
- thermometer-codes In the DAC with thermometer-codes to control the outputs from the current sources, the difference of the current source cells controlled by one thermometer-code and another is one cell only. Thus transient glitch can be reduced, but the size required by the current source cells is bigger, and the control circuit is very complicated.
- thermometer-code DAC combining thermometer-code and binary-weighted to control the outputs of the current sources.
- the configuration thereof is schematically shown in FIG. 4 .
- the M-bits, i.e. M MSBs, of N-bits signals are encoded to thermometer codes. That is, the M MSBs are encoded into 2 M ⁇ 1 thermometer-codes by a binary-to-thermometer encoder 410 , then sent to the thermometer-code DAC 420 .
- the DAC should have linearly increasing analog output value along with the increasing value of the input-code. Nevertheless, it is apparent to those skilled in the art that in terms of the output from the DAC, the non-linearity problem still remains. In particular, as binary values are converted to thermometer-codes, the differential non-linearity (DNL) error still remains.
- DNL differential non-linearity
- DAC digital-to-analog converter
- Another object of the present invention is to provide a digital-to-analog converter (DAC) which provides two different bias voltages to the most significant bit (MSB) portion and the least significant bit (LSB) portion.
- the two bias voltages are proportional, and can be synchronously adjusted according to the match among the current source cells.
- the present invention is suitable for a segment-type DAC combining thermometer-code and binary-weighted configuration.
- the segment-type DAC provides two different bias voltages to the thermometer-code portion for the MSBs and the binary-weighted portion for the LSBs. And, the two bias voltages can be adjusted according to the match among the current source cells.
- the present invention is suitable for a segment-type DAC combining thermometer-code and binary-weighted configuration.
- the segment-type DAC provides two different bias voltages to the thermometer-code portion for the MSBs and the binary-weighted portion for the LSBs. And, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- the present invention is suitable for a thermometer-code DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages can be adjusted according to the match among the current source cells.
- the present invention is suitable for a thermometer-code DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- the present invention is suitable for a binary-weighted DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages can be adjusted according to the match among the current source cells.
- the present invention is suitable for a binary-weighted DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- the present invention provides a DAC suitable for a segment-type configuration combining thermometer-code portion and binary-weighted portion.
- a MSB portion of an input-code is thermometer-encoded to generate multiple corresponding thermometer codes.
- a LSB portion of an input-code is binary-weighted to generate a plurality of binary-weighted codes.
- the DAC comprises a plurality of current source cells to provide currents. Wherein, a first portion of the current source cells receives a first bias voltage, and provides a current corresponding to the above-mentioned thermometer-code.
- a second portion of the current source cells receives a second bias voltage, and provides a current corresponding to the above-mentioned binary-weighted code.
- the first bias voltage and the second bias voltage would be adjusted according to match among the current resource cells, and remain a certain proportion.
- the above-described DAC further comprises a bias converter for receiving the first bias voltage, and adjusting the second bias voltage according to the match among the current resource cells.
- the above-described DAC further comprises a bias converter for receiving the second bias voltage, and adjusting the first bias voltage according to the match among the current resource cells.
- the above-described bias converter comprises a first transistor. And a gate thereof is coupled to the first bias voltage, a drain/source thereof is connected to an operation voltage, and another drain/source thereof is connected to a resistor element. Another end of the resistor element is connected to a current mirror circuit.
- the above-described bias converter further comprises a second transistor. A drain/source thereof is connected to said operation voltage, another drain/source thereof is connected to a gate thereof and connected to the current mirror circuit. And the second bias voltage just applies to the gate of the second transistor. According to the received first bias voltage, the second bias voltage is adjusted by the current mirror circuit and the resistor element.
- the above-described current mirror circuit comprises a third transistor. Wherein, a gate thereof is coupled to a drain/source thereof and connected to the resistor element, and another drain/source is grounded.
- the current mirror circuit further comprises a fourth transistor. Wherein, a gate thereof is connected to the gate of the third transistor, a drain/source thereof is connected to another drain/source of the second transistor and to the gate of the second transistor, and another drain/source is grounded.
- the above-described first transistor and second transistor have the same size, and the quantity thereof is equal to that of the current source cells in the first portion. These transistors are used for improving the device mismatch.
- the above-described resistor element is designed for compensating the channel length modulation of the DAC.
- FIG. 1A is a schematic circuit drawing of a conventional binary-weighted DAC.
- FIG. 1B is a schematic coordination diagram showing the relationship between input-codes and differential non-linearity (DNL) errors.
- DNL differential non-linearity
- FIG. 1C is a schematic diagram showing the generation of an unpredictable transient glitch in the data transforming process.
- FIG. 2 is a schematic circuit drawing of a conventional 8-bit DAC with thermometer-codes.
- FIG. 3 is a schematic diagram showing an arrangement of current source cells for LSBs and MSBs.
- FIG. 4 is a schematic block diagram of a segment-type DAC circuit combining thermometer-code and binary-weighted configuration.
- FIG. 5 is a schematic diagram illustrating a first bias voltage provided to the thermometer-code portion of the MSBs and a second bias voltage provided to the binary-weighted portion of the LSBs through a bias converter circuit according to an embodiment of the present invention.
- FIG. 6 is a schematic drawing of a bias generating circuit of the current source cells in a DAC.
- FIG. 7 is a schematic circuit drawing of a full current source cell in a DAC.
- FIG. 8 is a schematic diagram showing a configuration of current source cells in a DAC.
- FIG. 9 is a schematic drawing of a segment-type DAC circuit combining thermometer-code and binary-weighted in an embodiment of the present invention.
- FIG. 10 is a schematic drawing of a thermometer-code DAC in an embodiment of the present invention.
- FIG. 11 is a schematic drawing of a binary-weighted DAC in an embodiment of the present invention.
- the present invention provides a segment-type digital-to-analog converter (DAC) which provides two different bias voltages to the thermometer-code portion of the most significant bits (MSBs) and the binary-weighted portion of the least significant bits (LSBs). These two bias voltages can be adjusted according to the match among the current source cells. In addition, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- DAC segment-type digital-to-analog converter
- a second bias voltage is provided to the binary-weighted portion of the LSBs.
- the second bias voltage is obtained by converting the first bias voltage using a bias converter.
- FIG. 5 The configuration thereof is shown in FIG. 5 .
- the second bias voltage BIAS 2 is provided to the binary-weighted portion of the LSBs 510 and the first bias voltage BIAS 1 is provided to the thermometer-code portion of the MSBs 520 .
- the second bias voltage BIAS 2 is obtained by converting the first bias voltage BIAS 1 using a bias converter 530 .
- the first bias voltage can be obtained by converting the second bias voltage as well.
- FIG. 6 a schematic drawing of a bias generating circuit of current source cells in a DAC is shown.
- the bias voltage thereof is produced by a bias generating circuit 600 .
- the bias generating circuit 600 comprises an operation amplifier 610 , a transistor 620 and a resistor 630 .
- the produced current thereof is Vref/r, and the unit current thereof is Vref/(r*X), where r is resistance of the resistor 630 , and X is magnification multiple of the transistor 620 .
- thermometer-code portion of MSBs and the current source cells in the binary-weighted portion of LSBs are the same size and the same type, for example, P-type metal oxide semiconductor (PMOS), then, a controlled PMOS quantity is used to give weighting result, consequently control the output current.
- PMOS P-type metal oxide semiconductor
- a 10-bit DAC is a binary-weighted DAC
- the weight for each bit is 512, 256, 128, 64, 32, 16, 8, 4, 2 and 1, respectively.
- a 10-bit DAC is a DAC combining thermometer-code and binary-weighted
- the thermometer-code portion is 64*15
- the binary-weighted portion is 32, 16, 8, 4, 2 and 1.
- FIG. 7 A schematic circuit drawing of a full current source cell in a DAC is shown in FIG. 7 .
- a switch MOS transistor 710 is included. The gate thereof is connected to the bias voltage BIAS, a drain/source thereof is connected to the operation voltage VDD, another drain/source thereof is connected to the transistors MOSA and MOSB, and the transistors MOSA and MOSB are controlled by the control signal Q and QB, respectively.
- Another end of MOS transistor MOSA is grounded via a resistor element Rout.
- Another end of MOS transistor MOSB is directly grounded. When this transistor is selected to produce current, the control signal Q takes a logic-low level, and the control signal QB takes a logic-high level.
- thermometer-codes thereof and the binary weights thereof are 64*15 and (32, 16, 8, 4, 2, 1), respectively.
- the configuration of the current source cells is shown in FIG. 3 . If the total current produced by all current source cells in the LSB portion is not 63, the linearity of DAC would be ruined; that is, the above-described differential non-linearity (DNL) error occurs, or even a serious non-monotonic problem. With the non-monotonic problem, some output analog values corresponding to smaller digital input-codes IN are larger than those corresponding to larger digital input-codes, leading to serious error.
- DNL differential non-linearity
- the DNL error and/or the non-monotonic problem could be a matter of device mismatch; that is, the characteristic discrepancy among the formed transistors in the array of current source cells for LSB and MSB. And, the characteristic discrepancy among the formed transistors generally can be traced back to the inconsistency in semiconductor manufacturing process, such as inconsistent thickness of oxide layer, poor poly-silicon etching, or shift in ion implant, and so on. To avoid the discrepancy among the components, appropriate configurations must be applied.
- the U.S. Pat. No. 5,568,145 provides a solution where the current source cells of LSB are arranged between two portions of the current source cells of MSB. But the discrepancy still remains.
- FIG. 8 is a schematic diagram showing a configuration of current source cells.
- the dotted-line portion shows the arrangement of the current resource cells of LSB
- the remaining portion shows the arrangement of the current resource cells of MSB.
- the left arrow 810 indicates the path of output current llsb from the current source cell in the LSB portion
- the right arrow 820 indicates the path of output current lmsb from the current source cell in the MSB portion.
- the serial resistor for the output current from the current source cells in the MSB portion is larger due to a longer distance.
- the outside lines i.e., the bottom portion indicated by the arrow 820
- the appropriate compensation amount is very hard to estimate and to adjust. Moreover, this may result in a bigger layout area and becomes a disadvantage.
- Another potential problem is the channel length modulation. A various output level (voltage) leads to a various operation voltage VDD, and a various, inconsistent unit current.
- FIG. 9 a schematic drawing of a segment-type DAC 900 combining thermometer-code and binary-weighted configuration is provided according to an embodiment of the present invention.
- the DAC 900 provides two different bias voltages to the thermometer-code portion of the most significant bits (MSBs) and the binary-weighted portion of the least significant bits (LSBs). These two bias voltages can be adjusted according to the match among the current source cells. In addition, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- the DAC 900 is, for example but not limited to, a 10-bit DAC. That is, the present invention is suitable for all multi-bit segment-type DACs.
- the bias generating circuit 910 of the DAC 900 comprises an operation amplifier OP, a transistor A 5 and a resistor R 1 .
- One input end of the operation amplifier OP is connected to a reference voltage Vref. Another input end thereof is connected to the connecting point N 1 of the transistor A 5 and the resistor R 1 .
- the output from the operation amplifier OP, or a generated bias voltage is BIAS 1 , and is connected to the gate of the transistor A 5 .
- One drain/source of the transistor A 5 is connected to an operation voltage VDD, and another drain/source thereof is grounded via the resistor R 1 .
- thermometer-code portion For each segment in the 10-bit DAC 900 , the thermometer-code portion is 64*15, and the binary-weighted portion is 32, 16, 8, 4, 2 and 1.
- the arrangement of the current source cells in the DAC 900 is formed by the thermometer-code portion of MSBs and the binary-weighted portion of LSBs.
- the generated current thereof is Vref/r
- the unit current thereof is Vref/(r*X)
- r resistance of the resistor R 1
- X is the magnification multiple of the transistor A 5 .
- each segment comprises a thermometer-code portion and a binary-weighted portion.
- a bias converter 920 is disposed between the above-mentioned two portions. The bias converter 920 is used to adjust another bias voltage BIAS 2 for generating the binary-weighted portion according to both the bias voltage BIAS 1 from the bias generating circuit 910 and the match among the current source cells.
- these two bias voltages BIAS 1 and BIAS 2 are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells. Any circuit capable of adjusting these two bias voltages is applicable to the present invention. For a clear description, only one embodiment is described as follows, but the present invention is not limited thereto. The schematic circuit drawing from the embodiment is shown in FIG. 9 .
- the bias converter 920 comprises a transistor A 1 , a transistor A 2 , transistors A 3 and A 4 , and a resistor R 2 .
- the gate of the transistors A 1 is coupled to the bias voltage BIAS 1 generated by the bias generating circuit 910 , a drain/source thereof is connected to an operation voltage VDD, and another drain/source thereof is connected to the resistor element R 2 .
- Another end of the resistor element R 2 is connected to a current mirror circuit formed by the transistors A 3 and A 4 .
- a drain/source of the transistor A 2 is connected to an operation voltage VDD, and another drain/source thereof is connected to the gate thereof and connected to the current mirror circuit formed by the transistors A 3 and A 4 .
- the resistor element is not required depending on the layout of the transistor A 1 , A 2 , A 3 and A 4 .
- both the transistor A 1 and A 2 have the same size and the same quantity of 64 pieces, then the total sum in the binary-weighted portion is 63 . And, both the transistor A 3 and A 4 in the current mirror circuit have the same quantity as well.
- the resistor element R 2 is used for compensating the channel length modulation. In an embodiment, this resistance should be 32 times of the external resistor. Certainly, the compensation value can be adjusted according to the transistor A 3 and the resistor R 2 .
- thermometer-code segment Since the amount of the components in the thermometer-code segment is close to the amount of the transistor A 1 , and the both layouts are similar, the device mismatch is relatively reduced. But, in terms of the quantity and the arrangement of components, there is a big difference between the thermometer-code segment and the binary-weighted portion, leading to serious device mismatch.
- the bias converter 920 by means of an appropriate disposition of the bias converter 920 , the current match in both the thermometer-code segment portion and the binary-weighted portion can be improved.
- a current driving mode is used, not a conventional voltage compensation mode, so the improvement is more obvious.
- the transistors Al in the bias converter 920 can be arranged in parallel to the components in the thermometer-code segment to increase the matching degree.
- the transistor A 2 in the bias converter 920 can be arranged with the components in the binary-weighted portion to be close to the average.
- each segment comprises a thermometer-code portion and a binary-weighted portion.
- a bias converter 920 is disposed between the above-mentioned two portions.
- the bias converter 920 can generate the bias voltage BIAS 1 of the thermometer-code portion according to another bias voltage BIAS 2 of the binary-weighted portion and the match among the current source cells.
- These two bias voltages BIAS 1 and BIAS 2 are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- thermometer-code DAC design of the current driving mode to improve the match state is applicable in a thermometer-code DAC.
- FIG. 10 a schematic drawing of a thermometer-code DAC 1000 is shown.
- a bias converter 1020 is disposed between two thermometer-code portions I and II.
- the thermometer-code portion I is coupled to the bias voltage BIAS 1 generated by the bias generating circuit 1010 .
- the bias converter 1020 would adjust another bias voltage BIAS 2 of the thermometer-code portion II according to the bias voltage BIAS 1 generated by the bias generating circuit 1010 and the match among the current source cells.
- These two bias voltages BIAS 1 and BIAS 2 are proportional, and can be synchronously adjusted according to the match among the current source cells.
- thermometer-code DAC such design of the current driving mode to improve the match state is applicable in a thermometer-code DAC.
- FIG. 11 a schematic drawing of a binary-weighted DAC 1100 is shown.
- a bias converter 1120 is disposed between two binary-weighted portions I and II.
- the binary-weighted portion I is coupled to the bias voltage BIAS 1 generated by the bias generating circuit 1110 .
- the bias converter 1120 would adjust another bias voltage BIAS 2 of the binary-weighted portion II according to the bias voltage BIAS 1 generated by the bias generating circuit 1110 and the match among the current source cells.
- These two bias voltages BIAS 1 and BIAS 2 are proportional, and can be synchronously adjusted according to the match among the current source cells.
Abstract
Description
- This application claims the priority benefit of Taiwan application serial no. 94101266, filed on Jan. 17, 2005. All disclosure of the Taiwan application is incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to a digital-to-analog converter (DAC), more particularly, to a digital-to-analog converter providing the MSB (most significant bit) portion and the LSB (least significant bit) portion with different bias voltages, wherein these two bias voltages would be adjusted according to the match of current source cells.
- 2. Description of the Related Art
- The digital-to-analog converter (DAC) has been widely used for data transforming in electronic devices. The DAC mainly converts the digital signals to corresponding analog signals, which are used in electronic devices. The application of the DACs is very wide. The DACs with high resolution and high speed, for example, can be applied to mobile phones or base stations of communication systems, cordless communication networks, image processing and display systems, or audio/video systems, and so on.
- A conventional DAC can be, for example, a binary-weighted DAC. Such a DAC comprises various current sources and the corresponding switches. A conventional binary-weighted DAC is shown in
FIG. 1A , a schematic circuit block drawing. Wherein, a 3-bit DAC is taken as an example. The 3-bit DAC comprises threecurrent sources current source 102 is connected to the switch S1 via theline 112, and passes through theoutput line 118 for output. Thecurrent source 104 is connected to the switch S2 via theline 114, and passes through theoutput line 118 for output. Thecurrent source 106 is connected to the switch S3 via theline 116, and passes through theoutput line 118 for output. The proportion of currents provided by these threecurrent sources current source 106, then thecurrent source - During the operation, an input-code IN controls the turning-on and turning-off of switches S1, S2 and S3 and the corresponding output currents would reach the output end OUT via the
line 118. According to such control, the magnitude of the output current is proportional to the value of input code IN. And a conventional output circuit (not shown), such as an operation amplifier, can be connected in series thereto for converting the output current to a corresponding voltage value, or to an output voltage with low impedance. The control circuit for the kind of binary-weighted DAC is simpler. - However, in the above operation, there would be so-called transient glitch which may affect the accuracy of digital-analog conversion. When an input-code IN is changed from 011 (in binary system) to 100, all three switches S1, S2 and S3 will change their status, although only the “1” bit-value is changed. Therefore, the binary-weighted DAC is not suitable for converting the digital signal with large bits, and it doesn't guarantee a non-monotonic function. Referring to
FIG. 1B , a schematic coordination diagram of the relationship between input-codes and so-called corresponding differential non-linearity (DNL) errors is shown. For each input-code, major DNL errors would occur from time to time. That is, at two contiguous points of time to convert digital input-codes IN to analog signals, the actual output analog signal value is not an ideal value. The DNL error would affect the accuracy of output in the DAC. What is more, the DNL error will lead to a serious non-monotonic problem. That is, the output analog value converted from a smaller digital input-code is larger than that from a larger digital input-code, leading to serious error. It can be seen fromFIG. 1C , during data transformation process, an unpredictable transient glitch could occur. - In other words, if a binary-weighted DAC has more bits, and each received
digital bit controls 2(n−1) current source cells, where n ranges from 1 to 10, then, transient glitch would be more serious. The DNL error could be caused by characteristic discrepancy among the formed transistors in the array of current source cells. And, the characteristic discrepancy among the formed transistors can be traced back to the inconsistency in semiconductor manufacturing process, such as inconsistent thickness of oxide layer, poor poly-silicon etching, or shift in ion implant, and so on. In addition, the binary-weighted DAC needs a substantial chip layout area as well. - To improve the transient glitch, a DAC with so-called thermometer-code was introduced to control output of current source. Referring to
FIG. 2 , a schematic circuit drawing of an 8-bit DAC with thermometer-codes is shown. Wherein, the DAC 200 comprises two four-to-fifteenbit converters bit converter 210 is used for converting the four MSBs (most significant bits) in the input-code IN1, IN2, IN3 and IN4 to the corresponding fifteen pieces of data, M1, M2, M3, . . . , M15 (M1˜M15). And, the four-to-fifteenbit converter 220 is used for converting the four LSBs (least significant bits) in the input-code IN5, IN6, IN7 and IN8 to the corresponding fifteen pieces of data, L1, L2, L3, . . . , L15 (L1˜L15). These converted data are referred to as thermometer-code outputs. When the above-mentioned input-codes are on the increase, these thermometer-codes can avoid the transient glitch when switching all the switches, and consequently, suddenly changing the currents. - The
DAC 200 further comprises fifteen current source cells CSM1˜CSM15 corresponding to MSBs and fifteen current source cells CSL1˜CSL15 corresponding to LSBs. The current source cells CSM1˜CSM15 are connected to the outputs M1˜M15 of the four-to-fifteenbit converter 210 via the corresponding switches SWM1˜SWM15. And, the current source cells CSL1˜CSL15 are connected to the outputs L1˜L15 of the four-to-fifteenbit converter 220 via the corresponding switches SWL1˜SWL15. The outputs M1˜M15 of the four-to-fifteenbit converter 210 are used to control the turning-on and turning-off of the switches SWM1˜SWM15. And, the outputs L1˜L15 of the four-to-fifteenbit converter 220 are used to control the turning-on and turning-off of switches SWL1˜SWL15. - The arrangement of the current source cells CSL1˜CSL15 corresponding to LSBs and the arrangement of the current source cells CSM1˜CSM15 corresponding to MSBs in the above-described configuration can be seen with reference to
FIG. 3 . The current source cells for LSBs and MSBs comprise 255 MOS transistors in an array. The array is formed by 16 columns and 16 rows. Each of all transistors is labeled with Tij where i and j represent the column number and the row number, respectively. - In the DAC with thermometer-codes to control the outputs from the current sources, the difference of the current source cells controlled by one thermometer-code and another is one cell only. Thus transient glitch can be reduced, but the size required by the current source cells is bigger, and the control circuit is very complicated.
- To reduce the size of required current source cells and the complexity of the control circuit, those skilled in the art presented a segment-type DAC combining thermometer-code and binary-weighted to control the outputs of the current sources. The configuration thereof is schematically shown in
FIG. 4 . Assuming the segment-type DAC is capable of converting N-bits digital signal, then the M-bits, i.e. M MSBs, of N-bits signals are encoded to thermometer codes. That is, the M MSBs are encoded into 2M−1 thermometer-codes by a binary-to-thermometer encoder 410, then sent to the thermometer-code DAC 420. The rest of (N-M) LSBs pass through adelay device 430, and are directly sent to a binary-weightedDAC 440. Considering the die size and overall conversion, the segment-type DAC with a configuration combining thermometer-code and binary-weighted seems to be the best option available. But this configuration still has a match problem among the current source cells. - In the most ideal situation, the DAC should have linearly increasing analog output value along with the increasing value of the input-code. Nevertheless, it is apparent to those skilled in the art that in terms of the output from the DAC, the non-linearity problem still remains. In particular, as binary values are converted to thermometer-codes, the differential non-linearity (DNL) error still remains.
- It is an object of the present invention to provide a digital-to-analog converter (DAC) which provides two different bias voltages to the most significant bit (MSB) portion and the least significant bit (LSB) portion. These two bias voltages can be adjusted according to the match among the current source cells.
- Another object of the present invention is to provide a digital-to-analog converter (DAC) which provides two different bias voltages to the most significant bit (MSB) portion and the least significant bit (LSB) portion. The two bias voltages are proportional, and can be synchronously adjusted according to the match among the current source cells.
- In an embodiment, the present invention is suitable for a segment-type DAC combining thermometer-code and binary-weighted configuration. The segment-type DAC provides two different bias voltages to the thermometer-code portion for the MSBs and the binary-weighted portion for the LSBs. And, the two bias voltages can be adjusted according to the match among the current source cells.
- In an embodiment, the present invention is suitable for a segment-type DAC combining thermometer-code and binary-weighted configuration. The segment-type DAC provides two different bias voltages to the thermometer-code portion for the MSBs and the binary-weighted portion for the LSBs. And, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- In an embodiment, the present invention is suitable for a thermometer-code DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages can be adjusted according to the match among the current source cells.
- In an embodiment, the present invention is suitable for a thermometer-code DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- In an embodiment, the present invention is suitable for a binary-weighted DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages can be adjusted according to the match among the current source cells.
- In an embodiment, the present invention is suitable for a binary-weighted DAC which provides two different bias voltages to the MSB portion and the LSB portion. And, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- To achieve the above-described objects, the present invention provides a DAC suitable for a segment-type configuration combining thermometer-code portion and binary-weighted portion. Therewith, a MSB portion of an input-code is thermometer-encoded to generate multiple corresponding thermometer codes. And therewith, a LSB portion of an input-code is binary-weighted to generate a plurality of binary-weighted codes. The DAC comprises a plurality of current source cells to provide currents. Wherein, a first portion of the current source cells receives a first bias voltage, and provides a current corresponding to the above-mentioned thermometer-code. A second portion of the current source cells receives a second bias voltage, and provides a current corresponding to the above-mentioned binary-weighted code. The first bias voltage and the second bias voltage would be adjusted according to match among the current resource cells, and remain a certain proportion.
- In an embodiment, the above-described DAC further comprises a bias converter for receiving the first bias voltage, and adjusting the second bias voltage according to the match among the current resource cells.
- In another embodiment, the above-described DAC further comprises a bias converter for receiving the second bias voltage, and adjusting the first bias voltage according to the match among the current resource cells.
- In an embodiment, the above-described bias converter comprises a first transistor. And a gate thereof is coupled to the first bias voltage, a drain/source thereof is connected to an operation voltage, and another drain/source thereof is connected to a resistor element. Another end of the resistor element is connected to a current mirror circuit. The above-described bias converter further comprises a second transistor. A drain/source thereof is connected to said operation voltage, another drain/source thereof is connected to a gate thereof and connected to the current mirror circuit. And the second bias voltage just applies to the gate of the second transistor. According to the received first bias voltage, the second bias voltage is adjusted by the current mirror circuit and the resistor element.
- In an embodiment, the above-described current mirror circuit comprises a third transistor. Wherein, a gate thereof is coupled to a drain/source thereof and connected to the resistor element, and another drain/source is grounded. The current mirror circuit further comprises a fourth transistor. Wherein, a gate thereof is connected to the gate of the third transistor, a drain/source thereof is connected to another drain/source of the second transistor and to the gate of the second transistor, and another drain/source is grounded.
- In an embodiment, the above-described first transistor and second transistor have the same size, and the quantity thereof is equal to that of the current source cells in the first portion. These transistors are used for improving the device mismatch.
- In an embodiment, the above-described resistor element is designed for compensating the channel length modulation of the DAC.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve for explaining the principles of the invention.
-
FIG. 1A is a schematic circuit drawing of a conventional binary-weighted DAC. -
FIG. 1B is a schematic coordination diagram showing the relationship between input-codes and differential non-linearity (DNL) errors. -
FIG. 1C is a schematic diagram showing the generation of an unpredictable transient glitch in the data transforming process. -
FIG. 2 is a schematic circuit drawing of a conventional 8-bit DAC with thermometer-codes. -
FIG. 3 is a schematic diagram showing an arrangement of current source cells for LSBs and MSBs. -
FIG. 4 is a schematic block diagram of a segment-type DAC circuit combining thermometer-code and binary-weighted configuration. -
FIG. 5 is a schematic diagram illustrating a first bias voltage provided to the thermometer-code portion of the MSBs and a second bias voltage provided to the binary-weighted portion of the LSBs through a bias converter circuit according to an embodiment of the present invention. -
FIG. 6 is a schematic drawing of a bias generating circuit of the current source cells in a DAC. -
FIG. 7 is a schematic circuit drawing of a full current source cell in a DAC. -
FIG. 8 is a schematic diagram showing a configuration of current source cells in a DAC. -
FIG. 9 is a schematic drawing of a segment-type DAC circuit combining thermometer-code and binary-weighted in an embodiment of the present invention. -
FIG. 10 is a schematic drawing of a thermometer-code DAC in an embodiment of the present invention. -
FIG. 11 is a schematic drawing of a binary-weighted DAC in an embodiment of the present invention. - The present invention provides a segment-type digital-to-analog converter (DAC) which provides two different bias voltages to the thermometer-code portion of the most significant bits (MSBs) and the binary-weighted portion of the least significant bits (LSBs). These two bias voltages can be adjusted according to the match among the current source cells. In addition, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells.
- If a first bias voltage is, for example, provided to the thermometer-code portion of the MSBs, then a second bias voltage is provided to the binary-weighted portion of the LSBs. The second bias voltage is obtained by converting the first bias voltage using a bias converter. The configuration thereof is shown in
FIG. 5 . Referring toFIG. 5 , the second bias voltage BIAS2 is provided to the binary-weighted portion of theLSBs 510 and the first bias voltage BIAS1 is provided to the thermometer-code portion of theMSBs 520. And, the second bias voltage BIAS2 is obtained by converting the first bias voltage BIAS1 using abias converter 530. - On the other hand, in an alternative embodiment, the first bias voltage can be obtained by converting the second bias voltage as well.
- Referring to
FIG. 6 , a schematic drawing of a bias generating circuit of current source cells in a DAC is shown. The bias voltage thereof is produced by abias generating circuit 600. Thebias generating circuit 600 comprises anoperation amplifier 610, atransistor 620 and aresistor 630. The produced current thereof is Vref/r, and the unit current thereof is Vref/(r*X), where r is resistance of theresistor 630, and X is magnification multiple of thetransistor 620. If only the alltransistors 640 of the current source cells in the thermometer-code portion of MSBs and the current source cells in the binary-weighted portion of LSBs are the same size and the same type, for example, P-type metal oxide semiconductor (PMOS), then, a controlled PMOS quantity is used to give weighting result, consequently control the output current. For example, if a 10-bit DAC is a binary-weighted DAC, the weight for each bit is 512, 256, 128, 64, 32, 16, 8, 4, 2 and 1, respectively. If a 10-bit DAC is a DAC combining thermometer-code and binary-weighted, the thermometer-code portion is 64*15, and the binary-weighted portion is 32, 16, 8, 4, 2 and 1. - A schematic circuit drawing of a full current source cell in a DAC is shown in
FIG. 7 . Wherein, aswitch MOS transistor 710 is included. The gate thereof is connected to the bias voltage BIAS, a drain/source thereof is connected to the operation voltage VDD, another drain/source thereof is connected to the transistors MOSA and MOSB, and the transistors MOSA and MOSB are controlled by the control signal Q and QB, respectively. Another end of MOS transistor MOSA is grounded via a resistor element Rout. Another end of MOS transistor MOSB is directly grounded. When this transistor is selected to produce current, the control signal Q takes a logic-low level, and the control signal QB takes a logic-high level. When the quantity of the current source varies, the sizes of theswitch MOS transistor 710, the transistor MOSA and MOSB will accordingly be changed. For example, for a 10-bit DAC, the thermometer-codes thereof and the binary weights thereof are 64*15 and (32, 16, 8, 4, 2, 1), respectively. - The configuration of the current source cells is shown in
FIG. 3 . If the total current produced by all current source cells in the LSB portion is not 63, the linearity of DAC would be ruined; that is, the above-described differential non-linearity (DNL) error occurs, or even a serious non-monotonic problem. With the non-monotonic problem, some output analog values corresponding to smaller digital input-codes IN are larger than those corresponding to larger digital input-codes, leading to serious error. - The DNL error and/or the non-monotonic problem could be a matter of device mismatch; that is, the characteristic discrepancy among the formed transistors in the array of current source cells for LSB and MSB. And, the characteristic discrepancy among the formed transistors generally can be traced back to the inconsistency in semiconductor manufacturing process, such as inconsistent thickness of oxide layer, poor poly-silicon etching, or shift in ion implant, and so on. To avoid the discrepancy among the components, appropriate configurations must be applied. The U.S. Pat. No. 5,568,145, for example, provides a solution where the current source cells of LSB are arranged between two portions of the current source cells of MSB. But the discrepancy still remains. The other cause for the problem is layout limitation. To reduce the chip size, the adopted layout is very limited, and the lines between components are also limited, and thus the discrepancy problem.
FIG. 8 is a schematic diagram showing a configuration of current source cells. Wherein, the dotted-line portion shows the arrangement of the current resource cells of LSB, and the remaining portion shows the arrangement of the current resource cells of MSB. Theleft arrow 810 indicates the path of output current llsb from the current source cell in the LSB portion, and theright arrow 820 indicates the path of output current lmsb from the current source cell in the MSB portion. Apparently, the serial resistor for the output current from the current source cells in the MSB portion is larger due to a longer distance. In general, the outside lines, i.e., the bottom portion indicated by thearrow 820, can be adjusted, or compensated. However, the appropriate compensation amount is very hard to estimate and to adjust. Moreover, this may result in a bigger layout area and becomes a disadvantage. Another potential problem is the channel length modulation. A various output level (voltage) leads to a various operation voltage VDD, and a various, inconsistent unit current. - Referring to
FIG. 9 , a schematic drawing of a segment-type DAC 900 combining thermometer-code and binary-weighted configuration is provided according to an embodiment of the present invention. TheDAC 900 provides two different bias voltages to the thermometer-code portion of the most significant bits (MSBs) and the binary-weighted portion of the least significant bits (LSBs). These two bias voltages can be adjusted according to the match among the current source cells. In addition, the two bias voltages are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells. TheDAC 900 is, for example but not limited to, a 10-bit DAC. That is, the present invention is suitable for all multi-bit segment-type DACs. - First of all, the
bias generating circuit 910 of theDAC 900 comprises an operation amplifier OP, a transistor A5 and a resistor R1. One input end of the operation amplifier OP is connected to a reference voltage Vref. Another input end thereof is connected to the connecting point N1 of the transistor A5 and the resistor R1. The output from the operation amplifier OP, or a generated bias voltage is BIAS1, and is connected to the gate of the transistor A5. One drain/source of the transistor A5 is connected to an operation voltage VDD, and another drain/source thereof is grounded via the resistor R1. For each segment in the 10-bit DAC 900, the thermometer-code portion is 64*15, and the binary-weighted portion is 32, 16, 8, 4, 2 and 1. Thus, referring toFIG. 9 , the arrangement of the current source cells in theDAC 900 is formed by the thermometer-code portion of MSBs and the binary-weighted portion of LSBs. - Assuming the total output current from the
DAC 900 is 1 mini ampere (mA), and the required unit current is 1 μA. In thebias generating circuit 910 of the current source cells, the generated current thereof is Vref/r, and the unit current thereof is Vref/(r*X), where r is resistance of the resistor R1, and X is the magnification multiple of the transistor A5. Thus, when the reference voltage Vref is 1.2 volt (V), by using 10 as the magnification multiple in the transistor A5, and 120 kilo ohm (KΩ) as the resistance of R1, then the unit current is Vref/(r*X)=1.2/(120*10)=1 micro ampere (μA). - In the segment-
type DAC 900 combining thermometer-code and binary-weighted in an embodiment of the present invention, each segment comprises a thermometer-code portion and a binary-weighted portion. Abias converter 920 is disposed between the above-mentioned two portions. Thebias converter 920 is used to adjust another bias voltage BIAS2 for generating the binary-weighted portion according to both the bias voltage BIAS1 from thebias generating circuit 910 and the match among the current source cells. In addition, these two bias voltages BIAS1 and BIAS2 are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells. Any circuit capable of adjusting these two bias voltages is applicable to the present invention. For a clear description, only one embodiment is described as follows, but the present invention is not limited thereto. The schematic circuit drawing from the embodiment is shown inFIG. 9 . - The
bias converter 920 comprises a transistor A1, a transistor A2, transistors A3 and A4, and a resistor R2. The gate of the transistors A1 is coupled to the bias voltage BIAS1 generated by thebias generating circuit 910, a drain/source thereof is connected to an operation voltage VDD, and another drain/source thereof is connected to the resistor element R2. Another end of the resistor element R2 is connected to a current mirror circuit formed by the transistors A3 and A4. A drain/source of the transistor A2 is connected to an operation voltage VDD, and another drain/source thereof is connected to the gate thereof and connected to the current mirror circuit formed by the transistors A3 and A4. In an alternative embodiment, the resistor element is not required depending on the layout of the transistor A1, A2, A3 and A4. - If both the transistor A1 and A2 have the same size and the same quantity of 64 pieces, then the total sum in the binary-weighted portion is 63. And, both the transistor A3 and A4 in the current mirror circuit have the same quantity as well. The resistor element R2 is used for compensating the channel length modulation. In an embodiment, this resistance should be 32 times of the external resistor. Certainly, the compensation value can be adjusted according to the transistor A3 and the resistor R2.
- Since the amount of the components in the thermometer-code segment is close to the amount of the transistor A1, and the both layouts are similar, the device mismatch is relatively reduced. But, in terms of the quantity and the arrangement of components, there is a big difference between the thermometer-code segment and the binary-weighted portion, leading to serious device mismatch. Referring to
FIG. 9 , by means of an appropriate disposition of thebias converter 920, the current match in both the thermometer-code segment portion and the binary-weighted portion can be improved. In particular, in the embodiment of the present invention, a current driving mode is used, not a conventional voltage compensation mode, so the improvement is more obvious. The transistors Al in thebias converter 920 can be arranged in parallel to the components in the thermometer-code segment to increase the matching degree. In comparison, the transistor A2 in thebias converter 920 can be arranged with the components in the binary-weighted portion to be close to the average. - In the segment-
type DAC 900 combining thermometer-code and binary-weighted of another embodiment of the present invention, each segment comprises a thermometer-code portion and a binary-weighted portion. Abias converter 920 is disposed between the above-mentioned two portions. Thebias converter 920 can generate the bias voltage BIAS1 of the thermometer-code portion according to another bias voltage BIAS2 of the binary-weighted portion and the match among the current source cells. These two bias voltages BIAS1 and BIAS2 are proportional, and the two bias voltages can be synchronously adjusted according to the match among the current source cells. - In an alternative embodiment of the present invention, such design of the current driving mode to improve the match state is applicable in a thermometer-code DAC. As shown in
FIG. 10 , a schematic drawing of a thermometer-code DAC 1000 is shown. Wherein, abias converter 1020 is disposed between two thermometer-code portions I and II. The thermometer-code portion I is coupled to thebias voltage BIAS 1 generated by thebias generating circuit 1010. Thebias converter 1020 would adjust anotherbias voltage BIAS 2 of the thermometer-code portion II according to thebias voltage BIAS 1 generated by thebias generating circuit 1010 and the match among the current source cells. These two bias voltages BIAS1 and BIAS2 are proportional, and can be synchronously adjusted according to the match among the current source cells. - In one alternative embodiment of the present invention, such design of the current driving mode to improve the match state is applicable in a thermometer-code DAC. As shown in
FIG. 11 , a schematic drawing of a binary-weighted DAC 1100 is shown. Wherein, abias converter 1120 is disposed between two binary-weighted portions I and II. The binary-weighted portion I is coupled to thebias voltage BIAS 1 generated by thebias generating circuit 1110. Thebias converter 1120 would adjust anotherbias voltage BIAS 2 of the binary-weighted portion II according to thebias voltage BIAS 1 generated by thebias generating circuit 1110 and the match among the current source cells. These two bias voltages BIAS1 and BIAS2 are proportional, and can be synchronously adjusted according to the match among the current source cells. - It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims and their equivalents.
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US7068201B1 (en) | 2006-06-27 |
TW200627810A (en) | 2006-08-01 |
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