US20060199337A1 - Thin film transistor - Google Patents
Thin film transistor Download PDFInfo
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- US20060199337A1 US20060199337A1 US11/306,898 US30689806A US2006199337A1 US 20060199337 A1 US20060199337 A1 US 20060199337A1 US 30689806 A US30689806 A US 30689806A US 2006199337 A1 US2006199337 A1 US 2006199337A1
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- gate dielectric
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- 239000010409 thin film Substances 0.000 title claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 description 69
- 238000000034 method Methods 0.000 description 54
- 238000005530 etching Methods 0.000 description 32
- 150000002500 ions Chemical class 0.000 description 22
- 239000002019 doping agent Substances 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 125000004437 phosphorous atom Chemical group 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
Definitions
- the present invention relates to a semiconductor device, and more particularly, to a thin film transistor.
- a switch is formed for controlling the operation of the device.
- a thin film transistor TFT
- a thin film transistor TFT
- amorphous silicon (a-Si) thin film transistor amorphous silicon thin film transistor
- polysilicon thin film transistor A polysilicon thin film transistor has lower consuming power and higher electromigration than an amorphous silicon thin film transistor.
- the polysilicon thin film transistor receives increasing attention in the market after laser technology is employed for fabricating the polysilicon thin film transistor under 600 centigrade degrees.
- FIG. 1 is a schematic cross-sectional drawing of a conventional thin film transistor.
- a buffer layer 102 is formed on a substrate 100
- a polysilicon layer 104 and a gate dielectric layer 106 are sequentially formed over the buffer layer 102 .
- a gate layer 108 is formed on the gate dielectric layer 106 .
- a source region 110 a and a drain region 110 b are formed using a doping method with a doping mask.
- a channel region 112 is formed under the gate layer 108 .
- LDD lightly-doped-drain
- LDD lightly-doped-drain
- the source region/drain region and the lightly-doped-drain (LDD) regions are formed using two steps of the ion implanting process with two different doping masks formed by different masking processes. Therefore, the process for fabricating the thin film transistor with the lightly-doped-drain (LDD) regions is complicated and time-consuming. The mismatch of the positioning of the different doping masks is resulted during the fabrication of the thin film transistor.
- one object of the present invention is to provide a process for fabricating the thin film transistor with reduced processing steps.
- one object of the present invention is to provide a thin film transistor with improved leakage current and hot carrier effect.
- the present invention provides a method for fabricating the thin film transistor.
- a polysilicon layer and a gate dielectric layer are sequentially formed over a substrate.
- a patterned photoresist mask having a first portion and a second portion is formed over the gate dielectric layer, wherein the second portion has a thickness smaller than that of the first portion.
- the gate dielectric layer is patterned using an etching process with the patterned photoresist mask acting as an etching mask.
- the patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion is positioned at two sides of the third portion and has a thickness smaller than that of the third portion.
- An ion implanting process is performed with the patterned photoresist mask and the patterned gate dielectric layer acting as a doping mask to form a source region and a drain region in the polysilicon layer under the fourth portion of the patterned gate dielectric layer and to form a lightly-doped-drain (LDD) region in the polysilicon layer under the third portion of the patterned gate dielectric layer.
- a channel region is positioned in the polysilicon layer under the third portion of the patterned gate dielectric layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region.
- the patterned photoresist mask is removed and then a gate layer is formed over the gate dielectric layer over the channel region.
- the present invention provides a process for fabricating the thin film transistor.
- a polysilicon layer, a gate dielectric layer and a gate layer are sequentially formed over a substrate.
- a patterned photoresist mask having a first portion and a second portion is formed over the gate layer, wherein the first portion has a thickness smaller than that of the second portion.
- the gate layer and the gate dielectric layer are patterned using an etching process with the patterned photoresist mask acting as an etching mask.
- the patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion is positioned at two sides of the third portion and has a thickness smaller than that of the third portion.
- the patterned phosotresist mask is removed.
- An ion implanting process is performed with the patterned gate dielectric layer acting as a doping mask to form a source region and a drain region in the polysilicon layer under the fourth portion of the patterned gate dielectric layer and to form a lightly-doped-drain (LDD) region in the polysilicon layer under the third portion of the patterned gate dielectric layer.
- a channel region is positioned in the polysilicon layer under the third portion of the patterned gate layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region.
- the above patterned photoresist layer can be removed after the ion implantation process.
- the present invention provides a thin film transistor.
- the thin film transistor comprises a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a lightly-doped-drain (LDD) region.
- the polysilicon layer is positioned over the substrate.
- the patterned gate dielectric layer is positioned over the polysilicon layer.
- the patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion.
- the gate layer is positioned over the third portion of the patterned gate dielectric layer.
- the source region and the drain region are positioned in the polysilicon layer under the fourth portion of the patterned gate dielectric layer.
- the channel region is positioned in the polysilicon layer under the gate layer.
- the lightly-doped-drain (LDD) region is positioned in the polysilicon layer under the third portion of the patterned gate dielectric layer between the channel region and the source region or between the channel region and the drain region.
- the source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the ion implanting process with only one patterned gate dielectric layer and only one patterned photoresist mask acting as a doping mask. Therefore, the method for fabricating a thin film transistor according to the present invention is efficient. The mismatch of positioning two different doping masks, frequently occurred in the prior art, can be avoided.
- the present invention provides a process for fabricating the thin film transistor.
- a polysilicon layer, a gate dielectric layer and a gate layer are sequentially formed over a substrate.
- a patterned photoresist mask having a first portion and a second portion is formed over the gate layer, wherein the first portion has a thickness smaller than that of the second portion.
- the gate layer is patterned using an etching process with the patterned photoresist mask acting as an etching mask.
- the patterned gate layer has a fifth portion and a sixth portion, wherein the sixth portion has a thickness smaller than that of the fifth portion. Thereafter, the patterned photoresist layer is removed.
- a first ion implanting process for doping a source region and a drain region in the polysilicon layer is performed with the patterned photoresist mask and the patterned gate layer acting as a doping mask. Thereafter, the sixth portion of the patterned gate layer is removed.
- a second ion implanting process for doping the source region, the drain region and a lightly-doped-drain (LDD) region in the polysilicon layer is performed with the remaining patterned photoresist mask and the remaining patterned gate layer acting as a doping mask.
- a channel region is positioned in the polysilicon layer under the remaining patterned gate layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region.
- the patterned photoresist mask is removed. Further, the above patterned photoresist layer can be removed after the second ion implantation process.
- the source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the photolithography process. Therefore, the method for fabricating a thin film transistor according to the present invention is efficient. The mismatch of the positioning of two different doping masks as often occurred in the prior art, can be avoided.
- FIG. 1 is a schematic cross-sectional view of a conventional thin film transistor.
- FIGS. 2A-2C are schematic cross-sectional views of a thin film transistor showing the steps a thin film transistor according to a first embodiment of the present invention.
- FIGS. 3A-3B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention.
- FIGS. 4A-4B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention.
- FIGS. 5A-5B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention.
- FIGS. 6A-6D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a second embodiment of the present invention.
- FIGS. 7A-7B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention.
- FIGS. 8A-8B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention.
- FIGS. 9A-9B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention.
- FIG. 10 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention.
- FIG. 11 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.
- FIG. 12 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention.
- FIGS. 13A-13D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a third embodiment of the present invention.
- FIGS. 14A-14B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the third embodiment of the present invention.
- FIGS. 15A-15B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the third embodiment of the present invention.
- FIGS. 2A-2C are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a first embodiment of the present invention.
- a polysilicon layer 204 and a gate dielectric layer 206 are sequentially formed over a substrate 200 .
- the substrate 200 may be made of a transparent material, such as glass.
- the process for forming the polysilicon layer 204 includes forming an amorphous silicon layer (not shown) on the substrate 206 , melting the amorphous silicon layer by an excimer-laser annealing (ELA) process, and then recrystallize the melted silicon layer.
- the gate dielectric layer 206 made of silicon oxide, silicon nitride, or silicon oxynitride, for example, can be formed using a chemical-vapor-deposition process.
- a buffer layer 202 made of silicon oxide for example, can be formed over the substrate 200 before forming the polysilicon layer 204 .
- a patterned photoresist mask 208 having a first portion 210 a and a second portion 210 b is formed over the gate dielectric layer 206 .
- the second portion 210 b is positioned at two sides of the first portion 210 a and has a thickness smaller than that of the first portion 210 a .
- the process of forming patterned photoresist mask 208 may include the following steps. First, an original photoresist layer (not shown) is formed over the gate dielectric layer 206 .
- the original photoresist layer such as positive photoresist, can be exposed to light with a mask 212 having a semi-transparent region 214 a , a transparent region 214 b and a light-blocking region 214 c .
- the original photoresist layer can be developed to form the patterned photoresist mask 208 having the first portion 210 a and the second portion 210 b .
- the first portion 210 a is aligned with the light-blocking region 214 c of the mask 212
- the second portion 210 b is aligned with the semi-transparent region 214 a of the mask 212 .
- the original photoresist layer that is aligned with the transparent region 214 b during exposing can be completely removed during developing.
- the gate dielectric layer 206 a is patterned using an etching process with the patterned photoresist mask 208 acting as an etching mask.
- the patterned gate dielectric layer 206 a has a third portion 216 a and a fourth portion 216 b , wherein the fourth portion 216 b is positioned at two sides of the third portion 216 a and has a thickness smaller than that of the third portion 216 a .
- the gate dielectric layer 206 not covered by the patterned photoresist mask 208 can be partially removed to create the fourth portion 216 b .
- the gate dielectric layer 206 covered by the second portion 210 b of the patterned photoresist mask 208 , during etching, can be retained or slightly removed and can be exposed thereafter.
- the gate dielectric layer 206 covered by the first portion 210 a of the patterned photoresist mask 208 is not removed during etching.
- An ion implanting process 218 is performed with the patterned photoresist mask 208 and the patterned gate dielectric layer 206 a acting as a doping mask to form a source region 220 a and a drain region 220 b in the polysilicon layer 204 under the fourth portion 216 b of the patterned gate dielectric layer 206 a and to form lightly-doped-drain (LDD) regions 224 a and 224 b in the polysilicon layer 204 under the third portion 216 a of the patterned gate dielectric layer 206 a .
- LDD lightly-doped-drain
- a channel region 222 is configured in the polysilicon layer 204 under the third portion 216 a of the patterned gate dielectric layer 206 a , wherein the lightly-doped-drain (LDD) regions 224 a and 224 b are configured between the channel region 222 and the source region 220 a and between the channel region 222 and the drain region 220 b .
- LDD lightly-doped-drain
- the channel region 222 is defined under the thickest portion of the doping mask which includes the third portion 216 a of the patterned gate dielectric layer 206 a and the patterned photoresist mask 208 .
- the lightly-doped-drain (LDD) regions 224 a and 224 b can be formed under the second thickness portion of the doping mask which includes the third portion 216 a of the patterned gate dielectric layer 206 a .
- the source region 220 a and the drain region 220 b can be formed under the thinnest portion of the doping mask which includes the fourth portion 216 b of the patterned gate dielectric layer 206 a.
- the ion implanting process may provide a doping energy of 70 keV to 80 KeV, for example.
- the patterned photoresist mask 208 is removed as shown in FIG. 2C and then a gate layer 226 is formed over the patterned gate dielectric layer 206 a over the channel region 222 .
- a drain conductive layer and a source conductive layer will be formed.
- the detail will be described in the following.
- a dielectric layer 228 is formed over the substrate 200 and covers the gate layer 226 and the patterned gate dielectric layer 206 a .
- a source plug opening 230 a and a drain plug opening 230 b are formed passing through the dielectric layer 228 and the patterned gate dielectric layer 206 a and exposing the source region 220 a and the drain region 220 b .
- a conductive layer including a source conductive layer 232 a and a drain conductive layer 232 b is formed over the dielectric layer 228 and in the source plug opening 230 a and the drain plug opening 230 b .
- the source conductive layer 232 a is electrically connected to the source region 220 a .
- the drain conductive layer 232 b is electrically connected to the drain region 220 b.
- the widths w 1 and w 2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are equivalent as shown in FIG. 2A , but, alternatively, they can be different in practice. Referring to FIG. 3A , the widths w 1 and w 2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are different. Therefore, as shown in FIG. 3B , asymmetric lightly-doped-drain (LDD) regions 224 a and 224 b with different widths are formed after the steps of etching the gate dielectric layer 206 and implanting ions. Besides, referring to FIG.
- LDD lightly-doped-drain
- the second portion 210 b is positioned at only one side of the first portion 210 a of the patterned photoresist mask 208 . Accordingly, as shown in FIG. 4B , only one lightly-doped-drain (LDD) region 224 b is formed after the steps of etching the gate dielectric layer 206 and implanting ions.
- LDD lightly-doped-drain
- the gate dielectric layer 206 positioned over the polysilicon layer 204 can be formed from two layers 207 a and 207 b of gate dielectric material, wherein the two layers 207 a and 207 b may have different materials or a same material.
- the gate dielectric layer 207 b not covered by the patterned photoresist layer 208 is partially etched until the gate dielectric layer 207 a is exposed, as shown in FIG. 5B .
- FIGS. 6A-6D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a second embodiment of the present invention.
- a polysilicon layer 204 , a gate dielectric layer 206 and a gate layer 226 are sequentially formed over a substrate 200 .
- a buffer layer 202 can be formed over the substrate 200 before forming the polysilicon layer 204 .
- a patterned photoresist mask 208 having a first portion 210 a and a second portion 210 b is formed over the gate layer 226 .
- the second portion 210 b is positioned at two sides of the first portion 210 a and has a thickness smaller than that of the first portion 210 a .
- the process of forming patterned photoresist mask 208 may include the following steps. First, an original photoresist layer (not shown) is formed over the gate dielectric layer 206 .
- the original photoresist layer such as positive photoresist, can be exposed to light with a mask 212 having a semi-transparent region 214 a , a transparent region 214 b and a light-blocking region 214 c .
- the original photoresist layer can be developed to form the patterned photoresist mask 208 having the first portion 210 a and the second portion 210 b .
- the first portion 210 a is aligned with the light-blocking region 214 c of the mask 212
- the second portion 210 b is aligned with the semi-transparent region 214 a of the mask 212 .
- the original photoresist layer that is aligned with the transparent region 214 b during exposing can be completely removed during developing.
- the gate layer 226 a is patterned using an etching process with the patterned photoresist mask 208 acting as an etching mask.
- the patterned gate layer 226 a has a fifth portion 300 a and a sixth portion 300 b , wherein the sixth portion 300 b is positioned at two sides of the fifth portion 300 a and has a thickness smaller than that of the fifth portion 300 a .
- the gate layer 226 not covered by the patterned photoresist mask 208 can be completely removed.
- the gate layer 226 covered by the second portion 210 b of the patterned photoresist mask 208 can be partially removed to create the sixth portion 300 b .
- the gate layer 226 covered by the first portion 210 a of the patterned photoresist mask 208 is not removed.
- the gate dielectric layer 206 a is patterned using an etching process with the patterned photoresist mask 208 and the patterned gate layer 226 a acting as an etching mask.
- the sixth portion 300 b of the patterned gate layer 226 a is being removed.
- the patterned gate dielectric layer 206 a has a third portion 216 a and a fourth portion 216 b , wherein the fourth portion 216 b is positioned at two sides of the third portion 216 a and has a thickness smaller than that of the third portion 216 a .
- the gate dielectric layer 206 not covered by the patterned gate layer 226 a can be partially removed to create the fourth portion 216 b .
- the gate dielectric layer 206 covered by the sixth portion 300 b of the patterned gate layer 226 a can be retained or slightly removed and is exposed thereafter.
- the gate dielectric layer 206 covered by the fifth portion 300 a of the patterned gate layer 226 a is not removed.
- An ion implanting process is performed with the patterned photoresist mask 208 , the patterned gate layer 226 b and the patterned gate dielectric layer 206 a acting as a doping mask to form a source region 220 a and a drain region 220 b in the polysilicon layer 204 under the fourth portion 216 b of the patterned gate dielectric layer 206 a and to form lightly-doped-drain (LDD) regions 224 a and 224 b in the polysilicon layer 204 under the third portion 216 a of the patterned gate dielectric layer 206 a .
- LDD lightly-doped-drain
- a channel region 222 is configured in the polysilicon layer 204 under the patterned gate layer 226 b , wherein the lightly-doped-drain (LDD) regions 224 a and 224 b are positioned between the channel region 222 and the source region 220 a and between the channel region 222 and the drain region 220 b.
- LDD lightly-doped-drain
- the patterned photoresist mask 208 is removed.
- the removal of the patterned photoresist layer 208 can be conducted after the patterning of the gate dielectric layer 206 a and before the ion implantation process.
- a drain conductive layer and a source conductive layer are formed after the removal of the patterned photoresist layer 208 .
- a dielectric layer 228 is formed over the substrate 200 and covers the gate layer 226 and the patterned gate dielectric layer 206 a .
- a source plug opening 230 a and a drain plug opening 230 b are formed passing through the dielectric layer 228 and the patterned gate dielectric layer 206 a and exposing the source region 220 a and the drain region 220 b .
- a conductive layer including a source conductive layer 232 a and a drain conductive layer 232 b is formed over the dielectric layer 228 and in the source plug opening 230 a and the drain plug opening 230 b .
- the source conductive layer 232 a is electrically connected to the source region 220 a .
- the drain conductive layer 232 b is electrically connected to the drain region 220 b.
- the widths w 1 and w 2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are equivalent as shown in FIG. 6A , but, alternatively, they can be different in practice.
- the widths w 1 and w 2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are different. Therefore, as shown in FIG. 7B , asymmetric lightly-doped-drain (LDD) regions 224 a and 224 b with different widths are formed after the steps of etching the gate dielectric layer 206 and implanting ions.
- LDD lightly-doped-drain
- the second portion 210 b is positioned at only one side of the first portion 210 a of the patterned photoresist mask 208 . Accordingly, as shown in FIG. 8B , only one lightly-doped-drain (LDD) region 224 b can be formed after the steps of etching the gate dielectric layer 206 and implanting ions.
- LDD lightly-doped-drain
- the gate dielectric layer 206 positioned over the polysilicon layer 204 can be formed from two layers 207 a and 207 b of gate dielectric material, wherein the two layers 207 a and 207 b may have different materials or a same material.
- the gate dielectric layer 207 b not covered by the patterned photoresist layer 208 is partially etched until the gate dielectric layer 207 a is exposed, as shown in FIG. 9B .
- the thin film transistor as shown in FIGS. 10, 11 and 12 can be fabricated employing the above first and second embodiments.
- the thin film transistor includes a substrate 500 , a polysilicon layer 502 , a patterned gate dielectric layer 504 , a gate layer 506 , a channel region 514 , a source region 508 a , a drain region 508 b and lightly-doped-drain (LDD) regions 510 a and 510 b.
- LDD lightly-doped-drain
- the polysilicon layer 502 is positioned over the substrate 500 .
- the patterned gate dielectric layer 504 is positioned over the polysilicon layer 502 .
- the patterned gate dielectric layer 504 has a third portion 512 a and a fourth portion 512 b , wherein the fourth portion 512 b is positioned at two sides of the third portion 512 a and has a thickness smaller than that of the third portion 512 a.
- the gate layer 506 is positioned over the third portion 512 a of the patterned gate dielectric layer 504 .
- the source region 508 a and the drain region 508 b are positioned in the polysilicon layer 502 under the fourth portion 512 b of the patterned gate dielectric layer 504 .
- the channel region 514 is positioned in the polysilicon layer 502 under the gate layer 506 .
- the lightly-doped-drain (LDD) regions 510 a and 510 b are positioned in the polysilicon layer 502 under the third portion 504 of the patterned gate dielectric layer 504 between the channel region 514 and the source region 508 a and between the channel region 514 and the drain region 508 b.
- LDD lightly-doped-drain
- the thin film transistor further includes a dielectric layer 516 , a source conductive layer 518 a and a drain conductive layer 518 b .
- the dielectric layer 516 covers the gate layer 506 and the patterned gate dielectric layer 504 .
- the source conductive layer 518 a and the drain conductive layer 518 b are deposited over the dielectric layer 516 and pass through the dielectric layer 516 and the patterned gate dielectric layer 504 for electrically connecting with the source region 508 a and the drain region 508 b , respectively.
- the thin film transistor further includes a buffer layer 520 positioned between the substrate 500 and the polysilicon layer 502 .
- the lightly-doped-drain (LDD) region 510 a positioned between the channel region 514 and the source region 508 a has a width w 3 equivalent to the width w 4 of the lightly-doped-drain (LDD) region 510 b positioned between the channel region 514 and the drain region 508 b .
- the width w 3 of the lightly-doped-drain (LDD) region 510 a positioned between the channel region 514 and the source region 508 a is different from the width w 4 of the lightly-doped-drain (LDD) region 510 b positioned between the channel region 514 and the drain region 508 b .
- one of the lightly-doped-drain (LDD) region 510 a and 510 b can be formed between the channel region 514 and the source region 508 a or between the channel region 514 and the drain region 508 b.
- LDD lightly-doped-drain
- the ion implanting process only one step of the ion implanting process is performed to produce a source region, a drain region and lightly-doped-drain (LDD) regions with different dopant concentrations due to a patterned gate dielectric layer having different thicknesses.
- the patterned gate dielectric layer is formed by a single step of the photolithography process and then by a single step of the etching process.
- the photolithography process is performed to produce a patterned photoresist mask with different thicknesses by means of a mask having a semi-transparent region. Therefore, the method of the present invention is easier than the conventional method.
- leakage current and hot carrier effect can be effectively improved by forming lightly-doped-drain (LDD) regions having a same width or different widths.
- FIGS. 13A-13D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a third embodiment of the present invention.
- a polysilicon layer 204 , a gate dielectric layer 206 and a gate layer 226 are sequentially formed over a substrate 200 .
- a buffer layer 202 can be formed over the substrate 200 before forming the polysilicon layer 204 .
- a patterned photoresist mask 208 having a first portion 210 a and a second portion 210 b is formed over the gate layer 226 .
- the second portion 210 b is positioned at two sides of the first portion 210 a and has a thickness smaller than that of the first portion 210 a .
- the process of forming the patterned photoresist mask 208 over the gate layer 226 can be referred to the above discussion for the second embodiment, and the detailed explanation is omitted herein.
- the gate layer 226 a is patterned using an etching process with the patterned photoresist mask 208 acting as an etching mask.
- the patterned gate layer 226 a has a fifth portion 300 a and a sixth portion 300 b , wherein the sixth portion 300 b is positioned at two sides of the fifth portion 300 a and has a thickness smaller than that of the fifth portion 300 a .
- the process of forming the patterned gate layer 226 a can be referred to the discussion of the above second embodiment, and the concerning explanation is omitted herein.
- An ion implanting process for doping a source region 220 a and a drain region 220 b in the polysilicon layer 204 is performed with the patterned photoresist mask 208 , the patterned gate layer 226 a and the gate dielectric layer 206 acting as a doping mask.
- the ion implanting process may provide a doping energy of 70 to 80 keV, for example.
- the sixth portion 300 b of the patterned gate layer 226 a is removed using an etching process.
- Another ion implanting process for doping the source region 220 a , the drain region 220 b and lightly-doped-drain (LDD) regions 224 a and 224 b in the polysilicon layer 204 is performed with the remaining patterned photoresist mask 208 and the remaining patterned gate layer 226 c acting as a doping mask.
- LDD lightly-doped-drain
- a channel region 222 is configured in the polysilicon layer 204 under the remaining patterned gate layer 226 c , wherein the lightly-doped-drain (LDD) regions 224 a and 224 b are positioned between the channel region 222 and the source region 220 a and between the channel region 222 and the drain region 220 b.
- LDD lightly-doped-drain
- the ion implanting process may provide a doping energy of 70 to 80 keV, for example.
- the patterned photoresist mask 208 is removed.
- removing the patterned photoresist layer 208 is conducted after forming the patterned gate layer 226 and before performing ion implantation process 600 .
- a drain conductive layer and a source conductive layer are formed. The detail will be described in the following.
- a dielectric layer 228 is formed over the substrate 200 and covers the gate layer 226 and the patterned gate dielectric layer 206 a .
- a source plug opening 230 a and a drain plug opening 230 b are formed passing through the dielectric layer 228 and the patterned gate dielectric layer 206 a and exposing the source region 220 a and the drain region 220 b .
- a conductive layer including a source conductive layer 232 a and a drain conductive layer 232 b is formed over the dielectric layer 228 and in the source plug opening 230 a and the drain plug opening 230 b .
- the source conductive layer 232 a is electrically connected to the source region 220 a .
- the drain conductive layer 232 b is electrically connected to the drain region 220 b.
- the widths w 1 and w 2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are equivalent as shown in FIG. 13A , but, alternatively, they can be different in practice. Referring to FIG. 14A , the widths w 1 and w 2 of the second portion 210 b at two sides of the first portion 210 a of the patterned photoresist mask 208 are different. Therefore, as shown in FIG. 14B , asymmetric lightly-doped-drain (LDD) regions 224 a and 224 b with different widths are formed after the steps of etching the gate dielectric layer 206 and implanting ions. Besides, referring to FIG.
- LDD lightly-doped-drain
- the second portion 210 b is positioned at only one side of the first portion 210 a of the patterned photoresist mask 208 . Accordingly, as shown in FIG. 15B , only one lightly-doped-drain (LDD) region 224 b can be formed after the steps of etching the gate dielectric layer 206 and implanting ions.
- LDD lightly-doped-drain
- the source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the photolithography process. Therefore, the above method is more efficient than the conventional method. In addition, leakage current and hot carrier effect can be effectively improved by forming lightly-doped-drain (LDD) regions having a same width or different widths.
Abstract
A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.
Description
- This is a divisional application of application Ser. No. 10/906,041, filed on Feb. 1, 2005, which is now allowed and all disclosures of the application are incorporated herewith by reference.
- 1. Field of the Invention
- The present invention relates to a semiconductor device, and more particularly, to a thin film transistor.
- 2. Description of Related Art
- In a device, a switch is formed for controlling the operation of the device. As to an active display device, a thin film transistor (TFT) is generally made as a switch. Based on the material of the channel of thin film transistors, there are two types of TFT: amorphous silicon (a-Si) thin film transistor and polysilicon thin film transistor. A polysilicon thin film transistor has lower consuming power and higher electromigration than an amorphous silicon thin film transistor. The polysilicon thin film transistor receives increasing attention in the market after laser technology is employed for fabricating the polysilicon thin film transistor under 600 centigrade degrees.
-
FIG. 1 is a schematic cross-sectional drawing of a conventional thin film transistor. Referring toFIG. 1 , after abuffer layer 102 is formed on asubstrate 100, apolysilicon layer 104 and a gatedielectric layer 106 are sequentially formed over thebuffer layer 102. Agate layer 108 is formed on the gatedielectric layer 106. Thereafter, asource region 110 a and adrain region 110 b are formed using a doping method with a doping mask. Achannel region 112 is formed under thegate layer 108. Leakage current and hot carrier effect can be avoided by forming lightly-doped-drain (LDD)regions source region 110 a and thechannel region 112 and between thedrain region 110 b and thechannel region 112. A sourceconductive layer 118 a and a drainconductive layer 118 b passing through the gatedielectric layer 106 and adielectric layer 116 are electrically connected to thesource region 110 a and thedrain region 110 b, respectively. - In the above process, leakage current and hot carrier effect can be mitigated by the lightly-doped-drain (LDD) regions that are formed using an extra ion implanting process with an extra doping mask. In other words, the source region/drain region and the lightly-doped-drain (LDD) regions are formed using two steps of the ion implanting process with two different doping masks formed by different masking processes. Therefore, the process for fabricating the thin film transistor with the lightly-doped-drain (LDD) regions is complicated and time-consuming. The mismatch of the positioning of the different doping masks is resulted during the fabrication of the thin film transistor.
- Accordingly, one object of the present invention is to provide a process for fabricating the thin film transistor with reduced processing steps.
- Accordingly, one object of the present invention is to provide a thin film transistor with improved leakage current and hot carrier effect.
- To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a method for fabricating the thin film transistor. A polysilicon layer and a gate dielectric layer are sequentially formed over a substrate. A patterned photoresist mask having a first portion and a second portion is formed over the gate dielectric layer, wherein the second portion has a thickness smaller than that of the first portion. The gate dielectric layer is patterned using an etching process with the patterned photoresist mask acting as an etching mask. The patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion is positioned at two sides of the third portion and has a thickness smaller than that of the third portion. An ion implanting process is performed with the patterned photoresist mask and the patterned gate dielectric layer acting as a doping mask to form a source region and a drain region in the polysilicon layer under the fourth portion of the patterned gate dielectric layer and to form a lightly-doped-drain (LDD) region in the polysilicon layer under the third portion of the patterned gate dielectric layer. A channel region is positioned in the polysilicon layer under the third portion of the patterned gate dielectric layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region. Thereafter, the patterned photoresist mask is removed and then a gate layer is formed over the gate dielectric layer over the channel region.
- To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a process for fabricating the thin film transistor. A polysilicon layer, a gate dielectric layer and a gate layer are sequentially formed over a substrate. A patterned photoresist mask having a first portion and a second portion is formed over the gate layer, wherein the first portion has a thickness smaller than that of the second portion. The gate layer and the gate dielectric layer are patterned using an etching process with the patterned photoresist mask acting as an etching mask. The patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion is positioned at two sides of the third portion and has a thickness smaller than that of the third portion. Thereafter, the patterned phosotresist mask is removed. An ion implanting process is performed with the patterned gate dielectric layer acting as a doping mask to form a source region and a drain region in the polysilicon layer under the fourth portion of the patterned gate dielectric layer and to form a lightly-doped-drain (LDD) region in the polysilicon layer under the third portion of the patterned gate dielectric layer. A channel region is positioned in the polysilicon layer under the third portion of the patterned gate layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region. The above patterned photoresist layer can be removed after the ion implantation process.
- To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a thin film transistor. The thin film transistor comprises a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a lightly-doped-drain (LDD) region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third portion and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion of the patterned gate dielectric layer. The source region and the drain region are positioned in the polysilicon layer under the fourth portion of the patterned gate dielectric layer. The channel region is positioned in the polysilicon layer under the gate layer. The lightly-doped-drain (LDD) region is positioned in the polysilicon layer under the third portion of the patterned gate dielectric layer between the channel region and the source region or between the channel region and the drain region.
- The source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the ion implanting process with only one patterned gate dielectric layer and only one patterned photoresist mask acting as a doping mask. Therefore, the method for fabricating a thin film transistor according to the present invention is efficient. The mismatch of positioning two different doping masks, frequently occurred in the prior art, can be avoided.
- To achieve these and other advantages and in accordance with the purpose of the invention, the present invention provides a process for fabricating the thin film transistor. A polysilicon layer, a gate dielectric layer and a gate layer are sequentially formed over a substrate. A patterned photoresist mask having a first portion and a second portion is formed over the gate layer, wherein the first portion has a thickness smaller than that of the second portion. The gate layer is patterned using an etching process with the patterned photoresist mask acting as an etching mask. The patterned gate layer has a fifth portion and a sixth portion, wherein the sixth portion has a thickness smaller than that of the fifth portion. Thereafter, the patterned photoresist layer is removed. A first ion implanting process for doping a source region and a drain region in the polysilicon layer is performed with the patterned photoresist mask and the patterned gate layer acting as a doping mask. Thereafter, the sixth portion of the patterned gate layer is removed. A second ion implanting process for doping the source region, the drain region and a lightly-doped-drain (LDD) region in the polysilicon layer is performed with the remaining patterned photoresist mask and the remaining patterned gate layer acting as a doping mask. A channel region is positioned in the polysilicon layer under the remaining patterned gate layer, wherein the lightly-doped-drain (LDD) region is positioned between the channel region and the source region or between the channel region and the drain region. Thereafter, the patterned photoresist mask is removed. Further, the above patterned photoresist layer can be removed after the second ion implantation process.
- The source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the photolithography process. Therefore, the method for fabricating a thin film transistor according to the present invention is efficient. The mismatch of the positioning of two different doping masks as often occurred in the prior art, can be avoided.
- One or part or all of these and other features and advantages of the present invention will become readily apparent to those skilled in this art from the following description wherein there is shown and described a preferred embodiment of this invention, simply by way of illustration of one of the modes best suited to carry out the invention. As it will be realized, the invention is capable of different embodiments, and its several details are capable of modifications in various, obvious aspects all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention, and together with the description, serve to explain the principles of the invention.
-
FIG. 1 is a schematic cross-sectional view of a conventional thin film transistor. -
FIGS. 2A-2C are schematic cross-sectional views of a thin film transistor showing the steps a thin film transistor according to a first embodiment of the present invention. -
FIGS. 3A-3B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention. -
FIGS. 4A-4B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention. -
FIGS. 5A-5B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the first embodiment of the present invention. -
FIGS. 6A-6D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a second embodiment of the present invention. -
FIGS. 7A-7B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention. -
FIGS. 8A-8B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention. -
FIGS. 9A-9B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the second embodiment of the present invention. -
FIG. 10 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention. -
FIG. 11 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. -
FIG. 12 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention. -
FIGS. 13A-13D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a third embodiment of the present invention. -
FIGS. 14A-14B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the third embodiment of the present invention. -
FIGS. 15A-15B are schematic cross-sectional views of a thin film transistor showing the steps for fabricating another thin film transistor according to the third embodiment of the present invention. - Various specific embodiments of the present invention are disclosed below, illustrating examples of various possible implementations of the concepts of the present invention. The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
-
FIGS. 2A-2C are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a first embodiment of the present invention. - Referring to
FIG. 2A , apolysilicon layer 204 and agate dielectric layer 206 are sequentially formed over asubstrate 200. Thesubstrate 200 may be made of a transparent material, such as glass. The process for forming thepolysilicon layer 204 includes forming an amorphous silicon layer (not shown) on thesubstrate 206, melting the amorphous silicon layer by an excimer-laser annealing (ELA) process, and then recrystallize the melted silicon layer. Thegate dielectric layer 206 made of silicon oxide, silicon nitride, or silicon oxynitride, for example, can be formed using a chemical-vapor-deposition process. Alternatively, abuffer layer 202 made of silicon oxide, for example, can be formed over thesubstrate 200 before forming thepolysilicon layer 204. - A patterned
photoresist mask 208 having afirst portion 210 a and asecond portion 210 b is formed over thegate dielectric layer 206. Thesecond portion 210 b is positioned at two sides of thefirst portion 210 a and has a thickness smaller than that of thefirst portion 210 a. The process of forming patternedphotoresist mask 208 may include the following steps. First, an original photoresist layer (not shown) is formed over thegate dielectric layer 206. The original photoresist layer, such as positive photoresist, can be exposed to light with amask 212 having asemi-transparent region 214 a, atransparent region 214 b and a light-blockingregion 214 c. Afterwards, the original photoresist layer can be developed to form the patternedphotoresist mask 208 having thefirst portion 210 a and thesecond portion 210 b. During exposing, thefirst portion 210 a is aligned with the light-blockingregion 214 c of themask 212, and thesecond portion 210 b is aligned with thesemi-transparent region 214 a of themask 212. The original photoresist layer that is aligned with thetransparent region 214 b during exposing can be completely removed during developing. - Referring to 2B, the
gate dielectric layer 206 a is patterned using an etching process with the patternedphotoresist mask 208 acting as an etching mask. The patternedgate dielectric layer 206 a has athird portion 216 a and afourth portion 216 b, wherein thefourth portion 216 b is positioned at two sides of thethird portion 216 a and has a thickness smaller than that of thethird portion 216 a. Thegate dielectric layer 206 not covered by the patternedphotoresist mask 208, during etching, can be partially removed to create thefourth portion 216 b. Thegate dielectric layer 206 covered by thesecond portion 210 b of the patternedphotoresist mask 208, during etching, can be retained or slightly removed and can be exposed thereafter. Thegate dielectric layer 206 covered by thefirst portion 210 a of the patternedphotoresist mask 208, is not removed during etching. - An
ion implanting process 218 is performed with the patternedphotoresist mask 208 and the patternedgate dielectric layer 206 a acting as a doping mask to form asource region 220 a and adrain region 220 b in thepolysilicon layer 204 under thefourth portion 216 b of the patternedgate dielectric layer 206 a and to form lightly-doped-drain (LDD)regions polysilicon layer 204 under thethird portion 216 a of the patternedgate dielectric layer 206 a. Achannel region 222 is configured in thepolysilicon layer 204 under thethird portion 216 a of the patternedgate dielectric layer 206 a, wherein the lightly-doped-drain (LDD)regions channel region 222 and thesource region 220 a and between thechannel region 222 and thedrain region 220 b. After performing only one step of theion implanting process 218, the regions with different dopant concentrations can be produced due to the patternedgate dielectric layer 206 a having different thicknesses. Thechannel region 222 is defined under the thickest portion of the doping mask which includes thethird portion 216 a of the patternedgate dielectric layer 206 a and the patternedphotoresist mask 208. The lightly-doped-drain (LDD)regions third portion 216 a of the patternedgate dielectric layer 206 a. Thesource region 220 a and thedrain region 220 b can be formed under the thinnest portion of the doping mask which includes thefourth portion 216 b of the patternedgate dielectric layer 206 a. - In one embodiment, under the condition that the
gate dielectric layer 206 as shown inFIG. 2A is formed with a thickness of 1000 angstroms, and n-type dopants 218 such as phosphorous atoms are doped with a dopant concentration ranging from 1*1014 to 1*1016 atoms per square centimeter for fabricating a n-type polysilicon thin film transistor, the ion implanting process may provide a doping energy of 70 keV to 80 KeV, for example. - Thereafter, the patterned
photoresist mask 208 is removed as shown inFIG. 2C and then agate layer 226 is formed over the patternedgate dielectric layer 206 a over thechannel region 222. - After the
gate layer 226 is formed, a drain conductive layer and a source conductive layer will be formed. The detail will be described in the following. Adielectric layer 228 is formed over thesubstrate 200 and covers thegate layer 226 and the patternedgate dielectric layer 206 a. A source plug opening 230 a and adrain plug opening 230 b are formed passing through thedielectric layer 228 and the patternedgate dielectric layer 206 a and exposing thesource region 220 a and thedrain region 220 b. Afterwards, a conductive layer including a sourceconductive layer 232 a and a drainconductive layer 232 b is formed over thedielectric layer 228 and in the source plug opening 230 a and thedrain plug opening 230 b. The sourceconductive layer 232 a is electrically connected to thesource region 220 a. The drainconductive layer 232 b is electrically connected to thedrain region 220 b. - The widths w1 and w2 of the
second portion 210 b at two sides of thefirst portion 210 a of the patternedphotoresist mask 208 are equivalent as shown inFIG. 2A , but, alternatively, they can be different in practice. Referring toFIG. 3A , the widths w1 and w2 of thesecond portion 210 b at two sides of thefirst portion 210 a of the patternedphotoresist mask 208 are different. Therefore, as shown inFIG. 3B , asymmetric lightly-doped-drain (LDD)regions gate dielectric layer 206 and implanting ions. Besides, referring toFIG. 4A , thesecond portion 210 b is positioned at only one side of thefirst portion 210 a of the patternedphotoresist mask 208. Accordingly, as shown inFIG. 4B , only one lightly-doped-drain (LDD)region 224 b is formed after the steps of etching thegate dielectric layer 206 and implanting ions. - Alternatively, referring to
FIG. 5A , thegate dielectric layer 206 positioned over thepolysilicon layer 204 can be formed from twolayers layers gate dielectric layer 206, thegate dielectric layer 207 b not covered by the patternedphotoresist layer 208 is partially etched until thegate dielectric layer 207 a is exposed, as shown inFIG. 5B . - In the following embodiment, the explanation for the elements having the same reference numbers recited in the above embodiment will be omitted.
-
FIGS. 6A-6D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a second embodiment of the present invention. - Referring to
FIG. 6A , apolysilicon layer 204, agate dielectric layer 206 and agate layer 226 are sequentially formed over asubstrate 200. Alternatively, abuffer layer 202 can be formed over thesubstrate 200 before forming thepolysilicon layer 204. - A patterned
photoresist mask 208 having afirst portion 210 a and asecond portion 210 b is formed over thegate layer 226. Thesecond portion 210 b is positioned at two sides of thefirst portion 210 a and has a thickness smaller than that of thefirst portion 210 a. The process of forming patternedphotoresist mask 208 may include the following steps. First, an original photoresist layer (not shown) is formed over thegate dielectric layer 206. The original photoresist layer, such as positive photoresist, can be exposed to light with amask 212 having asemi-transparent region 214 a, atransparent region 214 b and a light-blockingregion 214 c. Afterwards, the original photoresist layer can be developed to form the patternedphotoresist mask 208 having thefirst portion 210 a and thesecond portion 210 b. During exposing, thefirst portion 210 a is aligned with the light-blockingregion 214 c of themask 212, and thesecond portion 210 b is aligned with thesemi-transparent region 214 a of themask 212. The original photoresist layer that is aligned with thetransparent region 214 b during exposing can be completely removed during developing. - Referring to 6B, the
gate layer 226 a is patterned using an etching process with the patternedphotoresist mask 208 acting as an etching mask. The patternedgate layer 226 a has afifth portion 300 a and asixth portion 300 b, wherein thesixth portion 300 b is positioned at two sides of thefifth portion 300 a and has a thickness smaller than that of thefifth portion 300 a. Thegate layer 226 not covered by the patternedphotoresist mask 208, during etching, can be completely removed. Thegate layer 226 covered by thesecond portion 210 b of the patternedphotoresist mask 208, during etching, can be partially removed to create thesixth portion 300 b. Thegate layer 226 covered by thefirst portion 210 a of the patternedphotoresist mask 208, during etching, is not removed. - Thereafter, referring to
FIG. 6C , thegate dielectric layer 206 a is patterned using an etching process with the patternedphotoresist mask 208 and the patternedgate layer 226 a acting as an etching mask. During the step of etchinggate dielectric layer 206, thesixth portion 300 b of the patternedgate layer 226 a is being removed. The patternedgate dielectric layer 206 a has athird portion 216 a and afourth portion 216 b, wherein thefourth portion 216 b is positioned at two sides of thethird portion 216 a and has a thickness smaller than that of thethird portion 216 a. Thegate dielectric layer 206 not covered by the patternedgate layer 226 a, during etching, can be partially removed to create thefourth portion 216 b. Thegate dielectric layer 206 covered by thesixth portion 300 b of the patternedgate layer 226 a, during etching, can be retained or slightly removed and is exposed thereafter. Thegate dielectric layer 206 covered by thefifth portion 300 a of the patternedgate layer 226 a, during etching, is not removed. - An ion implanting process is performed with the patterned
photoresist mask 208, the patternedgate layer 226 b and the patternedgate dielectric layer 206 a acting as a doping mask to form asource region 220 a and adrain region 220 b in thepolysilicon layer 204 under thefourth portion 216 b of the patternedgate dielectric layer 206 a and to form lightly-doped-drain (LDD)regions polysilicon layer 204 under thethird portion 216 a of the patternedgate dielectric layer 206 a. Achannel region 222 is configured in thepolysilicon layer 204 under the patternedgate layer 226 b, wherein the lightly-doped-drain (LDD)regions channel region 222 and thesource region 220 a and between thechannel region 222 and thedrain region 220 b. - Thereafter, as shown in
FIG. 6D , the patternedphotoresist mask 208 is removed. In one embodiment, the removal of the patternedphotoresist layer 208 can be conducted after the patterning of thegate dielectric layer 206 a and before the ion implantation process. Further, in another embodiment, a drain conductive layer and a source conductive layer are formed after the removal of the patternedphotoresist layer 208. The detail will be described in the following. After the patternedphotoresist mask 208 is removed, adielectric layer 228 is formed over thesubstrate 200 and covers thegate layer 226 and the patternedgate dielectric layer 206 a. A source plug opening 230 a and adrain plug opening 230 b are formed passing through thedielectric layer 228 and the patternedgate dielectric layer 206 a and exposing thesource region 220 a and thedrain region 220 b. Afterwards, a conductive layer including a sourceconductive layer 232 a and a drainconductive layer 232 b is formed over thedielectric layer 228 and in the source plug opening 230 a and thedrain plug opening 230 b. The sourceconductive layer 232 a is electrically connected to thesource region 220 a. The drainconductive layer 232 b is electrically connected to thedrain region 220 b. - The widths w1 and w2 of the
second portion 210 b at two sides of thefirst portion 210 a of the patternedphotoresist mask 208 are equivalent as shown inFIG. 6A , but, alternatively, they can be different in practice. Referring toFIG. 7A , the widths w1 and w2 of thesecond portion 210 b at two sides of thefirst portion 210 a of the patternedphotoresist mask 208 are different. Therefore, as shown inFIG. 7B , asymmetric lightly-doped-drain (LDD)regions gate dielectric layer 206 and implanting ions. Besides, referring toFIG. 8A , thesecond portion 210 b is positioned at only one side of thefirst portion 210 a of the patternedphotoresist mask 208. Accordingly, as shown inFIG. 8B , only one lightly-doped-drain (LDD)region 224 b can be formed after the steps of etching thegate dielectric layer 206 and implanting ions. - Alternatively, referring to
FIG. 9A , thegate dielectric layer 206 positioned over thepolysilicon layer 204 can be formed from twolayers layers gate dielectric layer 206, thegate dielectric layer 207 b not covered by the patternedphotoresist layer 208 is partially etched until thegate dielectric layer 207 a is exposed, as shown inFIG. 9B . - The thin film transistor as shown in
FIGS. 10, 11 and 12 can be fabricated employing the above first and second embodiments. The thin film transistor includes asubstrate 500, apolysilicon layer 502, a patternedgate dielectric layer 504, agate layer 506, achannel region 514, asource region 508 a, adrain region 508 b and lightly-doped-drain (LDD)regions - The
polysilicon layer 502 is positioned over thesubstrate 500. The patternedgate dielectric layer 504 is positioned over thepolysilicon layer 502. The patternedgate dielectric layer 504 has athird portion 512 a and afourth portion 512 b, wherein thefourth portion 512 b is positioned at two sides of thethird portion 512 a and has a thickness smaller than that of thethird portion 512 a. - The
gate layer 506 is positioned over thethird portion 512 a of the patternedgate dielectric layer 504. Thesource region 508 a and thedrain region 508 b are positioned in thepolysilicon layer 502 under thefourth portion 512 b of the patternedgate dielectric layer 504. Thechannel region 514 is positioned in thepolysilicon layer 502 under thegate layer 506. The lightly-doped-drain (LDD)regions polysilicon layer 502 under thethird portion 504 of the patternedgate dielectric layer 504 between thechannel region 514 and thesource region 508 a and between thechannel region 514 and thedrain region 508 b. - The thin film transistor further includes a
dielectric layer 516, a sourceconductive layer 518 a and a drainconductive layer 518 b. Thedielectric layer 516 covers thegate layer 506 and the patternedgate dielectric layer 504. The sourceconductive layer 518 a and the drainconductive layer 518 b are deposited over thedielectric layer 516 and pass through thedielectric layer 516 and the patternedgate dielectric layer 504 for electrically connecting with thesource region 508 a and thedrain region 508 b, respectively. - Alternatively, the thin film transistor further includes a
buffer layer 520 positioned between thesubstrate 500 and thepolysilicon layer 502. - Referring to
FIG. 10 , the lightly-doped-drain (LDD)region 510 a positioned between thechannel region 514 and thesource region 508 a has a width w3 equivalent to the width w4 of the lightly-doped-drain (LDD)region 510 b positioned between thechannel region 514 and thedrain region 508 b. Alternatively, referring toFIG. 11 , the width w3 of the lightly-doped-drain (LDD)region 510 a positioned between thechannel region 514 and thesource region 508 a is different from the width w4 of the lightly-doped-drain (LDD)region 510 b positioned between thechannel region 514 and thedrain region 508 b. Alternatively, referring toFIG. 12 , one of the lightly-doped-drain (LDD)region channel region 514 and thesource region 508 a or between thechannel region 514 and thedrain region 508 b. - According to the above method of the present invention, only one step of the ion implanting process is performed to produce a source region, a drain region and lightly-doped-drain (LDD) regions with different dopant concentrations due to a patterned gate dielectric layer having different thicknesses. The patterned gate dielectric layer is formed by a single step of the photolithography process and then by a single step of the etching process. The photolithography process is performed to produce a patterned photoresist mask with different thicknesses by means of a mask having a semi-transparent region. Therefore, the method of the present invention is easier than the conventional method. In addition, leakage current and hot carrier effect can be effectively improved by forming lightly-doped-drain (LDD) regions having a same width or different widths.
- In the following embodiment, the explanation for the elements having the same reference numbers recited in the above embodiments will be skipped.
-
FIGS. 13A-13D are schematic cross-sectional views of a thin film transistor showing the steps for fabricating a thin film transistor according to a third embodiment of the present invention. - Referring to
FIG. 13A , apolysilicon layer 204, agate dielectric layer 206 and agate layer 226 are sequentially formed over asubstrate 200. Alternatively, abuffer layer 202 can be formed over thesubstrate 200 before forming thepolysilicon layer 204. - A patterned
photoresist mask 208 having afirst portion 210 a and asecond portion 210 b is formed over thegate layer 226. Thesecond portion 210 b is positioned at two sides of thefirst portion 210 a and has a thickness smaller than that of thefirst portion 210 a. The process of forming the patternedphotoresist mask 208 over thegate layer 226 can be referred to the above discussion for the second embodiment, and the detailed explanation is omitted herein. - Referring to 13B, the
gate layer 226 a is patterned using an etching process with the patternedphotoresist mask 208 acting as an etching mask. The patternedgate layer 226 a has afifth portion 300 a and asixth portion 300 b, wherein thesixth portion 300 b is positioned at two sides of thefifth portion 300 a and has a thickness smaller than that of thefifth portion 300 a. The process of forming thepatterned gate layer 226 a can be referred to the discussion of the above second embodiment, and the concerning explanation is omitted herein. - An ion implanting process for doping a
source region 220 a and adrain region 220 b in thepolysilicon layer 204 is performed with the patternedphotoresist mask 208, the patternedgate layer 226 a and thegate dielectric layer 206 acting as a doping mask. - In one embodiment, under the condition that n-
type dopants 600 such as phosphorous atoms are doped with a dopant concentration ranging from 1*1014 to 1*1016 atoms per square centimeter for fabricating a n-type thin film transistor, the ion implanting process may provide a doping energy of 70 to 80 keV, for example. - Thereafter, the
sixth portion 300 b of the patternedgate layer 226 a is removed using an etching process. Another ion implanting process for doping thesource region 220 a, thedrain region 220 b and lightly-doped-drain (LDD)regions polysilicon layer 204 is performed with the remaining patternedphotoresist mask 208 and the remaining patternedgate layer 226 c acting as a doping mask. Achannel region 222 is configured in thepolysilicon layer 204 under the remaining patternedgate layer 226 c, wherein the lightly-doped-drain (LDD)regions channel region 222 and thesource region 220 a and between thechannel region 222 and thedrain region 220 b. - In another embodiment, under the condition that n-
type dopants 602 such as phosphorous atoms are doped with a dopant concentration ranging from 1*1013 to 1*1015 atoms per square centimeter for fabricating a n-type thin film transistor, the ion implanting process may provide a doping energy of 70 to 80 keV, for example. - Thereafter, as shown in
FIG. 13D , the patternedphotoresist mask 208 is removed. In one embodiment, removing the patternedphotoresist layer 208 is conducted after forming thepatterned gate layer 226 and before performingion implantation process 600. In another embodiment, after removing the patterned photoresist layer, a drain conductive layer and a source conductive layer are formed. The detail will be described in the following. After the patternedphotoresist mask 208 is removed, adielectric layer 228 is formed over thesubstrate 200 and covers thegate layer 226 and the patternedgate dielectric layer 206 a. A source plug opening 230 a and adrain plug opening 230 b are formed passing through thedielectric layer 228 and the patternedgate dielectric layer 206 a and exposing thesource region 220 a and thedrain region 220 b. Afterwards, a conductive layer including a sourceconductive layer 232 a and a drainconductive layer 232 b is formed over thedielectric layer 228 and in the source plug opening 230 a and thedrain plug opening 230 b. The sourceconductive layer 232 a is electrically connected to thesource region 220 a. The drainconductive layer 232 b is electrically connected to thedrain region 220 b. - The widths w1 and w2 of the
second portion 210 b at two sides of thefirst portion 210 a of the patternedphotoresist mask 208 are equivalent as shown inFIG. 13A , but, alternatively, they can be different in practice. Referring toFIG. 14A , the widths w1 and w2 of thesecond portion 210 b at two sides of thefirst portion 210 a of the patternedphotoresist mask 208 are different. Therefore, as shown inFIG. 14B , asymmetric lightly-doped-drain (LDD)regions gate dielectric layer 206 and implanting ions. Besides, referring toFIG. 15A , thesecond portion 210 b is positioned at only one side of thefirst portion 210 a of the patternedphotoresist mask 208. Accordingly, as shown inFIG. 15B , only one lightly-doped-drain (LDD)region 224 b can be formed after the steps of etching thegate dielectric layer 206 and implanting ions. - According to the above method of the present invention, the source region/drain region and the lightly-doped-drain (LDD) regions are formed by performing only one step of the photolithography process. Therefore, the above method is more efficient than the conventional method. In addition, leakage current and hot carrier effect can be effectively improved by forming lightly-doped-drain (LDD) regions having a same width or different widths.
- The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.
Claims (5)
1. A thin film transistor, comprising:
a substrate;
a polysilicon layer disposed over said substrate;
a patterned gate dielectric layer disposed over the polysilicon layer, said patterned gate dielectric layer having a third portion and a fourth portion, wherein said fourth portion has a thickness smaller than that of said third portion;
a gate layer positioned over said third portion of said patterned gate dielectric layer;
a source region configured in said polysilicon layer under said fourth portion of said patterned gate dielectric layer;
a drain region configured in said polysilicon layer under said fourth portion of said patterned gate dielectric layer;
a channel region configured in said polysilicon layer under said gate layer; and
a lightly-doped-drain (LDD) region configured in said polysilicon layer under said third portion of said patterned gate dielectric layer, and between said channel region and said source region or between said channel region and said drain region.
2. The transistor of claim 1 , wherein said lightly-doped-drain (LDD) region is configured between said channel region and said source region and between said channel region and said drain region, and said lightly-doped-drain (LDD) region formed between said channel region and said source region has a same width as said lightly-doped-drain (LDD) region formed between said channel region and said drain region.
3. The transistor of claim 1 , wherein said lightly-doped-drain (LDD) region is positioned between said channel region and said source region and between said channel region and said drain region, and said lightly-doped-drain (LDD) region formed between said channel region and said source region has a width different from that of said lightly-doped-drain (LDD) region formed between said channel region and said drain region.
4. The transistor of claim 1 , further comprising:
a dielectric layer covering said gate layer and said patterned gate dielectric layer;
a source conductive layer positioned over said dielectric layer and passing through said dielectric layer and said patterned gate dielectric layer, said source conductive layer electrically connecting with said source region; and
a drain conductive layer positioned over said dielectric layer and passing through said dielectric layer and said patterned gate dielectric layer, said drain conductive layer electrically connecting with said drain region.
5. The transistor of claim 1 , further comprising a buffer layer positioned between said substrate and said polysilicon layer.
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US11/306,898 US20060199337A1 (en) | 2005-02-01 | 2006-01-16 | Thin film transistor |
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US10/906,041 US7041540B1 (en) | 2005-02-01 | 2005-02-01 | Thin film transistor and method for fabricating the same |
US11/306,898 US20060199337A1 (en) | 2005-02-01 | 2006-01-16 | Thin film transistor |
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US20100006847A1 (en) * | 2008-07-10 | 2010-01-14 | Au Optronics Corporation | Semiconductor device, display apparatus, photo-electrical apparatus, and method for fabricating the same |
US20160254368A1 (en) * | 2014-04-25 | 2016-09-01 | Boe Technology Group Co., Ltd. | Poly-silicon thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device |
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