US20060199368A1 - Interconnect arrangement and associated production methods - Google Patents
Interconnect arrangement and associated production methods Download PDFInfo
- Publication number
- US20060199368A1 US20060199368A1 US11/362,269 US36226906A US2006199368A1 US 20060199368 A1 US20060199368 A1 US 20060199368A1 US 36226906 A US36226906 A US 36226906A US 2006199368 A1 US2006199368 A1 US 2006199368A1
- Authority
- US
- United States
- Prior art keywords
- interconnect
- layer
- sacrificial layer
- mount substrate
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to an interconnect arrangement and to associated production methods, and in particular to an interconnect arrangement with improved electrical characteristics as can be used as a bit line in a DRAM memory cell.
- interconnect arrangements are used to form wiring for semiconductor components.
- a dielectric layer or insulating layer is normally formed on an electrically conductive mount substrate, such as a semiconductor substrate, and an electrically conductive interconnect layer is formed on this dielectric layer, with the interconnect layer representing the final interconnect, after structuring. Further insulating layers and electrically conductive layers are then formed successively, thus resulting in a layer stack which allows even complex wiring structures.
- the electrical characteristics of the interconnect arrangement in this case depend primarily on the materials used and in particular on the electrical conductivity of the interconnects, as well on parasitic capacitances per area section or length section of the interconnect.
- FIG. 12 shows a simplified equivalent circuit of a conventional DRAM memory cell in which a storage capacitor CS is connected via a selection transistor AT to a bit line BL.
- the storage capacitor CS can be a trench capacitor or an MIM (metal-insulator-metal) capacitor.
- the selection transistor AT can be actuated via a word line WL such that the charge or information stored in the storage capacitor CS can be read via the bit line BL.
- the electrical characteristics of the bit line are determined primarily by their length 1 and the conductivity per unit length, and the parasitic capacitance CP per unit length and/or unit area. As shown in FIG.
- the parasitic capacitance CP is charged and discharged with the charge stored in the storage capacitor CS of the memory cell.
- the parasitic capacitance of the bit line as well as a parasitic line resistance (which is not illustrated) is minimized. To achieve this minimization, the length of the bit lines is optimized.
- U.S. Pat. No. 5,461,003 filed on May 27, 1994 and issued on Oct. 24, 1995 discloses an interconnect arrangement in which air gaps or non-conductive gases or a vacuum are/is used to reduce the capacitive coupling between adjacent interconnects.
- a porous dielectric covering layer was used for the removal of a sacrificial layer used for the air gap, while at the same time ensuring sufficient mechanical robustness.
- further improvements in the electrical characteristics are obtained.
- FIGS. 1A-1C to FIGS. 5A-5C show simplified section views and plan views to illustrate fabrication of an interconnect arrangement according to a first exemplary embodiment
- FIGS. 6A-6C to FIGS. 10A-10B show simplified section views and plan views to illustrate fabrication of an interconnect arrangement according to a second exemplary embodiment
- FIG. 11 shows a simplified plan view of an interconnect arrangement according to a third exemplary embodiment.
- An interconnect arrangement and method are disclosed in which a cavity is located at least underneath the interconnect and thus between the interconnect and the mount substrate. This makes it possible to reduce parasitic interconnect/substrate capacitances in semiconductor components such as semiconductor memory cells.
- the cavity may be bounded by a porous dielectric layer, which at the same time adheres to the interconnect and thus holds it, thus preventing the interconnect from falling or dropping down onto the mount substrate.
- this mounting option which may be regarded as suspension of the interconnects, can also be provided by means of a supporting structure. In this case, the dielectric supporting elements, which support the interconnect from underneath, are formed in the cavity.
- the interconnect may have a contact via and/or a dummy contact via which lead/leads from the interconnect to the substrate surface and either makes or make electrical contact with or connects or connect to the substrate, or else touch or touches it and are or is not electrically connected to it.
- Contacts and/or additionally inserted dummy contacts which are present may be used as further supporting structures for the interconnect, thus reliably preventing the interconnect from falling down onto the mount substrate and a short-circuit being formed between the interconnect and the mount substrate.
- the interconnect may have a barrier layer to prevent interconnect material from diffusing into the mount substrate.
- a residual decomposition layer can also be formed in the cavity on the surface of the mount substrate, which can be used in the same way as the barrier layer and is produced, as a byproduct during removal of the sacrificial layer for the cavity.
- a sacrificial layer is formed on an electrically conductive mount substrate to provide suspension for the interconnects, an interconnect layer is formed on the sacrificial layer, and is structured together with the sacrificial layer.
- a porous dielectric layer is then formed over the entire surface, and the sacrificial layer is removed to form a cavity underneath the interconnect.
- a polymer which is thermally stabilized up to about 300-400 degrees Celsius is applied as the sacrificial layer, with thermal conversion being carried out at temperatures from 300 to 600 degrees Celsius for removal of the sacrificial layer allowing the gaseous decomposition products created to escape through the porous layer.
- a support for interconnects supporting structures are formed on a mount substrate, a sacrificial layer is then formed over the entire surface and is planarized as far as the surface of the supporting structure to form an interconnect layer on the planarized surface, and to structure it. Finally, the sacrificial layer is removed to form a cavity at least underneath the interconnect, and a closed dielectric covering layer is formed above the interconnects.
- the interconnects are not mounted or suspended from above but are supported from underneath by means of a large number of supporting elements or pillars.
- the supporting elements may be arranged in straight lines or essentially at right angles to the interconnect, or may contain individual islands over which the interconnects pass.
- FIGS. 1A to 5 C show simplified section views and plan views that illustrate method steps in the production of an interconnect arrangement according to a first exemplary embodiment.
- the interconnects are held from above or at the sides by suspension.
- FIGS. C show plan views, with FIGS. A and B each showing the associated section views along a section A-A and B-B from the associated FIG. C.
- a sacrificial layer 2 is formed on a mount substrate 1 which, for example, represents a semiconductor substrate.
- the semiconductor substrate can be formed from, for example, monocrystalline silicon.
- the sacrificial layer 2 may have openings 0 that extend as far as the mount substrate 1 to provide subsequent contacts.
- a material which is thermally stable up to about 300-400 degrees Celsius e.g. a polymer
- Polyamides such as Parylene or Teflon may be used for this high-temperature-resistant polymer. These polyamides may be, for example, centrifuged on or deposited by CVD.
- an optional barrier layer 3 can then be formed on the surface of the sacrificial layer 2 and/or within the opening O and on the surface of the mount substrate 1 as well, to prevent interconnect material that will be formed later from diffusing into the mount substrate 1 .
- a TiN layer can be deposited for the optional barrier layer 3 by means of a sputtering method such as PVD (physical vapor deposition). If a barrier layer such as this has been formed, an interconnect layer 4 is then formed over the entire surface, that is to say either directly on the structured sacrificial layer 2 or on the barrier layer 3 .
- a tungsten CVD (chemical vapor deposition) method can be used to form an electrically conductive tungsten layer 4 , which at the same time also provides a contact via to the mount substrate within the opening O.
- the sacrificial layer 2 may have good temperature stability up to at least 300 degrees Celsius. Polyimide, which is thermally stable up to about 450 degrees Celsius, is thus suitable for the sacrificial layer 2 .
- a barrier layer is first of all formed on the surface of the sacrificial layer 2 by means of a sputtering method.
- a plug that is composed of copper, for example, is then produced as a contact via V electrochemically in the opening O.
- An aluminum layer is then deposited over the entire surface, for example by means of a PVD method, and is structured.
- a PVD/electrochemical method such as this, the thermal stability of the sacrificial layer 2 can be considerably less stringent so that it is also possible to use materials which are thermally stable up to only 100 degrees Celsius for the sacrificial layer 2 .
- the interconnect layer which comprises the barrier layer 3 and the tungsten layer 4 is structured together with the sacrificial layer 2 in a subsequent step, thus resulting in the actual shape and structure of the interconnect.
- Isotropic etching RIE, reactive ion etching
- both single-step and two-step etching processes may be used.
- the same ion etching process may be used for the sacrificial layer 2 as for the formation of the opening O in FIG. 1A . This results in the interconnects being straight lines or strips as illustrated in FIG.
- the contact vias V may, of course, be located at points which are covered by the interconnects.
- the width of the contact vias V may be less than the width of the interconnects.
- the interconnects can also be produced in the same way by means of a damascene or dual damascene process.
- respective interconnect depressions or channels are formed in addition to the sacrificial layer 2 in an SiO 2 layer, which is not illustrated but is located on the surface of the sacrificial layer, and depressions or channels are then filled with interconnect material, and planarized.
- Thin barrier and seed layers may be deposited by means of a PVD method, with a copper layer being then deposited by means of an ECD (electrochemical deposition) method, and being planarized by means of a CMP method.
- a porous dielectric layer 5 A is formed on the surface of the mount substrate 1 and of the structured sacrificial layer 2 , as well as the interconnect comprising the layer 4 and the optional barrier layer 3 .
- the porous dielectric is deposited, completely fills the gaps between the interconnects and at the same time reliably covers the interconnects.
- the characteristics of this porous dielectric may be chosen such that a good adhesion capability is provided with the interconnect, for example the tungsten layer 4 and the barrier layer 3 , to allow an adequate adhesion force for the interconnect during the subsequent removal of the sacrificial layer 2 .
- Porous SiO 2 may be deposited over the entire surface as the porous dielectric layer, although silicon-dioxide based xerogels can also be centrifuged on, by means of spin-on methods.
- the pores or openings in this porous dielectric layer 5 A may be of such a size that the decomposition products can be reliably dissipated during a subsequent decomposition step.
- the sacrificial layer 2 is now removed to form a cavity 6 underneath the interconnect or the barrier layer 3 .
- thermal conversion may be carried out on the sacrificial layer 2 , with the gaseous decomposition products of the sacrificial layer 2 escaping through the porous layer 5 A, and thus creating an air gap or the cavity 6 .
- polyimide is used as the sacrificial layer 2
- the entire layer stack is heated to a temperature of more than 450 degrees Celsius, thus resulting in the polymer or the sacrificial layer 2 being burnt away, and the combustion gases escaping through the porous dielectric 5 A.
- temperature step exceeds 600 degrees Celsius, however, in producing semiconductor circuits, doped junctions (pn) formed in the semiconductor material can be damaged. If other materials are used as the sacrificial layer 2 , heat treatment may even be sufficient in a temperature range from 300 to 600 degrees Celsius.
- the surrounding atmosphere may be air or pure oxygen, for example.
- the sacrificial layer 2 can also be dissolved by means of an acid plasma or hydrogen plasma, and can be dissipated via the pores of the porous dielectric 5 A.
- the air gap or cavity 6 that is created underneath the interconnect does not present any problems since the mechanical robustness is sufficiently ensured by the adhesion or holding forces of the porous layer 5 A which is in contact at the sides and on the surface of the interconnect. This results in a dielectric for the parasitic area capacitance between the interconnect and the substrate 1 .
- solid residual decomposition products are also deposited or precipitated on the surface of the mount substrate 1 within the cavity 6 as a residual decomposition layer 7 .
- a diffusion barrier layer can be produced automatically to protect the mount substrate 1 and, for example, a semiconductor substrate. The electrical characteristics of the semiconductor circuit thus remain uninfluenced, while the electrical characteristics of the interconnect are considerably improved, e.g. with respect to the parasitic capacitance.
- DRAM memory cells can be provided which have greatly improved electrical characteristics in which the size of the storage capacitors CS can be considerably reduced. The integration density is thus considerably increased.
- FIGS. 6A to 10 D show simplified section views and plan views in order to illustrate method steps in the production of an interconnect arrangement according to a second exemplary embodiment, with provision being made for the interconnect to be supported essentially from underneath.
- a supporting structure 10 for a subsequent interconnect is formed on the mount substrate 1 according to the second exemplary embodiment.
- dielectric supporting elements are arranged in the form of strips or lines on the surface of the mount substrate 1 , and are covered with a sacrificial layer 2 .
- the dielectric supporting structure is produced by deposition of a non-porous SiO 2 layer that is subsequently structured.
- anisotropic dry etching processes can be used for structuring, although wet etching processes can also be used.
- the SiO 2 material being used for the dielectric supporting structure 10 it is also possible to use low-k materials (materials whose dielectric constant k is considerably less than that of silicon dioxide).
- the k value of the dielectric constant of silicon dioxide is about 3.9, and is used as a reference value for classification of low-k and high-k materials.
- Si 3 N 4 can alternatively be used for the supporting structure 10 as well.
- SiO 2 can be used for the sacrificial layer 2 , with RF etching being carried out in a subsequent removal step to remove the sacrificial layer 2 . Since Si 3 N 4 and SiO 2 are available in every standard process, this results in a simple implementation.
- the second exemplary embodiment will also be described in the following text for a polymer of the sacrificial layer 2 and for SiO 2 as the supporting structure 10 .
- the sacrificial layer 2 is planarized to expose a surface of the supporting structure 10 .
- the polymer 2 may be polished back to the upper edge of the supporting structure 10 by means of a CMP method.
- any contact openings O are formed at this time, as in the exemplary embodiment 1 by etching of the sacrificial layer 2 as far as the mount substrate 1 .
- an interconnect layer 4 is now once again formed on the planarized surface (on the surface of the sacrificial layer 2 and of the supporting structure 10 ).
- a contact via V or else a dummy contact via can once again be provided within the contact opening O as in the first exemplary embodiment.
- the contact vias V allow electrical contact with the mount substrate 1 , while no electrical contact is produced in the dummy contact vias, for example because of an insulating base layer (which is not illustrated) between the interconnect 4 and the mount substrate 1 .
- the interconnect layer that comprises, for example, the tungsten layer 4 and the barrier layer 3 is also structured, thus resulting in the normal interconnects in the form of straight lines and strips.
- the interconnects may be arranged essentially at right angles to the supporting structure 10 , thus making it possible to produce a very simple design.
- the supporting structures can also be arranged at any desired angle to the interconnects.
- the interconnects can also be formed by means of a damascene or dual-damascene process.
- an SiO 2 layer is once again formed on the surface of the sacrificial layer 2 , with the subsequent interconnect lines being produced by means of trenches in this SiO 2 layer.
- thin barrier and seed layers can once again be deposited by means of a PVD method, with a copper layer being deposited on this by means of an ECD method, and being planarized by means of a CMP method.
- the sacrificial layer 2 may remain complete, for example, during this etching process. However, it can also be partially removed, as in FIG. 3B .
- the sacrificial layer 2 is then completely removed to form a cavity 6 , which is virtually complete except for the supporting elements 10 and covers at least the entire plane underneath the interconnect or interconnects 3 , 4 .
- thermal conversion can once again be carried out, with the polymer being chemically converted or burnt away at temperatures of 300 to 600 degrees Celsius.
- a residual decomposition layer 7 can also be formed on the surface of the mount substrate 1 , if desired as a further barrier layer to prevent materials from diffusing from the interconnect into the semiconductor material.
- the open arrangement in the second exemplary embodiment means that, as an alternative to this thermal conversion or to the use of the alternatively described oxygen or hydrogen plasmas, it is also possible to use conventional isotropic etching processes such as an RF wet etching process, in which case Si 3 N 4 can also be used as the supporting structure 10 and SiO 2 as the sacrificial layer 2 .
- the materials for the barrier layer 3 and the actual interconnect layer 4 can be chosen appropriately such that no on-etching is carried out during this removal of the sacrificial layer 2 .
- isotropic plasma etching can alternatively be carried out, by which means the sacrificial layer 2 is completely removed. In consequence, the interconnects are supported or borne from underneath only by the supporting structure 10 and, possibly, by the contact vias V or optional dummy contact vias.
- a closed dielectric covering layer 5 B is formed above the interconnect 3 , 4 in a final step.
- a non-porous dielectric for example SiO 2
- the interconnects are only partially covered by dielectric on their side surfaces, so that a side cavity 6 A can also be produced in an advantageous manner between adjacent interconnects.
- this results in the greatest possible reduction in the parasitic capacitances both with respect to the mount substrate 1 and with respect to adjacent interconnects, since not only does the entire plane below the-interconnects contain a cavity 6 , and is thus filled with air or a non-conductive gas or a vacuum, but a cavity 6 A with an optimum k value of k 1 is also produced, at least partially, at the side alongside the interconnects.
- the supporting structure 10 and the contact vias V are sufficiently mechanically robust to allow further metallization levels in subsequent layers.
- FIG. 11 shows a simplified plan view of an interconnect arrangement according to a third exemplary embodiment in which the supporting structure is essentially in the form of islands.
- rectangular supporting elements 10 A project beyond the interconnect width at the sides or, as square supporting elements 10 B, also have a narrower width than the interconnect width. This embodiment results in a further slight improvement in the parasitic capacitances.
- This cavity can run in the form of a tunnel just underneath the interconnects, or can occupy the entire plane underneath the interconnects, or may even extend laterally between the interconnects.
- the storage capacitors CS shown in this figure can be considerably reduced, and the electrical characteristics, such as the read speeds, can be considerably increased.
- the invention has been explained above with reference to selected materials. However, it is not restricted to these materials and in the same way also covers other alternative materials which are used for production of the cavities in conjunction with the holding and supporting elements. Furthermore, combinations of the exemplary embodiments mentioned above are also possible, with the use of porous materials for the covering layer 5 B also being mentioned.
- the present invention is not restricted just to interconnect arrangements in the field of semiconductor technology, but in the same way covers all other interconnect and conductor track arrangements, for example in printed circuits etc., in which the electrical characteristics of the interconnects and conductor tracks and the parasitic capacitances are important.
Abstract
An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect.
Description
- This application claims priority to German
Patent Application DE 10 2005 008 476.1, filed on Feb. 24, 2005, which is incorporated by reference in their entirety. - The present invention relates to an interconnect arrangement and to associated production methods, and in particular to an interconnect arrangement with improved electrical characteristics as can be used as a bit line in a DRAM memory cell.
- In semiconductor technology, interconnect arrangements are used to form wiring for semiconductor components. In this case, a dielectric layer or insulating layer is normally formed on an electrically conductive mount substrate, such as a semiconductor substrate, and an electrically conductive interconnect layer is formed on this dielectric layer, with the interconnect layer representing the final interconnect, after structuring. Further insulating layers and electrically conductive layers are then formed successively, thus resulting in a layer stack which allows even complex wiring structures.
- The electrical characteristics of the interconnect arrangement in this case depend primarily on the materials used and in particular on the electrical conductivity of the interconnects, as well on parasitic capacitances per area section or length section of the interconnect.
- Particularly in semiconductor memory cells such as DRAM memory cells, stored information is transported via a bit line to an evaluation circuit.
FIG. 12 shows a simplified equivalent circuit of a conventional DRAM memory cell in which a storage capacitor CS is connected via a selection transistor AT to a bit line BL. The storage capacitor CS can be a trench capacitor or an MIM (metal-insulator-metal) capacitor. The selection transistor AT can be actuated via a word line WL such that the charge or information stored in the storage capacitor CS can be read via the bit line BL. The electrical characteristics of the bit line are determined primarily by theirlength 1 and the conductivity per unit length, and the parasitic capacitance CP per unit length and/or unit area. As shown inFIG. 12 , the parasitic capacitance CP is charged and discharged with the charge stored in the storage capacitor CS of the memory cell. To attenuate the original signal as little as possible, the parasitic capacitance of the bit line as well as a parasitic line resistance (which is not illustrated) is minimized. To achieve this minimization, the length of the bit lines is optimized. - U.S. Pat. No. 5,461,003 filed on May 27, 1994 and issued on Oct. 24, 1995 discloses an interconnect arrangement in which air gaps or non-conductive gases or a vacuum are/is used to reduce the capacitive coupling between adjacent interconnects. In this case, a porous dielectric covering layer was used for the removal of a sacrificial layer used for the air gap, while at the same time ensuring sufficient mechanical robustness. However, further improvements in the electrical characteristics are obtained.
- The present invention is illustrated by way of example and not limited to the accompanying figures in which like references indicate similar elements. Exemplary embodiments will be explained in the following text with reference to the attached drawings, in which:
-
FIGS. 1A-1C toFIGS. 5A-5C show simplified section views and plan views to illustrate fabrication of an interconnect arrangement according to a first exemplary embodiment; -
FIGS. 6A-6C toFIGS. 10A-10B show simplified section views and plan views to illustrate fabrication of an interconnect arrangement according to a second exemplary embodiment; and -
FIG. 11 shows a simplified plan view of an interconnect arrangement according to a third exemplary embodiment. - Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
- An interconnect arrangement and method are disclosed in which a cavity is located at least underneath the interconnect and thus between the interconnect and the mount substrate. This makes it possible to reduce parasitic interconnect/substrate capacitances in semiconductor components such as semiconductor memory cells. The cavity may be bounded by a porous dielectric layer, which at the same time adheres to the interconnect and thus holds it, thus preventing the interconnect from falling or dropping down onto the mount substrate. Alternatively, this mounting option, which may be regarded as suspension of the interconnects, can also be provided by means of a supporting structure. In this case, the dielectric supporting elements, which support the interconnect from underneath, are formed in the cavity.
- The interconnect may have a contact via and/or a dummy contact via which lead/leads from the interconnect to the substrate surface and either makes or make electrical contact with or connects or connect to the substrate, or else touch or touches it and are or is not electrically connected to it. Contacts and/or additionally inserted dummy contacts which are present may be used as further supporting structures for the interconnect, thus reliably preventing the interconnect from falling down onto the mount substrate and a short-circuit being formed between the interconnect and the mount substrate.
- The interconnect may have a barrier layer to prevent interconnect material from diffusing into the mount substrate. In a similar way, a residual decomposition layer can also be formed in the cavity on the surface of the mount substrate, which can be used in the same way as the barrier layer and is produced, as a byproduct during removal of the sacrificial layer for the cavity.
- With regard to the production method, a sacrificial layer is formed on an electrically conductive mount substrate to provide suspension for the interconnects, an interconnect layer is formed on the sacrificial layer, and is structured together with the sacrificial layer. A porous dielectric layer is then formed over the entire surface, and the sacrificial layer is removed to form a cavity underneath the interconnect. This method makes it possible to also produce cavities underneath the interconnects.
- A polymer which is thermally stabilized up to about 300-400 degrees Celsius is applied as the sacrificial layer, with thermal conversion being carried out at temperatures from 300 to 600 degrees Celsius for removal of the sacrificial layer allowing the gaseous decomposition products created to escape through the porous layer.
- With regard to the alternative production method for provision of a support for interconnects, supporting structures are formed on a mount substrate, a sacrificial layer is then formed over the entire surface and is planarized as far as the surface of the supporting structure to form an interconnect layer on the planarized surface, and to structure it. Finally, the sacrificial layer is removed to form a cavity at least underneath the interconnect, and a closed dielectric covering layer is formed above the interconnects. In consequence, in this alternative, the interconnects are not mounted or suspended from above but are supported from underneath by means of a large number of supporting elements or pillars. The supporting elements may be arranged in straight lines or essentially at right angles to the interconnect, or may contain individual islands over which the interconnects pass.
- Turning to the figures,
FIGS. 1A to 5C show simplified section views and plan views that illustrate method steps in the production of an interconnect arrangement according to a first exemplary embodiment. In this embodiment, the interconnects are held from above or at the sides by suspension. Each of the FIGS. C show plan views, with FIGS. A and B each showing the associated section views along a section A-A and B-B from the associated FIG. C. - According to
FIGS. 1A to 1C, asacrificial layer 2 is formed on amount substrate 1 which, for example, represents a semiconductor substrate. The semiconductor substrate can be formed from, for example, monocrystalline silicon. Thesacrificial layer 2 may haveopenings 0 that extend as far as themount substrate 1 to provide subsequent contacts. By way of example, a material which is thermally stable up to about 300-400 degrees Celsius (e.g. a polymer) may be applied as thesacrificial layer 2. Polyamides such as Parylene or Teflon may be used for this high-temperature-resistant polymer. These polyamides may be, for example, centrifuged on or deposited by CVD. - As can be seen from
FIGS. 2A to 2C, anoptional barrier layer 3 can then be formed on the surface of thesacrificial layer 2 and/or within the opening O and on the surface of themount substrate 1 as well, to prevent interconnect material that will be formed later from diffusing into themount substrate 1. By way of example, a TiN layer can be deposited for theoptional barrier layer 3 by means of a sputtering method such as PVD (physical vapor deposition). If a barrier layer such as this has been formed, aninterconnect layer 4 is then formed over the entire surface, that is to say either directly on the structuredsacrificial layer 2 or on thebarrier layer 3. By way of example, a tungsten CVD (chemical vapor deposition) method can be used to form an electricallyconductive tungsten layer 4, which at the same time also provides a contact via to the mount substrate within the opening O. In metal deposition such as this, thesacrificial layer 2 may have good temperature stability up to at least 300 degrees Celsius. Polyimide, which is thermally stable up to about 450 degrees Celsius, is thus suitable for thesacrificial layer 2. - Alternative methods for formation of the interconnect layer or of the interconnects, such as electroplating methods, are also feasible. In this case, by way of example, a barrier layer is first of all formed on the surface of the
sacrificial layer 2 by means of a sputtering method. A plug that is composed of copper, for example, is then produced as a contact via V electrochemically in the opening O. An aluminum layer is then deposited over the entire surface, for example by means of a PVD method, and is structured. For a PVD/electrochemical method such as this, the thermal stability of thesacrificial layer 2 can be considerably less stringent so that it is also possible to use materials which are thermally stable up to only 100 degrees Celsius for thesacrificial layer 2. - As shown in
FIGS. 3A to 3C, the interconnect layer which comprises thebarrier layer 3 and thetungsten layer 4 is structured together with thesacrificial layer 2 in a subsequent step, thus resulting in the actual shape and structure of the interconnect. Isotropic etching (RIE, reactive ion etching) can be used. In this case, both single-step and two-step etching processes may be used. In two-step etching processes, the same ion etching process may be used for thesacrificial layer 2 as for the formation of the opening O inFIG. 1A . This results in the interconnects being straight lines or strips as illustrated inFIG. 3 , with thesacrificial layer 2 remaining only underneath the interconnects, and with the material otherwise being completely removed as far as the surface of themount substrate 1. The contact vias V may, of course, be located at points which are covered by the interconnects. The width of the contact vias V may be less than the width of the interconnects. - Although a subtractive structuring method for structuring of the interconnects has been proposed above, the interconnects can also be produced in the same way by means of a damascene or dual damascene process. In this case, respective interconnect depressions or channels are formed in addition to the
sacrificial layer 2 in an SiO2 layer, which is not illustrated but is located on the surface of the sacrificial layer, and depressions or channels are then filled with interconnect material, and planarized. Thin barrier and seed layers may be deposited by means of a PVD method, with a copper layer being then deposited by means of an ECD (electrochemical deposition) method, and being planarized by means of a CMP method. Once the SiO2 layer has been etched away and the polymer layer has been structured, during which process a metal web is used as a mask, this results in the same structure as inFIGS. 3A to 3C. - As shown in
FIGS. 4A to 4C, aporous dielectric layer 5A is formed on the surface of themount substrate 1 and of the structuredsacrificial layer 2, as well as the interconnect comprising thelayer 4 and theoptional barrier layer 3. The porous dielectric is deposited, completely fills the gaps between the interconnects and at the same time reliably covers the interconnects. The characteristics of this porous dielectric may be chosen such that a good adhesion capability is provided with the interconnect, for example thetungsten layer 4 and thebarrier layer 3, to allow an adequate adhesion force for the interconnect during the subsequent removal of thesacrificial layer 2. - Porous SiO2 may be deposited over the entire surface as the porous dielectric layer, although silicon-dioxide based xerogels can also be centrifuged on, by means of spin-on methods. The pores or openings in this
porous dielectric layer 5A may be of such a size that the decomposition products can be reliably dissipated during a subsequent decomposition step. - As shown in
FIGS. 5A to 5C, thesacrificial layer 2 is now removed to form acavity 6 underneath the interconnect or thebarrier layer 3. In this case, thermal conversion may be carried out on thesacrificial layer 2, with the gaseous decomposition products of thesacrificial layer 2 escaping through theporous layer 5A, and thus creating an air gap or thecavity 6. When polyimide is used as thesacrificial layer 2, the entire layer stack is heated to a temperature of more than 450 degrees Celsius, thus resulting in the polymer or thesacrificial layer 2 being burnt away, and the combustion gases escaping through theporous dielectric 5A. If temperature step exceeds 600 degrees Celsius, however, in producing semiconductor circuits, doped junctions (pn) formed in the semiconductor material can be damaged. If other materials are used as thesacrificial layer 2, heat treatment may even be sufficient in a temperature range from 300 to 600 degrees Celsius. The surrounding atmosphere may be air or pure oxygen, for example. - Alternatively, the
sacrificial layer 2 can also be dissolved by means of an acid plasma or hydrogen plasma, and can be dissipated via the pores of theporous dielectric 5A. The air gap orcavity 6 that is created underneath the interconnect does not present any problems since the mechanical robustness is sufficiently ensured by the adhesion or holding forces of theporous layer 5A which is in contact at the sides and on the surface of the interconnect. This results in a dielectric for the parasitic area capacitance between the interconnect and thesubstrate 1. - Furthermore, during this chemical conversion of the
sacrificial layer 2 into gaseous decomposition products, solid residual decomposition products are also deposited or precipitated on the surface of themount substrate 1 within thecavity 6 as aresidual decomposition layer 7. In this case, if suitable materials are used, a diffusion barrier layer can be produced automatically to protect themount substrate 1 and, for example, a semiconductor substrate. The electrical characteristics of the semiconductor circuit thus remain uninfluenced, while the electrical characteristics of the interconnect are considerably improved, e.g. with respect to the parasitic capacitance. - When a bit line BL as is illustrated in
FIG. 12 is provided, DRAM memory cells can be provided which have greatly improved electrical characteristics in which the size of the storage capacitors CS can be considerably reduced. The integration density is thus considerably increased. -
FIGS. 6A to 10D show simplified section views and plan views in order to illustrate method steps in the production of an interconnect arrangement according to a second exemplary embodiment, with provision being made for the interconnect to be supported essentially from underneath. - Although in the first exemplary embodiment described above, it has been possible to considerably improve the parasitic capacitances formed between the interconnects and the electrically
conductive mount substrate 1, undesirable parasitic capacitances can still be observed. This results from the areas which are located obliquely underneath the interconnect. Parasitic capacitances such as these which are located at an angle to the interconnect downwards towards themount substrate 1 have theporous layer 5A as the dielectric. The dielectric constant is approximately k=3.9 when using silicon dioxide. - According to the second exemplary embodiment, a cavity is formed not just immediately underneath the interconnect but an entire plane underneath the interconnect is defined as a cavity, thus resulting in the optimum dielectric constant of k=1 for all parasitic substrate capacitances.
- In the description of the following second exemplary embodiment, in which the interconnects are supported from underneath (the support passes through from the mount substrate and virtually the entire plane below the interconnect plane is defined as a cavity), the same reference symbols denote identical or similar layers and elements as in FIGS. 1 to 5, so that they will not be described again in the following text.
- As shown in
FIGS. 6A to 6C, a supportingstructure 10 for a subsequent interconnect is formed on themount substrate 1 according to the second exemplary embodiment. For example, dielectric supporting elements are arranged in the form of strips or lines on the surface of themount substrate 1, and are covered with asacrificial layer 2. The dielectric supporting structure is produced by deposition of a non-porous SiO2 layer that is subsequently structured. In this case, anisotropic dry etching processes can be used for structuring, although wet etching processes can also be used. As an alternative to the SiO2 material being used for thedielectric supporting structure 10, it is also possible to use low-k materials (materials whose dielectric constant k is considerably less than that of silicon dioxide). The k value of the dielectric constant of silicon dioxide is about 3.9, and is used as a reference value for classification of low-k and high-k materials. - Although the materials mentioned above, such as temperature-resistant polyimide, may be used for the
sacrificial layer 2, Si3N4 can alternatively be used for the supportingstructure 10 as well. SiO2 can be used for thesacrificial layer 2, with RF etching being carried out in a subsequent removal step to remove thesacrificial layer 2. Since Si3N4 and SiO2 are available in every standard process, this results in a simple implementation. The second exemplary embodiment will also be described in the following text for a polymer of thesacrificial layer 2 and for SiO2 as the supportingstructure 10. - As shown in
FIGS. 7A to 7C, thesacrificial layer 2 is planarized to expose a surface of the supportingstructure 10. Thepolymer 2 may be polished back to the upper edge of the supportingstructure 10 by means of a CMP method. Furthermore, any contact openings O are formed at this time, as in theexemplary embodiment 1 by etching of thesacrificial layer 2 as far as themount substrate 1. - As shown in
FIGS. 8A to 8C, aninterconnect layer 4, possibly with anoptional barrier layer 3, is now once again formed on the planarized surface (on the surface of thesacrificial layer 2 and of the supporting structure 10). In this case, a contact via V or else a dummy contact via can once again be provided within the contact opening O as in the first exemplary embodiment. The contact vias V allow electrical contact with themount substrate 1, while no electrical contact is produced in the dummy contact vias, for example because of an insulating base layer (which is not illustrated) between theinterconnect 4 and themount substrate 1. Once again, either the CVD methods described above for deposition of tungsten or the PVD/electrochemical method mentioned above is carried out, in which a copper plug is formed electrochemically in the contact via, with an aluminum layer being deposited above this by means of a sputtering method. The temperature requirements for thesacrificial layer 2 are correspondingly different for theexemplary embodiment 1. - Furthermore, as shown in
FIGS. 8A to 8C, the interconnect layer that comprises, for example, thetungsten layer 4 and thebarrier layer 3 is also structured, thus resulting in the normal interconnects in the form of straight lines and strips. When using a supporting structure in the form of straight lines and strips, the interconnects may be arranged essentially at right angles to the supportingstructure 10, thus making it possible to produce a very simple design. However, the supporting structures can also be arranged at any desired angle to the interconnects. - As in the case of the first exemplary embodiment, as an alternative to the subtractive structuring processes described above for production of the structured interconnects by means of photoresistive lacquer, exposure and subsequent etching, the interconnects can also be formed by means of a damascene or dual-damascene process. In this case, as shown in
FIGS. 7A to 7C after the planarization, an SiO2 layer is once again formed on the surface of thesacrificial layer 2, with the subsequent interconnect lines being produced by means of trenches in this SiO2 layer. As in the first exemplary embodiment, thin barrier and seed layers can once again be deposited by means of a PVD method, with a copper layer being deposited on this by means of an ECD method, and being planarized by means of a CMP method. - As is illustrated in
FIGS. 8A and 8B , thesacrificial layer 2 may remain complete, for example, during this etching process. However, it can also be partially removed, as inFIG. 3B . - As shown in
FIGS. 9A to 9C, thesacrificial layer 2 is then completely removed to form acavity 6, which is virtually complete except for the supportingelements 10 and covers at least the entire plane underneath the interconnect orinterconnects residual decomposition layer 7 can also be formed on the surface of themount substrate 1, if desired as a further barrier layer to prevent materials from diffusing from the interconnect into the semiconductor material. - The open arrangement in the second exemplary embodiment means that, as an alternative to this thermal conversion or to the use of the alternatively described oxygen or hydrogen plasmas, it is also possible to use conventional isotropic etching processes such as an RF wet etching process, in which case Si3N4 can also be used as the supporting
structure 10 and SiO2 as thesacrificial layer 2. The materials for thebarrier layer 3 and theactual interconnect layer 4 can be chosen appropriately such that no on-etching is carried out during this removal of thesacrificial layer 2. Furthermore, isotropic plasma etching can alternatively be carried out, by which means thesacrificial layer 2 is completely removed. In consequence, the interconnects are supported or borne from underneath only by the supportingstructure 10 and, possibly, by the contact vias V or optional dummy contact vias. - As shown in
FIGS. 10A and 10B , a closeddielectric covering layer 5B is formed above theinterconnect side cavity 6A can also be produced in an advantageous manner between adjacent interconnects. - In this second exemplary embodiment, this results in the greatest possible reduction in the parasitic capacitances both with respect to the
mount substrate 1 and with respect to adjacent interconnects, since not only does the entire plane below the-interconnects contain acavity 6, and is thus filled with air or a non-conductive gas or a vacuum, but acavity 6A with an optimum k value of k=1 is also produced, at least partially, at the side alongside the interconnects. In conjunction with thenon-conformal covering layer 5B, that is to say the layer with a different layer thickness, the supportingstructure 10 and the contact vias V are sufficiently mechanically robust to allow further metallization levels in subsequent layers. -
FIG. 11 shows a simplified plan view of an interconnect arrangement according to a third exemplary embodiment in which the supporting structure is essentially in the form of islands. In this case, rectangular supportingelements 10A project beyond the interconnect width at the sides or, as square supportingelements 10B, also have a narrower width than the interconnect width. This embodiment results in a further slight improvement in the parasitic capacitances. - This results in an interconnect arrangement in which the parasitic capacitances have been reduced to the greatest possible extent, with a cavity being formed at least immediately underneath the interconnect or between the interconnect and the mount substrate. This cavity can run in the form of a tunnel just underneath the interconnects, or can occupy the entire plane underneath the interconnects, or may even extend laterally between the interconnects.
- For example, when using an interconnect arrangement such as this as a bit line in a semiconductor memory cell as shown in
FIG. 12 , the storage capacitors CS shown in this figure can be considerably reduced, and the electrical characteristics, such as the read speeds, can be considerably increased. - The invention has been explained above with reference to selected materials. However, it is not restricted to these materials and in the same way also covers other alternative materials which are used for production of the cavities in conjunction with the holding and supporting elements. Furthermore, combinations of the exemplary embodiments mentioned above are also possible, with the use of porous materials for the
covering layer 5B also being mentioned. In the same way, the present invention is not restricted just to interconnect arrangements in the field of semiconductor technology, but in the same way covers all other interconnect and conductor track arrangements, for example in printed circuits etc., in which the electrical characteristics of the interconnects and conductor tracks and the parasitic capacitances are important. - It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention. Nor is anything in the foregoing description intended to disavow scope of the invention as claimed or any equivalents thereof.
Claims (25)
1. An interconnect arrangement comprising:
an electrically conductive mount substrate;
a dielectric layer formed on the mount substrate; and
an electrically conductive interconnect formed on the dielectric layer,
wherein at least a portion of the dielectric layer under the interconnect contains a cavity.
2. The interconnect arrangement of claim 1 , further comprising a porous dielectric layer that adheres to the interconnect and bounds the cavity.
3. The interconnect arrangement of claim 1 , wherein the interconnect comprises a contact via that leads from the interconnect to a surface of the substrate and electrically connects to the substrate.
4. The interconnect arrangement of claim 1 , wherein the interconnect comprises a dummy contact via that leads from the interconnect to a surface of the substrate and does not electrically connect to the substrate.
5. The interconnect arrangement of claim 1 , wherein the interconnect comprises a barrier layer that prevents interconnect material from diffusing into the mount substrate.
6. The interconnect arrangement of claim 1 , further comprising a residual decomposition layer formed in the cavity on a surface of the mount substrate.
7. An interconnect arrangement comprising:
an electrically conductive mount substrate;
a dielectric layer formed on the mount substrate;
an electrically conductive interconnect formed on the dielectric layer, at least a portion of the dielectric layer under the interconnect contains a cavity; and
dielectric supporting elements formed in the cavity on a surface of the mount substrate, the dielectric supporting elements support the interconnect.
8. The interconnect arrangement of claim 7 , further comprising a non-porous dielectric covering layer formed on the interconnect such that the cavity is also located to a side of the interconnect.
9. The interconnect arrangement of claim 7 , wherein the supporting elements are formed in a straight line and essentially at right angles to the interconnect.
10. The interconnect arrangement of claim 7 , wherein the supporting elements comprise islands.
11. A method for production of an interconnect arrangement, the method comprising:
a) forming a sacrificial layer on an electrically conductive mount substrate;
b) forming an interconnect layer on the sacrificial layer;
c) structuring the interconnect layer and the sacrificial layer to produce a structured interconnect on the structured sacrificial layer;
d) forming a porous dielectric layer on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer; and
e) removing the sacrificial layer to form a cavity under the interconnect.
12. The method of claim 11 , wherein, in a), an opening for a contact via or a dummy contact via is formed in the sacrificial layer.
13. The method of claim 11 , wherein, in a) to c), a damascene or dual damascene process is carried out.
14. The method of claim 11 , wherein, in e) thermal conversion of the sacrificial layer is carried out in a temperature range from 300 to 600 degrees Celsius, with the gaseous decomposition products escaping through the porous layer.
15. The method of claim 11 , wherein, in e), a residual decomposition layer is formed on the surface of the mount substrate.
16. A method for production of an interconnect arrangement, the method comprising:
a) forming a supporting structure on a mount substrate;
b) forming a sacrificial layer on a surface of the mount substrate and of the supporting structure;
c) planarizing the sacrificial layer to expose the surface of the supporting structure;
d) forming an interconnect layer on the surface of the sacrificial layer and of the supporting structure;
e) structuring the interconnect layer to produce a structured interconnect;
f) removing the sacrificial layer to form a cavity at least under the interconnect; and
g) forming a closed dielectric covering layer above the interconnect.
17. The method of claim 17 , wherein, after e), an opening for a contact via or a dummy contact via is formed in the sacrificial layer.
18. The method of claim 17 , wherein, in f), thermal conversion of the sacrificial layer is carried out in a temperature range from 300 to 600 degrees Celsius.
19. The method of claim 17 , wherein, in f), a residual decomposition layer is formed on the surface of the mount substrate.
20. The method of claim 17 , wherein, in a), the supporting structure is formed in a linear form or like islands.
21. An interconnect arrangement comprising:
an electrically conductive mount substrate;
means for insulating the mount substrate, at least a portion of the means comprising a cavity; and
means for electrically interconnecting elements formed on the insulating means.
22. The interconnect arrangement of claim 21 , further comprising porous means for bounding the cavity.
23. The interconnect arrangement of claim 21 , wherein the interconnect means comprises barrier means for preventing interconnect material from diffusing into the mount substrate during fabrication.
24. The interconnect arrangement of claim 21 , further comprising residual decomposition means for permitting gaseous decomposition products created during fabrication to escape from the interconnect arrangement.
25. The interconnect arrangement of claim 21 , further comprising support means for supporting the interconnect means.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/110,022 US8877631B2 (en) | 2005-02-24 | 2011-05-18 | Interconnect arrangement and associated production methods |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEDE102005008476.1 | 2005-02-24 | ||
DE102005008476A DE102005008476B4 (en) | 2005-02-24 | 2005-02-24 | Guideway arrangement and associated production method |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/110,022 Division US8877631B2 (en) | 2005-02-24 | 2011-05-18 | Interconnect arrangement and associated production methods |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060199368A1 true US20060199368A1 (en) | 2006-09-07 |
Family
ID=36914485
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/362,269 Abandoned US20060199368A1 (en) | 2005-02-24 | 2006-02-22 | Interconnect arrangement and associated production methods |
US13/110,022 Expired - Fee Related US8877631B2 (en) | 2005-02-24 | 2011-05-18 | Interconnect arrangement and associated production methods |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/110,022 Expired - Fee Related US8877631B2 (en) | 2005-02-24 | 2011-05-18 | Interconnect arrangement and associated production methods |
Country Status (3)
Country | Link |
---|---|
US (2) | US20060199368A1 (en) |
CN (1) | CN1832160B (en) |
DE (1) | DE102005008476B4 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8987907B2 (en) | 2012-03-15 | 2015-03-24 | Samsung Electronics Co., Ltd. | Semiconductor device |
CN111755602A (en) * | 2019-03-29 | 2020-10-09 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing the same |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5377066B2 (en) * | 2009-05-08 | 2013-12-25 | キヤノン株式会社 | Capacitive electromechanical transducer and method for producing the same |
US8535993B2 (en) * | 2010-09-17 | 2013-09-17 | Infineon Technologies Ag | Semiconductor device and method using a sacrificial layer |
US10593627B2 (en) * | 2015-06-25 | 2020-03-17 | Intel Corporation | Doric pillar supported maskless airgap structure for capacitance benefit with unlanded via solution |
US9853402B2 (en) * | 2015-09-30 | 2017-12-26 | Apple Inc. | Interconnect devices having a biplanar connection |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5461003A (en) * | 1994-05-27 | 1995-10-24 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
US5792706A (en) * | 1996-06-05 | 1998-08-11 | Advanced Micro Devices, Inc. | Interlevel dielectric with air gaps to reduce permitivity |
US6307263B1 (en) * | 1998-07-29 | 2001-10-23 | Siemens Aktiengesellschaft | Integrated semiconductor chip with modular dummy structures |
US6545361B2 (en) * | 1997-11-06 | 2003-04-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
US6737725B2 (en) * | 2000-08-31 | 2004-05-18 | International Business Machines Corporation | Multilevel interconnect structure containing air gaps and method for making |
US20040140506A1 (en) * | 2002-07-29 | 2004-07-22 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
US20040164419A1 (en) * | 2000-05-31 | 2004-08-26 | Micron Technology, Inc. | Multilevel copper interconnects with low-k dielectrics and air gaps |
US20040222533A1 (en) * | 2003-04-28 | 2004-11-11 | Naofumi Nakamura | Semiconductor device and method of manufacturing the same |
US20050179135A1 (en) * | 2002-10-31 | 2005-08-18 | Asm Japan K.K. | Semiconductor device having porous structure |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3074713B2 (en) * | 1990-09-18 | 2000-08-07 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JPH0722583A (en) * | 1992-12-15 | 1995-01-24 | Internatl Business Mach Corp <Ibm> | Multilayer circuit device |
DE4441898C1 (en) * | 1994-11-24 | 1996-04-04 | Siemens Ag | Semiconductor component with electrically conductive contacts and/or tracks |
US6815329B2 (en) * | 2000-02-08 | 2004-11-09 | International Business Machines Corporation | Multilayer interconnect structure containing air gaps and method for making |
US6699732B2 (en) * | 2002-04-17 | 2004-03-02 | Celerity Research Pte. Ltd. | Pitch compensation in flip-chip packaging |
US6867125B2 (en) * | 2002-09-26 | 2005-03-15 | Intel Corporation | Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material |
US7187081B2 (en) * | 2003-01-29 | 2007-03-06 | International Business Machines Corporation | Polycarbosilane buried etch stops in interconnect structures |
US7045452B2 (en) * | 2003-09-30 | 2006-05-16 | Intel Corporation | Circuit structures and methods of forming circuit structures with minimal dielectric constant layers |
KR100552856B1 (en) * | 2004-04-23 | 2006-02-22 | 동부아남반도체 주식회사 | Method of manufacturing semiconductor device |
-
2005
- 2005-02-24 DE DE102005008476A patent/DE102005008476B4/en not_active Expired - Fee Related
-
2006
- 2006-02-22 US US11/362,269 patent/US20060199368A1/en not_active Abandoned
- 2006-02-24 CN CN200610009576XA patent/CN1832160B/en not_active Expired - Fee Related
-
2011
- 2011-05-18 US US13/110,022 patent/US8877631B2/en not_active Expired - Fee Related
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5461003A (en) * | 1994-05-27 | 1995-10-24 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
US5792706A (en) * | 1996-06-05 | 1998-08-11 | Advanced Micro Devices, Inc. | Interlevel dielectric with air gaps to reduce permitivity |
US6545361B2 (en) * | 1997-11-06 | 2003-04-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having multilevel interconnection structure and method for fabricating the same |
US6307263B1 (en) * | 1998-07-29 | 2001-10-23 | Siemens Aktiengesellschaft | Integrated semiconductor chip with modular dummy structures |
US20040164419A1 (en) * | 2000-05-31 | 2004-08-26 | Micron Technology, Inc. | Multilevel copper interconnects with low-k dielectrics and air gaps |
US6737725B2 (en) * | 2000-08-31 | 2004-05-18 | International Business Machines Corporation | Multilevel interconnect structure containing air gaps and method for making |
US20040140506A1 (en) * | 2002-07-29 | 2004-07-22 | International Business Machines Corporation | Enhanced T-gate structure for modulation doped field effect transistors |
US20050179135A1 (en) * | 2002-10-31 | 2005-08-18 | Asm Japan K.K. | Semiconductor device having porous structure |
US20040222533A1 (en) * | 2003-04-28 | 2004-11-11 | Naofumi Nakamura | Semiconductor device and method of manufacturing the same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8987907B2 (en) | 2012-03-15 | 2015-03-24 | Samsung Electronics Co., Ltd. | Semiconductor device |
CN111755602A (en) * | 2019-03-29 | 2020-10-09 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing the same |
US11888018B2 (en) | 2019-03-29 | 2024-01-30 | SK Hynix Inc. | Semiconductor device and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US20110217839A1 (en) | 2011-09-08 |
US8877631B2 (en) | 2014-11-04 |
CN1832160A (en) | 2006-09-13 |
DE102005008476B4 (en) | 2006-12-21 |
CN1832160B (en) | 2010-06-02 |
DE102005008476A1 (en) | 2006-09-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8877631B2 (en) | Interconnect arrangement and associated production methods | |
EP1020905B1 (en) | Method for making integrated circuit device having dual damascene interconnect structure and metal electrode capacitor | |
KR100695026B1 (en) | Integrated circuit device having dual damascene capacitor and associated method for making | |
KR100643426B1 (en) | Tapered electrode for stacked capacitors | |
US7727837B2 (en) | Method of producing an integrated circuit having a capacitor with a supporting layer | |
TWI442512B (en) | An interconnect structure with dielectric air gaps | |
JPH0680737B2 (en) | Method for manufacturing semiconductor device | |
US6847077B2 (en) | Capacitor for a semiconductor device and method for fabrication therefor | |
KR100378771B1 (en) | Semi-sacrificial diamond for air dielectric formation | |
JP3296324B2 (en) | Method for manufacturing semiconductor memory device | |
US7199473B2 (en) | Integrated low-k hard mask | |
US8674404B2 (en) | Additional metal routing in semiconductor devices | |
US6100117A (en) | Method for manufacturing DRAM having a redundancy circuit region | |
CN101026122B (en) | Semiconductor device assembly and methods of manufacturing the same | |
US6686643B2 (en) | Substrate with at least two metal structures deposited thereon, and method for fabricating the same | |
US20080047118A1 (en) | Vertical parallel plate capacitor using spacer shaped electrodes and method for fabrication thereof | |
US7838381B2 (en) | Stud capacitor device and fabrication method | |
US6472740B1 (en) | Self-supporting air bridge interconnect structure for integrated circuits | |
US20040262638A1 (en) | Integrated circuit with dram memory cell | |
JP2000208743A (en) | Integrated circuit device provided with dual damascene capacitor and related method for manufacture | |
US6297121B1 (en) | Fabrication method for capacitors in integrated circuits with a self-aligned contact structure | |
CN109427649A (en) | Semiconductor structure and forming method thereof | |
KR100526458B1 (en) | Method for forming fuse in capacitor structure | |
KR100536625B1 (en) | Method for fabricating capacitor of semiconductor device | |
CN117425956A (en) | BEOL interconnect with improved isolation by subdivision of damascene conductors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ENGELHARDT, MANFRED;PAMLER, WERNER;SCHINDLER, GUENTHER;REEL/FRAME:017634/0924;SIGNING DATES FROM 20060407 TO 20060420 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |