US20060226114A1 - Method for producing a micromechanical device and a micromechanical device - Google Patents
Method for producing a micromechanical device and a micromechanical device Download PDFInfo
- Publication number
- US20060226114A1 US20060226114A1 US10/543,357 US54335703A US2006226114A1 US 20060226114 A1 US20060226114 A1 US 20060226114A1 US 54335703 A US54335703 A US 54335703A US 2006226114 A1 US2006226114 A1 US 2006226114A1
- Authority
- US
- United States
- Prior art keywords
- substrate material
- membrane layer
- membrane
- layer
- etching process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000012528 membrane Substances 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 58
- 239000000463 material Substances 0.000 claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 5
- 229910014263 BrF3 Inorganic materials 0.000 claims description 4
- 229910020323 ClF3 Inorganic materials 0.000 claims description 4
- FQFKTKUFHWNTBN-UHFFFAOYSA-N trifluoro-$l^{3}-bromane Chemical compound FBr(F)F FQFKTKUFHWNTBN-UHFFFAOYSA-N 0.000 claims description 4
- JOHWNGGYGAVMGU-UHFFFAOYSA-N trifluorochlorine Chemical compound FCl(F)F JOHWNGGYGAVMGU-UHFFFAOYSA-N 0.000 claims description 4
- 238000003631 wet chemical etching Methods 0.000 claims description 4
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims 2
- 229910018503 SF6 Inorganic materials 0.000 claims 2
- 229910017604 nitric acid Inorganic materials 0.000 claims 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 101
- 238000009413 insulation Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- DSHPMFUQGYAMRR-UHFFFAOYSA-N [Si].[Si].O=[Si] Chemical group [Si].[Si].O=[Si] DSHPMFUQGYAMRR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00047—Cavities
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
- B81C1/0069—Thermal properties, e.g. improve thermal insulation
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2203/00—Basic microelectromechanical structures
- B81B2203/01—Suspended structures, i.e. structures allowing a movement
- B81B2203/0127—Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0102—Surface micromachining
- B81C2201/0105—Sacrificial layer
- B81C2201/0109—Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
Definitions
- the present invention is directed to a method for producing a micromechanical device including a substrate and a membrane.
- a micromechanical device in which the components and the substrate material are thermally insulated from one another, the device being manufactured by a bulk micromechanical process, is described in an article by D. Moser and H. Baltes, “A high sensitivity CMOS gas flow sensor on a thin dielectric membrane,” and in the journal Sensors and Actuators A 37-38 (1993), pp. 33-37.
- a complex front- and back-side process is required for this method.
- the membrane needed for thermal insulation, on which temperature sensors and heaters are situated, for example, is produced via a bulk micromechanical process from the back side.
- the membrane is structured using a wet chemical etching process, for example, with the aid of KOH.
- the entire substrate must be etched in the area of the membrane starting from the back side, which results in long process times. Since wet chemical etching solutions attack the functional layers on the front side, the wafer must be embedded in an etching box to protect the front during the etching process. This conventional method involving the back-side process is therefore very complex and costly.
- the method and device according to the present invention have the advantage over the related art that a method in which only front-side processes are needed is provided for manufacturing the membranes.
- a surface micromechanical process (SMM) may therefore be used for the method and device according to the present invention.
- the method and device according to the present invention make it possible to provide thermal insulation between components on or in the membrane and the substrate material.
- Such components in or on the membrane may include temperature sensors and/or heating elements; however, any component whose manufacture is integratable in the manufacturing process of the device is possible and conceivable according to the present invention. Thermal insulation is needed in thermal sensors such as thermocouples, chemical sensors, and air mass sensors, for example.
- the method and device according to the present invention have the advantage over the related art that only surface micromechanical processes, i.e., only front-side processes, are needed for manufacturing the device.
- a surface micromechanical sacrificial layer method is used for producing the thermal insulation according to the present invention, and the method has high selectivity both with respect to thermally insulating materials such as oxides and nitrides and with respect to metals.
- Silicon may be used as the sacrificial layer in the method according to the present invention.
- the area of the sacrificial layer is initially deep structured according to the present invention via a first (anisotropic) etching step, e.g., a DRIE (deep reactive ion etching) process, and it is subsequently fully etched laterally in a second (isotropic) etching step using, e.g., a XeF 2 , ClF 3 , BrF 3 process in such a way that a cavity is formed underneath the membrane.
- a membrane cavity area i.e., the substrate area in which the membrane layer is unsupported and thus spans the cavity, is thus formed.
- the membrane layer includes a thermally poorly conductive material, for example, silicon oxide or silicon nitride.
- a thermally poorly conductive material for example, silicon oxide or silicon nitride.
- the combined sacrificial etching layer process of the present invention makes it possible to produce thick sacrificial layers.
- the compatibility of the etching media used in the sacrificial layer etching with the customary materials used in the standard CMOS processes makes it possible, according to the present invention, for the manufacture of the device according to the present invention and the manufacture of an integrated circuit (IC) using CMOS technology to be performed in an integrated manner, i.e., single manufacturing process (including a plurality of steps).
- the holes in the membrane are sealed after the second etching step, e.g., using a cover layer or a cap.
- a cover layer or a cap This makes it possible to protect the structures, for example, during a subsequent sawing process.
- a PECVD oxide layer or a spin-on glass layer or a combination of different layers is conceivable here as a sealing layer.
- a cap as a cover is also conceivable as a seal for the holes.
- a component to be thermally insulated from the substrate material is produced on or in the membrane before the first etching step.
- a silicon substrate or a SOI/EOI substrate (silicon-on-insulator/epipoly-on-insulator substrate), which may be monocrystalline, is provided as the substrate material.
- An SOI/EOI substrate according to the present invention is usable in an advantageous manner due to the fact that the oxide layer of the SOI/EOI substrate is used as a vertical etch stop during sacrificial layer etching, which makes it possible to set a defined sacrificial layer thickness.
- a SOI/EOI substrate is based on a layer structure in which an oxide layer and subsequently a silicon layer are applied to a monocrystalline silicon substrate.
- the method according to the present invention allows simple manufacture of a device according to the present invention, e.g., sensor elements, in which thermal insulation between temperature sensors and/or heating elements and the substrate material is needed. According to the present invention, only a few layers and photolitographic steps are needed for carrying out the method according to the present invention, so that the method is implementable in a simple and cost-effective manner.
- FIG. 1 shows a sectional view of a first example embodiment of the substrate material having a first part of a membrane layer.
- FIG. 2 shows a sectional view of the first embodiment of the substrate material having a first part of the membrane layer and a component integrated in the membrane layer.
- FIG. 3 shows a sectional view of the first embodiment of the substrate material having a membrane layer after a partially completed first etching step.
- FIG. 4 shows a sectional view of the first embodiment of the substrate material having a membrane layer after a completed first etching step.
- FIG. 5 shows a sectional view of the first embodiment of the substrate material having a membrane layer after completed first and second etching steps.
- FIGS. 6 and 7 show sectional views of the first embodiment of the substrate material having a membrane layer after completed first and second etching steps, including first and second example embodiments of a seal for the holes in the membrane, respectively.
- FIG. 8 shows a sectional view of a second example embodiment of the substrate material having a membrane layer after a completed first etching step.
- FIG. 9 shows a sectional view of the second embodiment of the substrate material having a membrane layer after completed first and second etching steps.
- FIG. 1 shows a sectional view of a first example embodiment of substrate material 10 having a first part 21 of a membrane layer.
- First part 21 of the membrane layer should be under tensile stress and have a certain thermal conductivity.
- first part 21 of the membrane layer includes a first partial membrane layer 22 , which is provided as an oxide layer, for example.
- first partial membrane layer 22 is produced, for example, as a thermal oxide layer or as a PECVD oxide layer.
- first part 21 of the membrane layer also includes a second partial membrane layer 24 , which is provided as a nitride layer, for example.
- Second partial membrane layer 24 is produced according to the present invention as a PECVD nitride layer or as an LPCVD nitride layer, for example.
- first part 21 of the membrane layer may be provided in the form of a layer system composed of oxide layers/nitride layers.
- the thicknesses of first and second partial membrane layers 22 , 24 are in the range of approximately 0.5 to 5 ⁇ m according to the present invention.
- substrate material 10 includes a semiconductor material 12 , e.g., a monocrystalline silicon material.
- FIG. 2 shows a sectional view of the first embodiment of substrate material 10 having a first part 21 of membrane layer 20 and a component, not identified with a particular reference symbol, integrated in membrane layer 20 .
- the component is provided as a thermocouple or temperature sensor, for example, but it may be any component integratable into or onto a membrane.
- the thermocouple has, for example, a platinum resistor or a Si/Al or Si/Ge thermopile.
- a structured layer provided as a polysilicon layer, for example, is applied to membrane 20 , which includes a first domain 201 and optionally a second domain 202 .
- First domain 201 forms a first resistor, which is also identified below with reference symbol 201 .
- First and second domains 201 , 202 may also be provided electrically fully insulated from one another, but structured from the same layer.
- an intermediate oxide layer 203 and a second resistor 204 made of aluminum or germanium according to the present invention are deposited and structured.
- a thermocouple composed of first and second resistors 201 , 204 results from the contact (not identified with a reference symbol) between first and second resistors 201 , 204 .
- a cover oxide layer 205 is deposited on the thermocouple and structured.
- Bond pads 206 or, in general, contact surfaces 206 , made, for example, of aluminum, are produced to contact the terminals of the thermocouple.
- membrane layer 20 including first part 21 of the membrane layer and the “structure” of the component—the thermocouple in the present embodiment—on first part 21 of the membrane layer.
- membrane layer 20 could also be designed in such a way that the component is provided underneath first and second partial membrane layers 22 , 24 , for example.
- substrate material 10 is situated “underneath” membrane layer 20 according to the present invention. This is provided in all the following figures in the same basic way and will therefore not be described repeatedly. The basic design of the component as a thermocouple, for example, is also maintained in the following figures; therefore it is not described repeatedly.
- FIG. 3 shows a sectional view of the first embodiment of substrate material 10 having a membrane layer 20 after a partially completed first etching step.
- vertical cutouts i.e., holes, are made in membrane layer 20 at certain perforation points, identified in FIG. 3 with arrows and reference numbers 28 , 29 .
- perforation points 28 and 29 are defined by photoresist mask 26 illustrated with the aid of dashed lines only in FIG. 3 in such a way that photoresist mask 26 covers the entire membrane layer 20 except perforation points 28 , 29 .
- holes 40 in membrane layer 20 using a wet chemical or dry chemical first etching step, i.e., to drive holes 40 through cover oxide layer 205 , intermediate oxide layer 203 , as well as first and second partial membrane layers 22 , 24 .
- the etching process for the first etching step is provided as an anisotropic process.
- Perforation points 28 , 29 and thus also holes 40 are located at points of membrane layer 20 at which no parts of the components located on or in membrane layer 20 may be damaged by the production of holes 40 .
- FIG. 4 shows a sectional view of the first embodiment of substrate material 10 having a membrane layer 20 after a completed first etching step.
- the difference with respect to FIG. 3 is only that the first etching step has been completed, i.e., holes 40 have been made to a certain depth 44 in substrate material 10 starting from holes 40 in membrane layer 20 at perforation points 28 , 29 (see the description of FIG. 3 ).
- an anisotropic etching process is used for deep patterning, a DRIE etching process, for example, as was used for the first part of the first etching step illustrated in FIG. 3 .
- Depth 44 is illustrated in FIG. 4 by a double arrow underneath first and second partial membrane layers 22 , 24 into substrate material 10 .
- holes 40 Depth 44 of holes 40 is between 2 ⁇ m and 200 ⁇ m underneath membrane layer 20 .
- the depth of the sacrificial layer etching process is defined by the deep patterning.
- Holes 40 which are referred to hereinafter as perforation holes 40 , may have a diameter between 0.5 ⁇ m and 500 ⁇ m.
- holes 40 may be smaller than 10 ⁇ m.
- Applications requiring a highly structured membrane e.g., thermal conductivity sensors for H 2 detection, sensors based on free convection flow for inclination measurement), may have holes 40 larger than 100 ⁇ m.
- FIG. 5 shows a sectional view of the first embodiment of substrate material 10 having a membrane layer 20 after completed first and second etching steps.
- the trench structure defined by holes 40 and not visible in the area of membrane layer 20 is etched laterally in the area of the sacrificial layer, i.e., underneath membrane 20 , using an isotropic semiconductor etching process as a second etching step. This is shown in FIG. 5 by four horizontal double arrows not provided with reference numbers.
- the access of the etching medium for the second etching step is illustrated in FIG. 5 by arrows 42 through holes 40 .
- the etching process may be carried out using a XeF 2 , ClF 3 or BrF 3 process, for example.
- a cavity 30 is thus formed in membrane cavity area 210 between membrane layer 20 and the unetched part of substrate material 10 , and unsupported membrane 20 over cavity 30 carrying or including the components is provided in the membrane area 21 .
- Cavity 30 has a depth 31 , which, according to the present invention, basically corresponds to depth 44 of the deep patterning of holes 40 underneath membrane layer 20 , illustrated in FIG. 4 .
- the thermocouples or generic components located on or in membrane 20 are thermally insulated from substrate material 10 by cavity 30 .
- FIGS. 6 and 7 show a sectional views of the first embodiment of substrate material 10 having a membrane layer 20 after a completed first and second etching steps, including first and second embodiments of a seal for the holes 40 in membrane 20 , respectively.
- FIG. 6 shows a first embodiment of a seal for the holes 40 as a sealing layer 50 .
- FIG. 7 shows a second embodiment of a seal for the holes 40 as a cap 52 .
- Components or other structures on or in membrane 20 are thus protected, for example, during a subsequent sawing process for separating a plurality of devices of the present invention manufactured jointly on a substrate wafer.
- Sealing layer 50 may be designed as a PECVD oxide or as spin-on glass.
- FIGS. 8 and 9 show sectional views of a second embodiment of substrate material 10 having a membrane layer 20 .
- the embodiment after the first completed etching step is illustrated in FIG. 8 .
- the embodiment after the first and second completed etching steps are illustrated in FIG. 9 .
- sequence of different layers are included in substrate material 10 , for example, a silicon-silicon oxide-silicon sequence.
- a (silicon) oxide layer 16 and then a silicon layer 15 are applied to a monocrystalline part 17 of substrate material 10 .
- Silicon layer 15 may be provided either as a monocrystalline silicon layer 15 or as an “epitaxially applied” polycrystalline silicon layer 15 (known as epi-poly silicon layer 15 ).
- substrate material 10 is referred to as an SOI material in the first case and as an EOI material in the second case.
- the steps of the manufacturing process are similar in the second embodiment of substrate material 10 to those described in FIGS. 1 through 7 .
- oxide layer 16 of substrate material 10 provides an etching stop when the first etching step is completed.
- holes 40 may not extend into substrate material 10 via the deep patterning method of the first etching step any deeper than to oxide layer 16 , i.e., going all the way through silicon layer 15 as the sacrificial layer. End point recognition of the first etching step is thus possible.
- Deep patterning of holes 40 beyond membrane layer 20 extends over depth 44 into substrate 10 , which corresponds to the layer thickness of silicon layer 15 .
- depth 31 of cavity 30 corresponds to the thickness of silicon layer 15 of the substrate material.
Abstract
A method for manufacturing a micromechanical device and a resulting micromechanical device are provided, the device having a substrate material, a membrane, and a cavity situated between the substrate and the membrane in a membrane cavity area. In this method, holes are first produced through the membrane in a first etching step, and the cavity is subsequently produced using a second etching step.
Description
- The present invention is directed to a method for producing a micromechanical device including a substrate and a membrane.
- A micromechanical device in which the components and the substrate material are thermally insulated from one another, the device being manufactured by a bulk micromechanical process, is described in an article by D. Moser and H. Baltes, “A high sensitivity CMOS gas flow sensor on a thin dielectric membrane,” and in the journal Sensors and Actuators A 37-38 (1993), pp. 33-37. A complex front- and back-side process is required for this method. The membrane needed for thermal insulation, on which temperature sensors and heaters are situated, for example, is produced via a bulk micromechanical process from the back side. The membrane is structured using a wet chemical etching process, for example, with the aid of KOH. In doing so, the entire substrate must be etched in the area of the membrane starting from the back side, which results in long process times. Since wet chemical etching solutions attack the functional layers on the front side, the wafer must be embedded in an etching box to protect the front during the etching process. This conventional method involving the back-side process is therefore very complex and costly.
- The method and device according to the present invention have the advantage over the related art that a method in which only front-side processes are needed is provided for manufacturing the membranes. A surface micromechanical process (SMM) may therefore be used for the method and device according to the present invention. Furthermore, the method and device according to the present invention make it possible to provide thermal insulation between components on or in the membrane and the substrate material. Such components in or on the membrane may include temperature sensors and/or heating elements; however, any component whose manufacture is integratable in the manufacturing process of the device is possible and conceivable according to the present invention. Thermal insulation is needed in thermal sensors such as thermocouples, chemical sensors, and air mass sensors, for example. The method and device according to the present invention have the advantage over the related art that only surface micromechanical processes, i.e., only front-side processes, are needed for manufacturing the device. This makes complex back-side processes such as KOH etching using an etching box for structuring the membrane unnecessary. Particles and scratches on the front of the wafer are minimized or avoided due to the omission of the back-side processes in which the wafer must be turned over and deposited on the front side. A surface micromechanical sacrificial layer method is used for producing the thermal insulation according to the present invention, and the method has high selectivity both with respect to thermally insulating materials such as oxides and nitrides and with respect to metals. Silicon may be used as the sacrificial layer in the method according to the present invention. The area of the sacrificial layer is initially deep structured according to the present invention via a first (anisotropic) etching step, e.g., a DRIE (deep reactive ion etching) process, and it is subsequently fully etched laterally in a second (isotropic) etching step using, e.g., a XeF2, ClF3, BrF3 process in such a way that a cavity is formed underneath the membrane. A membrane cavity area, i.e., the substrate area in which the membrane layer is unsupported and thus spans the cavity, is thus formed. According to the present invention, the membrane layer includes a thermally poorly conductive material, for example, silicon oxide or silicon nitride. The combined sacrificial etching layer process of the present invention makes it possible to produce thick sacrificial layers. The compatibility of the etching media used in the sacrificial layer etching with the customary materials used in the standard CMOS processes makes it possible, according to the present invention, for the manufacture of the device according to the present invention and the manufacture of an integrated circuit (IC) using CMOS technology to be performed in an integrated manner, i.e., single manufacturing process (including a plurality of steps).
- It is advantageous that the holes in the membrane are sealed after the second etching step, e.g., using a cover layer or a cap. This makes it possible to protect the structures, for example, during a subsequent sawing process. According to the present invention, a PECVD oxide layer or a spin-on glass layer or a combination of different layers is conceivable here as a sealing layer. A cap as a cover is also conceivable as a seal for the holes. It is furthermore advantageous that a component to be thermally insulated from the substrate material is produced on or in the membrane before the first etching step. As a result, no further steps for producing a component are needed after the second etching step, and thus no problems occur due to the fact that, for example, after the two etching steps there are holes in the membrane into which the material to be applied to the membrane may penetrate and the material may attack or damage the membrane from its back side. It is furthermore advantageous that the membrane is well insulated from the substrate material. This is achieved according to the present invention by a relatively great depth of the cavity which is provided in the membrane area over the substrate material. This results, via different heat transport mechanisms, in reduced heat transport from the membrane to the substrate material and thus good thermal insulation. It is furthermore advantageous that a silicon substrate or a SOI/EOI substrate (silicon-on-insulator/epipoly-on-insulator substrate), which may be monocrystalline, is provided as the substrate material. An SOI/EOI substrate according to the present invention is usable in an advantageous manner due to the fact that the oxide layer of the SOI/EOI substrate is used as a vertical etch stop during sacrificial layer etching, which makes it possible to set a defined sacrificial layer thickness. A SOI/EOI substrate is based on a layer structure in which an oxide layer and subsequently a silicon layer are applied to a monocrystalline silicon substrate.
- All in all, the method according to the present invention allows simple manufacture of a device according to the present invention, e.g., sensor elements, in which thermal insulation between temperature sensors and/or heating elements and the substrate material is needed. According to the present invention, only a few layers and photolitographic steps are needed for carrying out the method according to the present invention, so that the method is implementable in a simple and cost-effective manner.
-
FIG. 1 shows a sectional view of a first example embodiment of the substrate material having a first part of a membrane layer. -
FIG. 2 shows a sectional view of the first embodiment of the substrate material having a first part of the membrane layer and a component integrated in the membrane layer. -
FIG. 3 shows a sectional view of the first embodiment of the substrate material having a membrane layer after a partially completed first etching step. -
FIG. 4 shows a sectional view of the first embodiment of the substrate material having a membrane layer after a completed first etching step. -
FIG. 5 shows a sectional view of the first embodiment of the substrate material having a membrane layer after completed first and second etching steps. -
FIGS. 6 and 7 show sectional views of the first embodiment of the substrate material having a membrane layer after completed first and second etching steps, including first and second example embodiments of a seal for the holes in the membrane, respectively. -
FIG. 8 shows a sectional view of a second example embodiment of the substrate material having a membrane layer after a completed first etching step. -
FIG. 9 shows a sectional view of the second embodiment of the substrate material having a membrane layer after completed first and second etching steps. -
FIG. 1 shows a sectional view of a first example embodiment ofsubstrate material 10 having afirst part 21 of a membrane layer.First part 21 of the membrane layer should be under tensile stress and have a certain thermal conductivity. According to the present invention,first part 21 of the membrane layer includes a firstpartial membrane layer 22, which is provided as an oxide layer, for example. According to the present invention, firstpartial membrane layer 22 is produced, for example, as a thermal oxide layer or as a PECVD oxide layer. According to the present invention,first part 21 of the membrane layer also includes a secondpartial membrane layer 24, which is provided as a nitride layer, for example. Secondpartial membrane layer 24 is produced according to the present invention as a PECVD nitride layer or as an LPCVD nitride layer, for example. However, in other example embodiments (not shown) of the present invention,first part 21 of the membrane layer may be provided in the form of a layer system composed of oxide layers/nitride layers. The thicknesses of first and secondpartial membrane layers substrate material 10 includes asemiconductor material 12,e.g., a monocrystalline silicon material. -
FIG. 2 shows a sectional view of the first embodiment ofsubstrate material 10 having afirst part 21 ofmembrane layer 20 and a component, not identified with a particular reference symbol, integrated inmembrane layer 20. According to the present invention, the component is provided as a thermocouple or temperature sensor, for example, but it may be any component integratable into or onto a membrane. The thermocouple has, for example, a platinum resistor or a Si/Al or Si/Ge thermopile. To manufacture a thermopile as a thermocouple, a structured layer, provided as a polysilicon layer, for example, is applied tomembrane 20, which includes afirst domain 201 and optionally asecond domain 202.First domain 201 forms a first resistor, which is also identified below withreference symbol 201. First andsecond domains first resistor 201, anintermediate oxide layer 203 and asecond resistor 204 made of aluminum or germanium according to the present invention are deposited and structured. A thermocouple composed of first andsecond resistors second resistors cover oxide layer 205 is deposited on the thermocouple and structured.Bond pads 206 or, in general, contact surfaces 206, made, for example, of aluminum, are produced to contact the terminals of the thermocouple. This results inmembrane layer 20 includingfirst part 21 of the membrane layer and the “structure” of the component—the thermocouple in the present embodiment—onfirst part 21 of the membrane layer. In another embodiment of the present invention (not illustrated), however,membrane layer 20 could also be designed in such a way that the component is provided underneath first and second partial membrane layers 22, 24, for example. In any case,substrate material 10 is situated “underneath”membrane layer 20 according to the present invention. This is provided in all the following figures in the same basic way and will therefore not be described repeatedly. The basic design of the component as a thermocouple, for example, is also maintained in the following figures; therefore it is not described repeatedly. -
FIG. 3 shows a sectional view of the first embodiment ofsubstrate material 10 having amembrane layer 20 after a partially completed first etching step. To produce the cavity according to the present invention, vertical cutouts, i.e., holes, are made inmembrane layer 20 at certain perforation points, identified inFIG. 3 with arrows andreference numbers photoresist mask 26 illustrated with the aid of dashed lines only inFIG. 3 in such a way that photoresistmask 26 covers theentire membrane layer 20 except perforation points 28, 29. Subsequently, it is possible to produceholes 40 inmembrane layer 20 using a wet chemical or dry chemical first etching step, i.e., to driveholes 40 throughcover oxide layer 205,intermediate oxide layer 203, as well as first and second partial membrane layers 22, 24. For this purpose, the etching process for the first etching step is provided as an anisotropic process. Perforation points 28, 29 and thus also holes 40 are located at points ofmembrane layer 20 at which no parts of the components located on or inmembrane layer 20 may be damaged by the production ofholes 40. Therefore only one area ofsubstrate 10 is provided as a sacrificial layer “underneath” aperforation point dimensional membrane layer 29. This is clearly visible for perforation points 28, because thecorresponding holes 40 do not intersect the first or second resistor of the thermocouples identified withreference numbers FIG. 2 . For perforation points denoted byreference numeral 29 this is illustrated by the side walls of the correspondingholes 40 illustrated using dotted lines. This should clarify the fact thatholes 40 for perforation points 29 are not in the section plane illustrated (in which first and second resistors of the thermocouple are located), but in another section plane in which the component is not affected by holes 40. -
FIG. 4 shows a sectional view of the first embodiment ofsubstrate material 10 having amembrane layer 20 after a completed first etching step. The difference with respect toFIG. 3 is only that the first etching step has been completed, i.e., holes 40 have been made to acertain depth 44 insubstrate material 10 starting fromholes 40 inmembrane layer 20 at perforation points 28, 29 (see the description ofFIG. 3 ). For this purpose, an anisotropic etching process is used for deep patterning, a DRIE etching process, for example, as was used for the first part of the first etching step illustrated inFIG. 3 .Depth 44 is illustrated inFIG. 4 by a double arrow underneath first and second partial membrane layers 22, 24 intosubstrate material 10.Depth 44 ofholes 40 is between 2 μm and 200 μm underneathmembrane layer 20. The depth of the sacrificial layer etching process is defined by the deep patterning.Holes 40, which are referred to hereinafter as perforation holes 40, may have a diameter between 0.5 μm and 500 μm. For applications in which the membrane should have asfew holes 40 as possible (e.g., infrared detectors or mass flow sensors), holes 40 may be smaller than 10 μm. Applications requiring a highly structured membrane (e.g., thermal conductivity sensors for H2 detection, sensors based on free convection flow for inclination measurement), may haveholes 40 larger than 100 μm. -
FIG. 5 shows a sectional view of the first embodiment ofsubstrate material 10 having amembrane layer 20 after completed first and second etching steps. Starting from the manufacturing stage of the device according to the present invention illustrated inFIG. 4 , the trench structure defined byholes 40 and not visible in the area ofmembrane layer 20 is etched laterally in the area of the sacrificial layer, i.e., underneathmembrane 20, using an isotropic semiconductor etching process as a second etching step. This is shown inFIG. 5 by four horizontal double arrows not provided with reference numbers. The access of the etching medium for the second etching step is illustrated inFIG. 5 byarrows 42 throughholes 40. The etching process may be carried out using a XeF2, ClF3 or BrF3 process, for example. Acavity 30 is thus formed inmembrane cavity area 210 betweenmembrane layer 20 and the unetched part ofsubstrate material 10, andunsupported membrane 20 overcavity 30 carrying or including the components is provided in themembrane area 21.Cavity 30 has adepth 31, which, according to the present invention, basically corresponds todepth 44 of the deep patterning ofholes 40 underneathmembrane layer 20, illustrated inFIG. 4 . The thermocouples or generic components located on or inmembrane 20 are thermally insulated fromsubstrate material 10 bycavity 30. -
FIGS. 6 and 7 show a sectional views of the first embodiment ofsubstrate material 10 having amembrane layer 20 after a completed first and second etching steps, including first and second embodiments of a seal for theholes 40 inmembrane 20, respectively.FIG. 6 shows a first embodiment of a seal for theholes 40 as asealing layer 50.FIG. 7 shows a second embodiment of a seal for theholes 40 as acap 52. Components or other structures on or inmembrane 20, are thus protected, for example, during a subsequent sawing process for separating a plurality of devices of the present invention manufactured jointly on a substrate wafer. Sealinglayer 50 may be designed as a PECVD oxide or as spin-on glass. -
FIGS. 8 and 9 show sectional views of a second embodiment ofsubstrate material 10 having amembrane layer 20. The embodiment after the first completed etching step is illustrated inFIG. 8 . The embodiment after the first and second completed etching steps are illustrated inFIG. 9 . In the second embodiment ofsubstrate material 10, sequence of different layers are included insubstrate material 10, for example, a silicon-silicon oxide-silicon sequence. In this case, for example, a (silicon)oxide layer 16 and then asilicon layer 15 are applied to amonocrystalline part 17 ofsubstrate material 10.Silicon layer 15 may be provided either as amonocrystalline silicon layer 15 or as an “epitaxially applied” polycrystalline silicon layer 15 (known as epi-poly silicon layer 15). Accordingly,substrate material 10 is referred to as an SOI material in the first case and as an EOI material in the second case. The steps of the manufacturing process, however, are similar in the second embodiment ofsubstrate material 10 to those described inFIGS. 1 through 7 . One difference is thatoxide layer 16 ofsubstrate material 10 provides an etching stop when the first etching step is completed. As a result, holes 40 may not extend intosubstrate material 10 via the deep patterning method of the first etching step any deeper than tooxide layer 16, i.e., going all the way throughsilicon layer 15 as the sacrificial layer. End point recognition of the first etching step is thus possible. Deep patterning ofholes 40 beyondmembrane layer 20 extends overdepth 44 intosubstrate 10, which corresponds to the layer thickness ofsilicon layer 15. Furthermore,depth 31 ofcavity 30 corresponds to the thickness ofsilicon layer 15 of the substrate material.
Claims (15)
1-12. (canceled)
13. A method for manufacturing a micromechanical device having a substrate material and a membrane layer provided on the substrate material, wherein a cavity is provided between the substrate material and the membrane layer in a membrane cavity area, comprising:
providing holes in the membrane layer via a first anisotropic etching process; and
providing the cavity via a second isotropic etching process.
14. The method as recited in claim 13 , wherein a portion of the substrate material is provided as a sacrificial layer, and wherein, in the first anisotropic etching process, the holes are provided to extend into the sacrificial layer.
15. The method as recited in claim 14 , wherein the method is CMOS-compatible.
16. The method as recited in claim 15 , wherein the first anisotropic etching process includes a deep reactive ion etching.
17. The method as recited in claim 15 , wherein the second isotropic etching process includes one of: a) use of one XeF2, ClF3, BrF3 and SF6 plasma; and b) a wet chemical etching using one of tetramethylammonium hydroxide, KOH, and a combination of HNO3 and HF.
18. The method as recited in claim 16 , further comprising:
sealing the holes in the membrane layer after the second isotropic etching process, using one of a cover layer placed directly on the membrane layer surface and a cover positioned over the membrane layer.
19. The method as recited in claim 18 , further comprising:
providing one of on and in the membrane layer, before the first anisotropic etching process, a component to be thermally insulated from the substrate material.
20. The method as recited in claim 17 , further comprising:
sealing the holes in the membrane layer after the second isotropic etching process, using one of a cover layer placed directly on the membrane layer surface and a cover positioned over the membrane layer.
21. The method as recited in claim 20 , further comprising:
providing one of on and in the membrane layer, before the first anisotropic etching process, a component to be thermally insulated from the substrate material.
22. A micromechanical device, comprising:
a substrate material; and
a membrane layer provided on the substrate material;
wherein a cavity is provided between the substrate material and the membrane layer in a membrane cavity area, the cavity being provided by producing holes via a first anisotropic etching process in the membrane layer and a portion of the substrate material provided as a sacrificial layer and subsequently performing a second isotropic etching process, and wherein the first anisotropic etching process includes a deep reactive ion etching, and wherein the second isotropic etching process includes one of: a) use of one XeF2, ClF3, BrF3 and SF6 plasma; and b) a wet chemical etching using one of tetramethylammonium hydroxide, KOH, and a combination of HNO3 and HF.
23. The device as recited in claim 22 , wherein the membrane layer is insulated thermally from the substrate material.
24. The device as recited in claim 23 , wherein the substrate material is one of a silicon substrate and a silicon-on-insulator substrate.
25. The device as recited in claim 24 , wherein the depth of the cavity substantially corresponds to the depth of the holes within the substrate material.
26. The device as recited in claim 24 , further comprising at least one thermally insulated component provided one of on and in the membrane layer.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10305442.1 | 2003-02-11 | ||
DE10305442A DE10305442A1 (en) | 2003-02-11 | 2003-02-11 | A process for preparation of a micromechanical device with a substrate, a membrane, and a hollow space by etching useful in electronics for thermal decoupling between structural elements and substrates |
PCT/DE2003/003194 WO2004071941A2 (en) | 2003-02-11 | 2003-09-25 | Method for producing a micromechanical device and a micromechanical device |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060226114A1 true US20060226114A1 (en) | 2006-10-12 |
Family
ID=32730954
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/543,357 Abandoned US20060226114A1 (en) | 2003-02-11 | 2003-09-25 | Method for producing a micromechanical device and a micromechanical device |
Country Status (5)
Country | Link |
---|---|
US (1) | US20060226114A1 (en) |
EP (1) | EP1594799A2 (en) |
JP (1) | JP2006513047A (en) |
DE (1) | DE10305442A1 (en) |
WO (1) | WO2004071941A2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070093045A1 (en) * | 2005-10-26 | 2007-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN102922067A (en) * | 2012-11-13 | 2013-02-13 | 天津大学 | Device for performing groove notching and machining on inside of hollow part |
CN103715065A (en) * | 2013-12-30 | 2014-04-09 | 国家电网公司 | SiC etching method for gentle and smooth side wall morphology |
TWI698392B (en) * | 2016-02-29 | 2020-07-11 | 德商羅伯特博斯奇股份有限公司 | Micromechanical sensor apparatus and corresponding production method |
DE102020214925A1 (en) | 2020-11-27 | 2022-06-02 | Robert Bosch Gesellschaft mit beschränkter Haftung | Method of fabricating a single cavity polysilicon SOI substrate |
US11708265B2 (en) | 2020-01-08 | 2023-07-25 | X-FAB Global Services GmbH | Method for manufacturing a membrane component and a membrane component |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10352001A1 (en) | 2003-11-07 | 2005-06-09 | Robert Bosch Gmbh | Micromechanical component with a membrane and method for producing such a component |
JP4422624B2 (en) * | 2004-03-03 | 2010-02-24 | 日本航空電子工業株式会社 | Micro movable device and manufacturing method thereof |
US7495302B2 (en) | 2004-03-03 | 2009-02-24 | Robert Bosch Gmbh | Micromechanical component having a diaphragm |
US7264986B2 (en) * | 2005-09-30 | 2007-09-04 | Freescale Semiconductor, Inc. | Microelectronic assembly and method for forming the same |
DE102013210512B4 (en) | 2013-06-06 | 2016-01-07 | Robert Bosch Gmbh | Sensor with membrane and manufacturing process |
DE102016217123B4 (en) | 2016-09-08 | 2019-04-18 | Robert Bosch Gmbh | Method for producing a micromechanical component and micromechanical component |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5464966A (en) * | 1992-10-26 | 1995-11-07 | The United States Of America As Represented By The Secretary Of Commerce | Micro-hotplate devices and methods for their fabrication |
US5481102A (en) * | 1994-03-31 | 1996-01-02 | Hazelrigg, Jr.; George A. | Micromechanical/microelectromechanical identification devices and methods of fabrication and encoding thereof |
US6359276B1 (en) * | 1998-10-21 | 2002-03-19 | Xiang Zheng Tu | Microbolom infrared sensors |
US6383889B2 (en) * | 1998-04-10 | 2002-05-07 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
US20020072163A1 (en) * | 2000-08-24 | 2002-06-13 | Ark-Chew Wong | Module and method of making same |
US20020151100A1 (en) * | 2000-12-15 | 2002-10-17 | Stmicroelectronics S.R.L. | Pressure sensor monolithically integrated and relative process of fabrication |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19752208A1 (en) * | 1997-11-25 | 1999-06-02 | Bosch Gmbh Robert | Thermal membrane sensor and method for its manufacture |
EP1130631A1 (en) * | 2000-02-29 | 2001-09-05 | STMicroelectronics S.r.l. | Process for forming a buried cavity in a semiconductor material wafer |
FR2817050A1 (en) * | 2001-03-07 | 2002-05-24 | Commissariat Energie Atomique | High transmission rate optical telecommunication switching network manufacture method having optical guide channel row/columns with optical switch each intersection manufactured metallisation /multilayered etching |
US6602791B2 (en) * | 2001-04-27 | 2003-08-05 | Dalsa Semiconductor Inc. | Manufacture of integrated fluidic devices |
-
2003
- 2003-02-11 DE DE10305442A patent/DE10305442A1/en not_active Withdrawn
- 2003-09-25 WO PCT/DE2003/003194 patent/WO2004071941A2/en active Application Filing
- 2003-09-25 JP JP2004568081A patent/JP2006513047A/en active Pending
- 2003-09-25 EP EP03815817A patent/EP1594799A2/en not_active Withdrawn
- 2003-09-25 US US10/543,357 patent/US20060226114A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5464966A (en) * | 1992-10-26 | 1995-11-07 | The United States Of America As Represented By The Secretary Of Commerce | Micro-hotplate devices and methods for their fabrication |
US5481102A (en) * | 1994-03-31 | 1996-01-02 | Hazelrigg, Jr.; George A. | Micromechanical/microelectromechanical identification devices and methods of fabrication and encoding thereof |
US6383889B2 (en) * | 1998-04-10 | 2002-05-07 | Nec Corporation | Semiconductor device having improved parasitic capacitance and mechanical strength |
US6359276B1 (en) * | 1998-10-21 | 2002-03-19 | Xiang Zheng Tu | Microbolom infrared sensors |
US20020072163A1 (en) * | 2000-08-24 | 2002-06-13 | Ark-Chew Wong | Module and method of making same |
US20020151100A1 (en) * | 2000-12-15 | 2002-10-17 | Stmicroelectronics S.R.L. | Pressure sensor monolithically integrated and relative process of fabrication |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070093045A1 (en) * | 2005-10-26 | 2007-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8043950B2 (en) * | 2005-10-26 | 2011-10-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8624336B2 (en) | 2005-10-26 | 2014-01-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN102922067A (en) * | 2012-11-13 | 2013-02-13 | 天津大学 | Device for performing groove notching and machining on inside of hollow part |
CN103715065A (en) * | 2013-12-30 | 2014-04-09 | 国家电网公司 | SiC etching method for gentle and smooth side wall morphology |
TWI698392B (en) * | 2016-02-29 | 2020-07-11 | 德商羅伯特博斯奇股份有限公司 | Micromechanical sensor apparatus and corresponding production method |
US11708265B2 (en) | 2020-01-08 | 2023-07-25 | X-FAB Global Services GmbH | Method for manufacturing a membrane component and a membrane component |
DE102020214925A1 (en) | 2020-11-27 | 2022-06-02 | Robert Bosch Gesellschaft mit beschränkter Haftung | Method of fabricating a single cavity polysilicon SOI substrate |
Also Published As
Publication number | Publication date |
---|---|
EP1594799A2 (en) | 2005-11-16 |
WO2004071941A3 (en) | 2004-12-23 |
WO2004071941A2 (en) | 2004-08-26 |
DE10305442A1 (en) | 2004-08-19 |
JP2006513047A (en) | 2006-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5907765A (en) | Method for forming a semiconductor sensor device | |
EP0822578B1 (en) | Method of fabricating integrated semiconductor devices comprising a chemoresistive gas microsensor | |
US8316718B2 (en) | MEMS pressure sensor device and method of fabricating same | |
US7148077B2 (en) | Micromechanical structural element having a diaphragm and method for producing such a structural element | |
EP1417151B1 (en) | Method for the fabrication of suspended porous silicon microstructures and application in gas sensors | |
JP4298807B2 (en) | Integrated piezoresistive pressure sensor and method of manufacturing the same | |
US7495302B2 (en) | Micromechanical component having a diaphragm | |
KR101080496B1 (en) | Micromechanical capacitive pressure transducer and production method | |
JP4376322B2 (en) | Method for manufacturing a semiconductor member | |
JPH05304303A (en) | Acceleration sensor and manufacture thereof | |
US20060226114A1 (en) | Method for producing a micromechanical device and a micromechanical device | |
JP2005246601A (en) | Micro-machining type component and suitable manufacturing method | |
US20040065638A1 (en) | Method of forming a sensor for detecting motion | |
US6761829B2 (en) | Method for fabricating an isolated microelectromechanical system (MEMS) device using an internal void | |
KR20170002947A (en) | Pressure sensor element and method for manufacturing same | |
US8759136B2 (en) | Method for creating monocrystalline piezoresistors | |
JPH11142270A (en) | Integrated piezoresistive pressure-sensor with diaphragm of polycrystalline semiconductor material and manufacture thereof | |
JP2000155030A (en) | Manufacture of angular velocity sensor | |
US6867061B2 (en) | Method for producing surface micromechanical structures, and sensor | |
JP2009139340A (en) | Pressure sensor, its manufacturing method, semiconductor device, and electronic apparatus | |
EP1846321B1 (en) | Method of fabricating a silicon-on-insulator structure | |
Yamamoto et al. | Capacitive accelerometer with high aspect ratio single crystalline silicon microstructure using the SOI structure with polysilicon-based interconnect technique | |
JPH11186566A (en) | Manufacture of fine device | |
JP2005098795A (en) | Sensor system having membrane and its manufacturing method | |
JP4175309B2 (en) | Semiconductor dynamic quantity sensor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ROBERT BOSCH GMBH, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FISCHER, FRANK;METZGER, LARS;REEL/FRAME:017797/0156 Effective date: 20050907 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |