US20060231522A1 - Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device - Google Patents
Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device Download PDFInfo
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- US20060231522A1 US20060231522A1 US11/451,965 US45196506A US2006231522A1 US 20060231522 A1 US20060231522 A1 US 20060231522A1 US 45196506 A US45196506 A US 45196506A US 2006231522 A1 US2006231522 A1 US 2006231522A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Definitions
- This invention relates to the field of semiconductor manufacture and, more particularly, to an etch useful for removing silicon nitride selective to silicon and silicon dioxide.
- Etching silicon nitride selective to silicon (such as polysilicon) and to silicon dioxide with various etch ratios is often required.
- hot phosphoric acid isotropically etches silicon nitride selective to silicon dioxide and silicon.
- Other processes for etching Si 3 N 4 selective to SiO 2 and Si are discussed in “ Highly Selective Etching of Silicon Nitride Over Silicon and Silicon Dioxide, ” J. Vac. Sci. Technol. A 17(6), November/December 1999, which describes the use of oxygen (O 2 ) and nitrogen (N 2 ) in combination with CF 4 or NF 3 .
- the processes discussed achieve Si 3 N 4 to Si and to SiO 2 etch rate ratios of up to 100 and 70 respectively using nitrogen trifluoride.
- the processes use high flow rates of 800 standard cubic centimeters (sccm) O 2 and 110 sccm N 2 for most experiments.
- sccm standard cubic centimeters
- a Si 3 N 4 to polysilicon etch ratio of 40 was achieved while SiO 2 was not etched at all.
- Etch rates of silicon nitride are below about 50 angstroms ( ⁇ ) per minute.
- any decrease in temporal processing requirements can result in a large increase in product throughput.
- having options available to accomplish a task such as etching silicon nitride is advantageous, as one process may function better for certain manufacturing flows. Additional methods for etching silicon nitride selective to silicon and silicon nitride at an accelerated rate would be desirable.
- the present invention provides a new etch method which, among other advantages, reduces problems associated with the manufacture of semiconductor devices, particularly problems in etching silicon nitride selective to silicon and silicon dioxide.
- a semiconductor wafer substrate assembly having a layer of silicon nitride and a layer of at least one of silicon and silicon dioxide is placed into an etch chamber.
- Oxygen and either CHF 3 or CH 2 F 2 are introduced into an etch chamber under controlled flow rates, power, and pressure.
- the etch removes silicon nitride selective to silicon dioxide and silicon.
- FIG. 1 depicts a cross section of a semiconductor wafer assembly including a blanket layer of silicon nitride
- FIG. 2 depicts the cross section of FIG. 1 subsequent to an etch to form silicon nitride spacers.
- a silicon nitride etch selective to silicon (such as monocrystalline or polycrystalline silicon) and to silicon dioxide comprises the use of O 2 and either CHF 3 or CH 2 F 2 at relatively low flow rates. It should be noted that the parameters described herein are optimized for an Applied Materials 5000 (AME5000) etcher, but they may be converted easily by one of ordinary skill in the art for other systems.
- a semiconductor wafer having a layer of silicon nitride and a layer of silicon dioxide and/or silicon is placed into an etch chamber and subjected to an etch.
- This embodiment of the etch comprises an O 2 :CHF 3 or O 2 :CH 2 F 2 flow rate ratio of greater than about 3:1, which results in a relatively rapid, controllable Si 3 N 4 etch rate with good selectivity to Si and to SiO 2 .
- an O 2 flow rate of between about 20 sccm and about 80 sccm and a CHF 3 or CH 2 F 2 flow of between about 5 sccm and about 25 sccm would be sufficient.
- an O 2 flow rate of between about 35 sccm and about 60 sccm and a CHF 3 or CH 2 F 2 flow of between about 10 sccm and about 20 sccm would be sufficient, and most preferably an O 2 flow rate of about 60 sccm and a CHF 3 or CH 2 F 2 flow of about 20 sccm would be sufficient.
- a pressure of between about 10 millitorr to about 60 millitorr is maintained. More preferably, a pressure of between about 30 to about 60 millitorr, and most preferably, between about 30 to about 40 millitorr is maintained. Further, a power of between about 300 watts to about 600 watts, more preferably between about 300 watts to about 500 watts, and most preferably between about 300 to about 400 watts sustained within the chamber. With increasing power and/or pressure the etch rate increases and the selectivity to Si and SiO 2 decreases.
- an Si 3 N 4 :SiO 2 etch ratio of up to about 1.3:1 on a blanket film and up to about 3:1 over topography can be achieved, as well as an Si 3 N 4 :Si etch ratio of up to about 7:1.
- the O 2 :CHF 3 or O 2 :CH 2 F 2 increases beyond 3:1 the etch rate of the Si 3 N 4 decreases and the selectivity to Si and SiO 2 increases.
- the etch rate becomes so slow as to be decreasing usefulness in most instances.
- O 2 :CHF 3 or O 2 :CH 2 F 2 ratio decreases further below 3:1 the etch removes Si 3 N 4 at an increased rate but also becomes less selective to Si and SiO 2 .
- An O 2 :CHF 3 or O 2 :CH 2 F 2 ratio of about 3:1 is believed to provide a good balance between nitride etch rate and selectivity to Si and SiO 2 in many uses of the invention for semiconductor manufacture.
- the etch rate of Si 3 N 4 will be about 420 ⁇ /min.
- a pressure of about 40 millitorr a pressure of about 40 millitorr, a power of 300 watts, a CHF 3 or CH 2 F 2 flow rate of about 10 sccm and an O 2 flow rate of about 40 sccm, the etch rate increases to about 904 ⁇ /min.
- the Si 3 N 4 etch rate increases, such that at a pressure of 30 millitorr and a power of 300 watts, and a flow rate of 35 sccm for both O 2 and CHF 3 or CH 2 F 2 the etch rate increases to about 1270 ⁇ /min.
- These processes use a chuck temperature of about 10° C. and a sidewall temperature of about 20° C.
- FIG. 1 depicts a semiconductor substrate assembly 10 comprising a semiconductor wafer 12 , field oxide 14 , doped transistor source/drain regions 16 within the wafer 12 , and a transistor gate stack comprising gate oxide 18 , polycrystalline silicon (polysilicon) 20 , a conductive silicide layer 22 , and an oxide or nitride layer 24 , for example tetraethyl orthosilicate (TEOS) or silicon nitride.
- FIG. 1 further depicts a blanket silicon nitride layer 32 between about 300 ⁇ about 600 ⁇ thick. Such a structure can be manufactured by one of ordinary skill in the art.
- An exemplary etch includes processing the wafer in a chamber of an AME5000 etch chamber. After placing the wafer substrate assembly in the etch chamber, O 2 and CHF 3 or CH 2 F 2 are introduced into the chamber at flow rates of about 60 sccm and about 20 sccm respectively. Pressure is maintained at between about 30 millitorr and about 40 millitorr, and a power of between about 300 watts and about 400 watts is utilized. At a chuck temperature of about 10° C.
- the silicon nitride will etch at a rate of about 720 ⁇ /min in the vertical direction, and about 180 ⁇ /min in the horizontal direction. Generally, the vertical:horizontal etch rate will be about 4:1.
- the etch is performed for between about 35 seconds and about 60 seconds which results in the structure of FIG. 2 .
- Spacers 32 having a width of about 300 ⁇ to about 400 ⁇ are formed.
- the etch detailed above provides a silicon nitride etch which is selective to silicon and silicon dioxide. This is accomplished using the etch as described consisting essentially of a flow of O 2 and CHF 3 or CH 2 F 2 .
- the addition of hydrogen from CHF 3 or from CH 2 F 2 in addition to providing an etch of silicon nitride selective to silicon and silicon dioxide, further provides an etch which results in a more square profile of the completed transistor structures than conventional etches.
- the relatively low flow rates of CHF 3 or CH 2 F 2 may also contribute to the less rounded feature profile compared with conventional etches having high gas flow rates. Rounded profiles may adversely affect the self-aligned contact (SAC) etch performance, and possibly affect the electrical properties of the device.
- SAC self-aligned contact
- a semiconductor device formed in accordance with the invention may be attached along with other devices to a printed circuit board, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe.
- a device formed in accordance with the invention could further be useful in other electronic devices related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, and virtually any consumer or industrial electronic equipment.
Abstract
A method for etching silicon nitride selective to silicon dioxide and silicon (polycrystalline silicon or monocrystalline silicon) comprises the use of oxygen along with an additional etchant of either CHF3 or CH2F2. Flow rates, power, and pressure settings are specified.
Description
- This is a continuation of U.S. Ser. No. 10/819,517 filed May 6, 2004 and issued Jun. 13, 2006 as U.S. Pat. No. 7,060,629, which is a continuation of U.S. Ser. No. 09/854,206 filed May 11, 2001 and issued Apr. 6, 2004 as U.S. Pat. No. 6,716,759.
- This invention relates to the field of semiconductor manufacture and, more particularly, to an etch useful for removing silicon nitride selective to silicon and silicon dioxide.
- During the manufacture of semiconductor devices such as a memory devices, logic devices, and microprocessors, various processes are commonly performed. Etching silicon nitride selective to silicon (such as polysilicon) and to silicon dioxide with various etch ratios is often required. For example, hot phosphoric acid isotropically etches silicon nitride selective to silicon dioxide and silicon. Other processes for etching Si3N4 selective to SiO2 and Si are discussed in “Highly Selective Etching of Silicon Nitride Over Silicon and Silicon Dioxide,” J. Vac. Sci. Technol. A 17(6), November/December 1999, which describes the use of oxygen (O2) and nitrogen (N2) in combination with CF4 or NF3. The processes discussed achieve Si3N4 to Si and to SiO2 etch rate ratios of up to 100 and 70 respectively using nitrogen trifluoride. The processes use high flow rates of 800 standard cubic centimeters (sccm) O2 and 110 sccm N2 for most experiments. Further, using carbon tetrafluoride, a Si3N4 to polysilicon etch ratio of 40 was achieved while SiO2 was not etched at all. Etch rates of silicon nitride are below about 50 angstroms (Å) per minute.
- As semiconductor manufacture typically requires high volume processing to lower costs, any decrease in temporal processing requirements can result in a large increase in product throughput. Further, having options available to accomplish a task such as etching silicon nitride is advantageous, as one process may function better for certain manufacturing flows. Additional methods for etching silicon nitride selective to silicon and silicon nitride at an accelerated rate would be desirable.
- The present invention provides a new etch method which, among other advantages, reduces problems associated with the manufacture of semiconductor devices, particularly problems in etching silicon nitride selective to silicon and silicon dioxide. In accordance with one embodiment of the invention a semiconductor wafer substrate assembly having a layer of silicon nitride and a layer of at least one of silicon and silicon dioxide is placed into an etch chamber. Oxygen and either CHF3 or CH2F2 are introduced into an etch chamber under controlled flow rates, power, and pressure. At the parameters detailed herein, the etch removes silicon nitride selective to silicon dioxide and silicon.
- Additional advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
-
FIG. 1 depicts a cross section of a semiconductor wafer assembly including a blanket layer of silicon nitride; and -
FIG. 2 depicts the cross section ofFIG. 1 subsequent to an etch to form silicon nitride spacers. - It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.
- A silicon nitride etch selective to silicon (such as monocrystalline or polycrystalline silicon) and to silicon dioxide comprises the use of O2 and either CHF3 or CH2F2 at relatively low flow rates. It should be noted that the parameters described herein are optimized for an Applied Materials 5000 (AME5000) etcher, but they may be converted easily by one of ordinary skill in the art for other systems.
- In accordance with one embodiment of the invention, a semiconductor wafer having a layer of silicon nitride and a layer of silicon dioxide and/or silicon is placed into an etch chamber and subjected to an etch. This embodiment of the etch comprises an O2:CHF3 or O2:CH2F2 flow rate ratio of greater than about 3:1, which results in a relatively rapid, controllable Si3N4 etch rate with good selectivity to Si and to SiO2. For example, an O2 flow rate of between about 20 sccm and about 80 sccm and a CHF3 or CH2F2 flow of between about 5 sccm and about 25 sccm would be sufficient. More preferably, an O2 flow rate of between about 35 sccm and about 60 sccm and a CHF3 or CH2F2 flow of between about 10 sccm and about 20 sccm would be sufficient, and most preferably an O2 flow rate of about 60 sccm and a CHF3 or CH2F2 flow of about 20 sccm would be sufficient.
- During the etch, a pressure of between about 10 millitorr to about 60 millitorr is maintained. More preferably, a pressure of between about 30 to about 60 millitorr, and most preferably, between about 30 to about 40 millitorr is maintained. Further, a power of between about 300 watts to about 600 watts, more preferably between about 300 watts to about 500 watts, and most preferably between about 300 to about 400 watts sustained within the chamber. With increasing power and/or pressure the etch rate increases and the selectivity to Si and SiO2 decreases.
- Using the parameters described above, it is estimated that an Si3N4:SiO2 etch ratio of up to about 1.3:1 on a blanket film and up to about 3:1 over topography can be achieved, as well as an Si3N4:Si etch ratio of up to about 7:1. As the O2:CHF3 or O2:CH2F2 increases beyond 3:1 the etch rate of the Si3N4 decreases and the selectivity to Si and SiO2 increases. With a high O2:CHF3 or O2:CH2F2 ratio, above about 10:1, the etch rate becomes so slow as to be decreasing usefulness in most instances. As the O2:CHF3 or O2:CH2F2 ratio decreases further below 3:1 the etch removes Si3N4 at an increased rate but also becomes less selective to Si and SiO2. An O2:CHF3 or O2:CH2F2 ratio of about 3:1 is believed to provide a good balance between nitride etch rate and selectivity to Si and SiO2 in many uses of the invention for semiconductor manufacture.
- At a pressure of about 30 millitorr, a power of 300 watts, a CHF3 or CH2F2 flow rate of 20 sccm, and an O2 flow rate of 60, the etch rate of Si3N4 will be about 420 Å/min. With a pressure of 40 millitorr, a pressure of about 40 millitorr, a power of 300 watts, a CHF3 or CH2F2 flow rate of about 10 sccm and an O2 flow rate of about 40 sccm, the etch rate increases to about 904 Å/min. As the CHF3/O2 or CH2F2/O2 ratio increases the Si3N4 etch rate increases, such that at a pressure of 30 millitorr and a power of 300 watts, and a flow rate of 35 sccm for both O2 and CHF3 or CH2F2 the etch rate increases to about 1270 Å/min. These processes use a chuck temperature of about 10° C. and a sidewall temperature of about 20° C.
- Using the preferred parameters of the instant invention as discussed above results in an anisotropic nitride etch which removes nitride from horizontal surfaces faster than it removes nitride from vertical surfaces at an etch ratio of about 3.7:1. This is especially useful for etching structures similar to those depicted in
FIGS. 1 and 2 , as it allows sufficient etching to remove the nitride layer from the wafer surface without damaging the silicon wafer. The structure ofFIG. 1 depicts asemiconductor substrate assembly 10 comprising asemiconductor wafer 12,field oxide 14, doped transistor source/drain regions 16 within thewafer 12, and a transistor gate stack comprisinggate oxide 18, polycrystalline silicon (polysilicon) 20, aconductive silicide layer 22, and an oxide ornitride layer 24, for example tetraethyl orthosilicate (TEOS) or silicon nitride.FIG. 1 further depicts a blanketsilicon nitride layer 32 between about 300 Å about 600 Å thick. Such a structure can be manufactured by one of ordinary skill in the art. - The structure of
FIG. 1 is subjected to an inventive etch as described above. An exemplary etch includes processing the wafer in a chamber of an AME5000 etch chamber. After placing the wafer substrate assembly in the etch chamber, O2 and CHF3 or CH2F2 are introduced into the chamber at flow rates of about 60 sccm and about 20 sccm respectively. Pressure is maintained at between about 30 millitorr and about 40 millitorr, and a power of between about 300 watts and about 400 watts is utilized. At a chuck temperature of about 10° C. and a sidewall temperature of about 20° C., the silicon nitride will etch at a rate of about 720 Å/min in the vertical direction, and about 180 Å/min in the horizontal direction. Generally, the vertical:horizontal etch rate will be about 4:1. For the 525 Å thick layer of silicon nitride depicted inFIG. 1 , the etch is performed for between about 35 seconds and about 60 seconds which results in the structure ofFIG. 2 .Spacers 32 having a width of about 300 Å to about 400 Å are formed. - The etch detailed above provides a silicon nitride etch which is selective to silicon and silicon dioxide. This is accomplished using the etch as described consisting essentially of a flow of O2 and CHF3 or CH2F2. The addition of hydrogen from CHF3 or from CH2F2, in addition to providing an etch of silicon nitride selective to silicon and silicon dioxide, further provides an etch which results in a more square profile of the completed transistor structures than conventional etches. The relatively low flow rates of CHF3 or CH2F2 may also contribute to the less rounded feature profile compared with conventional etches having high gas flow rates. Rounded profiles may adversely affect the self-aligned contact (SAC) etch performance, and possibly affect the electrical properties of the device. In extreme cases, conventional etches can expose the conductive polysilicon, metal, or silicide which is protected by the oxide. Additionally, the structure depicted in
FIG. 1 , and other similar structures, can be etched with less concern for damaging the silicon wafer once the nitride has been cleared due to the high selectivity to silicon. - A semiconductor device formed in accordance with the invention may be attached along with other devices to a printed circuit board, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe. A device formed in accordance with the invention could further be useful in other electronic devices related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, and virtually any consumer or industrial electronic equipment.
- While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
Claims (8)
1. A method of forming a circuit structure comprising:
forming a first layer from a material selected from the group consisting of silicon and silicon dioxide over a semiconductor wafer substrate assembly;
forming a second layer comprising silicon nitride on the first layer;
placing the semiconductor wafer substrate into an etch chamber;
introducing an etchant consisting essentially of oxygen and one of CH2F2 and CHF3 into the etch chamber at a flow rate ratio of about 3:1 to etch at least a portion of the second layer, wherein the etchant etches through the second layer and stops on the first layer.
2. The method of claim 1 further comprising introducing oxygen into the chamber at a flow rate of between about 20 sccm to about 80 sccm and introducing the one of CH2F2 and CHF3 into the etch chamber at a flow rate of between about 5 sccm to about 25 sccm.
3. The method of claim 2 further comprising maintaining a pressure of between about 10 millitorr and about 60 millitorr during the introduction of the etchant.
4. The method of claim 3 further comprising sustaining a power of between about 300 watts and about 600 watts during the introduction of the etchant.
5. A method of etching silicon nitride selective to at least one of silicon and silicon dioxide, comprising:
forming a first layer from a material selected from the group consisting of silicon and silicon dioxide over a semiconductor wafer substrate assembly;
forming a second layer comprising silicon nitride on the first layer;
placing the semiconductor wafer substrate into an etch chamber;
introducing an etchant consisting essentially of oxygen and CH2F2 into the etch chamber at a flow rate ratio of about 3:1 to etch at least a portion of the second layer, wherein the etchant etches through the second layer and stops on the first layer.
6. The method of claim 5 wherein the oxygen is introduced into the chamber at a flow rate of between about 20 sccm to about 80 sccm and the CH2F2 is introduced into the etch chamber at a flow rate of between about 5 sccm to about 25 sccm.
7. The method of claim 6 further comprising maintaining a pressure of between about 10 millitorr and about 60 millitorr during the introduction of the etchant.
8. The method of claim 7 further comprising sustaining a power of between about 300 watts and about 600 watts during the introduction of the etchant.
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US11/451,965 US20060231522A1 (en) | 2001-05-11 | 2006-06-12 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
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US09/854,206 US6716759B2 (en) | 2001-05-11 | 2001-05-11 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
US10/819,517 US7060629B2 (en) | 2001-05-11 | 2004-04-06 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
US11/451,965 US20060231522A1 (en) | 2001-05-11 | 2006-06-12 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
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US10/819,517 Expired - Lifetime US7060629B2 (en) | 2001-05-11 | 2004-04-06 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
US11/451,965 Abandoned US20060231522A1 (en) | 2001-05-11 | 2006-06-12 | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
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WO2012047459A3 (en) * | 2010-09-28 | 2012-06-07 | Tokyo Electron Limited | Selective etch process for silicon nitride |
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US6716759B2 (en) * | 2001-05-11 | 2004-04-06 | Micron Technology, Inc. | Etch of silicon nitride selective to silicon and silicon dioxide useful during the formation of a semiconductor device |
US7338907B2 (en) * | 2004-10-04 | 2008-03-04 | Sharp Laboratories Of America, Inc. | Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications |
US20070111449A1 (en) * | 2005-11-16 | 2007-05-17 | Hsu-Sheng Yu | Non-volatile memory cell and method for manufacturing the same |
US7393788B2 (en) * | 2006-02-10 | 2008-07-01 | Cook Julie A | Method and system for selectively etching a dielectric material relative to silicon |
KR200455042Y1 (en) * | 2009-02-14 | 2011-08-11 | 한국철도공사 | Wheel Bearing Bearing of Railroad Cars |
CN110600377A (en) * | 2019-09-27 | 2019-12-20 | 扬州扬杰电子科技股份有限公司 | Etching method for reducing surface chromatic aberration generated by wafer positive gold corrosion |
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WO2012047459A3 (en) * | 2010-09-28 | 2012-06-07 | Tokyo Electron Limited | Selective etch process for silicon nitride |
US8501630B2 (en) | 2010-09-28 | 2013-08-06 | Tokyo Electron Limited | Selective etch process for silicon nitride |
Also Published As
Publication number | Publication date |
---|---|
US20040192054A1 (en) | 2004-09-30 |
US20020168865A1 (en) | 2002-11-14 |
US6716759B2 (en) | 2004-04-06 |
US7060629B2 (en) | 2006-06-13 |
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