US20060268355A1

US20060268355A1 - Method and system for promoting scanning speed

Info

Publication number: US20060268355A1
Application number: US11/502,063
Authority: US
Inventors: Chun-Jen Chen; Kuo-Jeng Wang
Original assignee: Transpacific IP Ltd
Current assignee: Cedar Lane Technologies Inc; Transpacific Systems LLC
Priority date: 2001-12-11
Filing date: 2006-08-09
Publication date: 2006-11-30
Also published as: US7420715B2; US20030107779A1

Abstract

In accordance with the present invention, a method and a system for promoting scanning speed are provided. The method comprises steps of determining a transmission rate of a transit interface, adjusting system clock responsive to the transmission rate of the transit interface to change a data generated rate, and scanning an original to generate data at the rate controlled by the system clock. The key aspect of the present invention is by adjusting system clock to change the data generated rate corresponding to the transmission rate of the transit interface. Therefore, in response to the transmission rate of the transit interface, the system clock is adjusted to produce the data at a rate that can reduce the possibility of memory buffer full leading to the reduction in the time wasting on start-stop processes and therefore promote the scanning speed without requiring the increase in size of a memory buffer.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention generally relates to a method and a system for promoting scanning speed, and more particularly to a method and a system for promoting scanning speed by adjusting system clock to change the data generated rate corresponding to the transmission rate of the transit interface.
2. Description of the Prior Art
Scanners are widely applied for the ability of generating digital representation of the information comprised by an original. The digital representation typically processed on a host device such as computer, and through an I/O cable data is transmitted from the scanner to the computer. The data transmission rate from the scanner to the host device is depended on the communication protocol used between the scanner and the host device. Ideally, digital data transferred to the host device is produced at the same rate that the host device can accept it. Therefore, no memory buffer is required for accumulating data that is waiting for transfer. However, the digital data is usually produced at a rate quite different from the data reception rate of the host device. If the transmission rate is higher than the data generated rate of the scanner, the scanner can run in full speed with no possible loss of data. However, the data generated rate of a scanner is usually faster than the transmission rate of the host computer. Therefore, when the transmission rate is lower than the data generated rate, issues related to the efficiency of the scanning operation often arise in the scanning operation.
Besides optical resolution, the scanning speed is another essential functional criteria of scanners. The scanning speed is the time that the scanner sends back scanned image to the host device after the scanning work is started. If the transmission rate is slower, the image data will be accumulated in a memory buffer, and the memory buffer may finally get full after only a portion of the original is scanned. In order to prevent the loss of the image data, the scanning operation is halted when the memory buffer is full and, then resumed when the memory buffer is empty or available for storing more data again. In other words, when the memory buffer is full, a scanning module driven by a motor is stopped and moved backward for a predetermined number of steps, due to the first few step motions of the scanning module being usually quite shaky and unstable that is caused by mechanical vibrations resulting in affecting the quality of the output in that period. Then, the scanning module is forwarded from there when the data accumulated in the memory buffer is transmitted to the host device. The processes of stopping and restarting the scan are alternatively performed till the scanning operation is completed. This method of preventing the loss of image data is useful, but it may cause the scanning of an original to take a long time because the scanning is stopped and restarted repeatedly.
The procedure of moving the scanning module backward and forward or, in other words, the procedure of stopping and restarting the scanning module is so called a smearing or start-stop process. This procedure might help to solve the problem of unstable scanning module or memory buffer full but it takes time to move the scanning module backward and forward, which may reduce the overall scanning speed of the scanner. Besides the start-stop process, in order to overcome the problems associated with data transfer from the scanner to the computer due to the varying transmission rate of the computer, lots of methods have been proposed. The increase in size of the memory buffer is one of the methods. The scanning of the original is thereby not affected by the varying capability of the computer to receive data. Enlarging memory buffer is quite straight forward and easy but with some drawbacks, that is, it also increases cost and complicates the manufacture of a scanner. Moreover, it may not really solve the problem when a high-resolution scan is performed, which can generate a huge amount of image data within a very short period of time, and it is not feasible to simply increase the memory buffer size to alleviate the problem.
A scanner with fast scanning speed can shorten the time while scanning of an original, speed up and increase work efficiency. Thus, it is imperative to develop a method and a system which reduces the possibility of memory buffer being full leading to the reduction of the time wasting on start-stop processes and thereby promoting the scanning speed without requiring the increase in size of a memory buffer.

SUMMARY OF THE INVENTION

The present invention is directed to a method and a system for promoting the scanning speed. The key aspect of the present invention is by adjusting system clock to change the data generated rate corresponding to the transmission rate of the transit interface. Therefore, in response to the transmission rate of the transit interface, the system clock is adjusted to produce the data at a rate that can reduce the possibility of memory buffer full leading to the reduction in the time wasting on start-stop processes and therefore promote the scanning speed without requiring the increase in size of a memory buffer.
It is another object of this invention that a method and a system for avoiding a start-stop process of the scanning mechanism are provided.
It is a further object of this invention that a method and a system for changing the data generated rate by use of adjusting the system clock corresponding to the transit interface are provided.
It is another further object of this invention that a method and a system for promoting scanning speed without requiring the increase in size of a memory buffer are provided.
In accordance with the present invention, in one embodiment, a method is provided for optimizing the scanning speed of a scanning system by adjusting system clock in response to a transit interface. The method comprises steps of determining a transmission rate of the transit interface, adjusting system clock responsive to the transmission rate of the transit interface to change a data generated rate, and scanning an original to generate data at the data generated rate. The data generated rate can be any rate reducing the data accumulation. The step of adjusting the system clock comprises multiplying a frequency generated by a clock generator by a multiplier according to the transmission rate, wherein the multiplier can be selected from a plurality of predetermined values. The method further comprises communicating the data from the scanning system to a host device through the transit interface.
In another embodiment, a method of optimizing scanning speed comprises steps of determining a transmission rate of a transit interface, comparing the transmission rate with a predetermined value, adjusting a system clock when the transmission rate is not equal to the predetermined value, and scanning an original to generate a data at a rate controlled by the system clock. The step of adjusting the system clock comprises increasing the system clock to increase the data generated rate when the transmission rate is faster than the predetermined value and reducing the system clock to reduce the data generated rate when the transmission rate is lower than the predetermined value. The method further comprises communicating the data from the scanning system to a host device through the transit interface.
In a third embodiment, a scanning system with adjustable data generated rate comprises a plurality of transit interfaces for data communicating between the scanning system and a host device, a system clock generator for generating a plurality of corresponding system clocks responsive to the transit interfaces, and a scanning module for scanning an original to generate the data at a rate controlled by the corresponding system clocks. The transit interface can be USB1.1, USB2.0, IEEE1394, EPP, and SCSI and not limited to those. When a transit interface with different transmission rates such as USB (USB1.1, USB2.0) and IEEE1394 (1394a, 1394b) series, the system clock generator generates the corresponding system clocks according to the transmission rates. The system clock generator comprises a clock generator such as crystal oscillator generating a frequency and a frequency multiplier for multiplying the frequency by a multiplier to generate the corresponding system clocks.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic block diagram of a scanning system in accordance with the present invention;
FIG. 2A is a flow diagram of a scanning method in accordance with one embodiment of the present invention; and
FIG. 2B is a flow diagram of a scanning method in accordance with another embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Some sample embodiments of the invention will now be described in greater detail. Nevertheless, it should be noted that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited except as specified in the accompanying claims.
It is widely known in the prior art that the digital data produced by a scanner is usually generated at a fixed rate due to the implement of a system clock of a constant duty cycle and operated at a fixed frequency. Therefore, the fixed data generated rate does not serve to optimize the scanning speed in response to the difference in transmission rate of a variety of transit interfaces. In other words, when the image data is generated at a rate faster than the transmission rate of a transit interface, or when a huge amount of the image data is generated within a very short time causing a memory buffer full, the start-stop process is unavoidable such that the time wasting on the start-stop process is also inevitable. Thus, the optimization of the scanning speed is out of question. In view of the drawbacks depicted in the prior art, the present invention provides a method and a system for adjusting the system clock corresponding to the transit interface to generate the image data at a rate for avoiding the start-stop processes and optimizing the scanning speed.
One aspect of the present invention is that due to the difference in transmission rate, the data is generated at a rate corresponding to the transmission rate of the transit interface to reduce the possibility of start-stop processes, that is, to prevent a memory buffer full. Other aspect of the present invention is that the data generated rate is changed by means of adjusting the system clock.
Referring to FIG. 1, in one embodiment, a schematic block diagram of a scanning system 100 is shown. The scanning system 100 comprises a clock generator 110, a frequency multiplier 120, a scanning module 130, a data memory buffer 140, and a plurality of transit interfaces 150 such as transit interfaces 150 a, 150 b, and 150 c. The scanning module 130 including a detector 160, an analog to digital converter (ADC) 170, and an image processor 180, is for scanning an original to generate image data at a rate controlled by a system clock. The transit interface 150 is for the data communication from a data generator to a host device, in the embodiment, from the scanning system 100 to a computer. The transit interface can be any commercial products with any communication protocols and transmission rates such as USB1.1, USB2.0, IEEE1394, EPP, and SCSI and not limited to those. The clock generator 110 can be a crystal oscillator, which produces a constant frequency (F). The frequency multiplier 120 can be a phase lock loop circuit, which multiplies the constant frequency (F) by a multiplier (M) to adjust the system clock according to the transit interface 150, thus the image data is generated at a rate preventing the memory buffer 140 full. In short, the combination of the clock generator 110 and the frequency multiplier 120 is a system clock generator, which generates corresponding system clocks according to the transit interface or the transmission rate of the transit interface. Therefore, the scanning system 130 is operated at a multiplied frequency (F times M) for generating data controlled by the system clock.
Additionally, the frequency of the system clock can be determined by multiplying the frequency (F) generated by the clock generator 110 by one multiplier selected from a plurality of built-in multipliers according to the transmission rate. In other words, every transit interface has a corresponding frequency of the system clock built in the scanning system. When the transit interface is determined, the scanning module 130 is operated at the corresponding frequency of the system clock to generate the image data. For example, if the transit interface is USB1.1 and IEEE 1394, the frequency of the system clock is the frequency (F) times 2 and 3, respectively, wherein 2 and 3 are selected from the plurality of built-in multipliers. That is, the frequency of the system clock for USB1.1 and IEEE1394 are 2F and 3F, respectively. Thus, the possibility of the memory buffer full is reduced and the start-stop process is diminished resulting in the optimization of the scanning speed.
In accordance with the present invention, a method for adjusting a system clock according to the transit interface is also provided, which promotes the scanning speed. Referring to FIG. 2A, a flow chart of implementing the present invention by the scanning system is illustrated. The method starts from step 210, the transit interface used in the scanning process is determined such as the transit interface 150 a is implemented. It is noted that when the transit interface is determined, the transmission rate can also be determined. For example the transit interface can be a USB 2.0 with a transmission rate of 480 Mbit/sec or running at a rate of 12 Mbit/sec, or a USB1.1 with a transmission rate of 12 Mbit/sec. The transmission rate of the transit interface can be determined by a signal sent to the scanning system in the process of initializing the scanning system or by a firmware prior to starting a scanning operation.
In the step of 220, a system clock is determined according to the transit interface. That is, the scanning module is operated at a frequency to generate data at a rate that prevents the memory buffer full. The frequency of the system clock can be determined by multiplying the frequency (F) of a clock generator by a multiplier responsive to the transmission rate of the transit interface. For example, the USB transit interface can have three transmission rates, high-speed of 480 Mbit/sec, full-speed of 12 Mbit/sec, and low-speed which is seldom used for data transfer. The frequency of the system clock (or the multiplier) is determined when the transmission rate is determined. If the transit interface has a high transmission rate such as IEEE 1394, EPP, and SCSI, the data is generated at highest frequency a system clock can produce due to the transmission rate is greatly faster than the data generated rate in the present technology. When the transit interface has a low transmission rate such as USB1.1, the data is generated at lower frequency a system clock can produces to prevent the memory buffer full. As depicted in step 230, the original is scanned to generate the data at a rate controlled by the system clock.
Additionally, FIG. 2B shows a flow diagram of promoting the scanning speed in accordance with another embodiment. The method starts from the same step of 210, the transit interface used in the scanning process is determined such as the transit interface 150 a is implemented. In the step of 240, decision of adjusting the system clock is made. The system clock is adjusted according to the result of comparing the transmission rate of the transit interface 150 a with a predetermined transmission rate. When the transmission rate of the transit is different from a predetermined value, the system clock is adjusted in the step of 250. In more details, when the transmission rate of the transit interface is faster than the predetermined transmission rate, the system clock is increased to increase the data generated rate. On the other hand, if the transmission rate of the transit interface is lower than the predetermined transmission rate, the system clock is adjusted to reduce the data generated rate. Then, in the step of 260, the scanning of an original is started to generate data at a rate controlled by the system clock.
For example, in accordance with the present invention, in the scanning procedure, the transmission rate of a transit interface 150 such as USB 1.1 is first determined. When an optical detector 160 such as charge coupled device (CCD) generates analog image data in the scanning of the original, the analog to digital converter (ADC) 170 is for converting the analog image data to digital data. Then, the image processor 180 of the scanning module 130 generates the image data under the control of the system clock with a corresponding frequency (such as 2F in the example) produced by the frequency multiplier 120 such as phase lock loop circuit, which is the frequency (F) generated by the clock generator 110 times a multiplier such as 2. Therefore, the data generated rate is changed to a rate preventing the memory buffer 140 full leading to the reduction in the time wasting on the start-stop process. Thus, the scanning speed is promoted without the requirement of increasing the memory buffer.
Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.

Claims

1.-19. (canceled)

20. An apparatus, comprising:

means for adjusting a scanning system clock to adjust a data generation rate of a scanning system, based at least in part on said data transmission rate of a data interface; and

means for performing a scanning operation to generate scanning data at said adjusted data generation rate.

21. The apparatus of claim 20, further comprising means for transmitting said scanning data from said scanning system to a host device through said data interface.

22. The apparatus of claim 20, wherein said means for adjusting said data generation rate comprises means for reducing said data generation rate.

23. An apparatus, comprising:

means for adjusting a scanning system clock based at least in part on a comparion of a data transmission rate of a data interface and a predetermined value; and

means for performing a scanning operation to generate scanning data at a rate controlled by said scanning system clock.

24. The apparatus of claim 23, further comprising means for transmitting said scanning data to a host device through said data interface.

25. The apparatus of claim 23, wherein means for adjusting said system clock comprises means for increasing a speed of said system clock to increase said controlled rate.

26. The apparatus of claim 23, wherein means for adjusting said system clock comprises means for reducing the speed of said system clock to reduce a data generation rate.

27. An article comprising a storage medium, having stored thereon instructions that, when executed, result in:

adjusting a scanning system clock to adjust a data generation rate of a scanning system, based at least in part on a data transmission rate of a data interface; and

performing a scanning operation to generate scanning data at said adjusted data generation rate.

28. The article of claim 27, wherein said instructions, when executed, further result in:

transmitting said scanning data from said scanning system to a host device through said data interface.

29. The article of claim 27, wherein said data interface comprises a data interface selected from the group comprising: USB1.1, USB2.0, IEEE1394, EPP, and/or a SCSI.

30. The article of claim 27, wherein said instructions, when executed, further results in:

adjusting said data generation rate in response to a reduction in said data generation rate.

31. The article of claim 27, wherein said instructions, when executed, further result in:

adjusting said system clock by scaling a frequency generated by a clock generator by a scalar, wherein the scalar is based at least in part on said data transmission rate.

32. The article of claim 31, wherein said multiplier comprises a value selected from a plurality of predetermined values.

33. An article comprising a storage medium, having stored thereon instructions that, when executed, result in:

adjusting a scanning system clock based at least in part on a comparison of a data transmission rate of a data inferrace with a predetermined value; and

performing a scanning operation to generate scanning data at a rate controlled by said scanning system clock.

34. The article of claim 33, wherein said instructions, when executed, further result in:

transmitting said scanning data to a host device through said data interface.

35. The article of claim 33, wherein said data interface comprises a data interface selected from the group comprising: USB1.1, USB2.0, IEEE1394, EPP, and/or a SCSI.

36. The article of claim 33, wherein said instructions, when executed, further result in:

adjusting said system clock by increasing the speed of said system clock to increase a data generation rate.

37. The article of claim 33, wherein said instructions, when executed, result in: adjusting said system clock by reducing the speed of said system clock to reduce a data generation rate.

38. The article of claim 33, wherein said instructions, when executed, further result in:

adjusting said system clock by multiplying a frequency generated by a clock generator by a multiplier, wherein the multiplier is based at least in part on said data transmission rate.

39. A scanning system comprising:

a plurality of data interfaces to provide data between the scanning system and a host device, the plurality of data interfaces, said data interfaces being associated with respective data transmission rates;

circuitry to select one of the plurality of data interfaces to transmit data between the scanning system and a host device;

a system clock generator to generate an associated system clock responsive to said selection of one of the plurality of data interfaces; and

a scanning module to generate scanning data at a data generation rate controlled by said associated generated system clock.

40. The system according to claim 39, wherein said data interfaces comprises one or more data interfaces selected from the group comprising: USB1.1, USB2.0, IEEE1394, EPP, and/or a SCSI.

41. The system according to claim 39, wherein said system clock generator is adapted to generate said associated system clock in accordance with the data transmission rate of the selected data interface.

42. The system according to claim 39, wherein said system clock generator further comprises:

a clock generator to generate a frequency; and

a frequency multiplier to multiply said frequency by a plurality of multipliers to generate said corresponding system clock.