US20060278341A1 - Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates - Google Patents
Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates Download PDFInfo
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- US20060278341A1 US20060278341A1 US11/506,833 US50683306A US2006278341A1 US 20060278341 A1 US20060278341 A1 US 20060278341A1 US 50683306 A US50683306 A US 50683306A US 2006278341 A1 US2006278341 A1 US 2006278341A1
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- semiconductor wafer
- focus ring
- process chamber
- electrostatic chuck
- ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
- C23C16/4585—Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/54—Apparatus specially adapted for continuous coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32623—Mechanical discharge control means
- H01J37/32642—Focus rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
- Y10T117/10—Apparatus
Abstract
A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.
Description
- CROSS REFERENCE TO RELATED APPLICATION(S)
- This is a divisional application based on pending application Ser. No. 10/234,135, filed Sep. 5, 2002, which in turn is a division of application Ser. No. 09/404,631, filed Sep. 23, 1999, the entire contents of which is hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to equipment for manufacturing semiconductor devices, and more particularly, to a process chamber used in the manufacture of semiconductor devices, capable of reducing contamination by particulates.
- 2. Description of the Related Art
- In general, integrated circuits (ICs) are manufactured on semiconductor wafers formed of, for example, silicon. During the manufacture of the ICs, a series of steps, for example, photo masking, deposition of material layers, oxidation, nitridation, ion implantation, diffusion and etching, are conducted to obtain a final product. Most of these steps are carried out in a process chamber. Thus, reducing contamination by particulate in the process chamber has been recognized as a critical factor for determining the quality of a semiconductor device. Particulates are generated in a process chamber depending on the structure of the process chamber, the material used to form the chamber, and the types of reaction gases used in the chamber. In general, the process chamber is contaminated by particulates due to the following two reasons.
- The first reason, which usually occurs in a process chamber used for etching, is the difference in temperature between edge rings (or focus rings) near a semiconductor wafer and the parts from which the process chamber is constructed. The second reason, which usually occurs in a process chamber used for a deposition process, is the unsmooth flow of a reaction gas near guide rings for guiding the edge of a semiconductor wafer.
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FIG. 1 is a view illustrating the generation of particulates in a process chamber during an etching process. In detail,FIG. 1 is a sectional view illustrating an electrostatic chuck supporting a semiconductor wafer in a conventional process chamber for an etching process using plasma.FIG. 2 is an enlarged view of the edge (portion A) of the semiconductor wafer shown inFIG. 1 , andFIG. 3 is a plan view ofFIG. 1 . - Referring to
FIG. 1 , anelectrostatic chuck 20 holds asemiconductor wafer 10 using electrostatic adsorption. Although not shown inFIG. 1 , a power supply for supplying a high voltage is connected to theelectrostatic chuck 20 to induce static electricity.Lift pins 21 for moving the semiconductor wafer 10 up and down when loading or unloading thesemiconductor wafer 10, pass through the center of theelectrostatic chuck 20. Thelift pins 21 are in contact with asupport plate 22 installed below theelectrostatic chuck 20. Thesupport plate 22 moves upwards in response to force applied by an external lifter (not shown), in a direction indicated by anarrow 23. Thelift pins 21 move upwards in response to upward movement of thesupport plate 22. Then, thelift pins 21 protrude past the surface of theelectrostatic chuck 20, and thesemiconductor wafer 10 supported by thelift pins 21 is separated from the surface of theelectrostatic chuck 20. -
Edge rings 24 are installed at the upper edges of theelectrostatic chuck 20 to fix thesemiconductor wafer 10. As shown inFIGS. 2 and 3 , theedge ring 24 is separated from the edge of the semiconductor wafer 10 by asmall gap 25. Also, there is aspace 26 between part of the surface of theedge ring 24 and the periphery of the bottom surface of the semiconductor wafer 10. Also, acoupling ring 27 made of aluminum (Al) is interposed between theedge ring 24 and theelectrostatic chuck 20. Thesemiconductor wafer 10 is surrounded by afocus ring 28. Thefocus ring 28 draws a plasma forming region to the edge of the semiconductor wafer 10 during the etching process, such that the plasma forming region is uniformly formed across thesemiconductor wafer 10. - However, in such a conventional process chamber, plasma enters into the
small gap 25 between theedge ring 24 and the edge of the semiconductor wafer 10, and thus the bottom surface of the semiconductor wafer may be etched. Polymers, which are byproducts generated by the etching, adhere to the bottom surface of the semiconductor wafer 10 and bind theedge ring 24 to theelectrostatic chuck 20. When theedge ring 24 is separated from theelectrostatic chuck 20 for repair and maintenance after the process is completed, theedge ring 24 can be broken due to it being bound to theelectrostatic chuck 20 by the polymer. - When the etching is repeated several times, the
edge ring 24 is etched along its inner circumference, so that the gap between theedge ring 24 and thesemiconductor wafer 10 becomes wider. As a result, theedge ring 24 strikes against the edge of a platen zone of the semiconductor wafer (portion B ofFIG. 3 ), so that a part of thesemiconductor wafer 10 can be broken. -
FIG. 4 is another view illustrating the generation of particulates in a process chamber used for an etching process. In detail,FIG. 4 is a sectional view of anelectrostatic chuck 20 in which afocus ring 40 is included but not the edge ring shown inFIG. 3 . - Referring to
FIG. 4 , asemiconductor wafer 10 is held by an electrostatic force produced by anelectrostatic chuck 20, through whichlift pins 21 are inserted. Anannular focus ring 40 is arranged around the edge of theelectrostatic chuck 20. Thefocus ring 40 draws a plasma forming region to the edge of the semiconductor wafer 10 during the etching process, such that the plasma forming region is uniformly formed across thesemiconductor wafer 10. Further, thefocus ring 40 acts as an edge ring, thereby preventing the semiconductor wafer 10 from deviating from its original position. - The upper part of the
focus ring 40 is rounded, and the height of the focus ring is higher than the surface of thesemiconductor wafer 10. Most of the polymers generated in the process chamber accumulate on the protruding top of thefocus ring 40. Here, the amount and type of accumulated polymer varies according to the material forming the metal layer to be etched, and the distribution in temperature in the reaction chamber. For example, if a metal layer to be etched is formed of tungsten (W), an etching gas used for etching the metal layer, for example, SF6, reacts with the Al component of the process chamber and increases the concentration of Al in the process chamber, thereby generating floating particulates of AlxFy. Also, if a metal layer to be etched is formed of Al, an etching gas used for etching the metal layer, for example, Cl2 or BCl3, generates polymers of AlxCly. Such polymers lie on the protruding portion of thefocus ring 40, which is the farthest away from a heat source (not shown), and may fall onto the semiconductor wafer 10 due to a change in internal pressure, thereby causing the process to fail. -
FIG. 5 is a sectional view illustrating the generation of particulates in a process chamber used for a deposition process.FIG. 5 shows a wafer support portion of a process chamber for chemical vapor deposition (CVD).FIG. 6 is an enlarged view of the portion C ofFIG. 5 . - Referring to
FIGS. 5 and 6 , asemiconductor wafer 10 is seated on awafer chuck 50, and aheater 51 is placed below thewafer chuck 50. Thesemiconductor wafer 10 is guided by anannular guide ring 52 placed around the edge of thewafer chuck 50. However, because a space d between theguide ring 52 and thewafer chuck 50 is very narrow, a reaction gas is stagnant in the space d and does not flow smoothly therein. As a result, the reaction gases staying in the space d react with each other abnormally, which results in the growth of anundesirable material layer 53. Thematerial layer 53 may undesirably contaminate thewafer 10. - As described above, a process chamber used for etching or deposition produces particulates for various reasons, increasing the likelihood of failure of the semiconductor devices on
wafer 10. Thus, it would be desirable to prevent such a failure by eliminating factors which may cause the generation of particulates in the process chamber during the manufacturing of the devices. - Consistent with the present invention, a process chamber for use in the manufacture of a semiconductor device, changes the structure or material of the process chamber to suppress generation of particulates.
- In one aspect, a process chamber used in the manufacture of semiconductor device for etching a material on a semiconductor wafer using plasma includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds a side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The distance between the side of the semiconductor wafer and the first side is preferably less than 0.15 mm.
- In another aspect, a process chamber used in the manufacture of a semiconductor device for etching a material on a semiconductor wafer using plasma includes an electrostatic chuck for holding the semiconductor wafer, and an annular focus ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position and to make the plasma distribution uniform by drawing the plasma. The annular focus ring has a first side which faces the side of the semiconductor wafer and contacts the side of the semiconductor wafer.
- In another aspect, a process chamber used in the manufacture of a semiconductor device for etching a material on a semiconductor wafer using plasma includes an electrostatic chuck for holding the semiconductor wafer, a gas supply conduit, installed facing the upper surface of the semiconductor wafer, for supplying reaction gases to the upper space of the semiconductor wafer, wherein the gas supply conduit formed is slanted at a first angle with respect to the vertical direction, such that relatively more reaction gases are provided to a center of the semiconductor wafer than to a periphery of the semiconductor wafer, and a radio frequency power source for forming plasma in the upper space of the semiconductor wafer by ionizing the supplied reaction gases.
- In another aspect, a process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer using plasma includes an electrostatic chuck for holding the semiconductor wafer, a slit valve, attached to a sidewall of the process chamber and separated by a first distance from the electrostatic chuck, having a wafer transfer path through which the semiconductor wafer placed above the electrostatic chuck can be loaded or unloaded in the horizontal direction from or to the outside of the process chamber, wherein the temperature of the slit valve is maintained at a higher temperature than the sidewall of the process chamber during an etching process.
- In another aspect, a process chamber used in the manufacture of a semiconductor device for depositing a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, a heater installed below the wafer chuck, for supplying heat, and a guide ring for guiding the semiconductor wafer, the guide ring installed at the edge of an upper surface of the wafer chuck and separated from the chuck by about 15-25 mm.
- The above object and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
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FIG. 1 is a sectional view of a wafer support portion in a conventional process chamber used in the manufacture of a semiconductor device; -
FIG. 2 is an enlarged sectional view of the portion A shown inFIG. 1 ; -
FIG. 3 is a plan view ofFIG. 1 ; -
FIG. 4 is a sectional view of another example of a wafer support portion in a conventional process chamber used in the manufacture of a semiconductor device; -
FIG. 5 is a sectional view of yet another example of a wafer support portion in a conventional process chamber used in the manufacture of a semiconductor device; -
FIG. 6 is an enlarged sectional view of the portion C ofFIG. 5 ; -
FIG. 7 is a sectional view of a wafer support portion in a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention; -
FIG. 8 is an enlarged sectional view of the portion D inFIG. 7 ; -
FIG. 9 is a plan view ofFIG. 7 ; -
FIG. 10 is a sectional view of a wafer support portion in a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention; -
FIG. 11 is a sectional view showing a focus ring used in a process chamber in accordance with an aspect of the present invention; -
FIG. 12 is a graph showing the adhering condition of polymer and the amount of adhering polymer with respect to the temperature across the surface of the focus ring shown inFIG. 11 ; -
FIG. 13 is a sectional view showing a sidewall of a process chamber in accordance with an aspect of the present invention; -
FIG. 14 is a sectional view showing a gas supply portion in a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention; -
FIG. 15 is a sectional view showing a part of a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention; -
FIG. 16 is a graph comparatively showing the amount of particulates generated in the processor chamber ofFIG. 15 and in a conventional processor chamber; -
FIG. 17 is a sectional view of a wafer support portion in a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention; -
FIG. 18 is an enlarged view of the portion E ofFIG. 17 ; -
FIG. 19 is a plan view ofFIG. 17 ; -
FIG. 20 is a plan view showing another example of the guide ring ofFIG. 17 ; and -
FIGS. 21A and 21B are graphs comparatively showing the amount of particulates generated in a conventional process chamber and the process chamber ofFIG. 17 . - The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In addition, Korean application nos. 98-39486 and 99-22541, filed Sep. 23, 1998 and Jun. 16, 1999, respectively, are hereby incorporated by reference as if fully set forth herein.
- In accordance with more preferred embodiments of the present invention, the annular edge ring has a first side which faces the side of the semiconductor wafer and contacts the side of the semiconductor wafer. The edge ring preferably has a first upper surface which overlaps the periphery of the bottom surface of the semiconductor wafer and contacts the bottom surface of the semiconductor wafer. Also, the edge ring may have a second side facing the side of the electrostatic chuck, the second side having a shape such that the contact area between the second side and the side of the electrostatic chuck is minimal. To minimize the contact area, the second side of the edge ring may be slanted such that only the edge of the second side contacts the side of the electrostatic chuck. Also, the edge ring may be fixed such that the edge ring cannot rotate. In this case, the edge ring may be fixed by a fixing pin, and may be fixed at two or more points separated from each other by a maximum distance.
- The edge ring is preferably made of quartz, silicon or aluminum nitride. Also, the process chamber may further comprise a focus ring formed around the edge ring to make distribution of the plasma uniform.
- The focus ring preferably has a first upper surface which overlaps the periphery of the bottom surface of the semiconductor wafer and contacts the bottom surface of the semiconductor wafer. Also, the focus ring may have a second side facing the side of the electrostatic chuck, and the second side preferably has a shape such that the contact area between the second side and the side of the electrostatic chuck is minimal. To minimize the contact area, the second side of the focus ring may be slanted such that only the edge of the second side contacts the side of the electrostatic chuck.
- The focus ring is preferably fixed such that the edge ring cannot rotate. Also, the edge ring may be fixed by a fixing pin. In this case, the focus ring may be fixed at two or more points separated from each other by a maximum distance. Preferably, the focus ring is made of quartz, silicon or aluminum nitride.
- Preferably, the surface temperature of the focus ring is maintained to be above at least 50° C. across the entire surface of the focus ring during a reaction. To achieve this, the upper surface of the focus ring is preferably flat without protrusions, and the upper surface, which is the farthest away from a heat source, is maintained to be above the surface temperature. In this case, the thickness of the focus ring, from the flat upper surface to the base thereof, may be equal to or less than 20 mm.
- The slant angle of the gas supply path in the vertical direction is preferably at least 2 degrees, and the gas supply plate is preferably formed of quartz, silicon or aluminum nitride.
- Heat transfer lines are preferably formed to pass near the slit valve, and the number of the heat transfer lines formed near the slit valve is larger than the number of heat transfer lines formed passing through the sidewall. Also, the temperature of the upper part of the sidewall, which is positioned above the wafer transfer path, is the same as or higher than that of the lower part of the sidewall.
- Preferably, the inner circumference of the guide ring comprises a first portion protruding toward the semiconductor wafer and separated from the semiconductor wafer by a first interval, and a second portion separated from the semiconductor wafer by a second interval which is longer than the first interval, to guide the semiconductor wafer. In this case, the first interval may be 0.5-1.0 mm, and the second interval may be 2-30 mm.
- In a process chamber for etching using plasma in accordance with aspects of the present invention, the edge ring (or focus ring) and a semiconductor wafer preferably contact each other firmly, such that the plasma cannot enter below the bottom surface of the semiconductor wafer, thereby suppressing generation of particulates. Also, because the contact area between the edge ring (or focus ring) and the electrostatic chuck is minimized, the edge ring (or focus ring) can be easily separated from the electrostatic chuck even when particulates are generated. Also, the edge ring (or focus ring) is preferably fixed, so that bumping into the semiconductor wafer due to rotation of the edge ring can be prevented. Also, by changing the temperature distribution in the process chamber or the materials used for the process chamber, the generation of particulates, which depends on the temperature and materials of the process chamber, can be reduced such that the effect of the particulates on the semiconductor wafer can be minimized.
- In a process chamber for CVD, the space between the guide ring and the wafer chuck can be maintained at a predetermined level such that reaction gases flow smoothly in the space, thereby suppressing the deposition of a foreign layer by reaction gases in the space between the guide ring and wafer chuck.
-
FIG. 7 is a sectional view of an electrostatic chuck for supporting a semiconductor wafer in a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention.FIG. 8 is an enlarged sectional view of the edge (portion D) of the semiconductor wafer ofFIG. 7 , andFIG. 9 is a plan view ofFIG. 7 . - Referring to
FIG. 7 , anelectrostatic chuck 200 holds asemiconductor wafer 100 by electrostatic adsorption. A power supply (not shown) for supplying a high voltage is connected to theelectrostatic chuck 200 in order to induce static electricity. Lift pins 210 for moving thesemiconductor wafer 100 up and down when loading or unloading thesemiconductor wafer 100, pass through the center of theelectrostatic chuck 200. The lift pins 210 are in contact with asupport plate 220 installed below theelectrostatic chuck 200. Thesupport plate 220 can move upwards in response to a force applied by an external lifter (not shown), in a direction indicated by anarrow 230. The lift pins 210 move upwards in response to upward movement of thesupport plate 220. Then, the lift pins 210 protrude past the surface of theelectrostatic chuck 200 and thesemiconductor wafer 100 supported by the lift pins 210 is separated from the surface of theelectrostatic chuck 200. - Edge rings 240 are installed at the upper edge of the
electrostatic chuck 200 to fix thesemiconductor wafer 100. Also, acoupling ring 270 made of, for example, aluminum (Al), is interposed between theedge ring 240 and theelectrostatic chuck 200. Thesemiconductor wafer 100 is surrounded by afocus ring 280. Thefocus ring 280 draws a plasma forming region to the edge of thesemiconductor wafer 100 during the etching process, such that the plasma forming region is uniformly formed across thesemiconductor wafer 100. - As shown in
FIG. 8 , there is almost no gap between theedge ring 240 and thesemiconductor wafer 100. Such a gap between theedge ring 240 and thesemiconductor wafer 100 can be reduced to about 0.1-0.15 mm. However, it is preferable to reduce the gap as much as possible. Also, a space between theedge ring 240 and the periphery of the bottom surface of thesemiconductor wafer 100 is reduced to a minimal distance. By minimizing the distance between theedge ring 240 and thesemiconductor wafer 100, infiltration of parasitic plasma into the space between theedge ring 240 and the bottom surface of thesemiconductor wafer 100 can be suppressed as much as possible. Further, the edge of theedge ring 240, which contacts theelectrostatic chuck 200, is preferably slanted, forming a triangular space at the contact region. As a result, only one edge point of theedge ring 240 contacts theelectrostatic chuck 200, so that the contact area between the edge ring and theelectrostatic chuck 200 is minimized. Alternatively, the edge of the chuck may be slanted to create the triangular space. Thus, even when polymers accumulate at the periphery of the bottom surface of thesemiconductor wafer 100, a binding area between theedge ring 240 and theelectrostatic chuck 200 by the polymers is minimized, so that theedge ring 240 can be easily separated from thesemiconductor wafer 100. - Also, as shown in
FIG. 9 , theedge ring 240 is preferably fixed to thecoupling ring 270 or the electrostatic chuck 200 (seeFIGS. 7 and 8 ) by fixingpins 290. The rotation of theedge ring 240 is prevented by the fixingpin 290, so that damage to the semiconductor wafer, which may occur by the rotation of theedge ring 240, can also be prevented. -
FIG. 10 is a sectional view of an electrostatic chuck for supporting a semiconductor wafer in a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention. The process chamber ofFIG. 10 is different from that ofFIG. 7 in that only a focus ring is used without an edge ring. - Referring to
FIG. 10 , anelectrostatic chuck 310 holds asemiconductor wafer 300 by electrostatic adsorption. A power supply (not shown) for supplying a high voltage is connected to theelectrostatic chuck 310 in order to induce static electricity, and lift pins (not shown) which are moved when loading or unloading thesemiconductor wafer 100, pass through theelectrostatic chuck 310. Also, anannular focus ring 320 is installed around the edge of theelectrostatic chuck 310. Thefocus ring 320 draws a plasma forming region to the edge of thesemiconductor wafer 300 during the etching process, such that the plasma forming region is uniformly formed across thesemiconductor wafer 300. Thefocus ring 320 can also fix thesemiconductor wafer 300. - In the case of only using the focus ring without the edge ring, as mentioned above, the gap between the
focus ring 320 and thesemiconductor wafer 300 and the space between thefocus ring 320 and the periphery of the bottom surface of thesemiconductor wafer 300 are both minimized. Also, the edge of thefocus ring 320, facing the upper side of theelectrostatic chuck 310, is preferably slanted to reduce the contact area between thefocus ring 320 and theelectrostatic chuck 310 as much as possible. Alternatively, the edge of the chuck may be slanted to create the triangular space. By doing so, the area between thefocus ring 320 and theelectrostatic chuck 310, which is bound by polymers can be minimized, so that thefocus ring 320 can be easily separated from theelectrostatic chuck 310 without damage to thefocus ring 320. Also, thefocus ring 320 is fixed to theelectrostatic chuck 310 by fixingpins 330. Because thefocus ring 320 is fixed, thefocus ring 320 does not rotate even though thefocus ring 320 is spaced further apart from thesemiconductor wafer 300. As a result, bumping of thefocus ring 320 into the semiconductor wafer can be minimized or prevented. - In general, the upper surface of the
focus ring 320 is partially etched during the etching process, so that the lifetime of thefocus ring 320 is shortened. In general, because the thickness d1 of thefocus ring 320 may affect the processing result, the thickness of thefocus ring 320 must be restricted. The thickness d1 of thefocus ring 320 which is widely in use, is approximately 3.6 mm. However, in the this embodiment, the thickness d1 of the focus ring was increased to approximately 4.5 mm. As a result, the lifetime of thefocus ring 320 was increased by about 2-3 times, without affecting the processing result. -
FIG. 11 shows a focus ring in a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention. Referring toFIG. 11 , afocus ring 420 used in a process chamber used in the manufacture of a semiconductor device is installed around the edge of theelectrostatic chuck 410 and has an annular shape, such that thefocus ring 420 is separated from the edge of thesemiconductor wafer 400 by a predetermined distance. However, aportion 420′ of thefocus ring 420 contacts firmly with the periphery of the bottom surface of thesemiconductor wafer 400 in order to prevent parasitic plasma from infiltrating into the space between the bottom surface of thesemiconductor wafer 400 and thefocus ring 420. The total height d2 of thefocus ring 420 is half that of the conventional focus ring. For example, assuming that the total height of the conventional focus ring from the base to the protruding portion is approximately 30 mm, the total height d2 of the focus ring used in a process chamber for manufacturing a semiconductor device can be less than 20 mm, preferably approximately 15 mm. That is, as shown inFIG. 11 , the upper surface of the focus ring can be flattened by removing the protruding portion from a conventional focus ring (drawn with dashed lines), such that the temperature distribution across the surface of thefocus ring 420 becomes uniform. In the case of adopting such a focus ring, the amount of polymer accumulated on the focus ring varies according to the difference in temperature of the focus ring. -
FIG. 12 is a graph showing the amount of adhered polymer with respect to the temperature at the surface of the focus ring. Referring toFIG. 12 , at a portion of the focus ring at below 50° C (hereinafter, referred to as portion A), the amount of adhered polymer is the largest and the adhering status is also very poor. Polymer also adheres to a portion of the focus ring at 50-55° C. (hereinafter, referred to as portion B). However, the amount of polymer adhering to the portion B is less than that adhering to the portion A, and the adhesion status is better than in the portion A. However, polymers do not adhere to a portion of the focus ring, at a temperature higher than 60° C. - The amount of polymers adhering to the focus ring and the adhesion status of the polymers vary according to the difference in temperature at the surface of the focus ring. The reason for the occurrence of a temperature difference in the focus ring is that the distance from a heat source to each portion of the focus ring is different. In general, a heater is installed below an electrostatic chuck as a heat source. Thus, the temperature of the focus ring is the highest at the base, and the temperature of the focus ring decreases toward the upper portion of the focus ring. Thus, the largest amount of polymers adheres to the upper protruding portion of the focus ring having the lowest temperature, and the adhesion status of the polymers at the upper portion is worst. In addition, a semiconductor wafer is placed adjacent to the protruding portion of the focus ring, and the semiconductor wafer can be deteriorated by the large amount of polymers which are poorly adhered to the focus ring. However, in the focus ring which is flattened by removing the upper protruding portion having the lowest temperature, the temperature can be evenly distributed over the focus ring. Here, the thickness of the focus ring is controlled such that the temperature of the focus ring is maintained at above 60° C., thereby reducing the amount of loosely adhered polymers.
- Such a change in the adhesion status of polymers due to the difference in temperature of each portion of the focus ring can be applied to other parts. The change in adhesion status of the polymer in other parts of the process chamber will be described with reference to
FIG. 13 . -
FIG. 13 is a sectional view showing a sidewall of a process chamber used for manufacturing a semiconductor device in accordance with an aspect of the present invention. Referring toFIG. 13 , aslit valve 520 for transferring asemiconductor wafer 560 is installed in asidewall 510 attached to anexternal wall 500 of the process chamber. Thesidewall 510 is formed of anodized aluminum (Al) andliners 520 a and 530 b are attached to thesidewall 510, facing the inner space of the process chamber. Theliners 520 a and 530 b are for preventing polymers from adhering to thesidewall 510 of the process chamber. Thesemiconductor wafer 560 is guided by afocus ring 550 placed on thewafer chuck 540, and theliners 520 a and 530 b are separated from thesemiconductor wafer 560 by a predetermined distance d3. In such a process chamber, a heater is placed below thewafer chuck 540 as a heat source. Thus, the temperatures of theliners 520 a and 530 b vary according to their height. For example, temperature of thelower liner 530 b, which is closer to the heater, is higher than that of theupper liner 530 b, which is farther from the heater. Thus, as described above, a larger amount of polymers accumulate on the upper liner 520 a than on thelower liner 530 b, and the adhesion status of polymers is poorer in the upper liner 520 a. If the upper liner 520 a is placed above a wafer transfer path, the polymer adhering to the upper liner 520 a may fall onto thesemiconductor wafer 560. Thus, by controlling the temperature of the upper liner 520 a so that is not lower than the temperature of thelower liner 530 b, the possibility of failure in the process can be lowered. In the same manner, the temperature of theslit valve 520, which forms the wafer transfer path, can be increased as much as possible, thereby preventing theslit valve 520 from being contaminated by the polymers. To accomplish this increase in temperature, more heat transfer lines passing near theslit valve 520 are installed than those passing through thesidewall 510 of the process chamber. -
FIG. 14 is a sectional view showing a gas supply portion used in a process chamber for manufacturing a semiconductor device in accordance with an aspect of the present invention. Referring toFIG. 14 , agas supply plate 600 is located in acover 610 of the process chamber. A gas supply line (not shown) for supplying gas is connected to the upper portion of thegas supply plate 600. A reaction gas, such as an etching gas, is supplied into the process chamber throughholes 620 formed in thegas supply plate 600. The energy of the etching gas supplied into the process chamber is increased by a high radio frequency (RF) power. High energy gas molecules collide with neighboring neutral molecules, generating electrons and ions. Due to repeated collisions, aplasma 630 is formed in the reaction chamber, and in particular, above thesemiconductor wafer 640. - In the etching process, the level of uniformity with which the
plasma 630 is distributed greatly affects the result of the process. That is, the distribution of theplasma 630 must be uniform in the space on thesemiconductor wafer 640. However, theplasma 630 can be drawn to the edge of thesemiconductor wafer 640 due to the focus ring formed around thesemiconductor wafer 640, so that theplasma 630 may be concentrated near the edge of thesemiconductor wafer 640. Thus, the structure of theholes 620 of thegas supply plate 600, which directly affects the distribution ofplasma 630, is changed such that the density of theplasma 630 is higher at the center than near the edge of thesemiconductor wafer 640. In particular, theholes 620 which pass through thegas supply plate 600 are slanted such that gas discharge portions thereof point toward the center of the semiconductor wafer. Preferably, the slant angle a of the gas discharge portions of theholes 620 with respect to the vertical direction, which is normal to a top surface of thesemiconductor wafer 640, of the gas supply line is can be about 2-5°. The vertical direction and the angle α are illustrated inFIG. 14 . If the angle a of the gas discharge portions of theholes 620 is too large, theplasma 630 is so dense at the center of the semiconductor substrate that theplasma 630 cannot be distributed uniformly. Because the reaction gas is supplied toward the center of thesemiconductor wafer 640, the plasma density is locally increased at the center. However, since the focus ring draws the plasma, the distribution of plasma becomes uniform. - The sidewall, gas supply plate, focus ring or edge ring of
FIGS. 7-14 can be made of, for example, quartz, silicon or aluminum nitride. That is, when a metal layer to be etched is formed of tungsten (W), SF3 is used as an etching gas for removing the tungsten layer, and Cl2 and BCl3 are used as etching gases for removing a barrier metal layer. In particular, SF6 gas leads to isotropic etching by a reaction with Al2O3 which is used to form a conventional focus ring, and increases etching damage by F ions, resulting in Al, F and O byproducts. However, the generation of byproducts can be suppressed by using quartz, silicon or aluminum nitride. -
FIG. 15 is a sectional view showing a part of a process chamber used in the manufacture of a semiconductor device in accordance with an aspect of the present invention. Referring toFIG. 15 , asemiconductor wafer 710 is seated on anelectrostatic chuck 720 in aprocess chamber 700. Theelectrostatic chuck 720 is placed on asupport stand 730. Asemiconductor wafer 710 is guided by anannular focus ring 740 formed around the edge of theelectrostatic chuck 720. Thefocus ring 740 also makes the density of plasma uniform across thesemiconductor wafer 710. Thefocus ring 740 for these functions has anupper portion 750. - The thickness d4 of the
upper portion 750 of thefocus ring 740 is controlled to be higher than the upper surface of thesemiconductor wafer 710. Preferably, the thickness d4 of theupper portion 750 is approximately 2.4-3.0 mm. If the thickness d4 of theupper portion 750 is more than 3 mm, a wafer transfer means, for example, a robotic arm (not shown), used to transfer thesemiconductor wafer 710, may contact theupper portion 750. If the thickness d4 of theupper portion 750 is less than 2.4 mm, the original function of theupper portion 750 is deteriorated, thereby shortening the lifetime of theupper portion 750. -
FIG. 16 is a graph comparatively showing the amount of particulates generated in a conventional process chamber and in a process chamber as shown inFIG. 15 . The conventional process chamber used for this comparison was a process chamber having a focus ring which has a wing extended in the vertical direction. - As shown in
FIG. 16 , the number of particulates generated in the process chamber according to the present invention is markedly reduced compared to the number of particulates generated in the conventional process.FIG. 17 is a sectional view of another process chamber used in manufacturing a semiconductor device in accordance with an aspect of the present invention, and in particular, showing a wafer support portion in a process chamber for chemical vapor deposition (CVD).FIG. 18 is an enlarged view of the portion E ofFIG. 17 , andFIG. 19 is a plan view ofFIG. 17 . - Referring to
FIGS. 17 through 19 , asemiconductor wafer 800 is seated on awafer chuck 810, and aheater 820 is installed below thewafer chuck 810. Also, anannular guide ring 830 is arranged around the edge of the upper surface of thewafer chuck 810. Theguide ring 830 is for preventing thesemiconductor wafer 800 from departing from its original position during the CVD process. For this, theguide ring 830 is separated by a predetermined distance, for example, about 0.1-1.0 mm, from thesemiconductor wafer 800. Theguide ring 830 is separated by a distance of approximately 15-25 mm from the upper surface of thewafer chuck 810, which allows reaction gases to flow smoothly in the space. As a result, the formation of an undesirable layer can be suppressed. -
FIG. 20 is a plan view showing another example of the guide ring shown inFIG. 17 . Referring toFIG. 20 , aguide ring 830′ is separated by a first interval, for example, about 2-30 mm, from asemiconductor wafer 800 around its inner circumference, which permits the reaction gas to flow smoothly in the space between thesemiconductor wafer 800 and theguide ring 830′. Also, to guide thesemiconductor wafer 800, a plurality ofprotrusions 831 are spaced around the inner circumstance of theguide ring 830′, and the plurality ofprotrusions 831 are separated by a second interval which is smaller than the first interval, for example, about 0.5-1.0 mm, from thesemiconductor wafer 800. -
FIG. 21A is a graph showing the number of particulates generated in a conventional process chamber with respect to the number of processed wafers, andFIG. 21B is a graph showing the number of particulates in a process chamber as shown inFIG. 17 with respect to the number of processed wafers. InFIGS. 21A and 21B , ♦ indicates the number of particulates having a diameter larger than 0.2 μm which are generated on the semiconductor wafer, and * indicates the number of particulates having a diameter larger than 0.2 μm which are generated in the process chamber. - Referring to
FIG. 21A , because the reaction gas cannot flow smoothly between a semiconductor wafer and a wafer chuck in the conventional process chamber, a cleaning process has to be performed using a predetermined cleaning gas, such as CIF3, after processing 500 sheets of semiconductor wafers. Nevertheless, when the number of processed semiconductor wafers reaches about 1000 sheets, a large amount of particulates are generated as shown inFIG. 21A . - However, referring to
FIG. 21B , in the process chamber according to the present invention, a small number of particulates are generated after 1000 or more sheets of semiconductor wafers are processed. Thus, an intermediate cleaning process is not required, thereby reducing the number of steps in processing.
Claims (15)
1-10. (canceled)
11. A process chamber used in the manufacture of a semiconductor device for etching a material on a semiconductor wafer using plasma, the process chamber comprising:
an electrostatic chuck for holding the semiconductor wafer; and
an annular focus ring, which surrounds a side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position and to make the plasma distribution uniform by drawing the plasma, having a first side which faces the side of the semiconductor wafer and contacts the side of the semiconductor wafers wherein the focus ring is fixed such that the focus ring cannot rotate.
12. The process chamber of claim 11 , wherein the focus ring has a first upper surface portion which overlaps the periphery of a bottom surface of the semiconductor wafer and contacts the bottom surface of the semiconductor wafer.
13. The process chamber of claim 12 , wherein the focus ring has a second upper surface portion which is higher than an upper surface of the semiconductor wafer.
14. The process chamber of claim 11 , wherein the focus ring has a second side facing a side of the electrostatic chuck, the second side of the edge ring having a shape such that the contact area between the second side and the side of the electrostatic chuck is minimal.
15. The process chamber of claim 14 , wherein the second side of the focus ring is slanted such that only the edge of the second side contacts the side of the electrostatic chuck.
16. (canceled)
17. The process chamber of claim 11 , wherein the focus ring is fixed by at least two fixing pins fixed at points separated from each other by a maximum distance.
18. The process chamber of claim 11 , wherein the focus ring contains a flat second upper surface portion.
19. The process chamber of claim 11 , wherein the edge ring comprises quartz, silicon or aluminum nitride.
20. The process chamber of claim 11 , wherein a surface temperature of the focus ring is maintained to be above at least 50° C. across the entire surface of the focus ring during etching.
21. The process chamber of claim 11 , wherein a surface temperature of the focus ring is maintained to be above or about 60° C. across the entire surface of the focus ring during etching.
22. The process chamber of claim 20 , wherein a second upper surface portion of the focus ring is flat without protrusions, and wherein the thickness of the focus ring is sufficient to maintain about the same temperature throughout the focus ring.
23. The process chamber of claim 22 , wherein a thickness of the focus ring from the flat upper surface to the base thereof is equal to or less than 20 mm.
24-42. (canceled)
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US11/506,833 US20060278341A1 (en) | 1998-09-23 | 2006-08-21 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
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US10/234,135 US20030000648A1 (en) | 1998-09-23 | 2002-09-05 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
US11/506,833 US20060278341A1 (en) | 1998-09-23 | 2006-08-21 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
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US10/234,135 Abandoned US20030000648A1 (en) | 1998-09-23 | 2002-09-05 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
US10/235,976 Expired - Fee Related US6797109B2 (en) | 1998-09-23 | 2002-09-06 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
US10/237,111 Abandoned US20030013315A1 (en) | 1998-09-23 | 2002-09-09 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
US11/506,833 Abandoned US20060278341A1 (en) | 1998-09-23 | 2006-08-21 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
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US10/235,976 Expired - Fee Related US6797109B2 (en) | 1998-09-23 | 2002-09-06 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
US10/237,111 Abandoned US20030013315A1 (en) | 1998-09-23 | 2002-09-09 | Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates |
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Also Published As
Publication number | Publication date |
---|---|
US6464794B1 (en) | 2002-10-15 |
US6797109B2 (en) | 2004-09-28 |
KR20000022645A (en) | 2000-04-25 |
KR100292410B1 (en) | 2001-06-01 |
US20030000648A1 (en) | 2003-01-02 |
US20030013315A1 (en) | 2003-01-16 |
US20030000459A1 (en) | 2003-01-02 |
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