US20070001264A1 - High performance integrated vertical transistors and method of making the same - Google Patents

High performance integrated vertical transistors and method of making the same Download PDF

Info

Publication number
US20070001264A1
US20070001264A1 US11/516,007 US51600706A US2007001264A1 US 20070001264 A1 US20070001264 A1 US 20070001264A1 US 51600706 A US51600706 A US 51600706A US 2007001264 A1 US2007001264 A1 US 2007001264A1
Authority
US
United States
Prior art keywords
layer
base
pnp
emitter
sige
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/516,007
Inventor
David Sheridan
Peter Gray
Jeffrey Johnson
Qizhi Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/516,007 priority Critical patent/US20070001264A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GRAY, PETER B., JOHNSON, JEFFREY B., LIU, QIZHI, SHERIDAN, DAVID C.
Publication of US20070001264A1 publication Critical patent/US20070001264A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66242Heterojunction transistors [HBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8228Complementary devices, e.g. complementary transistors
    • H01L21/82285Complementary vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826Combination of vertical complementary transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821Collector regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/737Hetero-junction transistors
    • H01L29/7371Vertical transistors
    • H01L29/7378Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Definitions

  • This invention relates to semiconductor integrated circuit devices, and specifically to integrated BICMOS vertical transistors, and a method for making the same. More specifically, the invention relates to a vertical PNP transistor, and a set of complementary vertical NPN and PNP transistors in a downward mode or collector down configuration.
  • Integrated circuit technologies are predominantly of the NPN type, generally without an available high-speed complementary PNP device. Circuit designers would certainly benefit from the inclusion of a complementary PNP device; however, in the development of a complementary PNP transistor, cost becomes a dominant factor. It has been a continuing technological challenge to integrate vertical PNP devices into a high performance NPN process without significantly degrading the performance of the NPN device.
  • a problem for complementary transistors using the same layers and process fabrication steps is that the mode of operation of the two devices is different, i.e., one operates in an upward direction and the other operates in a downward direction. This is due to the order of the material layers deposited and implanted with dopants for the emitter, base and collector regions of each transistor.
  • the Harame structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction.
  • the intrinsic vertical profiles for both the NPN and PNP transistors are formed by depositing a first layer of p-doped silicon and a second layer of n-doped silicon. These layers form the intrinsic base and collector regions for both the NPN and PNP transistors. The first layer forms the base and the second layer the collector for an NPN transistor operating in an upward direction.
  • Harame has two SiGe layers, one n-type and one p-type for forming the complementary pair of upward and downward transistors. In the present invention, only one SiGe layer is taught for two downward complementary transistors.
  • bipolar transistors are formed on a common substrate.
  • the transistors are vertical NPN and PNP transistors, which have identical structure and modes of operation with both devices operating in the downward direction.
  • the emitter region of the PNP transistor is not the same layer as the base region of the NPN transistor.
  • a further object of the invention is to provide a vertically aligned PNP transistor that shares its emitter layer with the base layer of a vertically aligned NPN transistor, and utilizes an epitaxial growth process to form a PNP base/collector region and NPN base/collector region where the PNP emitter layer is also used as the NPN base layer.
  • a semiconductor structure on a substrate comprising: a downwards operating vertical NPN transistor formed on the substrate and having an epitaxial extrinsic base region, an emitter region, and a collector region, and a downwards-operating vertical PNP transistor formed on the substrate having an epitaxial base region, an emitter region, and a collector region; wherein the base region of the vertical NPN transistor comprises a first portion of a first layer and the base region of the vertical PNP transistor comprises a second portion of the first layer.
  • the first layer may comprise epitaxial silicon germanium (SiGe).
  • the epitaxial SiGe may include a first dopant type, such as a p-type dopant.
  • a portion of the emitter of the PNP transistor may include a portion of the second portion of the first layer.
  • the intrinsic base of the NPN transistor may comprise the first portion of the first layer.
  • an extrinsic base of the NPN transistor may include a first portion of a second layer and the emitter of the PNP transistor may include a second portion of the second layer.
  • the present invention is directed to a semiconductor structure on a substrate comprising a downwards operating vertical PNP transistor formed on the substrate having a base region, an emitter region, and a collector region wherein the collector region of the vertical PNP transistor is formed on a same layer on the substrate as a collector region for a downwards operating vertical NPN transistor.
  • the present invention is directed to a method of fabricating complementary bipolar vertical NPN and PNP transistor structure in a wafer, having an NPN collector, base, and emitter region, and a PNP collector, base, and emitter region, the method comprising: forming a p-well and an n-region subcollector in the wafer along isolation trenches; implanting p+ and n+ collector reach through implants; applying a silicon germanium LTE layer and PNP base mask layer, wherein the silicon germanium LTE layer is formed on the p-well and the n-subcollector; forming a first photoresist mask to protect the p+ collector reach through implant, the n+ collector reach through implant, and the isolation trenches during implanting; implanting an n-type PNP base/collector within the silicon germanium LTE layer; patterning a barrier oxide etch stop layer over the silicon germanium LTE layer including patterning an opening in the etch stop layer over a PNP base/collector region and a portion
  • FIG. 1 depicts a cross-sectional view of a starting wafer for the present invention.
  • FIG. 2 depicts the vertical PNP transistor after the SiGe LTE layer and PNP base mask are applied.
  • FIG. 3 is depicts the vertical PNP transistor of FIG. 2 with an oxide layer patterned and formed over the SiGe LTE layer for the emitter opening.
  • FIG. 4 depicts the vertical PNP transistor of FIG. 3 with a polysilicon layer and barrier oxide layer applied.
  • FIG. 5 depicts the vertical PNP transistor of FIG. 4 after patterning and etching the emitter.
  • FIG. 6 depicts a nitride spacer formed on the sides of the PNP base/emitter of FIG. 5 .
  • FIG. 7 depicts a mask formed over the PNP emitter and a portion of the SiGe LTE layer up to the isolation trenches.
  • FIG. 8 depicts the vertical PNP transistor of FIG. 7 with the oxide layer removed.
  • FIG. 9 depicts the vertical PNP transistor patterned with a photoresist mask over the isolation trenches, with the exposed region implanted for an n+ extrinsic base.
  • FIG. 10 depicts the final vertical PNP structure with the emitter oxide removed and contacts deposited for the collector (c), base (b), and emitter (e).
  • FIG. 11 depicts the doping profile for the SiGe NPN and SiGe PNP transistors using the same LTE.
  • FIGS. 1-11 of the drawings in which like numerals refer to like features of the invention.
  • the present invention provides a complementary bipolar transistor fabricated using a shared silicon germanium (SiGe) low temperature epitaxial (LTE) layer, wherein the epitaxially deposited raised extrinsic base layer of the NPN transistor is also used for the PNP diffused emitter layer. Both the NPN and PNP base and emitter regions are fully or partially contained in the LTE layer. The collector region of the PNP and NPN transistors may be inside the LTE layer as well, although not necessitated. An available in-situ doped arsenic base polysilicon layer is used as the vertical PNP emitter layer.
  • SiGe silicon germanium
  • LTE low temperature epitaxial
  • the present invention utilizes advanced epitaxial techniques, such as molecular beam epitaxy (MBE) and low temperature epitaxy (LTE) by ultra high vacuum chemical vapor deposition (UHV/CVD) to provide identical vertical profiles.
  • MBE molecular beam epitaxy
  • LTE low temperature epitaxy
  • UHV/CVD ultra high vacuum chemical vapor deposition
  • Both the PNP and NPN transistors may share the same SiGe layer, which acts as the base layer for both transistors.
  • the p+ in-situ doped region of the SiGe layer acts as removed and contacts deposited for the collector (c), base (b), and emitter (e).
  • FIG. 11 depicts the doping profile for the SiGe NPN and SiGe PNP transistors using the same LTE.
  • FIGS. 1-11 of the drawings in which like numerals refer to like features of the invention.
  • the present invention provides a complementary bipolar transistor fabricated using a shared silicon germanium (SiGe) low temperature epitaxial (LTE) layer, wherein the epitaxially deposited raised extrinsic base layer of the NPN transistor is also used for the PNP diffused emitter layer. Both the NPN and PNP base and emitter regions are fully or partially contained in the LTE layer. The collector region of the PNP and NPN transistors may be inside the LTE layer as well, although not necessitated. An available in-situ doped arsenic base polysilicon layer is used as the vertical PNP emitter layer.
  • SiGe silicon germanium
  • LTE low temperature epitaxial
  • the present invention utilizes advanced epitaxial techniques, such as molecular beam epitaxy (MBE) and low temperature epitaxy (LTE) by ultra high vacuum chemical vapor deposition (UHV/CVD) to provide identical vertical profiles.
  • MBE molecular beam epitaxy
  • LTE low temperature epitaxy
  • UHV/CVD ultra high vacuum chemical vapor deposition
  • Both the PNP and NPN transistors may share the same SiGe layer, which acts as the base layer for both transistors.
  • the p+ in-situ doped region of the SiGe layer acts as the base for the NPN and part of the emitter for the PNP transistor.
  • the PNP and NPN transistors may share a silicon/polysilicon layer instead of a SiGe layer, where the extrinsic base of the NPN is formed on the same silicon/polysilicon layer as the emitter of the PNP transistor.
  • the PNP base and collector profile are obtained through selective implantation using an added mask.
  • the PNP emitter profile diffusion is simultaneously optimized with the NPN extrinsic base diffusion, ensuring the intrinsic p-type base is sufficiently covered by the out-diffusion from the p-type emitter polysilicon.
  • Using the SiGe LTE layer enables a higher breakdown PNP and additional capability for collector design.
  • FIGS. 1-10 depict cross-sectional views showing the method of making the vertical PNP transistor, or the complementary NPN and PNP transistors on a common substrate for the present invention.
  • FIG. 1 depicts a cross-sectional view of a starting wafer 10 for the present invention.
  • a p-well 12 is established in the wafer along with isolation trenches 14 and p+ implants 16 for collector contacts.
  • Wells and buried layer regions are formed from methods well know in the semiconductor industry.
  • the planar shallow or deep trench isolation structures are formed to isolate the active device regions. These isolation regions are preferably formed by a conventional low temperature deep trench process, wherein a masking layer, such as silicon nitride, is deposited on the surface of the substrate, and windows are etched in the region.
  • FIG. 1 depicts a cross-sectional view of a starting wafer 10 for the present invention.
  • a p-well 12 is established in the wafer along with isolation trenches 14 and p+ implants 16 for collector contacts.
  • FIG. 2 depicts the vertical PNP transistor after the SiGe LTE layer 18 and PNP base mask are applied.
  • the silicon germanium LTE layer 18 is formed on the prepared p-well.
  • a photoresist mask 20 is formed to protect the p+ source/drain implants 16 and the isolation trenches 14 during implanting.
  • An n-type PNP base/collector 22 is implanted within the SiGe LTE layer 18 .
  • an oxide layer 24 is then patterned and formed over the SiGe LTE layer 18 with a space 26 over the PNP base/collector 22 .
  • a p+ polysilicon layer 28 is then grown or deposited over the etch stop layer 24 .
  • This p+ polysilicon layer 28 is in-situ doped, and represents the emitter for the vertical PNP transistor and the extrinsic base of the NPN transistor.
  • a barrier oxide 30 is then deposited on the p+ emitter polysilicon layer 28 .
  • FIG. 5 depicts the vertical PNP transistor after patterning and etching of the emitter.
  • a photoresist mask 32 is formed over the barrier oxide layer 30 and the unprotected portions of the p+ polysilicon layer 28 and oxide layer 30 are removed by etching to the etch stop layer 24 . In this manner, the PNP base/emitter is patterned. Importantly, the mask is the same as that used for an NPN transistor extrinsic base formation, and does not require any extra process steps at this stage for the complementary PNP version.
  • a nitride spacer 34 is then formed on the sides of the PNP base/emitter, as shown in FIG. 6 .
  • FIG. 7 shows a mask 36 formed over the PNP-base/emitter and a portion of the SiGe LTE layer up to the isolation trenches 14 .
  • the unprotected portions of the SiGe LTE layer 18 and the etch stop layer 24 are removed by a second etch process.
  • the PNP base/collector 22 spans the length between the isolation trenches 14 within the SiGe LTE layer.
  • FIG. 8 depicts the vertical PNP transistor with the LE oxide layer removed.
  • the transistor is again patterned with a photoresist mask 38 over the isolation trenches, and the exposed region 40 is implanted for an n+ extrinsic base.
  • FIG. 10 depicts the final vertical PNP structure 100 with the emitter oxide removed and contacts deposited for the collector (c), base (b), and emitter (e).
  • the contact regions are defined and opened by removing the appropriate portions of the oxide layer.
  • a metallization step is then used to form the contacts.
  • the polysilicon layer is capable of forming a raised external base for an NPN configuration, or an emitter in a PNP configuration, or both.
  • a portion of the emitter may be formed intrinsically from the base layer of the NPN, which is part of the SiGe LTE layer.
  • the Germanium layer includes the p+ base of the NPN when the intrinsic base polysilicon layer of the NPN forms the emitter for the vertical PNP.
  • the base regions of the PNP and NPN transistors comprise the same SiGe LTE layer.
  • the SiGe LTE layer is preferably of a p-type dopant.
  • FIG. 11 depicts the doping profile for the SiGe NPN and SiGe PNP transistors using the same LTE.
  • the boron base represents the in-situ boron layer that acts as the NPN base and part of the PNP emitter. Doping as a function of depth is illustrated for the NPN transistor and compared to the PNP.
  • the complementary bipolar transistor structure of the invention is fabricated such that the NPN and PNP transistors both operate in a downward fashion while sharing the same SiGe layer.
  • the low temperature epitaxial techniques of MBE and LTE allow for the desired downward direction of the transistors' operation.

Abstract

A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention relates to semiconductor integrated circuit devices, and specifically to integrated BICMOS vertical transistors, and a method for making the same. More specifically, the invention relates to a vertical PNP transistor, and a set of complementary vertical NPN and PNP transistors in a downward mode or collector down configuration.
  • 2. Description of Related Art
  • Integrated circuit technologies are predominantly of the NPN type, generally without an available high-speed complementary PNP device. Circuit designers would certainly benefit from the inclusion of a complementary PNP device; however, in the development of a complementary PNP transistor, cost becomes a dominant factor. It has been a continuing technological challenge to integrate vertical PNP devices into a high performance NPN process without significantly degrading the performance of the NPN device. A problem for complementary transistors using the same layers and process fabrication steps is that the mode of operation of the two devices is different, i.e., one operates in an upward direction and the other operates in a downward direction. This is due to the order of the material layers deposited and implanted with dopants for the emitter, base and collector regions of each transistor.
  • One prior art example of a complementary transistor structure is found in U.S. Pat. No. 4,997,776 issued to Harame, et al., on Mar. 5, 1991 entitled, “COMPLEMENTARY BIPOLAR TRANSISTOR STRUCTURE AND METHOD FOR MANUFACTURE.” The Harame structure includes a vertical NPN transistor operating in the upward direction and a vertical PNP transistor operating in a downward direction. The intrinsic vertical profiles for both the NPN and PNP transistors are formed by depositing a first layer of p-doped silicon and a second layer of n-doped silicon. These layers form the intrinsic base and collector regions for both the NPN and PNP transistors. The first layer forms the base and the second layer the collector for an NPN transistor operating in an upward direction. Simultaneously, the second layer forms the base and the first layer forms the collector for a PNP transistor operating in a downward direction. Importantly, Harame has two SiGe layers, one n-type and one p-type for forming the complementary pair of upward and downward transistors. In the present invention, only one SiGe layer is taught for two downward complementary transistors.
  • In U.S. Pat. No. 5,930,635 issued to Bashir, et al., on Jul. 27, 1999 entitled, “COMPLEMENTARY SI/SIGE HETEROJUNCTION BIPOLAR TECHNOLOGY,” bipolar transistors are formed on a common substrate. The transistors are vertical NPN and PNP transistors, which have identical structure and modes of operation with both devices operating in the downward direction. However, the emitter region of the PNP transistor is not the same layer as the base region of the NPN transistor.
  • Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a complementary pair of transistors that are vertically aligned and operate in a single direction.
  • It is another object of the present invention to provide vertical transistors that share a single layer to form the extrinsic base of an NPN transistor and an emitter of a PNP transistor.
  • A further object of the invention is to provide a vertically aligned PNP transistor that shares its emitter layer with the base layer of a vertically aligned NPN transistor, and utilizes an epitaxial growth process to form a PNP base/collector region and NPN base/collector region where the PNP emitter layer is also used as the NPN base layer.
  • It is yet another object of the present invention to provide a method of making vertical transistors where the base layer for the NPN and PNP transistors are in the same SiGe LTE layer.
  • Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
  • SUMMARY OF THE INVENTION
  • The above and other objects, which will be apparent to those skilled in art, are achieved in the present invention, which in a first aspect is directed to a semiconductor structure on a substrate comprising: a downwards operating vertical NPN transistor formed on the substrate and having an epitaxial extrinsic base region, an emitter region, and a collector region, and a downwards-operating vertical PNP transistor formed on the substrate having an epitaxial base region, an emitter region, and a collector region; wherein the base region of the vertical NPN transistor comprises a first portion of a first layer and the base region of the vertical PNP transistor comprises a second portion of the first layer. The first layer may comprise epitaxial silicon germanium (SiGe). The epitaxial SiGe may include a first dopant type, such as a p-type dopant. A portion of the emitter of the PNP transistor may include a portion of the second portion of the first layer. The intrinsic base of the NPN transistor may comprise the first portion of the first layer. Additionally, an extrinsic base of the NPN transistor may include a first portion of a second layer and the emitter of the PNP transistor may include a second portion of the second layer.
  • In a second aspect, the present invention is directed to a semiconductor structure on a substrate comprising a downwards operating vertical PNP transistor formed on the substrate having a base region, an emitter region, and a collector region wherein the collector region of the vertical PNP transistor is formed on a same layer on the substrate as a collector region for a downwards operating vertical NPN transistor.
  • In a third aspect, the present invention is directed to a method of fabricating complementary bipolar vertical NPN and PNP transistor structure in a wafer, having an NPN collector, base, and emitter region, and a PNP collector, base, and emitter region, the method comprising: forming a p-well and an n-region subcollector in the wafer along isolation trenches; implanting p+ and n+ collector reach through implants; applying a silicon germanium LTE layer and PNP base mask layer, wherein the silicon germanium LTE layer is formed on the p-well and the n-subcollector; forming a first photoresist mask to protect the p+ collector reach through implant, the n+ collector reach through implant, and the isolation trenches during implanting; implanting an n-type PNP base/collector within the silicon germanium LTE layer; patterning a barrier oxide etch stop layer over the silicon germanium LTE layer including patterning an opening in the etch stop layer over a PNP base/collector region and a portion of the etch stop layer over the NPN base/collector region; growing a p+ polysilicon or p+ silicon layer over the etch stop layer; depositing a barrier oxide layer on the p+ polysilicon or p+ silicon layer; patterning and etching the barrier oxide layer over the NPN base/collector layer; depositing an n+ polysilicon layer or n+ silicon layer over the barrier oxide layer; patterning and etching the n+ polysilicon or n+ silicon layer; forming a second photoresist mask over the barrier oxide layer and unprotected portions of the p+ polysilicon layer or p+ silicon layer, and removing portions of the oxide layer by etching to the etch stop layer; forming a nitride spacer on sides of the PNP base and emitter and the NPN base and emitter; forming a mask over the PNP base and emitter, the NPN base and emitter, and a portion of the silicon germanium LTE layer up to the isolation trenches; removing unprotected portions of the silicon germanium LTE layer and the etch stop layer by a etch process; removing the etch stop layer to expose the silicon germanium LTE layer in all remaining areas except where the PNP and NPN bases and emitters reside; patterning the structure with a third photoresist mask over the isolation trenches; implanting exposed regions for an n+ region for the PNP extrinsic base; and depositing contacts for collectors, bases, and emitters of the PNP and NPN structures.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
  • FIG. 1 depicts a cross-sectional view of a starting wafer for the present invention.
  • FIG. 2 depicts the vertical PNP transistor after the SiGe LTE layer and PNP base mask are applied.
  • FIG. 3 is depicts the vertical PNP transistor of FIG. 2 with an oxide layer patterned and formed over the SiGe LTE layer for the emitter opening.
  • FIG. 4 depicts the vertical PNP transistor of FIG. 3 with a polysilicon layer and barrier oxide layer applied.
  • FIG. 5 depicts the vertical PNP transistor of FIG. 4 after patterning and etching the emitter.
  • FIG. 6 depicts a nitride spacer formed on the sides of the PNP base/emitter of FIG. 5.
  • FIG. 7 depicts a mask formed over the PNP emitter and a portion of the SiGe LTE layer up to the isolation trenches.
  • FIG. 8 depicts the vertical PNP transistor of FIG. 7 with the oxide layer removed.
  • FIG. 9 depicts the vertical PNP transistor patterned with a photoresist mask over the isolation trenches, with the exposed region implanted for an n+ extrinsic base.
  • FIG. 10 depicts the final vertical PNP structure with the emitter oxide removed and contacts deposited for the collector (c), base (b), and emitter (e).
  • FIG. 11 depicts the doping profile for the SiGe NPN and SiGe PNP transistors using the same LTE.
  • DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
  • In describing the preferred embodiment of the present invention, reference will be made herein to FIGS. 1-11 of the drawings in which like numerals refer to like features of the invention.
  • The present invention provides a complementary bipolar transistor fabricated using a shared silicon germanium (SiGe) low temperature epitaxial (LTE) layer, wherein the epitaxially deposited raised extrinsic base layer of the NPN transistor is also used for the PNP diffused emitter layer. Both the NPN and PNP base and emitter regions are fully or partially contained in the LTE layer. The collector region of the PNP and NPN transistors may be inside the LTE layer as well, although not necessitated. An available in-situ doped arsenic base polysilicon layer is used as the vertical PNP emitter layer. The present invention utilizes advanced epitaxial techniques, such as molecular beam epitaxy (MBE) and low temperature epitaxy (LTE) by ultra high vacuum chemical vapor deposition (UHV/CVD) to provide identical vertical profiles. Both the PNP and NPN transistors may share the same SiGe layer, which acts as the base layer for both transistors. In this embodiment, the p+ in-situ doped region of the SiGe layer acts as removed and contacts deposited for the collector (c), base (b), and emitter (e).
  • FIG. 11 depicts the doping profile for the SiGe NPN and SiGe PNP transistors using the same LTE.
  • Description of the Preferred Embodiment(s)
  • In describing the preferred embodiment of the present invention, reference will be made herein to FIGS. 1-11 of the drawings in which like numerals refer to like features of the invention.
  • The present invention provides a complementary bipolar transistor fabricated using a shared silicon germanium (SiGe) low temperature epitaxial (LTE) layer, wherein the epitaxially deposited raised extrinsic base layer of the NPN transistor is also used for the PNP diffused emitter layer. Both the NPN and PNP base and emitter regions are fully or partially contained in the LTE layer. The collector region of the PNP and NPN transistors may be inside the LTE layer as well, although not necessitated. An available in-situ doped arsenic base polysilicon layer is used as the vertical PNP emitter layer. The present invention utilizes advanced epitaxial techniques, such as molecular beam epitaxy (MBE) and low temperature epitaxy (LTE) by ultra high vacuum chemical vapor deposition (UHV/CVD) to provide identical vertical profiles. Both the PNP and NPN transistors may share the same SiGe layer, which acts as the base layer for both transistors. In this embodiment, the p+ in-situ doped region of the SiGe layer acts as the base for the NPN and part of the emitter for the PNP transistor.
  • Additionally, the PNP and NPN transistors may share a silicon/polysilicon layer instead of a SiGe layer, where the extrinsic base of the NPN is formed on the same silicon/polysilicon layer as the emitter of the PNP transistor.
  • The PNP base and collector profile are obtained through selective implantation using an added mask. The PNP emitter profile diffusion is simultaneously optimized with the NPN extrinsic base diffusion, ensuring the intrinsic p-type base is sufficiently covered by the out-diffusion from the p-type emitter polysilicon. Using the SiGe LTE layer enables a higher breakdown PNP and additional capability for collector design.
  • FIGS. 1-10 depict cross-sectional views showing the method of making the vertical PNP transistor, or the complementary NPN and PNP transistors on a common substrate for the present invention. FIG. 1 depicts a cross-sectional view of a starting wafer 10 for the present invention. A p-well 12 is established in the wafer along with isolation trenches 14 and p+ implants 16 for collector contacts. Wells and buried layer regions are formed from methods well know in the semiconductor industry. The planar shallow or deep trench isolation structures are formed to isolate the active device regions. These isolation regions are preferably formed by a conventional low temperature deep trench process, wherein a masking layer, such as silicon nitride, is deposited on the surface of the substrate, and windows are etched in the region. FIG. 2 depicts the vertical PNP transistor after the SiGe LTE layer 18 and PNP base mask are applied. In a similar fashion to the development of an NPN transistor, the silicon germanium LTE layer 18 is formed on the prepared p-well. A photoresist mask 20 is formed to protect the p+ source/drain implants 16 and the isolation trenches 14 during implanting. An n-type PNP base/collector 22 is implanted within the SiGe LTE layer 18.
  • As depicted in FIG. 3, an oxide layer 24 is then patterned and formed over the SiGe LTE layer 18 with a space 26 over the PNP base/collector 22. As shown in FIG. 4, a p+ polysilicon layer 28 is then grown or deposited over the etch stop layer 24. This p+ polysilicon layer 28 is in-situ doped, and represents the emitter for the vertical PNP transistor and the extrinsic base of the NPN transistor. A barrier oxide 30 is then deposited on the p+ emitter polysilicon layer 28.
  • FIG. 5 depicts the vertical PNP transistor after patterning and etching of the emitter. A photoresist mask 32 is formed over the barrier oxide layer 30 and the unprotected portions of the p+ polysilicon layer 28 and oxide layer 30 are removed by etching to the etch stop layer 24. In this manner, the PNP base/emitter is patterned. Importantly, the mask is the same as that used for an NPN transistor extrinsic base formation, and does not require any extra process steps at this stage for the complementary PNP version. A nitride spacer 34 is then formed on the sides of the PNP base/emitter, as shown in FIG. 6.
  • FIG. 7 shows a mask 36 formed over the PNP-base/emitter and a portion of the SiGe LTE layer up to the isolation trenches 14. The unprotected portions of the SiGe LTE layer 18 and the etch stop layer 24 are removed by a second etch process. As shown, the PNP base/collector 22 spans the length between the isolation trenches 14 within the SiGe LTE layer.
  • The oxide layer is then removed to expose the SiGe LTE layer 18 in all remaining areas except under the emitter and outside the nitride spacer. FIG. 8 depicts the vertical PNP transistor with the LE oxide layer removed. As shown in FIG. 9, the transistor is again patterned with a photoresist mask 38 over the isolation trenches, and the exposed region 40 is implanted for an n+ extrinsic base.
  • FIG. 10 depicts the final vertical PNP structure 100 with the emitter oxide removed and contacts deposited for the collector (c), base (b), and emitter (e). The contact regions are defined and opened by removing the appropriate portions of the oxide layer. A metallization step is then used to form the contacts.
  • Importantly, the polysilicon layer is capable of forming a raised external base for an NPN configuration, or an emitter in a PNP configuration, or both. A portion of the emitter may be formed intrinsically from the base layer of the NPN, which is part of the SiGe LTE layer. The Germanium layer includes the p+ base of the NPN when the intrinsic base polysilicon layer of the NPN forms the emitter for the vertical PNP. Additionally, the base regions of the PNP and NPN transistors comprise the same SiGe LTE layer. The SiGe LTE layer is preferably of a p-type dopant.
  • FIG. 11 depicts the doping profile for the SiGe NPN and SiGe PNP transistors using the same LTE. In FIG. 11, the boron base represents the in-situ boron layer that acts as the NPN base and part of the PNP emitter. Doping as a function of depth is illustrated for the NPN transistor and compared to the PNP.
  • The complementary bipolar transistor structure of the invention is fabricated such that the NPN and PNP transistors both operate in a downward fashion while sharing the same SiGe layer. The low temperature epitaxial techniques of MBE and LTE allow for the desired downward direction of the transistors' operation.
  • While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention. The terms and expressions employed are terms of description not limitation, and there is no intention of using such terms to exclude any equivalents of the features shown and described, or portions thereof.

Claims (15)

1. A semiconductor structure on a substrate comprising:
a downwards operating vertical NPN transistor formed on said substrate and having an epitaxial extrinsic base region, an emitter region, and a collector region, and
a downwards-operating vertical PNP transistor formed on said substrate having an epitaxial base region, an emitter region, and a collector region;
wherein said base region of said vertical NPN transistor comprises a first portion of a first layer and said base region of said vertical PNP transistor comprises a second portion of said first layer.
2. The semiconductor structure of claim 1, wherein said first layer comprises epitaxial silicon germanium (SiGe).
3. The semiconductor substrate of claim 1, wherein said epitaxial SiGe includes a first dopant type.
4. The semiconductor substrate of claim 3, wherein said first dopant type includes a p-type dopant.
5. The semiconductor substrate of claim 1, wherein a portion of said emitter of said PNP transistor comprises a portion of said second portion of said first layer.
6. The semiconductor substrate of claim 1, wherein an intrinsic base of said NPN transistor comprises said first portion of said first layer.
7. The semiconductor substrate of claim 1, wherein an extrinsic base of said NPN transistor comprises a first portion of a second layer and the emitter of said PNP transistor comprises a second portion of said second layer.
8. The semiconductor substrate of claim 7, wherein said second layer comprises polysilicon or silicon.
9. The semiconductor substrate of claim 8, wherein said polysilicon or silicon layer comprises a p-type dopant.
10. A semiconductor structure on a substrate comprising a downwards operating vertical PNP transistor formed on said substrate having a base region, an emitter region, and a collector region wherein said collector region of said vertical PNP transistor is formed on a same layer on said substrate as a collector region for a downwards operating vertical NPN transistor.
11. The semiconductor structure of claim 10, wherein said layer comprises epitaxial silicon germanium (SiGe).
12. The semiconductor structure of claim 10, wherein said layer comprises an epitaxial silicon germanium (SiGe) layer or a silicon layer.
13. The semiconductor substrate of claim 10, wherein said layer includes a first dopant type.
14. The semiconductor substrate of claim 13, wherein said first dopant type includes a p-type dopant or an n-type dopant.
15-26. (canceled)
US11/516,007 2005-01-17 2006-09-06 High performance integrated vertical transistors and method of making the same Abandoned US20070001264A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/516,007 US20070001264A1 (en) 2005-01-17 2006-09-06 High performance integrated vertical transistors and method of making the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,685 US7217628B2 (en) 2005-01-17 2005-01-17 High performance integrated vertical transistors and method of making the same
US11/516,007 US20070001264A1 (en) 2005-01-17 2006-09-06 High performance integrated vertical transistors and method of making the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/905,685 Continuation US7217628B2 (en) 2005-01-17 2005-01-17 High performance integrated vertical transistors and method of making the same

Publications (1)

Publication Number Publication Date
US20070001264A1 true US20070001264A1 (en) 2007-01-04

Family

ID=36683031

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/905,685 Expired - Fee Related US7217628B2 (en) 2005-01-17 2005-01-17 High performance integrated vertical transistors and method of making the same
US11/516,007 Abandoned US20070001264A1 (en) 2005-01-17 2006-09-06 High performance integrated vertical transistors and method of making the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/905,685 Expired - Fee Related US7217628B2 (en) 2005-01-17 2005-01-17 High performance integrated vertical transistors and method of making the same

Country Status (1)

Country Link
US (2) US7217628B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090020851A1 (en) * 2006-12-21 2009-01-22 International Business Machines Corporation (''ibm") Bicmos devices with a self-aligned emitter and methods of fabricating such bicmos devices
US7642168B1 (en) 2007-05-18 2010-01-05 National Semiconductor Corporation System and method for providing a self aligned bipolar transistor using a sacrificial polysilicon external base
US20100127352A1 (en) * 2006-12-01 2010-05-27 National Semiconductor Corporation Self-aligned bipolar transistor structure
US7838375B1 (en) 2007-05-25 2010-11-23 National Semiconductor Corporation System and method for providing a polyemit module for a self aligned heterojunction bipolar transistor architecture
US7910447B1 (en) 2007-05-15 2011-03-22 National Semiconductor Corporation System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter
US7927958B1 (en) 2007-05-15 2011-04-19 National Semiconductor Corporation System and method for providing a self aligned bipolar transistor using a silicon nitride ring
US11189724B2 (en) 2018-10-24 2021-11-30 International Business Machines Corporation Method of forming a top epitaxy source/drain structure for a vertical transistor

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI456762B (en) * 2011-10-21 2014-10-11 Rexchip Electronics Corp The manufacturing method of the vertical transistor
US8613861B2 (en) * 2011-12-07 2013-12-24 Rexchip Electronics Corporation Method of manufacturing vertical transistors
US8558282B1 (en) * 2012-09-08 2013-10-15 International Business Machines Corporation Germanium lateral bipolar junction transistor
US9105677B2 (en) * 2013-10-22 2015-08-11 International Business Machines Corporation Base profile of self-aligned bipolar transistors for power amplifier applications
US9847408B1 (en) 2016-06-21 2017-12-19 Globalfoundries Inc. Fabrication of integrated circuit structures for bipolor transistors
US9899375B1 (en) 2016-08-02 2018-02-20 Globalfoundries Inc. Co-integration of self-aligned and non-self aligned heterojunction bipolar transistors
US11355617B2 (en) * 2019-10-01 2022-06-07 Qualcomm Incorporated Self-aligned collector heterojunction bipolar transistor (HBT)
US11177158B2 (en) * 2020-02-25 2021-11-16 Globalfoundries U.S. Inc. Integrated circuit structure with semiconductor-based isolation structure and methods to form same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4951115A (en) * 1989-03-06 1990-08-21 International Business Machines Corp. Complementary transistor structure and method for manufacture
US5930635A (en) * 1997-05-02 1999-07-27 National Semiconductor Corporation Complementary Si/SiGe heterojunction bipolar technology
US20030219952A1 (en) * 2002-05-21 2003-11-27 Hirokazu Fujimaki Semiconductor device and method of manufacturing same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4997776A (en) * 1989-03-06 1991-03-05 International Business Machines Corp. Complementary bipolar transistor structure and method for manufacture
JPH0785476B2 (en) * 1991-06-14 1995-09-13 インターナショナル・ビジネス・マシーンズ・コーポレイション Emitter-embedded bipolar transistor structure
US5583059A (en) * 1994-06-01 1996-12-10 International Business Machines Corporation Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI
US6413806B1 (en) * 2000-02-23 2002-07-02 Motorola, Inc. Semiconductor device and method for protecting such device from a reversed drain voltage
US6472288B2 (en) * 2000-12-08 2002-10-29 International Business Machines Corporation Method of fabricating bipolar transistors with independent impurity profile on the same chip
US6794730B2 (en) * 2000-12-31 2004-09-21 Texas Instruments Incorporated High performance PNP bipolar device fully compatible with CMOS process
JP3976601B2 (en) * 2002-03-28 2007-09-19 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
US6909164B2 (en) * 2002-11-25 2005-06-21 International Business Machines Corporation High performance vertical PNP transistor and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4951115A (en) * 1989-03-06 1990-08-21 International Business Machines Corp. Complementary transistor structure and method for manufacture
US5930635A (en) * 1997-05-02 1999-07-27 National Semiconductor Corporation Complementary Si/SiGe heterojunction bipolar technology
US20030219952A1 (en) * 2002-05-21 2003-11-27 Hirokazu Fujimaki Semiconductor device and method of manufacturing same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100127352A1 (en) * 2006-12-01 2010-05-27 National Semiconductor Corporation Self-aligned bipolar transistor structure
US8148799B2 (en) * 2006-12-01 2012-04-03 National Semiconductor Corporation Self-aligned bipolar transistor structure
US20090020851A1 (en) * 2006-12-21 2009-01-22 International Business Machines Corporation (''ibm") Bicmos devices with a self-aligned emitter and methods of fabricating such bicmos devices
US7709338B2 (en) 2006-12-21 2010-05-04 International Business Machines Corporation BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices
US7910447B1 (en) 2007-05-15 2011-03-22 National Semiconductor Corporation System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter
US7927958B1 (en) 2007-05-15 2011-04-19 National Semiconductor Corporation System and method for providing a self aligned bipolar transistor using a silicon nitride ring
US7642168B1 (en) 2007-05-18 2010-01-05 National Semiconductor Corporation System and method for providing a self aligned bipolar transistor using a sacrificial polysilicon external base
US7838375B1 (en) 2007-05-25 2010-11-23 National Semiconductor Corporation System and method for providing a polyemit module for a self aligned heterojunction bipolar transistor architecture
US11189724B2 (en) 2018-10-24 2021-11-30 International Business Machines Corporation Method of forming a top epitaxy source/drain structure for a vertical transistor

Also Published As

Publication number Publication date
US20060157823A1 (en) 2006-07-20
US7217628B2 (en) 2007-05-15

Similar Documents

Publication Publication Date Title
US7217628B2 (en) High performance integrated vertical transistors and method of making the same
US7846805B2 (en) Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process
US6900519B2 (en) Diffused extrinsic base and method for fabrication
KR100294129B1 (en) High speed and low parasitic capacitance semiconductor device and method for fabricating the same
US6617220B2 (en) Method for fabricating an epitaxial base bipolar transistor with raised extrinsic base
US6780725B2 (en) Method for forming a semiconductor device including forming vertical npn and pnp transistors by exposing the epitaxial layer, forming a monocrystal layer and adjusting the impurity concentration in the epitaxial layer
US4902639A (en) Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts
US20050233536A1 (en) Method for the production of a bipolar transistor
US4997775A (en) Method for forming a complementary bipolar transistor structure including a self-aligned vertical PNP transistor
US8450179B2 (en) Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication
EP0386413B1 (en) Complementary transistor structure and method for manufacture
US6913981B2 (en) Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer
US10014397B1 (en) Bipolar junction transistors with a combined vertical-lateral architecture
US7217609B2 (en) Semiconductor fabrication process, lateral PNP transistor, and integrated circuit
US6319786B1 (en) Self-aligned bipolar transistor manufacturing method
US7968417B2 (en) Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure
US10833072B1 (en) Heterojunction bipolar transistors having bases with different elevations
US7008851B2 (en) Silicon-germanium mesa transistor
US6740560B1 (en) Bipolar transistor and method for producing same
JP2006310590A (en) Semiconductor device and its manufacturing method
JP3908023B2 (en) Manufacturing method of semiconductor device
KR100293978B1 (en) Bipolar transistor and method for manufacturing the same
US20060006416A1 (en) Bipolar transistor with nonselective epitaxial base and raised extrinsic base
JP2007311489A (en) Semiconductor device and its manufacturing method
JP2006294887A (en) Bipolar transistor and its manufacturing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHERIDAN, DAVID C.;JOHNSON, JEFFREY B.;GRAY, PETER B.;AND OTHERS;REEL/FRAME:018280/0313;SIGNING DATES FROM 20050111 TO 20050113

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION