US20070004135A1 - Source side injection storage device and method therefor - Google Patents
Source side injection storage device and method therefor Download PDFInfo
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- US20070004135A1 US20070004135A1 US11/170,444 US17044405A US2007004135A1 US 20070004135 A1 US20070004135 A1 US 20070004135A1 US 17044405 A US17044405 A US 17044405A US 2007004135 A1 US2007004135 A1 US 2007004135A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/943—Information storage or retrieval using nanostructure
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Abstract
Description
- This application is related to the following patent applications:
- U.S. Patent application titled, “Source Side Injection Storage Device with Control Gates Adjacent to Shared Source/Drain and Method Therefor,” by Hong et al., having docket number SC14220TP, filed concurrently herewith, and assigned to the assignee hereof; and
- U.S. patent application titled, “Source Side Injection Storage Device with Spacer Gates and Method Therefor,” by Hong et al., having docket number SC14169TP, filed concurrently herewith, and assigned to the assignee hereof.
- This invention relates to non-volatile memories, and more particularly to storage devices in the non-volatile memories that use source side injection.
- Source side injection (SSI) has been found to have benefits over regular hot carrier injection (HCI) used in the programming of non-volatile memories (NVMs). Programming by SSI is able to be performed at significantly lower power than programming by regular (HCI). This is particularly important in uses such as cell phones in which battery operation is very important. One of the disadvantages of SSI is that the storage devices require more area on the integrated circuit which increases cost. The design of the individual memory cells for SSI generally includes a transition in the gate structure over the channel which requires more area.
- One of the techniques in the attempt to reduce the impact of the increased storage-device size has been the use of a virtual ground array (VGA) architecture. VGA has been known to require relatively small area compared to other architectures while increasing other difficulties such as read disturb. This has nonetheless been a popular architecture for low cost NVMs. Further reductions in space in the storage cell would further reduce size and thus cost.
- The foregoing and further and more specific objects and advantages of the invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the following drawings:
-
FIG. 1 is a cross section of a storage device structure at a stage in processing according to one embodiment; -
FIG. 2 is a cross section of the storage device structure ofFIG. 1 at a subsequent stage in processing; -
FIG. 3 is a cross section of the storage device structure ofFIG. 2 at a subsequent stage in processing; -
FIG. 4 is a cross section of a storage device structure ofFIG. 3 at a subsequent stage; -
FIG. 5 is a cross section of the storage device structure ofFIG. 4 at a subsequent stage in processing; -
FIG. 6 is a cross section of the storage device structure ofFIG. 5 at a subsequent stage in processing; -
FIG. 7 is a cross section of the storage device structure ofFIG. 6 at a subsequent stage in processing; -
FIG. 8 is a cross section of the storage device structure ofFIG. 7 at a subsequent stage in processing; -
FIG. 9 is a cross section of the storage device structure ofFIG. 8 at a subsequent stage in processing; -
FIG. 10 is a cross section of the storage device structure ofFIG. 9 at a subsequent stage in processing; -
FIG. 11 is a cross section of the storage device structure ofFIG. 10 at a subsequent stage in processing; -
FIG. 12 is a cross section of the storage device structure ofFIG. 11 at a subsequent stage in processing; -
FIG. 13 is a top view of the storage device structure ofFIGS. 1-12 ; and -
FIG. 14 is a cross section of a storage that is an alternative to that shown inFIGS. 1-13 . - In one aspect a storage device has a control gate that is shared by two memory cells and the drain for both memory cells is a first doped region directly under the control gate. The control gate, in the channel direction, completely covers this doped region. The source, in a second doped region, for a given memory cell is disposed away from the shared control gate of the given memory cell. The second doped region is shared by an adjacent memory cell that has a different control gate. This structure provides for reduced area while retaining the ability to perform programming by SSI. This is better understood by reference to the drawings and the following description.
- Shown in
FIG. 1 is astorage device structure 10 comprising asemiconductor substrate 12, asilicon oxide layer 14 onsubstrate 12, and a plurality of patternedsilicon nitride layers 16 onsilicon oxide layer 14.Silicon oxide layer 14 is preferably 50-100 Angstroms thick. Patternednitride layers 16 are preferably about 1000 Angstroms thick, about 1500 Angstroms wide, and about 1500 Angstroms apart. These layers may run for a comparatively long length, for example the length of a memory array.Semiconductor substrate 12 is preferably silicon but could be another semiconductor material. - Shown in
FIG. 2 isstorage device structure 10 after formation ofsidewall spacers 18 around patternednitride layers 16. - Shown in
FIG. 3 isstorage device structure 10 after animplant 20 to form dopedregions nitride layers 16 as masked bysidewall spacers 18.Doped regions regions - Shown in
FIG. 4 isstorage device structure 10 afterremoval sidewall spacers 18 and the portion ofoxide layer 14 between the nitride layers. This can be achieved with a wet HF etch which is highly selective between nitride and oxide. - Shown in
FIG. 5 isstorage device structure 10 after forming a layer of astorage layer 28 which in this example comprises a nanocrystals in a dielectric. - Shown in
FIG. 6 isstorage device structure 10 after formation of agate layer 30. This is shown as a planar layer but it may also be formed as a conformal layer.Gate layer 30 may also be a stack of different conductive layers.Gate layer 30 is preferably a metal that is deposited by plating but could be another material and could be deposited by another method for depositing a layer that can be useful as a gate. In the case of plating, a seed layer (not separately shown) would be formed before the plating ofultimate gate layer 30. In this example the metal is preferably tungsten. - Shown in
FIG. 7 isstorage device structure 10 after a planarizing process that removesgate metal layer 30 from over patternednitride layer 16. Thisleaves control gates gate layer 30 between patternednitride layer 16. Chemical mechanical polishing (CMP) using nitride as the etch stop is preferably used for the planarizing. Another etch back process may alternatively be used. - Shown in
FIG. 8 isstorage device structure 10 after removal of patternednitride layers 16 and the remaining portions ofoxide layer 14. This is achieved using a dry chlorine etch which is commonly used for etching nitride. This also removes oxide but is selective to silicon. This leavescontrol gates substrate 12 exposed. Undercontrol gates storage layers storage layer 28. - Shown in
FIG. 9 isstorage device structure 10 after forming aliner 47 on the exposed portions ofsubstrate 12 andcontrol gates spacer 48 aroundcontrol gate 32,spacer 50 aroundcontrol gate 34,spacer 52 aroundcontrol gate 36, andspacer 54 aroundcontrol gate 38.Spacers - Shown in
FIG. 10 isstorage device structure 10 after animplant 56 forms dopedregions control gates sidewall spacers implant 20 shown inFIG. 3 . - Shown in
FIG. 11 isstorage device structure 10 after removal ofsidewall spacers - Shown in
FIG. 12 isstorage device structure 10 after formation of aselect gate 64 which is preferably formed in the same manner asgate layer 30 ofFIG. 6 but could be a different material and could be formed differently. - Shown in
FIG. 13 isstorage device structure 10 ofFIG. 12 from a top view depicting a VGAtype memory array 80 using the storage device structure ofFIG. 12 .Select gate 64 runs in what is commonly described as the row direction. Similarly controlgates doped regions select gate structures gate 64. An actual memory would of course have many more structures than those shown inFIG. 13 . In this example, the dopedregions control gates Doped region 60 between the control gates functions as sources. - In operation, a memory cell is defined as the structure between one doped region under a control gate and an adjacent doped region between control gates. Thus for example, one memory cell comprises doped
region 22, dopedregion 60, and the portion ofcontrol gate 34 betweendoped regions select gate 64 betweendoped regions substrate 12 betweendoped regions substrate 12.Oxide 47 functions as the gap dielectric where the electrons in the channel region gain energy for injection during programming whereselect gate 64 is closer to the channel thancontrol gate 34. To program this memory cell,select gate 64 is biased to a voltage of about 2 to 3 volts, dopedregion 60, which functions as a source, is grounded,control gate 34 is biased to a voltage of about 5 to 6 volts, and dopedregion 22, which functions a drain, is biased to about 5 volts. This establishes a current flow through the channel. Electrons come from the source, dopedregion 60, and are injected intostorage layer 42 at the edge ofcontrol gate 34 which is closest to the source. Thus, source side injection is achieved. This is continued untilprogram layer 42 has captured sufficient electrons for providing enough bias to significantly impede current in the channel during a read operation. During a read, bothselect gate 64 andcontrol gate 34 are biased sufficiently to cause measurable current flow through the channel in the absence of being programmed. In the programmed condition, the accumulation of electrons instorage layer 42 prevents the channel from inverting in that the region of the channel immediately under where the electrons accumulated. This impedes current betweendoped regions control gate 34 to about minus 6 volts andsubstrate 12 to about plus 6 volts. - Similar operation is applied to the other memory cells shown in
FIG. 12 . The other memory cell that sharescontrol gate 34 and dopedregion 22 has its channel betweendoped regions region 60 and has its channel betweendoped regions - Shown in
FIG. 14 is astorage device structure 10′ similar tostorage structure 10 ofFIG. 12 . In this example analogous features have the same numeral with but with an accent mark.Storage device structure 10′ is made by using the same process but skipping the sidewall spacer formation ofFIG. 9 and the processes ofFIGS. 10 and 11 . This can be viewed as going fromFIG. 8 toFIG. 12 but with a liner analogous toliner 47 added. In this case, patterned nitride layers 16 would be about half as wide but maintaining the same spacing as that shown inFIG. 1 . The result is that there is no doped region analogous todoped regions - In the case of
storage device 10′ ofFIG. 14 , a memory cell is the structure between adjacent doped regions and each memory cell is two bits that is achieved by changing the polarities of the doped regions. For example, one memory cell comprises dopedregions 42′ and 44′, the portions ofcontrol gates 34′ and 36′ that is betweendoped regions 42′ and 44′, and the portion ofselect gate 64′ betweendoped regions 22′ and 24′. The channel is betweendoped regions 22′ and 24′ along the top surface ofsubstrate 12. One bit is represented by the portion ofstorage layer 42 that is betweendoped regions 22′ and 24′ and a second bit is represented by the portion ofstorage layer 44 that is betweendoped regions 22′ and 24′. Similarly, two more bits are represented by the structure between and includingdoped regions 24′ and 26′. - As an example, for programming the bit at
storage layer 42′ betweendoped regions 22′ and 24′, dopedregion 22′ functions as the drain and dopedregion 24′ functions as the source.Control gate 36′ is positively biased to invert the channel thereunder,select gate 64′ is positively biased to invert the channel betweencontrol gates 34′ and 36′,control gate 34′ is positively biased to attract electrons intostorage layer 42′, and dopedregion 22′ is positively biased to induce channel current that generates hot carriers. Similarly for the bit represented atstorage layer 44′ that is betweendoped regions 22′ and 24′, programming is achieved by reversing the biases atdoped regions 22′ and 24′ and atcontrol gates 34′ and 36′ while keepingsubstrate 12 andselect gate 64′ the same. - Reading is achieved by using doped
region 22′ as the drain for reading the bits instorage layer 42′ and using dopedregion 24′ as the drain while reading the bits atstorage layer 44′. Programming is achieved in the same way as forstorage device 10 ofFIG. 12 . - Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. For example, these embodiments have been shown using a bulk silicon substrate but another substrate type, such as semiconductor on insulator (SOI) or SOI hybrid, could also be used. Also, hot carrier injection (HCI) can also be used in conjunction with SSI to cause programming at interior portions of the storage layers. Thus for example programming could be at both the left and right side of
storage layer 42 close to dopedregion 22. By injecting electrons in the central area ofstorage layer 42 using HCI and injecting electrons at the lateral outside edge ofstorage layer 42 using SSI, two bits of information may be programmed on each side ofstorage layer 42. Literally then,storage layer 42 could actually store four bits. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.
Claims (18)
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US11/170,444 US7157345B1 (en) | 2005-06-29 | 2005-06-29 | Source side injection storage device and method therefor |
TW095121982A TWI395297B (en) | 2005-06-29 | 2006-06-20 | Source side injection storage device and method therefor |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060019447A1 (en) * | 2004-07-20 | 2006-01-26 | Martin Gutsche | Process for the self-aligning production of a transistor with a U-shaped gate |
US20080153274A1 (en) * | 2006-12-26 | 2008-06-26 | Timothy Thurgate | Deep bitline implant to avoid program disturb |
US20080153223A1 (en) * | 2006-12-20 | 2008-06-26 | Spansion Llc | Using thick spacer for bitline implant then remove |
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6133098A (en) * | 1999-05-17 | 2000-10-17 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic flash memory |
US20020028541A1 (en) * | 2000-08-14 | 2002-03-07 | Lee Thomas H. | Dense arrays and charge storage devices, and methods for making same |
US6373096B1 (en) * | 1999-01-22 | 2002-04-16 | Nec Corporation | Method of manufacturing semiconductor device, nonvolatile semiconductor memory device and method of manufacturing the same |
US20030080372A1 (en) * | 2001-10-30 | 2003-05-01 | Thomas Mikolajick | Semiconductor memory cell, method for fabricating the memory cell, and semiconductor memory device |
US6687156B2 (en) * | 1999-07-14 | 2004-02-03 | Hitachi, Ltd. | Semiconductor integrated circuit device, production and operation method thereof |
US20050218522A1 (en) * | 2001-07-19 | 2005-10-06 | Sony Corporation | Semiconductor device and method of producing the same |
US20050243603A1 (en) * | 1999-07-14 | 2005-11-03 | Takashi Kobayashi | Semiconductor integrated circuit device including first, second and third gates |
US20060018164A1 (en) * | 2004-02-18 | 2006-01-26 | Koucheng Wu | Nor-type channel-program channel-erase contactless flash memory on SOI |
US20060079455A1 (en) * | 2003-01-07 | 2006-04-13 | Ramot At Tel Aviv University Ltd. | Peptide nanostructures encapsulating a foreign material and method of manufacturing same |
US20060076606A1 (en) * | 2004-10-13 | 2006-04-13 | Bohumil Lojek | Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device |
US20060076586A1 (en) * | 2004-10-08 | 2006-04-13 | Swift Craig T | Virtual ground memory array and method therefor |
US20060079051A1 (en) * | 2004-10-08 | 2006-04-13 | Chindalore Gowrishankar L | Method for forming a multi-bit non-volatile memory device |
US20060086970A1 (en) * | 2004-10-21 | 2006-04-27 | Samsung Electronics Co., Ltd. | Non-volatile memory cell structure with charge trapping layers and method of fabricating the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5830794A (en) * | 1996-03-11 | 1998-11-03 | Ricoh Company, Ltd. | Method of fabricating semiconductor memory |
TW497236B (en) * | 2001-08-27 | 2002-08-01 | Chipmos Technologies Inc | A soc packaging process |
-
2005
- 2005-06-29 US US11/170,444 patent/US7157345B1/en active Active
-
2006
- 2006-06-20 TW TW095121982A patent/TWI395297B/en not_active IP Right Cessation
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6373096B1 (en) * | 1999-01-22 | 2002-04-16 | Nec Corporation | Method of manufacturing semiconductor device, nonvolatile semiconductor memory device and method of manufacturing the same |
US6133098A (en) * | 1999-05-17 | 2000-10-17 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic flash memory |
US6687156B2 (en) * | 1999-07-14 | 2004-02-03 | Hitachi, Ltd. | Semiconductor integrated circuit device, production and operation method thereof |
US20050243603A1 (en) * | 1999-07-14 | 2005-11-03 | Takashi Kobayashi | Semiconductor integrated circuit device including first, second and third gates |
US6992349B2 (en) * | 2000-08-14 | 2006-01-31 | Matrix Semiconductor, Inc. | Rail stack array of charge storage devices and method of making same |
US20020028541A1 (en) * | 2000-08-14 | 2002-03-07 | Lee Thomas H. | Dense arrays and charge storage devices, and methods for making same |
US20050218522A1 (en) * | 2001-07-19 | 2005-10-06 | Sony Corporation | Semiconductor device and method of producing the same |
US20030080372A1 (en) * | 2001-10-30 | 2003-05-01 | Thomas Mikolajick | Semiconductor memory cell, method for fabricating the memory cell, and semiconductor memory device |
US20060079455A1 (en) * | 2003-01-07 | 2006-04-13 | Ramot At Tel Aviv University Ltd. | Peptide nanostructures encapsulating a foreign material and method of manufacturing same |
US20060018164A1 (en) * | 2004-02-18 | 2006-01-26 | Koucheng Wu | Nor-type channel-program channel-erase contactless flash memory on SOI |
US20060076586A1 (en) * | 2004-10-08 | 2006-04-13 | Swift Craig T | Virtual ground memory array and method therefor |
US20060076609A1 (en) * | 2004-10-08 | 2006-04-13 | Freescale Semiconductor, Inc. | Electronic device including an array and process for forming the same |
US20060079051A1 (en) * | 2004-10-08 | 2006-04-13 | Chindalore Gowrishankar L | Method for forming a multi-bit non-volatile memory device |
US20060076606A1 (en) * | 2004-10-13 | 2006-04-13 | Bohumil Lojek | Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device |
US20060086970A1 (en) * | 2004-10-21 | 2006-04-27 | Samsung Electronics Co., Ltd. | Non-volatile memory cell structure with charge trapping layers and method of fabricating the same |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060019447A1 (en) * | 2004-07-20 | 2006-01-26 | Martin Gutsche | Process for the self-aligning production of a transistor with a U-shaped gate |
US20080153223A1 (en) * | 2006-12-20 | 2008-06-26 | Spansion Llc | Using thick spacer for bitline implant then remove |
US7888218B2 (en) * | 2006-12-20 | 2011-02-15 | Spansion Llc | Using thick spacer for bitline implant then remove |
US20080153274A1 (en) * | 2006-12-26 | 2008-06-26 | Timothy Thurgate | Deep bitline implant to avoid program disturb |
US7671405B2 (en) * | 2006-12-26 | 2010-03-02 | Spansion Llc | Deep bitline implant to avoid program disturb |
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
US9030877B2 (en) | 2007-08-30 | 2015-05-12 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
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Publication number | Publication date |
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TWI395297B (en) | 2013-05-01 |
US7157345B1 (en) | 2007-01-02 |
TW200705610A (en) | 2007-02-01 |
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