US20070019859A1

US20070019859A1 - Method for measuring registration

Info

Publication number: US20070019859A1
Application number: US11/446,145
Authority: US
Inventors: Eugene DeLaRosa; Troy Gugel
Original assignee: Individual
Current assignee: Individual
Priority date: 2000-03-01
Filing date: 2006-06-05
Publication date: 2007-01-25
Also published as: US7095885B1; US20060274935A1

Abstract

A method and apparatus for measuring registration between two or more integrated circuit layers is disclosed. Images of actual operative circuitry of different layers of a semiconductor wafer, obtained by optical or scanning electron microscopy, are digitized and analyzed for the relative placement of pattern shapes of the corresponding layers. This relative placement is then compared to a predetermined database and the registration calculated.

Description

FIELD OF THE INVENTION

The present invention relates to semiconductor processing, and in particular, to a method for measuring the registration between two or more integrated circuit layers.

BACKGROUND OF THE INVENTION

Semiconductor-based integrated circuits are typically manufactured through the formation of a set of layers on a wafer containing many integrated circuit areas that are later separated into individual dies. Very thin layers of material are deposited one on top of the other in patterns to form integrated circuit components.
One technique of deposition and patterning is photolithography where a material layer is first coated with a light-sensitive photoresist. The photoresist is exposed through a pattern mask of a desired circuit pattern. Depending upon the type of photoresist used, the exposed photoresist is developed to remove either the exposed or unexposed resist. Etching and/or deposition processes are then used to create the desired circuit within the pattern created.
In most cases, the pattern mask should be precisely aligned on a wafer during processing. The overlay of the mask, the measure of how accurately the pattern mask was aligned, will often determine whether the wafer will be functional or must be discarded. Because each wafer may undergo numerous photolithography processing steps, the alignment of each pattern mask, especially the last ones used, is dependant upon the correct alignment of earlier masks. Poor overlay may destroy the intended electrical properties of a circuit device on a wafer.
A common practice in registration, or matching in position, of overlying layers in a semiconductor wafer is to use metrology structures such as registration patterns or marks in each layer of the wafer. In particular, the box-in-box registration pattern is commonly used today. This technique employs squares of different sizes on the layers to be registered. When the two layers are exactly matched in position, or registered, the squares are concentric. Any registration error produces a displacement of the squares relative to each other. To ensure ideal registration between masks, four box-in-box alignments are performed simultaneously, with the boxes located at the four corners of the image field.
Since semiconductor devices are expensive to fabricate, it is desirable to verify registration after the application of each layer. If the displacement of the layers is outside tolerable limits, sometimes the defective layer can be removed or replaced with an accurately registered layer. In other cases, the substrate is discarded so that further processing steps are not performed on a defective substrate.
In the prior art, monitoring and verification of registration was done manually. Laboratory operators examined the registration of overlying layers on each semiconductor wafer. Unavoidably, this technique was slow, subject to human errors and substrate contamination.
Recently, the registration of overlying layers has been measured by automated systems, such as optical microscopy and scanning electron microscopy (SEM). For example, registration errors can be measured by a process in which an image of a set of registration patterns, recorded by a video camera through a microscope, are processed to obtain a measurement of the registration error. U.S. Pat. No. 4,805,123 to Specht et al. discloses a photomask and reticle inspection method and apparatus where an examined selected surface area of a given image is compared with a corresponding reference area.
U.S. Pat. No. 4,938,600 to Into teaches a method for measuring displacement between layers of a semiconductor wafer, using an optical system that employs a camera and a microscope. A first measurement is taken, the wafer is then rotated 180° about the measurement axis, after which a second measurement is taken. The actual displacement between semiconductor layers is calculated form the first and second measurements.
The ability of optical systems to classify defects remains, however, highly limited. Optical microscopy cannot examine and measure the patterns of submicron dimensions with sufficient accuracy and reliability. Many times, the features are discernable, yet the measurements to the accuracy required are impossible because the microscopes currently used in defect review stations lack sufficient resolution to resolve defects of such small size. In addition, the use of conventional microscopes risks contamination of the semiconductor wafer because the presence of the microscope causes turbulent flow in the proximity of the wafer which in turn tends to pull in nearby contaminants to the wafer.
Consequently, the semiconductor processing industry has attempted the use of scanning electron microscopes (SEM) performing energy dispersive (EDX) analysis to provide increased resolution and to permit precise measurements. In EDX analysis, a specimen is placed into a vacuum chamber where a focused electron beam is directed toward the surface of the semiconductor wafer. Electrons resulting from the physical interaction between the electron beam and the semiconductor wafer are sensed by a detector so that signal data having a wavelength characteristic of the measurement subject is generated. This signal data is further digitized and processed as a video signal producing an image on a video display screen.
Various methods for registration measurements in semiconductor wafers using SEM based equipment have been reported. However, these methods are used primarily for detecting semiconductor wafer pattern defects, such as critical dimension (CD), and not for registration measurements. Although the prior art does not teach the solution that will further be outlined, the following references are of interest, in that they exempliiy the industry practice for the use of SEM based equipment.
For example, U.S. Pat. No. 4,794,646 to Jakeucky et al. discloses an apparatus for detecting semiconductor wafer pattern defects that compares an inspected wafer area to an image constructed from information, such as design rules, in a database.
Similarly, U.S. Pat. No. 5,659,172 to Wagner et al. discloses a method for defect detection on semiconductor devices by comparing images from a single perspective followed by a cross-check between at least two perspectives. A SEM with at least two electron detectors is employed to collect electrons from different angular sectors. The area of the semiconductor wafer that is to be inspected generates “base” images from both perspectives. For each perspective base image, a perspective “reference” image is then generated and compared with the base image. At the end, a comparison map of possible defect locations is produced and a cross-check is performed between the perspective comparison maps.
Recently, U.S. Pat. No. 5,887,080 to Tsubusaki et al. refers to a method and pattern processing apparatus with analog-digital conversion means for converting analog image data having repeated patterns obtained by a SEM into digital image data. The digital data is further processed by a spatial filtering processing, histogram processing, threshold value setting, three-valued image data processing, and noise reduction among others. The area of a pattern in the three-valued image data is then calculated and a pattern is sequentially detected by comparing the area of the pattern with a reference area value. The comparison and detection of the same or similar patterns repeated in the SEM image are performed by using the area of the pattern, and are not performed by a shape of the pattern.
Both optical and SEM automated systems for measuring registration pose various problems, such as lens distortions and reticle anomalies, to the semiconductor processing industry. These system errors arise both in the electrical and optical portions of the system. Most of the errors are systematic, in that they have the same magnitude and direction from measurement to measurement. Typical examples are optical and illumination errors, errors due to camera and image processor response, or mechanical errors. Attempts have been made in the past to calibrate such registration systems by comparing the measurements with those provided by a SEM, for example, which is known to be accurate. These calibration methods, however, are relatively complex and they require additional equipment.
Accordingly, a method for measuring displacement between layers of a semiconductor wafer, which is inexpensive to implement, fast in operation and simple to automate is needed. There is also a need for a method that allows accurate measurement registration of pattern masks, while avoiding the systematic errors associated with the prior art measurement systems.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus that overcome some of the problems regarding the alignment of pattern masks during the semiconductor processing fabrication, in particular the registration measurements.
The present invention utilizes optical or scanning electron microscopy images of two or more integrated circuit layers. The portion of the integrated circuit layers that is imaged contains the actual operative circuitry of the chip. The patterns are digitized from the images and the digitized patterns are further analyzed for the relative placement of the two layers. The measured offset can then be compared to a database containing previously computed data for the ideal relative placement of the two layers. The difference between the imaged and the ideal placement is then converted to an offset, or registration, number. The registration number may then be used to correct processing errors or inefficiencies.
The above and other advantages and features of the present invention will be better understood from the following detailed description of the preferred embodiment which is provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a registration system using a box-in-box test pattern in accordance with the prior art.
FIG. 2 is a top view of a registration system using an alternative box-in-box test pattern in accordance with the prior art.
FIG. 3 is a cross-sectional view of the registration system of FIG. 1 taken along lines I-II, in accordance with the prior art.
FIG. 4 illustrates the measurement technique in accordance with the prior art.
FIG. 5 illustrates a registration measurement system according to one embodiment of the present invention.
FIG. 6 is a block diagram of the illustration of FIG. 5.
FIG. 7 is a flow diagram of the registration steps in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural, electrical and methodology changes may be made without departing from the invention. Accordingly, the following detailed description is not to be taken in a limiting sense and the scope of the present invention is defined by the appended claims.
The present invention provides a method for measuring registration between layers of a semiconductor wafer. The registration method measures the displacement of the actual patterns on the scanned semiconductor layers, rather than that of metrology structures such as, for example, the box-in-box pattern set.
Referring now to the drawings, a conventional box-in-box registration pattern set is shown in FIG. 1, where an outer box 12 has been formed by photolithography. On top of outer box 12, a smaller box 14 is formed by a subsequent and separate photolithography step. Both boxes have a square pattern, with dimensions on the order of 10 to 20 micrometers. The separation between boxes, as illustrated by area S, is typically about 3 microns.
Various box-in-box test patterns are used in the semiconductor processing industry. FIG. 2, for example, represents an alternative registration pattern, with angled lines 32 situated on a first layer of a semiconductor wafer, and angled lines 34 situated on a second layer of same semiconductor wafer.
Referring further to the drawings, FIG. 3 represents a cross-sectional view of wafer 20 containing the box-in-box registration pattern set 10. When layers 22 and 24 are perfectly registered or matched, then the square patterns of the two boxes 12 and 14, respectively, are concentric. This is the case in FIG. 1, where the center of pattern 12 coincides with the center of pattern 14 at point O.
In contrast, when layers 22 and 24 are not perfectly registered, the square patterns 12 and 14 are displaced in the plane of wafer 20. By measuring the displacement of boxes 12 and 14, the registration between layers 22 and 14 can be consequently quantified.
The displacement in a box-in-box registration pattern set is exemplified in FIG. 4, which shows the center of patterns 12 as point O and the center of pattern 14 as point A. An x-axis displacement and an y-axis displacement are first calculated and then used for quantfying the registration or the actual value of displacement between layers 22 and 24.
According to a preferred embodiment of the present invention, the apparatus 100 of the present invention comprises a prealigner 42 for handling cassette wafer holder 40, an automated imaging system 46, an image processor 48, and a computer 50 that further comprises an image monitor 52, a text screen 54, a keyboard 56, and a disk drive 58. FIG. 5 is an illustration of an apparatus for a registration system of the present invention, and FIG. 6 provides a sequence of steps in the process for measuring registration that will be outlined below in more detail.
As illustrated in FIG. 6, at an initial step of the registration measuring system in accordance with the present invention, cassette wafer holder 40 that contains semiconductor wafers to be measured is mounted on apparatus 100. A wafer transport system or a wafer handler (not shown) removes semiconductor silicon wafer 20 from cassette 40 and places it on prealigner 42. A typical wafer transport system is a model CKG1 or CKG3 available from FSI. Semiconductor wafer 20 has a given size, typically ranging from 75 mm (3 inches) to 200 mm (8 inches) in diameter.
The wafer transport system further transfers semiconductor silicon wafer 20 from the prealigner 42 onto stage 18. Stage 18 has three dimensional movements that permit the positioning of semiconductor wafer 20 relative to the automated imaging system 46. Stage 18 may be any conventional device, such as a piezoelectrically driven stage, that provides precise movement over a broad range of distances.
The automated imaging system 46 may be either an optical system or a scanning electron microscope (SEM) (not shown), both being used in the present invention only for generating cross sectional images of wafer 20.
The optical system could include a microscope and a video camera positioned above semiconductor wafer 20. The microscope could carry objectives ranging in power from 2.5× to 200× magnification. For example, the microscope of the optical system could be a Zeiss Axiotron type and the video camera a Dage MT168 series.
Similarly, the present invention could use a scanning electron microscope (SEM) as the imaging system 46. As described in the background section of this application, a conventional SEM includes a lens that focuses an emitted electron beam toward the semiconductor wafer 20. The SEM would be used only for generating cross sectional images of semiconductor wafer 20.
Referring now to FIG. 7, after system initialization at step 100, step 102 begins with the automated imaging system 46 taking a first image of the first layer of semiconductor wafer 20. The electrical signals representative of the first image are further channeled towards the image processor 48, and to the computer 50. At this point, computer will further process the signals from the imaging system 46 and identify the location of a predetermined first indicator in the first layer of the semiconductor wafer 20. In step 104, therefore, the first set of measurements generates values X₁Y₁.
At step 106 of FIG. 7, the automated system 46 takes a second image of the second-layer of semiconductor wafer 20 that is processed similarly to the first image of the first layer. Accordingly, the location of a predetermined second indicator in the second layer of the semiconductor wafer 20 is computer recognized. The second set of measurements generates values X₂,Y₂at step 108.
At the comparison step 110, both sets of measurements are consequently stored in a disk drive 38 and the locations of the first and second indicators are compared. The two sets of measurements are combined to yield the actual displacement between the two circuit layers. At this point, computer 50 calculates the offset, or registration, value. The offset value is then compared to a database containing predetermined data for the ideal relative placement of the two layers.
Accordingly, in step 112, a query is made as to whether the above calculated offset value is within a predetermined acceptable target quantity range, or tolerance. If so, then the fabrication process to which semiconductor wafer 20 is being subjected will terminate at step 116. If, however, the calculated offset value is not within the acceptable target tolerance, then the process moves to step 118 at which point a determination is made as to the required adjustment to the fabrication process to which semiconductor wafer 20 is subjected.
During step 118, the difference between the imaged placement and the ideal placement is calculated and converted to the final registration number, which could be further used to correct processing errors or inefficiencies. Any algorithm known for the metrology structures, such as, for example, the one described in U.S. Pat. No. 5,659,172 to Wagner et al., could be used.
After the proper adjustment to the fabrication process, the process returns to step 110 to measure again the locations of first and second indicators, and their corresponding offset.
While the invention has been described in detail with reference to semiconductor silicon wafers it should be readily apparent that the present invention can be used with other semiconductor substrates.
While the invention has been described in detail in connection with the preferred embodiments known at the time, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not described here, but which are commensurate with the spirit and scope of the invention. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.

Claims

1-39. (canceled)

40. A system for measuring the registration between at least two integrated circuit layers, one residing over the other, the system comprising:

an imaging system for generating a top-down field of the at least two integrated circuit layers, each of the layers having a respective visible feature in the image;

an image processor for digitizing the image;

a computer for processing the digitized image to determine a location of a first feature reference point in the visible feature of one of the layers, and allocation of a second feature reference point in the visible feature of the other of the layers, to indicate a relative location of the visible feature of one of the layers, relative to the visible feature of the other of the layers, wherein at least one of the visible features is a non-metrological structure on the one of the integrated circuit layers and for determining if the relative location is within acceptable design limits for the integrated circuit layers.

41. The system of claim 40, wherein the computer further determines an x-axis value, X₁, and a y-axis value, Y₁.

42. The system of claim 40, wherein the computer further determines an x-axis value, X₂, and a y-axis value, Y₂.

43. The system of claim 40, wherein the computer further determines an x-axis value, Δx, and a y-axis value, Δy, wherein:

Δx=X ₁ −X ₂; and
Δy=Y ₁ −Y ₂.

44. The system of claim 40, wherein the computer further compares said relative location to a stored data having reference locations and tolerable limits.

45. The system of claim 44, wherein the computer further calculates an offset value.

46. The system of claim 45, wherein the computer further compares the offset value to a predetermined tolerance.

47. The system of claim 40, wherein the imaging system includes a scanning electron microscope.

48. The system of claim 40, wherein the imaging system includes an optical system.