US20070038817A1 - Memory access control in a multiprocessor system - Google Patents
Memory access control in a multiprocessor system Download PDFInfo
- Publication number
- US20070038817A1 US20070038817A1 US11/503,673 US50367306A US2007038817A1 US 20070038817 A1 US20070038817 A1 US 20070038817A1 US 50367306 A US50367306 A US 50367306A US 2007038817 A1 US2007038817 A1 US 2007038817A1
- Authority
- US
- United States
- Prior art keywords
- processor
- program
- processors
- access
- memory area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims description 14
- 230000006870 function Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000007792 addition Methods 0.000 description 1
- 238000013475 authorization Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
Definitions
- the invention relates to controlling memory access in a multiprocessor system.
- Multiprocessor architectures have at least a first processor and a second processor, and a memory area to which each of these processors have access. One of the processors at a time is allowed access to the memory. Access to the memory area can be effected by appropriately programmed or fashioned hardware architecture.
- the computing power of a system that is built on discrete components or implemented with an integrated circuit is continually enhanced.
- the processors in the system can be improved or driven at higher clock speeds for this purpose. It is also possible to increase the number of processors or processor kernels. Because it is not always possible to boost the power of the individual processor kernel, more and more often a plurality of processors or processor kernels, which are capable of processing the required computational steps in parallel with one another, are placed in one system.
- a problem in such arrangements is that between the individual processors an interface is needed via which the processors can exchange data.
- a memory having a memory area that all processors can access is preferably used as interface for this purpose.
- dual-port RAM random access memory
- a memory exhibits separate address and data bus systems as well as arbitration logic, which initiates appropriate collision-prevention actions in the case of simultaneous write operations.
- Such a dual-port RAM is disadvantageously larger than a normal RAM, so that a larger footprint area is required.
- the expensive arbitration logic must prevent simultaneous writing to the same RAM cell, that is, to the same memory area at the same time by both processors. Usually one of the two processors is halted by the arbitration logic in case of a conflict.
- RISC computing systems have a reduced instruction set.
- any individual instruction executes only relatively simple operations.
- an individual processor program or an individual program sequence is allocated to each one of the processors.
- Each of these program sequences uses corresponding instructions to control the processing of data as well as memory accesses to a memory area individually allocated to the processor and also to memory areas used in common by a plurality of processors.
- In the program sequence there can also be jumps, which relocate the processing sequence of the allocated processor from one program address to another program address within the program sequence.
- a processor program furnishes memory accesses at cyclically uniquely allocated program addresses.
- the processor program for one of the processors provides memory accesses to the memory area at cyclically uniquely allocated program addresses, which, in comparison with the program addresses for memory accesses of another processor program of another of the processors, are furnished at a value offset relative to a cycle time.
- the processor programs may run temporally offset relative to one another and memory accesses within the processor programs may be entered at program addresses cyclically equal relative to other processor programs of another processor.
- the processor programs of the processors may run temporally simultaneously with one another and memory accesses within the processor programs may be entered at program addresses cyclically equal relative to other processor programs of another processor.
- a program jump may be entered from an instantaneous program address ad to a subsequent program address ad new according to the cyclical allocation for this processor.
- Memory accesses and/or program jumps within one of the processor programs may be allocated to one or a plurality of last address bits of a corresponding program address of the corresponding processor, with the cyclical allocation taken into account.
- the processor programs for the various ones of the processors are furnished in mutually matched fashion by a higher-level instance or a higher-level process. This may be implemented for example by appropriate programming on the part of a programmer and/or by a suitably set-up assembling or compiling device.
- a multiprocessor system includes at least a first processor and a second processor, and a memory area to which the first and second processors have access.
- a processor program individually allocated to the processor in question permits access to the memory area only at times cyclically uniquely allocated for this processor and, within the cycle, temporally offset relative to the other processors.
- Logic links times for memory accesses to the memory area and/or jumps within the processor program in question in cyclical fashion in dependence on the last bit or bits of a program address of the processor program.
- the program sequences or processor programs of the individual processors may be constructed and/or driven in such fashion that relatively expensive hardware arbitration logic is not required. This makes it possible to save footprint area and computing power.
- the program sequences to control access to the memory area may be suitably constructed during programming and implemented by a compiler and/or assembler. Within the system, the program sequences offset all processors that can access a common memory area into a clearly defined state relative to one another.
- a cyclically unique allocation of permissible times for access to the memory area may be implemented by the use of the modulo function in the creation of the program sequences.
- the last bits of the program addresses of the respective processors can advantageously exhibit a cyclically unique spacing relative to one another independently of the program sequence, in simple cases for example a constant difference.
- the last bits of the address can then be evaluated and then correspondingly, in dependence thereon, the memory area or memory can be associated with a uniquely allocated one of the processors, so that access to the memory or a part of the memory is always permitted to only one of the processors.
- the executable program instructions in the form of the program sequences ensures that a processor accesses the memory or memory area only when, according to the corresponding address bit of its program sequence, it also has access authorization from the logic circuit.
- the number of program address bits that are used for memory access control depends on the number of processors that can use the memory area in common. In the case of two processors, only the last bit of the program addresses of these two processors need to be considered. In the case of four processors, the last two bits are used. If the number of processors is greater, the number of bits of the corresponding program addresses used is increased correspondingly.
- all processors of the system are advantageously permitted to execute jumps only with consideration of the cyclical spacing of the permitted memory access times.
- a jump from an even program address is correspondingly allowed only to an odd program address, and from an odd program address only to an even program address.
- the implementation can be effected for example by hardware or directly by the software or the compiler.
- a logic circuit may correspondingly perform a configuration of one or a plurality of memory areas or RAM blocks in such fashion that a certain one of the processors always accesses the memory area in an even clock cycle, while the other processor always accesses the memory area in an odd clock cycle. Write or read rights thus alternate with each processor cycle.
- FIG. 1 schematically illustrates a multiprocessor architecture having two processors that use a common memory area, as well as program sequences that are allocated to the processors;
- FIG. 2 schematically illustrates a multiprocessor architecture having two alternative program sequences
- FIG. 3 schematically illustrates a multiprocessor architecture having four processors that can access the same memory area, and having four program sequences correspondingly allocated to the processors.
- FIG. 1 illustrates a multiprocessor architecture that includes a first processor 0 and a second processor 1 and at least one memory device M, which the first and second processors can access in order to write and/or read data.
- the embodiment illustrated in FIG. 1 illustrates two processors for ease of illustrating, one of ordinary skill will recognize that the present invention is certainly not limited to two processors.
- Allocated to each of the processors 0 , 1 is an individual processor program p 0 , p 1 , respectively which is programmed into its respective one of the processors 0 , 1 via a programming interface I or is entered directly when the processor is manufactured.
- Each of the processors 0 , 1 thus has its own processor program p 0 or p 1 respectively for controlling it.
- Separate individual processor memory area M 0 or M 1 respectively in the memory device M may be allocated to each of the processors 0 , 1 .
- the memory device M includes a memory area MX to which both the processors 0 , 1 have access.
- the memory area MX may also be a freestanding memory device. Access of the processors 0 , 1 to the memory area MX is controlled such that only at most one of the processors 0 , 1 is always granted access, in particular write access, to this memory area at a time t. Control of memory access times is effected by logic L, which is illustrated as structural components in the form of a switch solely for pictorial illustration.
- the logic L may be implemented by software control using processor programs p 0 , p 1 , without a switching apparatus fashioned in hardware. However, it is contemplated that hardware switching may also be used or even a combined hardware/software switching solution.
- Control of memory accesses to the memory area MX by the logic L is implemented in such that the processors 0 , 1 and/or their program sequences gets access to the memory area MX only at times t at which access is cyclically uniquely allocated for the processor in question.
- the processors 0 , 1 For coordination of the processors 0 , 1 , their processor programs p 0 , p 1 are synchronized by a synchronization signal t 0 so the program sequences both begin with the same address, for example program address 0 . At each clock pulse, the program sequences advance by one program step, unless program jumps are provided within one of the program sequences.
- the second processor 1 may access the memory area MX only at odd program addresses 1 , 3 , 5 , 7 , 9 , . . . , which can be described by the modulo function mod 2 equals 1.
- modulo function mod 2 equals 1.
- the first processor 0 accesses the memory area MX to store data at a sixth program address ad equals 6, while the second processor 1 accesses the memory area MX for storage at the program step of its ninth program address ad equals 9.
- the first processor 0 accesses the memory area MX to load data from the memory area MX at, for example, its second program step, that is, at the instruction according to the second program address ad equals 2.
- both the processors 0 , 1 access the memory area MX only at cyclically uniquely allocated times t or at cyclically uniquely allocated program addresses ad.
- the processor program p 0 of the first processor 0 there is an optional jump from the third program step or the third program address ad to the eighth program address.
- jumps between program addresses ad are also sketched in the processor program p 1 of the second processor 1 , jumps again taking place from even program addresses ad to odd program addresses ad and from odd program addresses ad to even program addresses ad.
- both the processors 0 , 1 are always either at an even or at an odd program address ad, and indeed even if there are program jumps in the program sequence.
- the program sequences are programmed with the conditions for cyclical access rights to the memory area MX and with the additional conditions for program jumps, if any, collision-free memory access to the memory area MX can be ensured without relatively expensive arbitration logic and in particular without totally halting the processors.
- FIG. 2 illustrates an alternative or, as appropriate, also a combined embodiment wherein both the processors 0 , 1 are started and/or synchronized at offset times using a synchronization signal to.
- the two program sequences are offset in such fashion that an odd program address ad of the processor program p 1 of the second processor 1 falls simultaneously with an even program address ad of the process program p 0 of the first processor 0 .
- the program sequences are so fashioned that both the processors 0 , 1 may each access the memory area MX when the program sequence of the processor programs p 0 , p 1 is at an even program address ad.
- the programmer, assembler or compiler makes certain that an access to the memory area MX always takes place on an even—or alternatively always on an odd—program address ad, because at a time t both the processor programs p 0 , p 1 are always at an even program address ad on the one hand and at an odd program address ad on the other. This lightens the work of programming and avoids programming errors.
- program jumps the same conditions apply as in the embodiment illustrated in to FIG. 1 .
- FIG. 3 illustrates an embodiment of a multiprocessor architecture that includes four processors 0 , 1 , 2 , 3 .
- an individually allocated memory segment M 0 -M 3 or memory may be allocated to each of the processors 0 - 3 .
- MX memory area
- FIG. 3 illustrates an embodiment of a multiprocessor architecture that includes four processors 0 , 1 , 2 , 3 .
- an individually allocated memory segment M 0 -M 3 or memory may be allocated to each of the processors 0 - 3 .
- MX memory area
- accesses to memory area M are controlled by logic L, preferably implemented in software by suitable programming of individual processor programs p 0 -p 3 of the processors 0 - 3 .
- a cycle of permissible program addresses ad is stipulated, which cycle takes into account that a number m of the four processors 0 - 3 may access the memory area MX.
- memory accesses to the memory area MX for loading or storing data are provided, for example, at program addresses ad equals 0 and ad equals 8 in processor program p 0 of the first processor 0 .
- processor programs p 1 , p 2 , p 3 for the processors 1 - 3 correspondingly, memory accesses to the memory area MX are provided for example at program addresses ad equals 9, ad equals 6 and ad equals 3, respectively.
- Jumps after processing of the corresponding instructions may stand correspondingly, for example, at addresses 0 , 3 , 7 , 11 and 15 and point to jump destinations 1 , 5 , 9 and 13 .
- Jumps after processing of the corresponding instructions may correspondingly stand, for example, at addresses 2 , 6 , 10 , 14 and point to jump destinations 3 , 7 , 11 and 15 .
- Jumps after processing of the corresponding instructions may correspondingly stand, for example, at addresses 0 , 4 , 8 , 12 and 16 and point to jump destinations 1 , 5 , 9 and 13 .
- the quantity m which governs the cycle time or cycle length, need not necessarily be tied to the number of processors P actually present but may also exhibit a larger value. This is advantageous for example when other processors or devices are to be permitted access to the memory area MX in the intervening time.
- the cycle time m is also expediently set correspondingly larger than the actual number of processors P when a larger permissible number of cyclical memory accesses is allocated to one of the processors P than to the others of processors P. This correspondingly impacts access times t or program addresses ad for memory accesses as well as the conditions for permissible jumps within respective processor programs p 0 -p 3 .
Abstract
Description
- This patent application claims priority from
German patent application 10 2005 038 567.2 filed Aug. 12, 2005, which is hereby incorporated by reference. - The invention relates to controlling memory access in a multiprocessor system.
- Multiprocessor architectures have at least a first processor and a second processor, and a memory area to which each of these processors have access. One of the processors at a time is allowed access to the memory. Access to the memory area can be effected by appropriately programmed or fashioned hardware architecture.
- In general, the computing power of a system that is built on discrete components or implemented with an integrated circuit is continually enhanced. The processors in the system can be improved or driven at higher clock speeds for this purpose. It is also possible to increase the number of processors or processor kernels. Because it is not always possible to boost the power of the individual processor kernel, more and more often a plurality of processors or processor kernels, which are capable of processing the required computational steps in parallel with one another, are placed in one system.
- A problem in such arrangements is that between the individual processors an interface is needed via which the processors can exchange data. A memory having a memory area that all processors can access is preferably used as interface for this purpose.
- As known, dual-port RAM (random access memory) can be accessed simultaneously from two sides by two processors. In order to make this possible, such a memory exhibits separate address and data bus systems as well as arbitration logic, which initiates appropriate collision-prevention actions in the case of simultaneous write operations. Such a dual-port RAM is disadvantageously larger than a normal RAM, so that a larger footprint area is required. In addition, the expensive arbitration logic must prevent simultaneous writing to the same RAM cell, that is, to the same memory area at the same time by both processors. Usually one of the two processors is halted by the arbitration logic in case of a conflict.
- Also known is the use of a separate arbitration logic in conjunction with a RAM that is subdivided into smaller blocks of individual memory areas. If a plurality of processors want to access the same block at the same time, only one of these processors receives write/read permission. The other processors are halted. This requires an expensive logic in the processor kernels and in the driving of the RAMs.
- RISC computing systems have a reduced instruction set. In computers having a corresponding processor architecture, any individual instruction executes only relatively simple operations. In such a processor architecture, an individual processor program or an individual program sequence is allocated to each one of the processors. Each of these program sequences uses corresponding instructions to control the processing of data as well as memory accesses to a memory area individually allocated to the processor and also to memory areas used in common by a plurality of processors. In the program sequence there can also be jumps, which relocate the processing sequence of the allocated processor from one program address to another program address within the program sequence.
- There is a need for improved memory access control in a multiprocessor architecture.
- To control memory accesses to a memory area by a first and a second processor access to the memory area is cyclically uniquely allocated to each of the processors by executable program instructions within the first and second processors.
- A processor program furnishes memory accesses at cyclically uniquely allocated program addresses. The processor program for one of the processors provides memory accesses to the memory area at cyclically uniquely allocated program addresses, which, in comparison with the program addresses for memory accesses of another processor program of another of the processors, are furnished at a value offset relative to a cycle time.
- Memory accesses of an o-th one of the processors take place at times and/or at processor program addresses ad satisfying the criteria:
(ad mod m)=o
where m is a value equal to or greater than the number of processors that cyclically uniquely access the memory area. - The processor programs may run temporally offset relative to one another and memory accesses within the processor programs may be entered at program addresses cyclically equal relative to other processor programs of another processor.
- The processor programs of the processors may run temporally simultaneously with one another and memory accesses within the processor programs may be entered at program addresses cyclically equal relative to other processor programs of another processor.
- In one of the processor programs, a program jump may be entered from an instantaneous program address ad to a subsequent program address adnew according to the cyclical allocation for this processor. A technique is preferred wherein a program jump satisfying:
(ad new−1)mod m=ad mod m
is entered, where m is a value equal to or greater than the number of processors. - Memory accesses and/or program jumps within one of the processor programs may be allocated to one or a plurality of last address bits of a corresponding program address of the corresponding processor, with the cyclical allocation taken into account.
- The processor programs for the various ones of the processors, with regard to the times or program addresses for memory accesses and/or program jumps, are furnished in mutually matched fashion by a higher-level instance or a higher-level process. This may be implemented for example by appropriate programming on the part of a programmer and/or by a suitably set-up assembling or compiling device.
- A multiprocessor system includes at least a first processor and a second processor, and a memory area to which the first and second processors have access. A processor program individually allocated to the processor in question permits access to the memory area only at times cyclically uniquely allocated for this processor and, within the cycle, temporally offset relative to the other processors.
- Logic links times for memory accesses to the memory area and/or jumps within the processor program in question in cyclical fashion in dependence on the last bit or bits of a program address of the processor program.
- The program sequences or processor programs of the individual processors may be constructed and/or driven in such fashion that relatively expensive hardware arbitration logic is not required. This makes it possible to save footprint area and computing power.
- The program sequences to control access to the memory area may be suitably constructed during programming and implemented by a compiler and/or assembler. Within the system, the program sequences offset all processors that can access a common memory area into a clearly defined state relative to one another.
- A cyclically unique allocation of permissible times for access to the memory area may be implemented by the use of the modulo function in the creation of the program sequences. In such a system the last bits of the program addresses of the respective processors can advantageously exhibit a cyclically unique spacing relative to one another independently of the program sequence, in simple cases for example a constant difference. Alternatively, it is also possible to have a separate counter running at the same time, the counter values ultimately being in a fixed relation to the last bits of the program addresses. The last bits of the address can then be evaluated and then correspondingly, in dependence thereon, the memory area or memory can be associated with a uniquely allocated one of the processors, so that access to the memory or a part of the memory is always permitted to only one of the processors. The executable program instructions in the form of the program sequences ensures that a processor accesses the memory or memory area only when, according to the corresponding address bit of its program sequence, it also has access authorization from the logic circuit.
- The number of program address bits that are used for memory access control depends on the number of processors that can use the memory area in common. In the case of two processors, only the last bit of the program addresses of these two processors need to be considered. In the case of four processors, the last two bits are used. If the number of processors is greater, the number of bits of the corresponding program addresses used is increased correspondingly.
- In the case of jumps within one of the program sequences from an instantaneous program address not to a program address that follows directly but instead to a program address lying behind or further ahead, in order to ensure the control of suitable memory access times for one of these processors, all processors of the system are advantageously permitted to execute jumps only with consideration of the cyclical spacing of the permitted memory access times. In the case of a system having just two processors, a jump from an even program address is correspondingly allowed only to an odd program address, and from an odd program address only to an even program address. The implementation can be effected for example by hardware or directly by the software or the compiler.
- It is advantageously ensured that all processors at a certain time within their individual program sequences each process a certain program address or a program address cyclically uniquely allocated to this certain program address. For example, after a reset, all processors can simultaneously start at
address 0 or offset by a defined number of clock cycles relative thereto. This ensures that all processors are always left with instructions for a memory access in the processing of program steps in cyclical fashion relative to one another. - A logic circuit may correspondingly perform a configuration of one or a plurality of memory areas or RAM blocks in such fashion that a certain one of the processors always accesses the memory area in an even clock cycle, while the other processor always accesses the memory area in an odd clock cycle. Write or read rights thus alternate with each processor cycle. Thus it is possible to ensure in simple fashion, through the software or the compiler that controls the allocated one of the processors as program sequence in each case, that the two processors always access the memory area only when they are in the correct clock cycle.
- It is especially advantageous if an instruction or an instruction word always has the same length for all processors, as is generally the case in so-called RISC processors.
- These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.
-
FIG. 1 schematically illustrates a multiprocessor architecture having two processors that use a common memory area, as well as program sequences that are allocated to the processors; -
FIG. 2 schematically illustrates a multiprocessor architecture having two alternative program sequences; and -
FIG. 3 schematically illustrates a multiprocessor architecture having four processors that can access the same memory area, and having four program sequences correspondingly allocated to the processors. -
FIG. 1 illustrates a multiprocessor architecture that includes afirst processor 0 and asecond processor 1 and at least one memory device M, which the first and second processors can access in order to write and/or read data. Although the embodiment illustrated inFIG. 1 illustrates two processors for ease of illustrating, one of ordinary skill will recognize that the present invention is certainly not limited to two processors. Allocated to each of theprocessors processors processors processors - The memory device M includes a memory area MX to which both the
processors processors processors - Control of memory accesses to the memory area MX by the logic L is implemented in such that the
processors - For coordination of the
processors example program address 0. At each clock pulse, the program sequences advance by one program step, unless program jumps are provided within one of the program sequences. For the control of the cyclically unique access of theprocessors first processor 0 may access the memory area MX only at even program addresses 0, 2, 4, 6, 8, . . . . This is mathematically describable by themodulo function mod 2=0. Similarly, thesecond processor 1 may access the memory area MX only at odd program addresses 1, 3, 5, 7, 9, . . . , which can be described by themodulo function mod 2 equals 1. Such a stipulation in relation to the processor programs p0, p1 or their program sequences furnishes a simple logic or logic circuit that prevents a collision of accesses to the memory area MX by the twoprocessors - For example, as illustrated in
FIG. 1 , thefirst processor 0 accesses the memory area MX to store data at a sixth program address ad equals 6, while thesecond processor 1 accesses the memory area MX for storage at the program step of its ninth program address ad equals 9. Thefirst processor 0 accesses the memory area MX to load data from the memory area MX at, for example, its second program step, that is, at the instruction according to the second program address ad equals 2. - In the programming, or as appropriate in the assembly or compilation, of both the processor programs p0 and p1, it is correspondingly made certain that both the
processors - In order to make this certain in the case of program sequences having program jumps within the processor program p0, p1, it is stipulated for such program jumps that they are to be executed with uniquely allocated times or program addresses ad taken into account. In the case of the arrangement having two
processors
(ad new−1)mod 2=ad mod 2
where adnew is the program address to which the jump is to be made and ad is the instantaneous program address. - For example, referring still to
FIG. 1 , in the processor program p0 of thefirst processor 0 there is an optional jump from the third program step or the third program address ad to the eighth program address. Instead of proceeding from the third program address (i.e., ad=3) to fourth program address (i.e., ad=4), that is, to an immediately following even program address ad, the program sequence proceeds to another even program address ad, namely the eighth program address (i.e., ad=8). An additional program jump is illustrated from the seventh program address (i.e., ad=7) to the tenth program address (i.e., ad=10). If a program jump is executed starting from an even program address ad, the jump must take place to an odd program address, as for example from twelfth program address (i.e., ad=12) to first program address (i.e., ad=1). Similarly, jumps between program addresses ad are also sketched in the processor program p1 of thesecond processor 1, jumps again taking place from even program addresses ad to odd program addresses ad and from odd program addresses ad to even program addresses ad. - In this way, starting at the synchronization time, both the
processors first processor 0, if a memory access would otherwise fall at an impermissible access time. -
FIG. 2 illustrates an alternative or, as appropriate, also a combined embodiment wherein both theprocessors second processor 1 falls simultaneously with an even program address ad of the process program p0 of thefirst processor 0. In this embodiment the program sequences are so fashioned that both theprocessors first processor 0 and, respectively, at eighth program address ad=8 of the processor program p1 of thesecond processor 1. In this embodiment the programmer, assembler or compiler makes certain that an access to the memory area MX always takes place on an even—or alternatively always on an odd—program address ad, because at a time t both the processor programs p0, p1 are always at an even program address ad on the one hand and at an odd program address ad on the other. This lightens the work of programming and avoids programming errors. With regard to program jumps, the same conditions apply as in the embodiment illustrated in toFIG. 1 . -
FIG. 3 illustrates an embodiment of a multiprocessor architecture that includes fourprocessors FIG. 1 , an individually allocated memory segment M0-M3 or memory may be allocated to each of the processors 0-3. Here it is important that the four processors 0-3 all have access to a memory area MX, which as appropriate is also embodied in a freestanding memory device. Once again accesses to memory area M are controlled by logic L, preferably implemented in software by suitable programming of individual processor programs p0-p3 of the processors 0-3. With respect to memory accesses, a cycle of permissible program addresses ad is stipulated, which cycle takes into account that a number m of the four processors 0-3 may access the memory area MX. For an o-th one of the m processors 0-3 the permissible program addresses ad for memory accesses are preferably stipulated by the modulo function according to:
ad mod m=o
in the context of programming of the processor programs p0-p3. Naturally, other cyclical access times are also possible, for example two memory access times or addresses within each cycle for a certain one of the processors P if this processor is assigned tasks that necessitate more frequent accesses to the memory area MX than are necessary for the other processors P. In the program sequences illustrated, memory accesses to the memory area MX for loading or storing data are provided, for example, at program addresses ad equals 0 and ad equals 8 in processor program p0 of thefirst processor 0. In the processor programs p1, p2, p3 for the processors 1-3, correspondingly, memory accesses to the memory area MX are provided for example at program addresses ad equals 9, ad equals 6 and ad equals 3, respectively. - The calculation of permissible jumps within the processor programs p0-p3 is also modified in correspondence with the increased number of processors P may be calculated as follows:
(ad new−1)mod m=ad mod m
where adnew is the program address to which the jump is to be executed, ad is the instantaneous program address and m is the number of processors P used. - In the example with four processors 0-3, which are all synchronized at the same time t=0 using synchronization signal to, jumps from one of the program addresses ad to another program address adnew are correspondingly executed, only from an address value x*4 to another address value [(x*4)+1].
- Jumps after processing of the corresponding instructions may stand correspondingly, for example, at
addresses destinations first processor 0 may access the memory area MX or RAM at program addresses ad=0, 4, 8, 12, . . . . Thesecond processor 1 may access the memory area MX or RAM at program addresses ad=1, 5, 9, 13, . . . . Jumps after processing of the corresponding instructions may correspondingly stand, for example, ataddresses destinations third processor 2 may access the memory area MX or RAM at program addresses ad=2, 6, 10, 14, . . . . Jumps after processing of the corresponding instructions may correspondingly stand, for example, ataddresses destinations fourth processor 3 may access the memory area MX or RAM at program addresses ad=3, 7, 11, 15, . . . . - In general, for the special case according to
FIG. 3 , where for example m is the cycle time and also the number of processors; q is the next-greater power of two of m in the case of jumps directed only upward; i is a whole number with i=0, . . . , q−1; r is a whole number greater than zero; and ad is the program address, it is the case that jumps may stand only at a program address satisfying n=[(r*q)+1] and may lead only to an address n+1. In this case, the processors 0-3 are always in a cyclically defined state relative to one another. In such a case, logic L can grant access by one of the processors to a memory address or a memory when [(ad mod q)=i]. - The quantity m, which governs the cycle time or cycle length, need not necessarily be tied to the number of processors P actually present but may also exhibit a larger value. This is advantageous for example when other processors or devices are to be permitted access to the memory area MX in the intervening time. The cycle time m is also expediently set correspondingly larger than the actual number of processors P when a larger permissible number of cyclical memory accesses is allocated to one of the processors P than to the others of processors P. This correspondingly impacts access times t or program addresses ad for memory accesses as well as the conditions for permissible jumps within respective processor programs p0-p3.
- Although the present invention has been illustrated and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/749,011 US8095743B2 (en) | 2005-08-12 | 2010-03-29 | Memory access control in a multiprocessor system |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102005038567A DE102005038567A1 (en) | 2005-08-12 | 2005-08-12 | Multi-processor architecture and method for controlling memory access in a multi-process architecture |
DE102005038567.2 | 2005-08-12 | ||
DE102005038567 | 2005-08-12 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/749,011 Continuation US8095743B2 (en) | 2005-08-12 | 2010-03-29 | Memory access control in a multiprocessor system |
Publications (2)
Publication Number | Publication Date |
---|---|
US20070038817A1 true US20070038817A1 (en) | 2007-02-15 |
US7689779B2 US7689779B2 (en) | 2010-03-30 |
Family
ID=37662152
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/503,673 Expired - Fee Related US7689779B2 (en) | 2005-08-12 | 2006-08-14 | Memory access control in a multiprocessor system |
US12/749,011 Active US8095743B2 (en) | 2005-08-12 | 2010-03-29 | Memory access control in a multiprocessor system |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/749,011 Active US8095743B2 (en) | 2005-08-12 | 2010-03-29 | Memory access control in a multiprocessor system |
Country Status (3)
Country | Link |
---|---|
US (2) | US7689779B2 (en) |
EP (1) | EP1770521B1 (en) |
DE (2) | DE102005038567A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090113159A1 (en) * | 2007-10-29 | 2009-04-30 | Mekhiel Nagi N | Data processing with time-based memory access |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140331019A1 (en) * | 2013-05-06 | 2014-11-06 | Microsoft Corporation | Instruction set specific execution isolation |
US20160070662A1 (en) * | 2014-09-04 | 2016-03-10 | National Instruments Corporation | Reordering a Sequence of Memory Accesses to Improve Pipelined Performance |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4484273A (en) * | 1982-09-03 | 1984-11-20 | Sequoia Systems, Inc. | Modular computer system |
US6314505B1 (en) * | 1998-10-13 | 2001-11-06 | Mitsubishi Denki Kabushiki Kaisha | Processor and method for accessing rectangular areas in memory |
US20050050282A1 (en) * | 2003-09-02 | 2005-03-03 | Vantalon Nicolas P. | Memory reallocation and sharing in electronic systems |
US20050080999A1 (en) * | 2003-10-08 | 2005-04-14 | Fredrik Angsmark | Memory interface for systems with multiple processors and one memory system |
US6931506B2 (en) * | 2002-02-20 | 2005-08-16 | Stmicroelectronics Sa | Electronic device for data processing, such as an audio processor for an audio/video decoder |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5010476A (en) * | 1986-06-20 | 1991-04-23 | International Business Machines Corporation | Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units |
US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
US6473821B1 (en) * | 1999-12-21 | 2002-10-29 | Visteon Global Technologies, Inc. | Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems |
-
2005
- 2005-08-12 DE DE102005038567A patent/DE102005038567A1/en not_active Ceased
-
2006
- 2006-08-01 EP EP06015962A patent/EP1770521B1/en not_active Not-in-force
- 2006-08-01 DE DE502006007257T patent/DE502006007257D1/en active Active
- 2006-08-14 US US11/503,673 patent/US7689779B2/en not_active Expired - Fee Related
-
2010
- 2010-03-29 US US12/749,011 patent/US8095743B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4484273A (en) * | 1982-09-03 | 1984-11-20 | Sequoia Systems, Inc. | Modular computer system |
US6314505B1 (en) * | 1998-10-13 | 2001-11-06 | Mitsubishi Denki Kabushiki Kaisha | Processor and method for accessing rectangular areas in memory |
US6931506B2 (en) * | 2002-02-20 | 2005-08-16 | Stmicroelectronics Sa | Electronic device for data processing, such as an audio processor for an audio/video decoder |
US20050050282A1 (en) * | 2003-09-02 | 2005-03-03 | Vantalon Nicolas P. | Memory reallocation and sharing in electronic systems |
US20050080999A1 (en) * | 2003-10-08 | 2005-04-14 | Fredrik Angsmark | Memory interface for systems with multiple processors and one memory system |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090113159A1 (en) * | 2007-10-29 | 2009-04-30 | Mekhiel Nagi N | Data processing with time-based memory access |
US8914612B2 (en) | 2007-10-29 | 2014-12-16 | Conversant Intellectual Property Management Inc. | Data processing with time-based memory access |
Also Published As
Publication number | Publication date |
---|---|
US8095743B2 (en) | 2012-01-10 |
EP1770521A2 (en) | 2007-04-04 |
EP1770521A3 (en) | 2008-01-16 |
DE102005038567A1 (en) | 2007-02-15 |
US20100235589A1 (en) | 2010-09-16 |
EP1770521B1 (en) | 2010-06-23 |
DE502006007257D1 (en) | 2010-08-05 |
US7689779B2 (en) | 2010-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102269504B1 (en) | Control device for a motor vehicle | |
US9063907B2 (en) | Comparison for redundant threads | |
US4583162A (en) | Look ahead memory interface | |
EP0637802A2 (en) | Interrupt vector method and apparatus | |
US20080034132A1 (en) | Memory interface for controlling burst memory access, and method for controlling the same | |
US8095743B2 (en) | Memory access control in a multiprocessor system | |
US5615140A (en) | Fixed-point arithmetic unit | |
US6292853B1 (en) | DMA controller adapted for transferring data in two-dimensional mapped address space | |
JP2005332370A (en) | Control unit | |
US7076641B2 (en) | Programmable controller | |
JP3562215B2 (en) | Microcomputer and electronic equipment | |
EP0334738A1 (en) | Device for control and for acquisition of data at high speed | |
US7120760B2 (en) | Harvard architecture microprocessor having a linear addressable space | |
JPH11250025A (en) | Processor, loop program controller and multiprocessor system | |
US7707450B1 (en) | Time shared memory access | |
US20240126709A1 (en) | Direct memory access controller | |
US6980314B1 (en) | Method and device for improving utilization of a bus | |
JP2010191511A (en) | Microprocessor | |
JPS61253559A (en) | Microprocessor | |
JPH0333951A (en) | Microcomputer system | |
JPH01124038A (en) | Microprocessor | |
JP2001117862A (en) | Microcomputer | |
US20150058505A1 (en) | Method for operating a buffer memory of a data processing system and data processing system | |
JP2003228546A (en) | Control device for direct memory access | |
JP2001155006A (en) | Bus control circuit and microcomputer system using the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MICRONAS GMBH,GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VIERTHALER, MATTHIAS;NOESKE, CARSTEN;REEL/FRAME:018309/0165 Effective date: 20060913 Owner name: MICRONAS GMBH, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VIERTHALER, MATTHIAS;NOESKE, CARSTEN;REEL/FRAME:018309/0165 Effective date: 20060913 |
|
AS | Assignment |
Owner name: TRIDENT MICROSYSTEMS (FAR EAST) LTD.,CAYMAN ISLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRONAS GMBH;REEL/FRAME:024456/0453 Effective date: 20100408 Owner name: TRIDENT MICROSYSTEMS (FAR EAST) LTD., CAYMAN ISLAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRONAS GMBH;REEL/FRAME:024456/0453 Effective date: 20100408 |
|
AS | Assignment |
Owner name: ENTROPIC COMMUNICATIONS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TRIDENT MICROSYSTEMS, INC.;TRIDENT MICROSYSTEMS (FAR EAST) LTD.;REEL/FRAME:028153/0530 Effective date: 20120411 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140330 |