US20070077724A1 - Etching methods and apparatus and substrate assemblies produced therewith - Google Patents
Etching methods and apparatus and substrate assemblies produced therewith Download PDFInfo
- Publication number
- US20070077724A1 US20070077724A1 US11/469,010 US46901006A US2007077724A1 US 20070077724 A1 US20070077724 A1 US 20070077724A1 US 46901006 A US46901006 A US 46901006A US 2007077724 A1 US2007077724 A1 US 2007077724A1
- Authority
- US
- United States
- Prior art keywords
- resist
- etching
- thickness
- substrate assembly
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3343—Problems associated with etching
- H01J2237/3345—Problems associated with etching anisotropy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
- H01J2237/32—Processing objects by plasma generation
- H01J2237/33—Processing objects by plasma generation characterised by the type of processing
- H01J2237/334—Etching
- H01J2237/3343—Problems associated with etching
- H01J2237/3347—Problems associated with etching bottom of holes or trenches
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
- Y10T428/2457—Parallel ribs and/or grooves
Abstract
Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched.
Description
- This application is a continuation of co-pending application Ser. No. 10/895,502, filed Jul. 20, 2004, which is a continuation of application Ser. No. 09/916,734, filed Jul. 26, 2001, now U.S. Pat. No. 6,784,111, which is a division of application Ser. No. 09/342,677, filed Jun. 29, 1999, now U.S. Pat. No. 6,635,335, which are incorporated herein by reference.
- The invention pertains to methods and apparatus for etching silicon wafers or other substrate assemblies and to substrate assemblies.
- The fabrication of very large-scale integrated circuits requires processes that are compatible with small feature sizes (e.g., 0.25 μm). A particular problem is the etching of a silicon wafer or other substrate assembly to produce damascene layers, self-aligned contacts (SACs), or trench isolation. These features typically require etching relatively deeply into the wafer while maintaining a small footprint on the surface of the substrate assembly, i.e., these features have a high-aspect-ratio (HAR), with a depth-to-width (on the surface of the substrate assembly) ratio of 4:1 or larger.
- Features to be etched into a substrate assembly are typically defined with a layer of photoresist that is spin-coated or otherwise applied onto a surface of the substrate assembly and then photolithographically patterned. After patterning, some areas of the substrate assembly surface remain covered by the photoresist layer while other areas are exposed. The covered substrate assembly is exposed to an etch, and the photoresist layer prevents etching except in the exposed areas.
- Etching of HAR features requires anisotropic etches that etch more rapidly in one direction than another. Conventional wet etches include dilute solutions of acids such as hydrofluoric acid. While wet etching is simple and inexpensive, wet etching is generally inadequate to produce HAR features because wet etches tend to etch isotropically. In addition, it is difficult to etch deep HAR features into a substrate assembly because the etchant does not flow freely into and out of the feature. Therefore, even if a wet etch begins to etch properly, etchant is consumed within the feature being etched and is replenished slowly.
- Dry etching with plasmas is also used for etching substrate assemblies. In plasma etching, a gas or gas mixture is fragmented and ionized and the ions produced are accelerated toward the substrate assembly. When the ions reach the substrate assembly, they combine chemically with the substrate assembly to form volatile compounds that are readily driven off of the substrate assembly. In some cases, the mechanical impact of the ions with the substrate assembly also serves to etch the substrate. Because of the acceleration of the ions toward the substrate assembly, etching is anisotropic and proceeds rapidly on surfaces that are perpendicular to the propagation direction of the ions.
- Unfortunately, dry etching with a plasma has significant limitations. While plasmas etch anisotropically, a plasma etches both the substrate assembly and the photoresist that defines the features to be produced. As a result, the total etching time is limited by the time required for the plasma etch to penetrate the photoresist. When the photoresist is penetrated, further etching is no longer limited to the intended substrate locations, but occurs in all substrate areas that are not protected by the photoresist. Photoresists typically etch four to five times more slowly than typical substrate materials to be etched (such as silicon or silicon oxide). Etching processes in which a substrate material is etched at a rate of less than about eight times the rate at which a resist etches are referred to herein as “resist-consuming.”
- Etching deep HAR features requires thick layers of photoresist to permit long etch times, and such thick layers complicate the photolithographic patterning process. For example, to etch a HAR feature 3000 nm deep requires a photoresist thickness of as much as 750 nm. Patterning a feature as small as about 250 nm is very difficult in such a thick layer of photoresist.
- Other factors limiting plasma etching include the difficulty of providing a selected distribution of ions (charged particles) and neutral particles at the substrate surface and at the bottom of a feature being etched. Accordingly, improved etching methods are needed, especially for etching high-aspect-ratio features. A resist layer has a nominal thickness and a facet thickness, either or both of which are maintained, preserved, or increased in the disclosed methods and apparatus.
- Methods and apparatus for etching substrate assemblies are disclosed in which a surface of a substrate assembly is etched while a thickness of a resist layer increases, remains constant, or decreases much more slowly than in a conventional etching process.
- In a representative embodiment, the substrate assembly is exposed to a plasma made in a selected gas, which may be a gas mixture, at a selected flow rate. The gas and flow rate are selected by exposing a resist layer to the plasma formed in the gas and determining a range of flow rates for which the thickness of the resist layer, including any material deposited on the resist layer by the plasma, increases, remains constant or decreases more slowly than in known approaches. The etching rate of the selected gas is then measured for this range of flow rates on a surface of a substrate assembly. A flow rate is then selected for etching the surface of the substrate assembly for which the resist thickness increases or otherwise changes in the desired manner while a surface is etched.
- In an alternative embodiment, the flow rate is selected so that the resist is etched much more slowly (for example ten to twenty times) than the surface of the substrate assembly. In some embodiments, the substrate assembly includes a silicon oxide layer that is etched with the selected gas at the selected flow rate.
- A method of plasma etching is provided in which a high-aspect-ratio feature is etched into a surface of a substrate assembly while a resist layer covering a portion of the surface thickens, remains a constant thickness, or thins by less than about 25 nm. In addition, the method may provide a controlled-etch profile so that the sides of the etched feature have taper or undercut angles of less than about ten degrees and, more specifically, in one approach less than about five degrees.
- A method of anisotropically etching a substrate assembly is provided that comprises forming a resist layer on a surface of a substrate assembly and defining patterns in the resist layer by removing portions of the resist layer. The resist layer and the surface of the substrate are exposed to a plasma etch. In one specific approach, an exposed portion of the surface of the substrate assembly is etched by the plasma while the plasma increases the thickness of the resist layer. In another representative embodiment, the surface of the substrate assembly is exposed to a plasma generated in a gas consisting essentially of a fluorinated, chlorinated, or hydrogenated hydrocarbon gas, or a mixture thereof. In additional embodiments, the thickness of the resist layer formed on the substrate assembly is less than about 600 nm. In a further embodiment, the resist layer has a thickness of d, and a high-aspect-ratio feature is etched into the substrate assembly to a depth D such that D/d>10.
- Etched substrate assemblies are disclosed that may include an etched feature having an aspect ratio of at least 10:1 or higher, such as at least 20:1.
- In additional embodiments, the substrate assembly includes a silicon oxide layer formed on a silicon wafer and the etched feature is etched into the silicon oxide layer.
- In another method, a feature is etched into a substrate assembly by forming a resist layer on a surface of the substrate assembly and defining a feature on the surface by patterning the resist layer by removing the resist layer from at least a portion of the substrate assembly. The portion of the substrate assembly that is not covered by the resist layer is etched with a plasma generated in a flow of a first halogenated hydrocarbon-containing gas or gas mixture. Simultaneously with the etching of the substrate assembly, the plasma increases the thickness of the resist layer, and the feature is etched to have an aspect ratio of at least 10:1. In a further embodiment, one or more subsequent or prior etches, including a resist-consuming etch, may be performed to etch the portion of the substrate assembly that is not covered by the resist.
- In another embodiment a method of etching a high-aspect-ratio feature having a controlled profile is provided. The method includes the steps of selecting a substrate assembly and selecting a surface of the substrate assembly to be etched. A depth D and width d of a high-aspect-ratio feature are selected, for example such that D/d>10. In this example, a resist layer of thickness less than about D/5 is formed on the selected surface of the substrate assembly. The high-aspect-ratio feature is then etched into the selected surface of the substrate assembly with a controlled profile. In one embodiment, the substrate assembly is a silicon wafer with a layer of silicon oxide. In other embodiments, the thickness of the resist layer is selected to be less than about D/7, D/10 or D/15.
- In another embodiment, a resist layer having a nominal thickness is deposited on a surface of a substrate assembly and patterned by removing selected portions of the resist layer, exposing a portion of the surface of the substrate assembly. The substrate assembly is etched to a depth of at least five times the nominal thickness at the exposed portion of the surface.
- An etched substrate assembly is disclosed that comprises a selected surface and a feature etched into the selected surface to a depth D and width w, wherein D/w is greater than about 10. The substrate assembly may include a resist layer covering the surface except at the high-aspect-ratio feature, the resist layer having a thickness d, wherein d/D is greater than about 1/10.
- The invention is directed to novel and non-obvious aspects of this disclosure, both individually and in combination as set forth in the claims below.
-
FIG. 1A is a sectional view of an ideal high-aspect-ratio feature etched into a substrate assembly. -
FIG. 1B is a sectional view of a high-aspect-ratio feature etched into a substrate assembly illustrating a taper with a local bow. -
FIG. 1C is a sectional view of a high-aspect-ratio feature etched into a substrate assembly illustrating a taper with a barrel-shaped bow. -
FIG. 1D is a sectional view of a high-aspect-ratio feature etched into a substrate assembly illustrating undercut. -
FIG. 2 is a sectional view of one example of a plasma etcher for etching a substrate assembly. -
FIG. 3A is a plan view of a portion of the substrate assembly ofFIG. 2 prior to etching. -
FIG. 3B is a sectional view of a portion of the substrate assembly ofFIG. 2 prior to etching. -
FIG. 3C is a sectional view of a portion of the substrate assembly ofFIG. 2 after etching. -
FIG. 4A is a sectional view of a substrate assembly coated with a patterned resist. -
FIG. 4B is a sectional view of the substrate assembly ofFIG. 4A after etching. -
FIG. 4C is a sectional view of the substrate assembly ofFIG. 4B after additional etching. - Methods, apparatus, and etched substrate assemblies are disclosed. In semiconductor manufacturing, a common starting material is a silicon wafer that is either doped or undoped. For some semiconductor devices, other wafer materials are used such as GaAs and InP. During device manufacturing, layers of various materials are applied to a surface of the wafer and circuit features are defined on the wafer. As used herein, a substrate assembly refers to a semiconductor wafer including any features or layers formed on the wafer.
- The methods and apparatus disclosed are suitable for etching so-called high-aspect-ratio (“HAR”) features as well as other features. As used herein, a high-aspect-ratio feature is a feature having a depth-to-width ratio of at least 5:1, wherein a depth is a dimension of a feature measured in a direction perpendicular to the etched surface of the substrate assembly, and a width is a dimension of a feature measured in a direction parallel to the etched surface. In approaches described below, extremely high-aspect-ratios are achievable, such as at least 10:1 and higher, such as at least 20:1.
-
FIGS. 1A-1D are sectional views (not to scale) of HAR features etched into asurface 22 of asubstrate assembly 21. Referring toFIG. 1A , anideal HAR feature 23 has anend surface 25 andside walls 27; theside walls 27 are perpendicular to theend surface 25 and to thesurface 22 of thesubstrate assembly 21. In practice, HAR features tend to differ from this ideal shape. Referring toFIG. 1B , aHAR feature 33 etched in thesubstrate assembly 21 has aside wall 37 and anend surface 35. Theside wall 37 is an example of taper. At theend surface 35 theside wall 37 is tilted with respect to aline 40 that is perpendicular to thesurface 22 at a taper angle A. Taper is typically associated with alocal bow 39. Referring toFIG. 1C , theHAR feature 33 is shown with a barrel-shapedbow 41.FIG. 1D shows aHAR feature 53 that is etched so that aside wall 57 is tilted with respect to aline 54 that is perpendicular to asurface 52 at an undercut angle B. For HAR features, the angles A, B are preferably less than about 10 degrees, and more preferably less than about 5 degrees. HAR features having taper angles or undercut angles less than a selected angle are referred to herein as “controlled-profile” features.FIGS. 1A-1D illustrate HAR features but features with lesser aspect ratios also exhibit bow, undercut, and taper. -
FIG. 2 is a cross-sectional schematic view of one form of aplasma etcher 200. The illustratedplasma etcher 200 includes achamber 203 defined by anRF window 205, anenclosure 207, ahot ring 209, and a substrate-assembly chuck 211. The substrate-assembly chuck 211 includes acollar 213 and aceramic base 215 to support a substrate-assembly 217, such as a silicon wafer or other substrate assembly.Exhaust ports 219 are defined by gaps between theenclosure 207 and thehot ring 209, and connect to exhaustchambers 221. TheRF window 205 and thehot ring 209 are maintained at selected temperatures withrespective temperature controllers RF window 205 and thehot ring 209 are typically maintained between 120-200 degrees Centigrade and 150-300 degrees Centigrade, respectively. TheRF window 205 and theenclosure 207 may be made of either silicon (Si) or silicon carbide (SiC) or a combination thereof, and thehot ring 209 and thecollar 213 may be made of quartz and silicon, respectively. Silicon, especially when heated, can remove or “getter” fluorine from thechamber 203 and thus can alter the composition of a fluorine-containing gas mixture if included in thechamber 203. - In this etcher, a first set of
induction coils 233 and a second set ofinduction coils 235 are coaxially placed in proximity to theRF window 205, with thesecond set 235 placed within thefirst set 233.RF generators 239, 237 connect to the first and second set ofinduction coils bias generator 241 is provided that connects to thesubstrate assembly chuck 211. RF excitations (RF voltages or currents) from theRF generators 239, 237 are applied to the first and second sets ofinduction coils RF window 205. TheRF window 205 and thechamber walls 207 in this example are grounded. Because theRF window 205 is at least partially electrically conducting, theRF window 205 shields thechamber 203 from the oscillating electric fields produced by thecoils RF window 205. As a result of the shielding effect of theRF window 205, the oscillating magnetic field produced by thecoils chamber 203. TheRF generators 237, 239 in the illustrated etcher provide RF excitations at frequencies of between about 1.0-3.0 MHz at respective powers between about 400-1250 W and 500-1200 W. The RF bias 241 provides an RF power of between about 0-250 W to thesubstrate assembly chuck 211 at a frequency between about 1-3 MHz. - A
gas inlet 251 is connected to agas supply manifold 253. Gases, which may be gas mixtures, for thechamber 203 are mixed at thegas manifold 253 and supplied to thechamber 203 through agas inlet 251. Avacuum pump 255 is situated to evacuate thechamber 203 and is connected to thechamber 203 via avalve 256. During etching, the pressure in the chamber may generally be maintained in the range of from about 2 mTorr to 50 mTorr. - One specific etcher of the type shown in
FIG. 2 is an IPS Dielectric Etcher from Applied Materials, Inc., of Santa Clara, Calif. -
FIGS. 3A-3B show thesubstrate assembly 217 prior to etching. Thesubstrate assembly 217 may be asilicon wafer 217 b covered with asilicon oxide layer 217 a. Thesilicon wafer 217 b typically has a thickness of less than 1-2 mm and a diameter of 50-600 mm and can be doped or undoped. Thesilicon oxide layer 217 a can be formed in different ways such as, for example, deposited from a gas such as tetraethyoxysilane (TEOS) or thermally grown (thermal oxide). Theoxide layer 217 a is coated with a patterned resistlayer 301, the resist layer having a nominal thickness tN.Apertures layer 301 to permit substrate etching. Although fabrication processes attempt to maintain planarity of thesubstrate assembly 217, thesubstrate assembly 217 generally has one or more high regions such as theregion 307. At theregion 307, the thickness of the resistlayer 301 is less than the nominal thickness tN. When situated on thesubstrate assembly chuck 211, theoxide layer 217 a and the resistlayer 301 are exposed to the plasma in thechamber 203. The resistlayer 301 can be made of any suitable resist material, including photoresists, deep ultraviolet resists, X-ray resists, electron-beam resists, I-line resists, and multilayer resists. The selected resist material can be deposited by spin coating or any other suitable method, and patterned with conventional photolithographic or other patterning process, such as X-ray, I-line, and electron-beam lithography. - Conventional plasma etching etches the resist
layer 301 as well as thesilicon oxide layer 217 a. The rate at which the resistlayer 301 etches is generally slower than the rate at which thesilicon oxide layer 217 a etches. The ratio of the etch rate of a substrate assembly layer such as thesilicon oxide layer 217 a to the etch rate of the resistlayer 301, referred to herein as etch “selectivity,” is less than 8:1, and is typically less than about 5:1. The term “resist-consuming” approach refers to an approach wherein the selectivity is less than 8:1. Because both the resistlayer 301 and silicon oxide (substrate)layer 217 a etch in a conventional approach, production of a HAR feature in a conventional approach requires a resist layer thick enough so that the resist layer is not etched through before the HAR feature is etched to the required depth. The use of thick layers of resist in conventional etching complicates the deposition of the resist layer and especially the lithographic patterning of the resist layer. In addition, the limited selectivity reduces the aspect ratio which is achievable. - Surprisingly, these disadvantages of conventional etching are overcome by the approach disclosed herein. For example, by selectively adjusting a flow rate of a gas or gas mixture in the
chamber 203, the rate at which resist material is etched significantly decreases. Even more surprisingly, in some embodiments of this approach, the nominal thickness tN of the resist layer does not change significantly during etching. Thus, the nominal resist thickness tN increases, stabilizes, or slowly decreases, providing selectivities of greater than 10:1, 100:1, or larger, while still permitting etching with a controlled profile. Although not limited to a specific theory of operation, the changes in the etch rate of the resist may be attributable to plasma deposition of additional material on the resistlayer 301, chemical reactions induced by the plasma in the resistlayer 301 so that constituents of the gas mixture are incorporated into the resist, or chemical reactions of the resistlayer 301 with the plasma. As used herein, an etch process in which a resist thickness is increased is a “resist-enhancing” process and an etch process in which an etch rate of a resist is less than about one-tenth that of a substrate material is a “resist-conserving” process. - Because the nominal resist thickness tN increases, stabilizes, or decreases more slowly than in a “resist-consuming” etching process, substrate assemblies having surfaces that have ideal planarity as well as those that deviate from planarity are more reading etched. To etch nonplanar surfaces, the nominal thickness tN of the resist layer is selected to protect high regions such as the
region 307 until etching is complete. The resistlayer 301 is then thicker in planar regions of thesubstrate assembly 217 in order to protect theregion 307. With the resist-conserving or resist-enhancing processes described herein, a thinner nominal thickness can be applied and is sufficient to protect the substrate assembly, even at higher regions such as theregion 307. Subsequent photolithographic steps are simpler because patterns to be etched can be better focused in a thin resist layer than a thick layer. For thick resist layers, precise focusing during photolithography is important. For thin resist layers, larger focus errors are more readily tolerated. -
FIG. 3C shows thesubstrate assembly 217 after partial etching. As is apparent fromFIG. 3C , the resistlayer 301 is etched and the nominal thickness tN of the resistlayer 301 is changed. A facet region is a region at the edge of a feature. The thickness of the resist at the facet may be the same as the nominal thickness. Alternatively, the resist at the facet may differ from the nominal thickness, for example, be thinner as a result of etching. InFIG. 3C , afacet region 313 of the resistlayer 301 is shown etched so that the nominal thickness tN is not the same as a face thickness tF. The facet thickness tF is particularly important for etching high resolution features. Once the resistlayer 301 is removed so that the facet thickness tF is zero, the etched feature size is not longer controlled by the resistlayer 301. In the resist-conserving and resist-enhancing methods and apparatus disclosed herein, the facet thickness tF changes more slowly, stabilizes, or increases during etching. Thus, etch processes can be resist-enhancing or resist-conserving with respect to facet thickness tF, nominal thickness tN, or both. As used herein, the phrase “resist-layer thickness” means nominal thickness tN, facet thickness tF, or both. - In one example, by etching with a selected gas-flow rate, the resist-layer thickness increases or remains constant during etching, or is etched very much more slowly than in conventional plasma etching. In some cases, the resist layer is thicker after etching than it was initially, i.e., the etching process is resist-enhancing. In some cases, the resist layer thins slightly (by no more than about 25-50 nm) at the start of etching, and then the resist-layer thickness either stabilizes, begins to increase, or decreases more slowly than in a resist-consuming process. The initial thinning of the resist is referred to as “start-up loss.” The composition of the added material is a function of the resist material, the gas used to generate the plasma, or both. Using a plasma generated in a fluorinated hydrocarbon gas, the increased or stabilized thickness may result from incorporation of additional fluorine into the resist or deposition of a fluorinated material on the resist.
- Maintaining the selected gas-flow rate permits etching of a substrate material to proceed while the resist thickens. Note that the resist-enhancing etch process disclosed herein differs from conventional chemical vapor deposition (CVD) in that etching and thickening occur simultaneously and that there is no thickening (or deposition) at surfaces that are unprotected by resist.
- For the
etching system 200 ofFIG. 2 , the powers provided to the source and the bias can be selected in conjunction with a flowrate to provide a resist-enhancing or a resist-conserving process. Generally low powers are preferred, but for selected power levels, the flowrate can be adjusted to provide a resist-enhancing or resist-conserving process. In addition, higher selectivity processes are associated with slower etch rates and for a particular application, etch selectivity can be selected in conjunction with etch rate. For example, if high throughput is intended, the lowest selectivity consistent with the thickness (either facet thickness or nominal thickness) of the resistlayer 301 can be selected. -
FIGS. 4A-4C are cross-sectional views of asubstrate assembly 403 illustrating a resist-enhancing process. Referring toFIG. 4A , a resistlayer 407 covers asurface 401 of anoxide layer 409 of thesubstrate assembly 403 except in a representativeexposed region 405 that is defined in the resistlayer 407 using a lithographic or other process. Before etching begins, the initial thickness t0 of the resistlayer 407 is in the range of 25 nm to 2,000 nm, or preferably in the range of between about 25 nm to 1,500 nm, or still more preferably in the range of between about 50 nm and 1,000 nm. Thesubstrate assembly 403 is then exposed to the etch, and a trench 411 (or other feature) is etched into theoxide layer 409 to an initial depth d1. During etching, the resistlayer 407 thins to an etched resist thickness t1 that is slightly smaller than the initial resist thickness t0 as illustrated inFIG. 4B . Etching of thewafer 403 continues, and alayer 413 of material from the etching process is deposited on the resistlayer 407. Alternatively, the thickness of the resistlayer 407 increases by a thickness corresponding to the thickness of thelayer 413 by another mechanism. The additional thickness of thelayer 413 that is added to the thickness of the resistlayer 407 after the initial thinning of the resistlayer 407 continues to increase as thetrench 411 becomes deeper. As shown inFIG. 4C , the combined thickness of the resistlayer 407 and thelayer 413 is greater than the thickness t0 of the resistlayer 407 before etching. (The sum of the thickness of the resistlayer 407 and thelayer 413 is referred to as the combined thickness.) As shown in FIG. 4C, the aspect ratio of thetrench 411 is the ratio of the final depth D to the width W. For convenience, only a single resist thickness is shown inFIGS. 4A-4C , but the resist-enhancing process is configurable to enhance either the nominal thickness tN or the facet thickness tF, or both. - In a representative example, the initial nominal thickness tN and facet thickness tF of the resist
layer 407 is about 750 nm and the nominal (etched) resist thickness t1 is about 710 nm after etching for about 80 sec (i.e., the start-up loss is 40 nm). During this same 80 sec., the facet thickness tF decreases to about 600 nm and thetrench 411 is etched to an initial depth d1 of about 100 nm. Etching for an additional 80 sec. increases the nominal thickness tN of the resistlayer 407 and thelayer 413 to a final combined nominal thickness tF of about 800 nm and a final etch depth of about 1,842 nm. After this same 80 sec., the selectivity of etching of the nominal thickness tN is undefined because the nominal thickness increases. The selectivity of etching of the facet thickness tF is infinite because the facet thickness is unchanged. Etch conditions for performing this etch with theplasma etcher 200 ofFIG. 2 are listed in Table 1.TABLE 1 RF power to coils 233 725 W RF power to coils 235 125 W RF bias to substrate stage 211700 W Temperature of hot ring 209200 C. Temperature of RF window 205 and140 C. enclosure 207 Temperature of substrate stage −10 C. Etch gas CH2F2 Gas- flow rate 40 sccm He backside pressure 20 Torr Chamber pressure 20 mTorr - In specific examples, the etch depths available by simultaneously etching the
oxide layer 409 and thickening the resistlayer 407 have been achieved to depths corresponding to aspect ratios of about 10:1. For example, for a 0.25 μm wide feature, etching has been achieved to depths of about 2.5 μm. With deeper etching, some undercut or taper in the etched features has been observed. However, the use of a resist-enhancing or resist-conserving process following or preceded by a conventional (resist-consuming) process can result in features with higher aspect ratios and a controlled etch profile. In addition, using a resist-enhancing (or resist-conserving) process in conjunction with a conventional resist-consuming process permits the use of thinner resist layers, simplifying other substrate-processing steps. - As another example, consider etching a HAR feature of width of 250 nm to a depth of 2,5000 nm in an oxide layer (a 10:1 aspect ratio). Using the resist-conserving process, a resist layer of
thickness 200 nm (an arbitrary minimum thickness) plus an additional 12.5 nm of resist (to compensate for the slight initial etch of the resist process), or a total resist thickness of 212.5 nm is satisfactory. Lesser resist thicknesses are also satisfactory. In comparison, a conventional resist-consuming process typically etches oxide four times faster than resist, so that a resist thickness of 200 nm plus 2500/4 nm is required, or a total resist thickness of 825 nm. Thus, with the resist-enhancing or resist-conserving process of this example, the resist layer can be 612.5 nm thinner than in the conventional approach. Defining a pattern corresponding to a 250-nm feature width in an 825 nm resist thickness is impractical and may be unachievable because of small dose and focus latitude. Therefore, the etching/thickening (resist-enhancing) process permits etching of an extremely broad range of HAR features. - The resist-enhancing and resist-conserving processes of the above specific example may be used to, for example, etch a feature with a controlled profile only to a first depth. Little or no resist is consumed by this first etch and, in some cases, the resist thickness increases (i.e., the combined thickness of the resist layer and the newly deposited material is greater than the original resist thickness t0). Therefore, after the first etch by such a resist-enhancing or resist-conserving process, additional etching steps can be performed, such as using conventional etches that consume significant resist. The total etch depth available is the sum of the etch depth available with the conventional (resist-consuming) etch and the etch depth available with the resist-enhancing or resist-conserving process. The aspect ratio achievable is the sum of the aspect ratios available in each of these processes independently. For example, in a resist-conserving process having about 800 nm of combined thickness after etching by this process to a depth of 2.5 μm, a conventional etch having a selectivity of 5 can be used to etch up to, for example, 4.0 μm deeper, if process conditions permit all the resist to be removed. (Typically 50-100 nm of resist remain when etching is complete so that small process variations do not lead to unusable etched parts.) In this specific example, the result of the combined etching processes is a controlled profile feature with a depth of 6.5 μm and a width of 0.25 μm, or an aspect ratio of 25:1. If the etch rate of the conventional resist-consuming process decreases as the etched depth increases as is typical of many resist-consuming etches, then the achievable aspect ratio is smaller. In this example, the resist-enhancing and resist-conserving process is followed by a conventional resist-consuming process, but the resist-conserving process could be performed first, or the processes could be applied alternately.
- In the representative example discussed above, an oxide-coated substrate is etched in a plasma generated with CH2F2 gas. Other suitable gases include halogenated hydrocarbons, including iodinated, chlorinated, and fluorinated hydrocarbons, including CF4, CHF3, CH3F, C2F6, C2HF5, C3F8, C4F8, C4F6, and C5F8, and mixtures of these gases, as well as mixtures of these gases with the noble gases and hydrogen. Other substrate-assembly layers can be selected as well. For example, a polysilicon layer can be etched with a plasma formed by a chlorinated hydrocarbon gas.
- If a resist-enhancing or resist-conserving process is to be achieved by varying gas and gas-flow rate, the gas and gas-flow rate for etching a particular layer material are selected as follows. A substrate coated with a resist is exposed to a plasma obtained with a selected gas, and the deposition of material on the substrate or other thickening of the resist as a function of gas-flow rate is measured. If the selected gas does not thicken the resist at any flow rate, another gas is selected. (In some cases, the resist is initially thinned during the etching process and then begins to increase in thickness, and gas selection can include a determination of etch rate as a function of etching time to detect this initial thinning.) This is repeated until a gas is identified for which the plasma increases the resist thickness on the substrate. Then the etch rate as a function of gas-flow rate is measured, varying the gas-flow rate only in the range for which thickening is possible. Using these measurements, a preferred flow rate for the gas is selected. In addition, the gas-flow rates and RF excitation powers can be selected in view of etch uniformity and etch rate. Higher gas pressures generally provide higher etch rates. The selection of gas and gas-flow rate is typically specific to a particular type of plasma etcher and is repeated for different plasma etchers.
- Although the gas and the gas-flow rate are significant parameters for the resist-enhancing and resist-conserving processes, other parameters can be varied as well. In most plasma etchers, RF power levels, chamber pressure, and chamber temperature can be adjusted to improve these processes.
- While the invention is described with respect to particular implementations, the invention is not limited to these implementations.
Claims (12)
1.-46. (canceled)
47. A method of etching a high-aspect-ratio feature having a controlled profile, comprising:
selecting a surface of a substrate assembly to be etched;
selecting a depth D and width d of the high-aspect-ratio feature such that D/d>10;
forming a resist layer of thickness less than about D/5 on the selected surface of the substrate assembly; and
etching the high-aspect-ratio feature into the selected surface with a controlled profile.
48. The method of claim 47 , wherein the substrate assembly comprises a silicon wafer.
49. The method of claim 47 , wherein the substrate assembly comprises a silicon wafer having a layer of silicon oxide on the selected surface.
50. The method of claim 47 , wherein the thickness of the resist layer is selected to be less than about D/7.5.
51. The method of claim 47 , wherein the thickness of the resist layer is selected to be less than about D/10.
52. The method of claim 47 , wherein the thickness of the resist layer is selected to be less than about D/15.
53. A method of etching a high-aspect-ratio feature having a controlled profile, comprising:
forming a layer of insulating material above a semiconducting substrate;
selecting a surface of the layer of insulating material to be etched;
selecting a depth D and width d of the high-aspect-ratio feature such that D/d>10;
forming a resist layer of thickness less than about D/5 on the selected surface of the layer of insulating material; and
etching the high-aspect-ratio feature into the selected surface of the layer of insulating material with a controlled profile.
54. The method of claim 53 , wherein the semiconducting substrate comprises a silicon wafer.
55. The method of claim 53 , wherein the thickness of the resist layer is selected to be less than about D/7.5.
56. The method of claim 53 , wherein the thickness of the resist layer is selected to be less than about D/10.
57. The method of claim 53 , wherein the thickness of the resist layer is selected to be less than about D/15.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/469,010 US20070077724A1 (en) | 1999-06-29 | 2006-08-31 | Etching methods and apparatus and substrate assemblies produced therewith |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/342,677 US6635335B1 (en) | 1999-06-29 | 1999-06-29 | Etching methods and apparatus and substrate assemblies produced therewith |
US09/916,734 US6784111B2 (en) | 1999-06-29 | 2001-07-26 | Etching methods and apparatus and substrate assemblies produced therewith |
US10/895,502 US7125804B2 (en) | 1999-06-29 | 2004-07-20 | Etching methods and apparatus and substrate assemblies produced therewith |
US11/469,010 US20070077724A1 (en) | 1999-06-29 | 2006-08-31 | Etching methods and apparatus and substrate assemblies produced therewith |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/895,502 Continuation US7125804B2 (en) | 1999-06-29 | 2004-07-20 | Etching methods and apparatus and substrate assemblies produced therewith |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070077724A1 true US20070077724A1 (en) | 2007-04-05 |
Family
ID=23342809
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/342,677 Expired - Lifetime US6635335B1 (en) | 1999-06-29 | 1999-06-29 | Etching methods and apparatus and substrate assemblies produced therewith |
US09/916,734 Expired - Lifetime US6784111B2 (en) | 1999-06-29 | 2001-07-26 | Etching methods and apparatus and substrate assemblies produced therewith |
US10/895,502 Expired - Lifetime US7125804B2 (en) | 1999-06-29 | 2004-07-20 | Etching methods and apparatus and substrate assemblies produced therewith |
US11/469,010 Abandoned US20070077724A1 (en) | 1999-06-29 | 2006-08-31 | Etching methods and apparatus and substrate assemblies produced therewith |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/342,677 Expired - Lifetime US6635335B1 (en) | 1999-06-29 | 1999-06-29 | Etching methods and apparatus and substrate assemblies produced therewith |
US09/916,734 Expired - Lifetime US6784111B2 (en) | 1999-06-29 | 2001-07-26 | Etching methods and apparatus and substrate assemblies produced therewith |
US10/895,502 Expired - Lifetime US7125804B2 (en) | 1999-06-29 | 2004-07-20 | Etching methods and apparatus and substrate assemblies produced therewith |
Country Status (1)
Country | Link |
---|---|
US (4) | US6635335B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104347409A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure formation method |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6492279B1 (en) | 2000-01-27 | 2002-12-10 | Micron Technology, Inc. | Plasma etching methods |
WO2002021586A1 (en) * | 2000-09-07 | 2002-03-14 | Daikin Industries, Ltd. | Dry etching gas and method for dry etching |
US6989108B2 (en) * | 2001-08-30 | 2006-01-24 | Micron Technology, Inc. | Etchant gas composition |
TW200301238A (en) * | 2001-11-08 | 2003-07-01 | Zeon Corp | Gas for plasma reaction, process for producing the same, and use |
US6518164B1 (en) * | 2001-11-30 | 2003-02-11 | United Microelectronics Corp. | Etching process for forming the trench with high aspect ratio |
US20030221616A1 (en) * | 2002-05-28 | 2003-12-04 | Micron Technology, Inc. | Magnetically-actuatable throttle valve |
DE10246063A1 (en) * | 2002-10-02 | 2004-04-22 | Robert Bosch Gmbh | Anisotropic etching of structures defined by etching mask in silicon substrate involves periodic deposition of fluoropolymer from exotic fluorocarbon by plasma polymerization, alternating with plasma etching |
DE10247913A1 (en) * | 2002-10-14 | 2004-04-22 | Robert Bosch Gmbh | Process for the anisotropic etching of structures in a substrate arranged in an etching chamber used in semiconductor manufacture comprises using an etching gas and a passivating gas which is fed to the chamber in defined periods |
US7229930B2 (en) * | 2003-01-13 | 2007-06-12 | Applied Materials, Inc. | Selective etching of low-k dielectrics |
US20050054206A1 (en) * | 2003-09-04 | 2005-03-10 | Nanya Technology Corporation | Etching method and recipe for forming high aspect ratio contact hole |
US20060011578A1 (en) * | 2004-07-16 | 2006-01-19 | Lam Research Corporation | Low-k dielectric etch |
US8153502B2 (en) * | 2006-05-16 | 2012-04-10 | Micron Technology, Inc. | Methods for filling trenches in a semiconductor material |
US20080050871A1 (en) * | 2006-08-25 | 2008-02-28 | Stocks Richard L | Methods for removing material from one layer of a semiconductor device structure while protecting another material layer and corresponding semiconductor device structures |
DE602007013281D1 (en) * | 2006-12-12 | 2011-04-28 | Nxp Bv | METHOD FOR PRODUCING OPENINGS IN A SUBSTRATE, IN PARTICULAR THROUGH A SUBSTRATE |
JP5214152B2 (en) * | 2007-02-08 | 2013-06-19 | 東京エレクトロン株式会社 | Plasma etching method, plasma etching apparatus, control program, and computer storage medium |
US7863180B2 (en) * | 2008-05-06 | 2011-01-04 | International Business Machines Corporation | Through substrate via including variable sidewall profile |
WO2010042209A1 (en) * | 2008-10-09 | 2010-04-15 | Bandgap Engineering, Inc. | Process for structuring silicon |
US10615050B2 (en) * | 2017-04-24 | 2020-04-07 | Applied Materials, Inc. | Methods for gapfill in high aspect ratio structures |
JP6913569B2 (en) * | 2017-08-25 | 2021-08-04 | 東京エレクトロン株式会社 | How to process the object to be processed |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4255230A (en) * | 1980-02-22 | 1981-03-10 | Eaton Corporation | Plasma etching process |
US4473435A (en) * | 1983-03-23 | 1984-09-25 | Drytek | Plasma etchant mixture |
US4612085A (en) * | 1985-04-10 | 1986-09-16 | Texas Instruments Incorporated | Photochemical patterning |
US4717448A (en) * | 1986-10-09 | 1988-01-05 | International Business Machines Corporation | Reactive ion etch chemistry for providing deep vertical trenches in semiconductor substrates |
US4992136A (en) * | 1987-07-29 | 1991-02-12 | Hitachi, Ltd. | Dry etching method |
US5025427A (en) * | 1989-04-28 | 1991-06-18 | Casio Computer Co., Ltd. | Electronic display device for displaying calendar information |
US5310454A (en) * | 1992-03-04 | 1994-05-10 | Kabushiki Kaisha Toshiba | Dry etching method |
US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
US5843820A (en) * | 1997-09-29 | 1998-12-01 | Vanguard International Semiconductor Corporation | Method of fabricating a new dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor |
US5874362A (en) * | 1986-12-19 | 1999-02-23 | Applied Materials, Inc. | Bromine and iodine etch process for silicon and silicides |
US6074957A (en) * | 1998-02-26 | 2000-06-13 | Micron Technology, Inc. | Methods of forming openings and methods of controlling the degree of taper of openings |
US6074954A (en) * | 1998-08-31 | 2000-06-13 | Applied Materials, Inc | Process for control of the shape of the etch front in the etching of polysilicon |
US6093655A (en) * | 1998-02-12 | 2000-07-25 | Micron Technology, Inc. | Plasma etching methods |
US6117786A (en) * | 1998-05-05 | 2000-09-12 | Lam Research Corporation | Method for etching silicon dioxide using fluorocarbon gas chemistry |
US6123862A (en) * | 1998-04-24 | 2000-09-26 | Micron Technology, Inc. | Method of forming high aspect ratio apertures |
US6136722A (en) * | 1997-10-15 | 2000-10-24 | Nec Corporation | Plasma etching method for forming hole in masked silicon dioxide |
US6362109B1 (en) * | 2000-06-02 | 2002-03-26 | Applied Materials, Inc. | Oxide/nitride etching having high selectivity to photoresist |
US6451705B1 (en) * | 2000-08-31 | 2002-09-17 | Micron Technology, Inc. | Self-aligned PECVD etch mask |
US20040098338A1 (en) * | 2000-04-26 | 2004-05-20 | Computer Applications Co., Ltd. | Method for managing buyer transactions and settlements using communication network between computers, and method for relaying information following buyer consumption trends to the buyer |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2746167B2 (en) * | 1995-01-25 | 1998-04-28 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1999
- 1999-06-29 US US09/342,677 patent/US6635335B1/en not_active Expired - Lifetime
-
2001
- 2001-07-26 US US09/916,734 patent/US6784111B2/en not_active Expired - Lifetime
-
2004
- 2004-07-20 US US10/895,502 patent/US7125804B2/en not_active Expired - Lifetime
-
2006
- 2006-08-31 US US11/469,010 patent/US20070077724A1/en not_active Abandoned
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4255230A (en) * | 1980-02-22 | 1981-03-10 | Eaton Corporation | Plasma etching process |
US4473435A (en) * | 1983-03-23 | 1984-09-25 | Drytek | Plasma etchant mixture |
US4612085A (en) * | 1985-04-10 | 1986-09-16 | Texas Instruments Incorporated | Photochemical patterning |
US4717448A (en) * | 1986-10-09 | 1988-01-05 | International Business Machines Corporation | Reactive ion etch chemistry for providing deep vertical trenches in semiconductor substrates |
US5874362A (en) * | 1986-12-19 | 1999-02-23 | Applied Materials, Inc. | Bromine and iodine etch process for silicon and silicides |
US4992136A (en) * | 1987-07-29 | 1991-02-12 | Hitachi, Ltd. | Dry etching method |
US5025427A (en) * | 1989-04-28 | 1991-06-18 | Casio Computer Co., Ltd. | Electronic display device for displaying calendar information |
US5310454A (en) * | 1992-03-04 | 1994-05-10 | Kabushiki Kaisha Toshiba | Dry etching method |
US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
US5843820A (en) * | 1997-09-29 | 1998-12-01 | Vanguard International Semiconductor Corporation | Method of fabricating a new dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor |
US6136722A (en) * | 1997-10-15 | 2000-10-24 | Nec Corporation | Plasma etching method for forming hole in masked silicon dioxide |
US6093655A (en) * | 1998-02-12 | 2000-07-25 | Micron Technology, Inc. | Plasma etching methods |
US6074957A (en) * | 1998-02-26 | 2000-06-13 | Micron Technology, Inc. | Methods of forming openings and methods of controlling the degree of taper of openings |
US6123862A (en) * | 1998-04-24 | 2000-09-26 | Micron Technology, Inc. | Method of forming high aspect ratio apertures |
US6342165B1 (en) * | 1998-04-24 | 2002-01-29 | Micron Technology, Inc. | Method of forming high aspect ratio apertures |
US6117786A (en) * | 1998-05-05 | 2000-09-12 | Lam Research Corporation | Method for etching silicon dioxide using fluorocarbon gas chemistry |
US6074954A (en) * | 1998-08-31 | 2000-06-13 | Applied Materials, Inc | Process for control of the shape of the etch front in the etching of polysilicon |
US20040098338A1 (en) * | 2000-04-26 | 2004-05-20 | Computer Applications Co., Ltd. | Method for managing buyer transactions and settlements using communication network between computers, and method for relaying information following buyer consumption trends to the buyer |
US6362109B1 (en) * | 2000-06-02 | 2002-03-26 | Applied Materials, Inc. | Oxide/nitride etching having high selectivity to photoresist |
US6451705B1 (en) * | 2000-08-31 | 2002-09-17 | Micron Technology, Inc. | Self-aligned PECVD etch mask |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104347409A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure formation method |
Also Published As
Publication number | Publication date |
---|---|
US6635335B1 (en) | 2003-10-21 |
US7125804B2 (en) | 2006-10-24 |
US6784111B2 (en) | 2004-08-31 |
US20040262263A1 (en) | 2004-12-30 |
US20020000422A1 (en) | 2002-01-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20070077724A1 (en) | Etching methods and apparatus and substrate assemblies produced therewith | |
US6670278B2 (en) | Method of plasma etching of silicon carbide | |
JP5265100B2 (en) | How to open a carbon-based hard mask | |
US6322714B1 (en) | Process for etching silicon-containing material on substrates | |
US7470625B2 (en) | Method of plasma etching a substrate | |
KR100849707B1 (en) | Selective etching of carbon-doped low-k dielectrics | |
US6284149B1 (en) | High-density plasma etching of carbon-based low-k materials in a integrated circuit | |
US6361705B1 (en) | Plasma process for selectively etching oxide using fluoropropane or fluoropropylene | |
US7273566B2 (en) | Gas compositions | |
JPS6252455B2 (en) | ||
JP2001521283A (en) | Self-aligned contact etching using difluoromethane and trifluoromethane | |
JP2003511857A (en) | Method for uniform shallow trench etch profile | |
US6653237B2 (en) | High resist-selectivity etch for silicon trench etch applications | |
JPH06181190A (en) | Fabrication of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |