|Numéro de publication||US20070108529 A1|
|Type de publication||Demande|
|Numéro de demande||US 11/272,661|
|Date de publication||17 mai 2007|
|Date de dépôt||14 nov. 2005|
|Date de priorité||14 nov. 2005|
|Autre référence de publication||US8835291, US20090203202|
|Numéro de publication||11272661, 272661, US 2007/0108529 A1, US 2007/108529 A1, US 20070108529 A1, US 20070108529A1, US 2007108529 A1, US 2007108529A1, US-A1-20070108529, US-A1-2007108529, US2007/0108529A1, US2007/108529A1, US20070108529 A1, US20070108529A1, US2007108529 A1, US2007108529A1|
|Inventeurs||Chien-Chao Huang, Fu-Liang Yang|
|Cessionnaire d'origine||Taiwan Semiconductor Manufacturing Company, Ltd.|
|Exporter la citation||BiBTeX, EndNote, RefMan|
|Référencé par (17), Classifications (8), Événements juridiques (1)|
|Liens externes: USPTO, Cession USPTO, Espacenet|
This invention relates generally to semiconductor devices, and more specifically to metal oxide semiconductor (MOS) devices having strained channel regions.
Miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) has improved speed performance and reduced cost per unit function of integrated circuits. One way to improve transistor performance is through selective application of stress to the transistor channel region. Stress distorts or strains the semiconductor crystal lattice and interatomic bonding. The strain, in turn, affects the band alignment and charge transport properties of the semiconductor. By controlling the magnitude and distribution of stress in a finished device, manufacturers can increase carrier mobility and improve device performance. There are several existing approaches of introducing stress in the transistor channel region.
One approach includes forming an epitaxial, strained silicon layer on a relaxed silicon germanium (SiGe) layer. Because SiGe has a larger lattice constant than Si, the epitaxial Si grown on SiGe will have its lattice stretched in the lateral direction, so the Si will be under biaxial tensile stress. In this approach, the relaxed SiGe buffer layer is referred to as a stressor that introduces stress in the channel region. The stressor, in this case, is placed below the transistor channel region. In another approach, a high-stress film is formed over a completed transistor. The high-stress film distorts the silicon lattice thereby straining the channel region.
One problem facing CMOS manufacturing is that NMOS and PMOS devices require different types of stress in order to achieve increased carrier mobility. For example, a biaxial, tensile stress increases NMOS performance approximately twofold. However, for a PMOS device, such a stress yields almost no improvement. With a PMOS device, a tensile stress improves performance when its perpendicular to the channel, but it has nearly the opposite effect when it is parallel to the channel. Therefore, when a biaxial, tensile film is applied to a PMOS device, the two stress effects almost cancel each other out.
Workers are aware of these problems. Therefore, new CMOS manufacturing techniques selectively address PMOS and NMOS devices. An NMOS fabrication method includes using tensile films to improve carrier mobility. A PMOS fabrication method includes using substrate structures that apply a compression stress to the channel. One PMOS method includes selective application of a SiGe layer into the source/drain regions. Another method uses modified shallow trench isolation (STI) structures that compress the PMOS channel.
The use of additional materials, however, adds further processing steps and complexity to the manufacturing process. Therefore, there remains a need for improving the carrier mobility of both NMOS and PMOS devices without significantly adding to the cost or complexity of the manufacturing process.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved by preferred embodiments of the present invention that provide methods and structures for introducing stress and strain into semiconductor devices in order to improve charge carrier mobility.
Embodiments of the invention provide a semiconductor device and a method of manufacture. A preferred embodiment of the invention includes forming a tensile strained channel region in an NMOS device and a compressive strained channel region in a PMOS device.
One embodiment comprises forming an intermediate structure, wherein the intermediate structure comprises a first active region, a second active region, a first gate electrode layer over the first active region, and a second gate electrode layer over the second active region. Embodiments may further comprise converting the first gate electrode layer to an amorphous portion and a polycrystalline portion, and forming a capping layer over the intermediate structure. The first and second gate electrode layers are recrystallized so that an average crystal grain size of the first recrystallized layer is less than an average crystal grain size of the second recrystallized layer. The cap layer may be removed after the recrystallizing. The first and second gate electrode layers are patterned to form a first gate electrode over the first active region and a second gate electrode over the second active region, wherein the first and second gate electrodes have different intrinsic stresses.
Another embodiment of the invention provides a semiconductor structure. The structure comprises a first gate electrode over a first active region and a second gate electrode over a second active region. Preferably, the first gate electrode comprises one of an amorphous gate electrode and a polycrystalline gate electrode. In another embodiment, the first gate electrode is an amorphous gate electrode, and the second gate electrode is a polycrystalline gate electrode. In an embodiment, the first active region includes a tensile strained region under the first gate electrode. The second active region may include a compressive strained region under the second gate electrode.
Another embodiment of the invention provides a semiconductor device. The device comprises a first gate electrode over a first active region and a second gate electrode over a second active region. The first gate electrode comprises a first plurality of crystal grains having a first average grain size, and the second gate electrode comprises a second plurality of crystal grains having a second average grain size. Preferably, the first average grain size is less than the second average grain size.
In still another embodiment, the semiconductor device may comprise an NMOS device and a PMOS device, each device comprising a source/drain region in a substrate, a channel region in the substrate between the source/drain region, and a polycrystalline gate electrode over the channel region. Preferably, an average crystal grain size of the NMOS polycrystalline gate electrode is less than an average crystal grain size of the PMOS polycrystalline gate electrode. The NMOS polycrystalline gate electrode may be a material having an intrinsic compressive stress that causes a tensile strain in the NMOS channel region. The PMOS polycrystalline gate electrode may comprise a material having an intrinsic tensile stress that causes a compressive strain in the PMOS channel region.
In embodiments of the invention, the second recrystallized layer comprises a plurality of crystal grains having a columnar growth orientation, and the first recrystallized layer comprises a plurality of crystal grains having an equiaxed growth orientation. The first recrystallized layer may comprise a first portion on a second portion, wherein an average crystal grain size of the first portion is less than an average crystal grain size of the second portion.
Embodiments may further include adding a stressor to the gate electrode stack. The embodiments include forming a first stressor having an intrinsic compressive stress under the first gate electrode, and forming a second stressor having an intrinsic tensile stress under the second gate electrode.
Note that although the term layer is used throughout the specification and in the claims, the resulting features formed using the layer should not be interpreted as only a continuous or uninterrupted feature. As will be clear from reading the specification, the layer may be separated into distinct and isolated features (e.g., active regions or device fabrication regions), some or all of which comprise portions of the semiconductor layer.
Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the specific embodiments disclosed might be readily utilized as a basis for modifying or designing other structures or processes for carrying out the purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions and variations on the example embodiments described do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. The intermediated stages of manufacturing a preferred embodiment of the present invention are illustrated throughout the various views and illustrative embodiments of the present invention.
This invention relates generally to semiconductor device fabrication and more particularly to structures and methods for strained transistors. The present invention will now be described with respect to preferred embodiments in a specific context, namely the creation of PMOS and NMOS transistors. It is believed that embodiments described herein will benefit other applications not specifically mentioned. Therefore, the specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
An isolation structure, such as a shallow trench isolation (STI) region 121, may be formed within the substrate 101 to isolate active regions. STI regions 121 are formed using conventional thermal growth methods and isolation region deposition and patterning methods. In
Formed over the active regions 103 is a gate dielectric layer 130. The gate dielectric 130 may include a thermally grown silicon oxide having a thickness from about 6 to 100 Å, and more preferably less than about 20 Å. In other embodiments, the gate dielectric 130 may include a high-k dielectric having a k-value substantially greater than about 7. Possible high-k dielectrics include Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, L2O3, and their aluminates and silicates. Other suitable high-k gate dielectrics may include hafnium-based materials such as HfO2, HfSiOx, HfAlOx.
A layer of gate electrode material 133 is formed over the gate dielectric 130 layer. The gate electrode material 133 may comprise metals, metal alloys, metal-containing materials, polysilicon (polycrystalline silicon), and polycide (doped polysilicon/metal silicide stack) gate electrode materials. Preferably, the gate electrode material 133 comprises chemical vapor deposition (CVD) polysilicon between about 100 and 10,000 angstroms thick and more preferably between about 500 and 2,000 angstroms. The gate electrode material 133 may further include about 1E20 cm-3 dopant of polarity opposite the channel region of the corresponding MOS device to be formed therefrom. Such doping advantageously provides for enhanced off current (Ioff) performance, enhanced drain saturation current (Idsat) performance and possibly enhanced short channel effect (SCE) performance of a field effect transistor (FET) device formed employing a gate electrode formed from the patterned first gate electrode material layer 133.
Turning now to
An amorphization implant, which is symbolized by arrows 230, is performed next. The amorphization implant 230 may be a conventional beam-line ion implantation process, a plasma immersion ion implantation (PIII), or another ion implantation process known and used in the art. The implant 230 depth in the gate electrode material 133 is preferably from about 100 to 5000 angstroms and more preferably from about 500 to 1000 angstroms at a concentration of preferably from about 1E19 to 1E22 atoms/cm2 and more preferably from about 1E20 to 1E21 atoms/cm2 using In, B, Sb, C, BF2, or O atoms. Other preferred implant species may include As, P, N, Ge, Ar, Kr, or combinations thereof.
As shown in
In an alternative embodiment of the invention shown in
Turning now to
As used herein, recrystallizing refers to the process that converts a polycrystalline material having a first grain size to a polycrystalline material having a second grain size. Recrystallizing may also refer to the conversion of an amorphous material to a polycrystalline material.
Next, without removing the capping layer 235, an annealing process 245 recrystallizes the gate electrode material as shown in
As shown in
In preferred embodiments of the invention, the capping layer 235 stabilizes the solid phase structure of the pre-anneal gate electrode material. That is, if the pre-anneal gate electrode is amorphous, the capping layer 235 stabilizes the amorphous phase. If the pre-anneal material is polycrystalline, the capping layer 235 stabilizes the polycrystalline phase. Therefore, during recrystallization, grain growth within the recrystallized gate electrode material, 133 c, 133 d and 133 e, preferably proceeds from the gate oxide layer 130 towards the capping layer 235. Preferably, the third recrystallized region 133 e lies over the second active region 103 b of the substrate, and it also lies substantially adjacent the first and second recrystallized regions, 133 c and 133 d.
In embodiments of the invention, a thickness, d1, of the first recrystallized region 133 c is preferably less than a thickness, d2, of the second recrystallized region 133 d. More preferably, d1 is between about 0.5*d2 and 0.2*d2. In other embodiments of the invention, d1 is between about 200 and 450 A. In still other embodiments of the invention, the first and second recrystallized regions, 133 c and 133 d, comprise nano-grain polysilicon. The nano-grain polysilicon may have a crystal grain size of about 10 nm or less in an embodiment of the invention.
In other embodiments of the invention, d1 is approximately 0 nm. Such an embodiment corresponds to the situation where the amorphous region is initially very thin and/or grain growth from the underlying polycrystalline region dominates the recrystallization. In yet still other embodiments, d2 is approximately 0 nm. Such an arrangement may correspond to the further processing of the embodiment illustrated in
Further details of the grain structure within the first, second, and third recrystallized regions 133 c, 133 d, 133 e are illustrated in
In the embodiment illustrated in
In the embodiment illustrated in
Yet another alternative preferred embodiment of the invention, the grain structure of the recrystallized gate electrode material is schematically illustrated in
In an embodiment, the grain structure of the fourth region 133 f comprises an amorphous material. This electrode material may be formed by processing the intermediate structure illustrated in
As described above, other embodiments of the invention (not illustrated) may further include a glue layer (see e.g., 135
Turning now to
The average grain size of the first gate electrode 269 is preferably smaller than the average grain size of the second gate electrode 270. Preferably, the difference in the average grain size is greater than about 2 nm, and more preferably greater than about 10 nm. The grain distribution within the first and second gate electrodes, 269 and 270, may be widely distributed or mono-dispersed, randomly oriented, columnar or equiaxed, or combinations thereof.
In further keeping with embodiments of the invention, the respective grain size of each gate electrode induces a corresponding strain effect within an underlying substrate portion. Continuing with
By allowing for the selective control of the gate electrode crystal grains, embodiments of the invention provide methods and structures that are optimized for the fabrication of NMOS and PMOS transistors. In the embodiment illustrated in
Turning now to
As shown in
In order to further control the stress/strain distribution, embodiments may further include using implant dopants, which may induce or inhibit nucleation, grain growth, and recrystallization. Typically, a gate electrode having an intrinsic compressive/tensile stress induces the opposite stress (i.e. tensile/compressive) within the substrate underlying the gate electrode. For example, a gate electrode having an intrinsic tensile stress of about 4.50E9 dyne/cm2 may induce a compressive stress in the channel region of approximately the same magnitude. In other embodiments, a gate electrode having an intrinsic tensile/compressive stress of about 2500 MPa may induce a corresponding channel strain in the range of about compressive/tensile 1.5%.
Turning now to
Using the gate electrodes, 269 and 270, as a mask, lightly doped source/drain (LDS/LDD) regions are formed in the substrate 101 to a depth between about 100 and 1000 angstroms and preferably between about 200 and 400 angstroms. An N-LDS/LDD region 307 is formed by ion implanting phosphorus or arsenic dopant ions from about 1*1013 ions/cm2 to about 5*1014 ions/cm2 at an energy from about 30 keV to about 80 keV. After annealing the concentration of phosphorus or arsenic dopant in the LDS/LDD regions 307 is from about 5*1016 atoms/cm3 to about 1*1019 atoms/cm3.
Between the N-LDS/LDD regions 307 there is an NMOS channel region 330. Preferably, the NMOS channel region 330 lies within the first strain region 271. More preferably, the first strain region 271 comprises a tensile stress that is aligned substantially between the N-LDS/LDD regions 307.
A P-LDS/LDD region 308 is formed by ion implanting boron or boron difluoride, BF2, with a dose from about 1*1013 ions/cm2 to about 5*1014 ions/cm2 at an energy from about 15 keV to about 50 keV. After annealing the concentration of boron dopant in the P-LDS/LDD region 308 is about 5*1016 atoms/cm3 to about 1*1019 atoms/cm3. Preferably, the PMOS channel region 331 lies within the second strain region 273.
Formed on sidewalls of the gate electrodes 269 and 270 are sidewall spacers 315. The sidewall spacers 315 are a dielectric, such as CVD silicon oxide. Using the gate electrodes 269 and 270 and also sidewall spacers 315 as a mask, heavily doped source/drain regions are formed.
Heavily doped P+ doped source/drain regions 319 in N-well 105 are self-aligned with gate electrode 270 and sidewall spacers 315. The P+ source/drain regions 319 extend below the P− lightly doped LDS/LDD regions 308. The P+ regions source/drain regions may be implanted with a dose of boron dopant in a range from about 1*1014 ions/cm 2 to about 1*1016 ions/cm2 at an energy from about 10 keV to about 80 keV. After annealing, the concentration of boron dopant in the regions 319 is preferably between about 5*1018 atoms/cm3 and 5*1020 atoms/cm3.
Heavily doped N+ doped source/drain regions 317 are formed in the first active area 103 a and self-aligned with gate electrode 269 and also with sidewall spacers 315. The heavily doped N+ source/drain regions 317 preferably extend below the P− lightly doped LDS/LDD regions 307 as shown in
One skilled in the art will recognize that embodiments of the invention may be integrated with other methods and structures suitable for strained channel transistors. For example, shallow trench isolation (STI) structures may induce stress in n-channel and p-channel transistors separately. A first isolation trench may include a first liner, and a second isolation trench may include a second liner. The liners may comprise a suitable stress layer material, and it may be used to modulate channel stress. For example, in modulating the channel stress may include implanting the liner with ions removed. A liner may be modified in some but not all of a plurality of trenches.
For example, yet another embodiment of the invention may comprise incorporating a stressor 410 as shown in
Another strained semiconductor method that may be integrated with embodiments includes forming a stressor such as a stress layer formed over NMOS and PMOS devices to induce a strain in the channel region. For example, a highly tensile stress/strain film is known to induce a tensile channel stress/strain. Likewise, a highly compressive stress/strain film is known to induce a compressive channel stress/strain. Embodiments of the invention may further include depositing a uniform stress film over a device, such as a CMOS device and thereafter modulating or adjusting an appropriate stress property of the film in order to achieve a desired channel stress.
One modulating treatment may comprise local stress relaxation by ion bombardment or implantation using, for example, germanium, silicon, xenon, argon, oxygen, nitrogen, carbon, or germanium, and combinations thereof. Other treatments may include changing the composition (e.g., oxidation and/or nitridation) of the stress layer using, for example, a process such as thermal, plasma, ozone, UV, a steam oxidation, a steam environment, and/or combinations thereof. Other treatment methods may include film densification using, for example, a zone treatment, e-beam curing, UV curing, laser treatment (either with or without an absorption or reflection capping layer).
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
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|Classification aux États-Unis||257/368, 257/E21.637, 257/E21.633|
|Classification coopérative||H01L21/823842, H01L21/823807|
|Classification européenne||H01L21/8238C, H01L21/8238G4|
|14 nov. 2005||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,T
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, CHIEN-CHAO;YANG, FU-LIANG;REEL/FRAME:017237/0427
Effective date: 20051114