US20070138628A1 - Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package - Google Patents

Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package Download PDF

Info

Publication number
US20070138628A1
US20070138628A1 US11/304,084 US30408405A US2007138628A1 US 20070138628 A1 US20070138628 A1 US 20070138628A1 US 30408405 A US30408405 A US 30408405A US 2007138628 A1 US2007138628 A1 US 2007138628A1
Authority
US
United States
Prior art keywords
substrate
electronic component
attached
electronic
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/304,084
Inventor
Ken Lam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to US11/304,084 priority Critical patent/US20070138628A1/en
Assigned to ATMEL CORPORATION reassignment ATMEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAM, KEN M.
Priority to US11/456,685 priority patent/US8258599B2/en
Publication of US20070138628A1 publication Critical patent/US20070138628A1/en
Priority to US12/534,819 priority patent/US8860195B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention generally concerns fabrication of semiconductor devices, particularly semiconductor devices incorporated in integrated circuit packages.
  • Miniaturization of integrated circuit (IC) packages which may be incorporated in portable consumer products such as cellular phones, and mobile or laptop computers, has become increasingly important.
  • One approach to miniaturization is the use of multi-chip modules where multiple chips having related functions are incorporated in a single package.
  • Single packages may also include stacked chips, in which chips are vertically stacked on top of each other.
  • a potential drawback to using stacked die techniques is that no interconnection exists on the surfaces of the stacked die; the die interconnect is limited to die-to-die and die-to-substrate interconnections. Therefore, the IC die count is typically limited to one die per attach surface. It is not feasible to attach discrete electronic components to these surfaces since they typically require solderable attachment lands and interconnect circuitry or a noble metal surface for low contact resistance connections.
  • a method of fabrication comprises providing a substrate with a first surface having a passivation layer. At least one structure is built on a second surface of the substrate; an electronic component is to be attached to at least one structure.
  • the structures that may be built include a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached.
  • the electronic package comprises a substrate which is coupled to a first surface of an integrated circuit die.
  • the first surface of the integrated circuit die has means for coupling to the first surface of the substrate and has at least one first electronic component attached to the first surface of the integrated circuit die.
  • At least one structure is attached to a second surface of the integrated circuit die.
  • Yet another embodiment is an electronic package comprising a substrate which is coupled to a flip chip. At least one first electronic component and means for coupling the flip chip to the substrate is attached to a first surface of the flip chip. At least one structure is attached to a second surface of the flip chip.
  • a semiconductor device comprises a substrate having a first surface and a second surface, a passivation layer on the first surface of the substrate, and at least one structure attached to the second surface of the substrate.
  • the structure is configured to be coupled to an electronic component.
  • a method of integrated circuit device packaging comprises providing a substrate, coupling a first surface of an integrated circuit die to the substrate, and attaching at least one electronic component to at least one structure on a second surface of the integrated circuit die.
  • the first surface of the integrated circuit die is coupled to at least one electronic component.
  • FIGS. 1 a - 1 b are flowcharts of a fabrication process in an exemplary embodiment of the invention.
  • FIGS. 2 a - 2 j are diagrams showing stages of fabrication in an exemplary embodiment of the invention.
  • FIG. 3 is a view of a chip fabricated in accordance with steps shown in FIGS. 2 a - 2 j attached to a substrate.
  • FIG. 4 is an overhead plan of a multi-chip module incorporating chips fabricated in accordance with steps shown in FIGS. 2 a - 2 j.
  • FIG. 5 is a side view of a multi-chip module incorporating chips fabricated in accordance with steps shown in FIGS. 2 a - 2 j.
  • FIG. 1 a an exemplary process for fabricating a semiconductor device with circuitry on both surfaces of the device (such that one surface connects the device to an electronic package's substrate (such as a printed circuit board (“PCB”) and another surface may be used to attach discrete electronic components) is shown.
  • a wafer is provided with fabricated circuitry on a first surface of the wafer (block 100 ).
  • the wafer may be made of any suitable semiconductor material, such as silicon or gallium arsenide, used in the art. It should also be appreciated that any substrate (such as silicon on an insulator), or semiconductor substrate, including the wafer, may be used in various embodiments.
  • the device substrate should not be confused with the same substrate often used to generally label PCBs.
  • the fabricated devices on the first surface are produced through conventional semiconductor manufacturing methods.
  • the wafer 14 has a first surface 80 and a second surface 82 , with a passivation layer 12 and a layer of protective material 10 on a first surface of the wafer 80 , which also contains the fabricated devices (not shown here).
  • the layer of protective material 10 is typically 1 to 10 microns thick and provides mechanical protection to the passivation layer 12 , which in turn protects the active device circuitry.
  • the layer of protective material is formed using methods well-known to those of skill in the art.
  • the second surface of the wafer is then metallized ( FIG. 1 a , block 104 ).
  • the wafer 14 is turned “upside down” and a metal layer 16 is formed over the second surface 82 of the wafer 14 .
  • the second surface 82 of the wafer 14 is blanket metallized by standard metal deposition processes, such as evaporation or chemical vapor deposition (“CVD”), sputtering, and plating.
  • the resulting metal layer 16 is typically about 0.1 micron to 10 microns thick.
  • the metal layer 16 provides RF shielding and wirebonding functions.
  • the metal layer 16 may be a single layer, for example, aluminum (Al), or may be formed of multiple layers, using metals such as titanium tungsten-god (TiW—Au), titanium-gold (Ti—Au), chromium-gold (Cr—Au), titanium tungsten-nickel-gold (Ti—Ni—Au), titanium-nickel-gold (Ti—Ni—Au), titanium-copper-nickel-gold (Ti—Cu—Ni—Au), titanium-tungsten-copper-nickel-silver (TiW—Cu—Ni—Ag), etc.
  • Metal layer 16 choices may be selected based on the mechanism used to attach components to the semiconductor device fabricated on the wafer.
  • the use of gold, silver, and/or palladium is suitable for wire-bonding and the use of nickel and copper is suitable for soldering and electrical conductivity.
  • Nickel is a good diffusion barrier. Titanium, titanium tungsten, and chromium provide adhesion of the metal film stack to the wafer.
  • An insulating layer is formed over the metal layer ( FIG. 1 a , block 106 ).
  • an insulating film 18 such as polyimide, benzocyclobutene (BCB), etc., is formed over the metal layer 16 .
  • the insulating film 18 is typically about 2 to 15 microns thick.
  • the insulating film 18 is formed using methods well-known to those of skill in the art. This insulating film 18 may be either photo-definable or standard non-photo-sensitive film.
  • a photosensitive material such as photoresist
  • a layer of photosensitive film typically 1 to 10 microns
  • photoresist 20 is deposited over the insulating film 18 .
  • This layer 20 of photoresist is patterned and developed using methods well-known to those of skill in the art.
  • a mask is placed over the photosensitive material, such as photoresist, and then exposed and etched away ( FIG. 1 a , block 110 ).
  • the insulating film layer that is now exposed is removed using wet etch or dry etch techniques.
  • the remaining photosensitive material is also removed using methods well-known to those of skill in the art ( FIG. 1 a , block 110 ).
  • the second surface 82 of the wafer 14 has a patterned insulating film layer 18 remaining on the metal layer 16 after the removal of the layer of photoresist.
  • the method just described uses a negative acting photoresist.
  • a positive acting photoresist can also be used to achieve the same goal.
  • the remaining insulating film and exposed metal layer is covered with a second metal layer ( FIG. 1 a , block 112 ).
  • the surface is blanket metallized; in other embodiments, other metal deposition processes, such as sputtering and plating, may also be employed.
  • the second metal layer 22 covers the insulating film 18 and the exposed metal layer 16 .
  • the second metal layer is typically about 0.1 to 10 microns thick.
  • the second metal layer 22 may be a single layer, for example, aluminum (Al), or may be formed of multiple layers, using metals such as titanium tungsten-god (TiW—Au), titanium-gold (Ti—Au), chromium-gold (Cr—Au), titanium tungsten-nickel-gold (Ti—Ni—Au), titanium-nickel-gold (Ti—Ni—Au), titanium-copper-nickel-gold (Ti—Cu—Ni—Au), titanium-tungsten-copper-nickel-silver (TiW—Cu—Ni—Ag), etc.
  • the metal layer 22 may be formed of metal which are wirebondable or solderable (such as copper, silver, etc.) or have a diffusion barrier (e.g., nickel).
  • a layer of photosensitive material such as photoresist, is deposited over the second metal layer ( FIG. 1 b , block 116 ).
  • a photosensitive film layer 24 has been deposited on the second metal layer 22 .
  • the photosensitive film layer 24 is typically about 1 to 10 microns thick. This layer 24 is patterned and developed using methods well-known to those of skill in the art.
  • a mask is placed over the photosensitive material, such as photoresist, and then exposed and developed.
  • the metal in the developed areas is then etched away ( FIG. 1 b , block 118 ).
  • the remaining photosensitive material is also removed using methods well-known to those of skill in the art ( FIG. 1 , block 118 ).
  • FIG. 2 h the exposed areas of the second metal layer which were not protected by the mask are etched away, leaving only the patterned second metal layer. These remaining areas of the second metal layer 22 form interconnect circuitry, bond pads, discrete passive component attach pads, etc.
  • the metal circuitry on the second surface 82 of the wafer 14 may be protected by an optional coating 26 of insulation, such as polyimide, BCB, etc.
  • the coating 26 may be deposited and then patterned (for instance, by forming, patterning, developing, and etching photoresist in a manner known to those of skill in the art) to form the desired coating 26 .
  • the layer of protective material initially formed over the passivation layer on the first surface of the wafer is removed using methods well-known to those of skill in the art. With reference to FIG. 2 j , the passivation layer 12 is now the top-most layer on the first surface 80 of the wafer 14 .
  • the “build-up” fabrication discussed above in FIGS. 1 a - 1 b and 2 a - 2 j may be carried out at a substrate level. Where the substrate is a wafer, the wafer may be subsequently singulated at package assembly, forming IC dies.
  • the IC dies created from the fabrication process described in FIGS. 1 a - 1 b and 2 a - 2 j serve as the semiconductor device that will be implemented in the IC device package.
  • the IC dies are used to form flip chips or wafer level chip size packages (CSP), although other types of chips may be used.
  • CSP wafer level chip size packages
  • an exemplary flip-chip 36 with fabricated structures on the bare silicon side of the chip 36 is shown attached to an electronic package's substrate, here a PCB, such as a package 4-layer laminate substrate 34 .
  • the chip 36 may have components on the front, or passivation, side of the chip in other embodiments; however, these are not pictured in this embodiment.
  • the chip 36 is attached to the 4-layer laminate substrate 34 with solder balls 32 .
  • the area of fabrication 50 on the silicon side of the chip 36 includes a metal layer 16 which provides RF shielding and/or circuit grounding. Components 30 , 28 may be mounted on attach pads 70 , 68 formed over the metal layer 16 .
  • Component 30 is wirebonded 54 to metal bond pad 52 while component 28 is also wirebonded 56 , 60 to metal bond pads 52 , 22 .
  • Metal bond pad 52 also serves as an interconnect.
  • Component 28 is also wirebonded 66 to a bond pad 58 on the package substrate 34 .
  • Leads 62 , 64 connect the metal layer 16 to substrate connection pad 58 , or ground, and thus provide ground-signal-ground shielding.
  • the active and passive components which may be attached include, but are not limited to, crystals, transceiver ICs, power management ICs, EEPROM ICs, switches, baluns, capacitors, etc.
  • the components may be attached in a variety of ways, including soldering and attaching with a conductive epoxy. These components may be attached and interconnected at wafer level prior to wafer dicing, or attached after saw singulation, or may be attached and interconnected at package assembly, after the chip has been attached to the product substrate.
  • FIG. 4 shows an exemplary plan view of a multi-chip module using IC chips 36 , in this case, flip-chips, with fabricated structures on the bare silicon side of the chip.
  • a number of different components have been attached to the chips 36 mounted on the four-layer substrate 34 .
  • These components include a crystal 48 , a power management IC 46 , a balun 44 , a switch 42 , a transceiver IC 38 , and an EEPROM IC 40 .
  • any number of different components and arrangements may be employed and may be mounted on chips other than flip-chips; a wide range of package substrates, with different numbers of layers which may be made of various materials may also be employed.
  • a side elevation of this package is shown in FIG. 5 (with some passives omitted for clarity). In this exemplary embodiment, the height of the package 72 , including the substrate and the attached components does not exceed 1.5 mm.
  • the size of electronic packages may be reduced. This is particularly important given the trend towards miniaturization, especially for portable products such as cellular phones.
  • metal or conductive layers other than those described and shown may be used (e.g., platinum, tantalum, etc.).
  • conductive layers may be deposited or formed by methods and techniques other than those described herein (e.g., copper may be formed by a dual damascene technique known to those of skill in the art).

Abstract

An apparatus and method for incorporating discrete passive components into an integrated circuit package. A first surface of a substrate is coated with a material to mechanically protect the first surface. A first metal layer and then an insulating layer are formed on a second surface of the substrate. Selected areas are removed from the insulating and a second metal layer is formed over the insulating layer and the exposed metal layer. Selected areas of the second metal layer are removed to form a plurality of structures, including at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached. An electronic component may be attached to at least one of the structures. The resulting integrated circuit die may be incorporated into an electronic package.

Description

    TECHNICAL FIELD
  • The present invention generally concerns fabrication of semiconductor devices, particularly semiconductor devices incorporated in integrated circuit packages.
    • BACKGROUND
  • Miniaturization of integrated circuit (IC) packages which may be incorporated in portable consumer products such as cellular phones, and mobile or laptop computers, has become increasingly important. One approach to miniaturization is the use of multi-chip modules where multiple chips having related functions are incorporated in a single package.
  • Single packages may also include stacked chips, in which chips are vertically stacked on top of each other. A potential drawback to using stacked die techniques is that no interconnection exists on the surfaces of the stacked die; the die interconnect is limited to die-to-die and die-to-substrate interconnections. Therefore, the IC die count is typically limited to one die per attach surface. It is not feasible to attach discrete electronic components to these surfaces since they typically require solderable attachment lands and interconnect circuitry or a noble metal surface for low contact resistance connections.
  • As such, it would be desirable to improve the manner in which discrete electronic components are incorporated in IC packages, such as utilizing die surfaces not conventionally used for die interconnections.
    • SUMMARY
  • In one embodiment, a method of fabrication comprises providing a substrate with a first surface having a passivation layer. At least one structure is built on a second surface of the substrate; an electronic component is to be attached to at least one structure. The structures that may be built include a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached.
  • Another embodiment is an electronic package. The electronic package comprises a substrate which is coupled to a first surface of an integrated circuit die. The first surface of the integrated circuit die has means for coupling to the first surface of the substrate and has at least one first electronic component attached to the first surface of the integrated circuit die. At least one structure is attached to a second surface of the integrated circuit die.
  • Yet another embodiment is an electronic package comprising a substrate which is coupled to a flip chip. At least one first electronic component and means for coupling the flip chip to the substrate is attached to a first surface of the flip chip. At least one structure is attached to a second surface of the flip chip.
  • In another embodiment, a semiconductor device comprises a substrate having a first surface and a second surface, a passivation layer on the first surface of the substrate, and at least one structure attached to the second surface of the substrate. The structure is configured to be coupled to an electronic component.
  • In yet another embodiment, a method of integrated circuit device packaging comprises providing a substrate, coupling a first surface of an integrated circuit die to the substrate, and attaching at least one electronic component to at least one structure on a second surface of the integrated circuit die. The first surface of the integrated circuit die is coupled to at least one electronic component.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1 a-1 b are flowcharts of a fabrication process in an exemplary embodiment of the invention.
  • FIGS. 2 a -2 j are diagrams showing stages of fabrication in an exemplary embodiment of the invention.
  • FIG. 3 is a view of a chip fabricated in accordance with steps shown in FIGS. 2 a-2 j attached to a substrate.
  • FIG. 4 is an overhead plan of a multi-chip module incorporating chips fabricated in accordance with steps shown in FIGS. 2 a-2 j.
  • FIG. 5 is a side view of a multi-chip module incorporating chips fabricated in accordance with steps shown in FIGS. 2 a-2 j.
    • DETAILED DESCRIPTION
  • In FIG. 1 a, an exemplary process for fabricating a semiconductor device with circuitry on both surfaces of the device (such that one surface connects the device to an electronic package's substrate (such as a printed circuit board (“PCB”) and another surface may be used to attach discrete electronic components) is shown. A wafer is provided with fabricated circuitry on a first surface of the wafer (block 100). The wafer may be made of any suitable semiconductor material, such as silicon or gallium arsenide, used in the art. It should also be appreciated that any substrate (such as silicon on an insulator), or semiconductor substrate, including the wafer, may be used in various embodiments. The device substrate should not be confused with the same substrate often used to generally label PCBs. The fabricated devices on the first surface are produced through conventional semiconductor manufacturing methods.
  • A removable layer, for mechanical protection for the first surface of the semiconductor substrate, such as photoresist or dry film, is deposited over a top passivation layer on the first surface of the wafer (block 102), where the fabricated circuitry is located. In FIG. 2 a, the wafer 14 has a first surface 80 and a second surface 82, with a passivation layer 12 and a layer of protective material 10 on a first surface of the wafer 80, which also contains the fabricated devices (not shown here). The layer of protective material 10 is typically 1 to 10 microns thick and provides mechanical protection to the passivation layer 12, which in turn protects the active device circuitry. The layer of protective material is formed using methods well-known to those of skill in the art.
  • The second surface of the wafer is then metallized (FIG. 1 a, block 104). In FIG. 2 b, the wafer 14 is turned “upside down” and a metal layer 16 is formed over the second surface 82 of the wafer 14. In one embodiment, the second surface 82 of the wafer 14 is blanket metallized by standard metal deposition processes, such as evaporation or chemical vapor deposition (“CVD”), sputtering, and plating. The resulting metal layer 16 is typically about 0.1 micron to 10 microns thick. The metal layer 16 provides RF shielding and wirebonding functions. The metal layer 16 may be a single layer, for example, aluminum (Al), or may be formed of multiple layers, using metals such as titanium tungsten-god (TiW—Au), titanium-gold (Ti—Au), chromium-gold (Cr—Au), titanium tungsten-nickel-gold (Ti—Ni—Au), titanium-nickel-gold (Ti—Ni—Au), titanium-copper-nickel-gold (Ti—Cu—Ni—Au), titanium-tungsten-copper-nickel-silver (TiW—Cu—Ni—Ag), etc. Metal layer 16 choices may be selected based on the mechanism used to attach components to the semiconductor device fabricated on the wafer. For example, the use of gold, silver, and/or palladium is suitable for wire-bonding and the use of nickel and copper is suitable for soldering and electrical conductivity. Nickel is a good diffusion barrier. Titanium, titanium tungsten, and chromium provide adhesion of the metal film stack to the wafer.
  • An insulating layer is formed over the metal layer (FIG. 1 a, block 106). In FIG. 2 c, an insulating film 18, such as polyimide, benzocyclobutene (BCB), etc., is formed over the metal layer 16. The insulating film 18 is typically about 2 to 15 microns thick. The insulating film 18 is formed using methods well-known to those of skill in the art. This insulating film 18 may be either photo-definable or standard non-photo-sensitive film.
  • In the case of using a non-photo-sensitive insulating film, a photosensitive material, such as photoresist, is deposited over the insulating film layer (FIG. 1 a, block 108). In FIG. 2 d, a layer of photosensitive film (typically 1 to 10 microns), such as photoresist 20, is deposited over the insulating film 18. This layer 20 of photoresist is patterned and developed using methods well-known to those of skill in the art.
  • A mask is placed over the photosensitive material, such as photoresist, and then exposed and etched away (FIG. 1 a, block 110). The insulating film layer that is now exposed is removed using wet etch or dry etch techniques. The remaining photosensitive material is also removed using methods well-known to those of skill in the art (FIG. 1 a, block 110). In FIG. 2 e, the second surface 82 of the wafer 14 has a patterned insulating film layer 18 remaining on the metal layer 16 after the removal of the layer of photoresist. The method just described uses a negative acting photoresist. A positive acting photoresist can also be used to achieve the same goal.
  • The remaining insulating film and exposed metal layer is covered with a second metal layer (FIG. 1 a, block 112). In one embodiment, the surface is blanket metallized; in other embodiments, other metal deposition processes, such as sputtering and plating, may also be employed. In FIG. 2 f, the second metal layer 22 covers the insulating film 18 and the exposed metal layer 16. The second metal layer is typically about 0.1 to 10 microns thick. The second metal layer 22 may be a single layer, for example, aluminum (Al), or may be formed of multiple layers, using metals such as titanium tungsten-god (TiW—Au), titanium-gold (Ti—Au), chromium-gold (Cr—Au), titanium tungsten-nickel-gold (Ti—Ni—Au), titanium-nickel-gold (Ti—Ni—Au), titanium-copper-nickel-gold (Ti—Cu—Ni—Au), titanium-tungsten-copper-nickel-silver (TiW—Cu—Ni—Ag), etc. In other embodiments, the metal layer 22 may be formed of metal which are wirebondable or solderable (such as copper, silver, etc.) or have a diffusion barrier (e.g., nickel).
  • A layer of photosensitive material, such as photoresist, is deposited over the second metal layer (FIG. 1 b, block 116). In FIG. 2 g, a photosensitive film layer 24 has been deposited on the second metal layer 22. The photosensitive film layer 24 is typically about 1 to 10 microns thick. This layer 24 is patterned and developed using methods well-known to those of skill in the art.
  • A mask is placed over the photosensitive material, such as photoresist, and then exposed and developed. The metal in the developed areas is then etched away (FIG. 1 b, block 118). The remaining photosensitive material is also removed using methods well-known to those of skill in the art (FIG. 1, block 118). In FIG. 2 h, the exposed areas of the second metal layer which were not protected by the mask are etched away, leaving only the patterned second metal layer. These remaining areas of the second metal layer 22 form interconnect circuitry, bond pads, discrete passive component attach pads, etc.
  • In one embodiment shown in FIG. 2 i, the metal circuitry on the second surface 82 of the wafer 14 may be protected by an optional coating 26 of insulation, such as polyimide, BCB, etc. The coating 26 may be deposited and then patterned (for instance, by forming, patterning, developing, and etching photoresist in a manner known to those of skill in the art) to form the desired coating 26.
  • The layer of protective material initially formed over the passivation layer on the first surface of the wafer is removed using methods well-known to those of skill in the art. With reference to FIG. 2 j, the passivation layer 12 is now the top-most layer on the first surface 80 of the wafer 14.
  • The “build-up” fabrication discussed above in FIGS. 1 a-1 b and 2 a-2 j may be carried out at a substrate level. Where the substrate is a wafer, the wafer may be subsequently singulated at package assembly, forming IC dies. The IC dies created from the fabrication process described in FIGS. 1 a-1 b and 2 a-2 j (including other embodiments where the substrate is not a wafer) serve as the semiconductor device that will be implemented in the IC device package. The IC dies are used to form flip chips or wafer level chip size packages (CSP), although other types of chips may be used.
  • With reference to FIG. 3, an exemplary flip-chip 36 with fabricated structures on the bare silicon side of the chip 36 is shown attached to an electronic package's substrate, here a PCB, such as a package 4-layer laminate substrate 34. (The chip 36 may have components on the front, or passivation, side of the chip in other embodiments; however, these are not pictured in this embodiment.) The chip 36 is attached to the 4-layer laminate substrate 34 with solder balls 32. The area of fabrication 50 on the silicon side of the chip 36 includes a metal layer 16 which provides RF shielding and/or circuit grounding. Components 30, 28 may be mounted on attach pads 70, 68 formed over the metal layer 16. Component 30 is wirebonded 54 to metal bond pad 52 while component 28 is also wirebonded 56, 60 to metal bond pads 52, 22. Metal bond pad 52 also serves as an interconnect. Component 28 is also wirebonded 66 to a bond pad 58 on the package substrate 34. Leads 62, 64 connect the metal layer 16 to substrate connection pad 58, or ground, and thus provide ground-signal-ground shielding.
  • Various components can be attached to the attach pads. The active and passive components which may be attached include, but are not limited to, crystals, transceiver ICs, power management ICs, EEPROM ICs, switches, baluns, capacitors, etc. The components may be attached in a variety of ways, including soldering and attaching with a conductive epoxy. These components may be attached and interconnected at wafer level prior to wafer dicing, or attached after saw singulation, or may be attached and interconnected at package assembly, after the chip has been attached to the product substrate.
  • FIG. 4 shows an exemplary plan view of a multi-chip module using IC chips 36, in this case, flip-chips, with fabricated structures on the bare silicon side of the chip. In this exemplary embodiment, a number of different components have been attached to the chips 36 mounted on the four-layer substrate 34. These components include a crystal 48, a power management IC 46, a balun 44, a switch 42, a transceiver IC 38, and an EEPROM IC 40. In other embodiments, any number of different components and arrangements may be employed and may be mounted on chips other than flip-chips; a wide range of package substrates, with different numbers of layers which may be made of various materials may also be employed. A side elevation of this package is shown in FIG. 5 (with some passives omitted for clarity). In this exemplary embodiment, the height of the package 72, including the substrate and the attached components does not exceed 1.5 mm.
  • Using the approaches described above, the size of electronic packages may be reduced. This is particularly important given the trend towards miniaturization, especially for portable products such as cellular phones.
  • While the preceding description has described specific embodiments, it will be evident to a skilled artisan that various changes and modifications can be made to these embodiments. For example, metal or conductive layers other than those described and shown may be used (e.g., platinum, tantalum, etc.). A skilled artisan will recognize that such conductive layers may be deposited or formed by methods and techniques other than those described herein (e.g., copper may be formed by a dual damascene technique known to those of skill in the art). The specification and drawings, therefore, are to be regarded in an illustrative rather than a restrictive sense.

Claims (43)

1. A method of fabrication comprising:
a) providing a substrate with a first surface having a passivation layer; and
b) building a plurality of structures on a second surface of the substrate, the plurality of structures including at least one structure to which an electronic component may be attached, the plurality of structures including at least one of the following:
i) a wirebonding pad;
ii) a solder-bonding pad;
iii) a device interconnect circuit; or
iv) an attach pad to which an electronic component can be attached.
2. The method of claim 1 wherein building the plurality of structures includes forming a metal layer on the second surface of the substrate.
3. The method of claim 2 wherein building the plurality of structures includes forming an insulating layer on the metal layer.
4. The method of claim 3 wherein building the plurality of structures includes removing selected areas of the insulating layer, thereby exposing portions of the first metal layer.
5. The method of claim 4 wherein building the plurality of structures includes forming a second metal layer over the insulating layer and the exposed portions of the first metal layer.
6. The method of claim 5 wherein building the plurality of structures includes removing selected areas of the second metal layer to form the plurality of structures.
7. The method of claim 1 further comprising attaching the substrate to an electronic package.
8. The method of claim 7 wherein the package is a multi-chip module package.
9. The method of claim 1 further comprising coating the first surface with a material to mechanically protect the first surface.
10. The method of claim 1 further comprising attaching the electronic component to the attach pad.
11. The method of claim 10 wherein the electronic component is either an active or passive component.
12. The method of claim 1 wherein the substrate is a semiconductor substrate.
13. The method of claim 1 wherein the second surface is silicon or gallium arsenide.
14. An electronic package comprising:
a) a substrate;
b) an integrated circuit die coupled to a first surface of the substrate, a first surface of the integrated circuit die having a means for coupling to the first surface of the substrate, at least one first electronic component attached to the first surface of the integrated circuit die, at least one structure attached to a second surface of the integrated circuit die, the at least one structure configured to be coupled to a second electronic component.
15. The electronic package of claim 14 wherein the at least one structure attached to the second surface includes at least one of the following:
a) a wirebonding pad;
b) a solder-bonding pad;
c) a device interconnect circuit; or
d) an attach pad to which the second electronic component may be coupled.
16. The electronic package of claim 15 further comprising the second electronic component attached to the at least one structure.
17. The electronic package of claim 16 further comprising the second electronic component coupled to the substrate.
18. The electronic package of claim 17 wherein the second electronic component is coupled to the substrate by a wirebond.
19. The electronic package of claim 16 wherein the second electronic component is either an active or passive component.
20. The electronic package of claim 14 wherein the electronic package is a multi-chip module package.
21. The electronic package of claim 14 wherein the substrate is a printed circuit board.
22. An electronic package comprising:
a) a substrate;
b) a flip chip attached to a first surface of the substrate, a first surface of the flip chip having a means for attachment to the first surface of the substrate, at least one first electronic component attached to the first surface of the flip chip, at least one structure attached to a second surface of the flip chip, the at least one structure configured to be coupled to a second electronic component.
23. The electronic package of claim 14 wherein the at least one structure attached to the second surface includes at least one of the following:
a) a wirebonding pad;
b) a solder-bonding pad;
c) a device interconnect circuit; or
d) an attach pad to which the second electronic component may be coupled.
24. The electronic package of claim 23 further comprising a second electronic component attached to the at least one structure.
25. The electronic package of claim 23 wherein the second electronic component is either an active or passive component.
26. The electronic package of claim 22 wherein the electronic package is a multi-chip module package.
27. The electronic package of claim 22 wherein the substrate is a printed circuit board.
28. A semiconductor device comprising:
a) a first substrate having a first surface and a second surface;
b) a passivation layer on the first surface of the first substrate; and
c) at least one structure attached to the second surface of the first substrate, the at least one structure configured to be coupled to an electronic component.
29. The semiconductor device of claim 28 wherein the at least one structure includes at least one of the following:
a) a wirebonding pad;
b) a solder-bonding pad;
c) a device interconnect circuit; or
d) an attach pad to which the electronic component may be attached.
30. The semiconductor device of claim 28 further comprising a means for attachment to a second substrate, the means for attachment coupled to the first surface of first substrate.
31. The semiconductor device of claim 30 wherein the second substrate is attached to an electronic package.
32. The semiconductor device of claim 30 further comprising at least one electronic component attached to the at least one structure.
33. The semiconductor device of claim 28 wherein the first substrate is a semiconductor substrate.
34. The semiconductor device of claim 28 wherein the semiconductor substrate is silicon or gallium arsenside.
35. The semiconductor device of claim 32 wherein the at least one electronic component is an active or passive component.
36. The semiconductor device of claim 30 wherein the second substrate is a semiconductor substrate.
37. A method of integrated circuit device packaging comprising:
a) providing a substrate;
b) coupling a first surface of an integrated circuit die to the substrate, the first surface coupled to at least one electronic component; and
c) attaching at least one electronic component to at least one structure on a second surface of the integrated circuit die.
38. The method of claim 37 wherein the first surface of the integrated circuit die is coupled to the substrate by solder balls.
39. The method of claim 37 wherein the first surface of the integrated circuit die is coupled to the substrate by wirebond.
40. The method of claim 37 further comprising coupling the at least one electronic component to the substrate.
41. The method of claim 37 wherein the at least one electronic component is coupled to the substrate by a wirebond.
42. The method of claim 37 wherein the electronic component is either an active or passive component.
43. The method of claim 37 wherein the substrate is a printed circuit board.
US11/304,084 2005-12-15 2005-12-15 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package Abandoned US20070138628A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/304,084 US20070138628A1 (en) 2005-12-15 2005-12-15 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US11/456,685 US8258599B2 (en) 2005-12-15 2006-07-11 Electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US12/534,819 US8860195B2 (en) 2005-12-15 2009-08-03 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/304,084 US20070138628A1 (en) 2005-12-15 2005-12-15 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/456,685 Continuation-In-Part US8258599B2 (en) 2005-12-15 2006-07-11 Electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US12/534,819 Division US8860195B2 (en) 2005-12-15 2009-08-03 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package

Publications (1)

Publication Number Publication Date
US20070138628A1 true US20070138628A1 (en) 2007-06-21

Family

ID=38172476

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/304,084 Abandoned US20070138628A1 (en) 2005-12-15 2005-12-15 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US12/534,819 Active US8860195B2 (en) 2005-12-15 2009-08-03 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/534,819 Active US8860195B2 (en) 2005-12-15 2009-08-03 Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package

Country Status (1)

Country Link
US (2) US20070138628A1 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070138572A1 (en) * 2005-12-15 2007-06-21 Atmel Corporation An electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US20080054428A1 (en) * 2006-07-13 2008-03-06 Atmel Corporation A stacked-die electronics package with planar and three-dimensional inductor elements
US20090294957A1 (en) * 2005-12-15 2009-12-03 Lam Ken M Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US20110316160A1 (en) * 2006-10-20 2011-12-29 Infineon Technologies Ag Semiconductor Arrangement, Semiconductor Module, and Method for Connecting a Semiconductor Chip to a Ceramic Substrate
US20120026337A1 (en) * 2010-07-27 2012-02-02 Flir Systems, Inc. Infrared camera architecture systems and methods
US20120181706A1 (en) * 2011-01-18 2012-07-19 Jian-Hong Zeng Power semiconductor package structure and manufacturing method thereof
CN102956629A (en) * 2011-08-17 2013-03-06 英特赛尔美国有限公司 Back-to-back stacked dies
US20160247752A1 (en) * 2015-02-25 2016-08-25 United States Of America, As Represented By The Secretary Of The Navy Compensation Of Bondwires In The Microwave Regime
US9741591B2 (en) 2012-12-31 2017-08-22 Flir Systems, Inc. Wafer level packaging of microbolometer vacuum package assemblies
US20190088576A1 (en) * 2017-09-19 2019-03-21 Nxp Usa, Inc. Packaged integrated circuit having stacked die and method for therefor
US10734312B2 (en) 2018-07-18 2020-08-04 Nxp Usa, Inc. Packaged integrated circuit having stacked die and method for therefor
CN116845038A (en) * 2023-08-29 2023-10-03 之江实验室 Heat dissipation device for wafer-level processor and preparation method thereof

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075712A (en) * 1999-01-08 2000-06-13 Intel Corporation Flip-chip having electrical contact pads on the backside of the chip
US6091144A (en) * 1996-09-09 2000-07-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US20020086533A1 (en) * 1999-08-30 2002-07-04 Syun-Ming Jang Method of improving the bondability between Au wires and Cu bonding pads
US6538313B1 (en) * 2001-11-13 2003-03-25 National Semiconductor Corporation IC package with integral substrate capacitor
US6780677B2 (en) * 1997-03-27 2004-08-24 Hitachi, Ltd. Process for mounting electronic device and semiconductor device
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
US20050002167A1 (en) * 2003-07-02 2005-01-06 John Hsuan Microelectronic package
US20050046041A1 (en) * 2003-08-29 2005-03-03 Advanced Semiconductor Engineering, Inc. Integrated circuit device with embedded passive component by flip-chip connection and method for manufacturing the same
US6890829B2 (en) * 2000-10-24 2005-05-10 Intel Corporation Fabrication of on-package and on-chip structure using build-up layer process
US20050127397A1 (en) * 2001-02-23 2005-06-16 Nitronex Corporation Gallium nitride materials including thermally conductive regions
US20050133916A1 (en) * 2003-12-17 2005-06-23 Stats Chippac, Inc Multiple chip package module having inverted package stacked over die
US20060027841A1 (en) * 2004-08-04 2006-02-09 Sharp Kabushiki Kaisha Stack type semiconductor apparatus package and manufacturing method thereof
US20060286716A1 (en) * 2002-12-18 2006-12-21 K-Tec Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
US20070138572A1 (en) * 2005-12-15 2007-06-21 Atmel Corporation An electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US7239025B2 (en) * 1999-02-19 2007-07-03 Micron Technology, Inc. Selective deposition of solder ball contacts
US7335994B2 (en) * 2003-01-27 2008-02-26 Micron Technology, Inc. Semiconductor component having multiple stacked dice

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829128A (en) * 1993-11-16 1998-11-03 Formfactor, Inc. Method of mounting resilient contact structures to semiconductor devices
GB2288286A (en) 1994-03-30 1995-10-11 Plessey Semiconductors Ltd Ball grid array arrangement
US5478773A (en) * 1994-04-28 1995-12-26 Motorola, Inc. Method of making an electronic device having an integrated inductor
US5541135A (en) * 1995-05-30 1996-07-30 Motorola, Inc. Method of fabricating a flip chip semiconductor device having an inductor
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US6008102A (en) * 1998-04-09 1999-12-28 Motorola, Inc. Method of forming a three-dimensional integrated inductor
US6191468B1 (en) * 1999-02-03 2001-02-20 Micron Technology, Inc. Inductor with magnetic material layers
US6218729B1 (en) 1999-03-11 2001-04-17 Atmel Corporation Apparatus and method for an integrated circuit having high Q reactive components
US6486530B1 (en) * 2000-10-16 2002-11-26 Intarsia Corporation Integration of anodized metal capacitors and high temperature deposition capacitors
US6441483B1 (en) * 2001-03-30 2002-08-27 Micron Technology, Inc. Die stacking scheme
JP2003060153A (en) * 2001-07-27 2003-02-28 Nokia Corp Semiconductor package
US6744114B2 (en) * 2001-08-29 2004-06-01 Honeywell International Inc. Package with integrated inductor and/or capacitor
US6444517B1 (en) * 2002-01-23 2002-09-03 Taiwan Semiconductor Manufacturing Company High Q inductor with Cu damascene via/trench etching simultaneous module
JP3991788B2 (en) * 2002-07-04 2007-10-17 日本電気株式会社 Solder and mounted product using it
US6859129B2 (en) * 2002-08-20 2005-02-22 Asia Pacific Microsystems Three-dimensional integrated adjustable inductor, its module and fabrication method of the same
JP4243117B2 (en) * 2002-08-27 2009-03-25 新光電気工業株式会社 Semiconductor package, manufacturing method thereof, and semiconductor device
US7312101B2 (en) * 2003-04-22 2007-12-25 Micron Technology, Inc. Packaged microelectronic devices and methods for packaging microelectronic devices
US7382056B2 (en) * 2004-04-29 2008-06-03 Sychip Inc. Integrated passive devices
US20060245308A1 (en) * 2005-02-15 2006-11-02 William Macropoulos Three dimensional packaging optimized for high frequency circuitry
US7947535B2 (en) * 2005-10-22 2011-05-24 Stats Chippac Ltd. Thin package system with external terminals
US20070138628A1 (en) * 2005-12-15 2007-06-21 Lam Ken M Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US7932590B2 (en) * 2006-07-13 2011-04-26 Atmel Corporation Stacked-die electronics package with planar and three-dimensional inductor elements

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091144A (en) * 1996-09-09 2000-07-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor package
US6780677B2 (en) * 1997-03-27 2004-08-24 Hitachi, Ltd. Process for mounting electronic device and semiconductor device
US6075712A (en) * 1999-01-08 2000-06-13 Intel Corporation Flip-chip having electrical contact pads on the backside of the chip
US7239025B2 (en) * 1999-02-19 2007-07-03 Micron Technology, Inc. Selective deposition of solder ball contacts
US20020086533A1 (en) * 1999-08-30 2002-07-04 Syun-Ming Jang Method of improving the bondability between Au wires and Cu bonding pads
US6890829B2 (en) * 2000-10-24 2005-05-10 Intel Corporation Fabrication of on-package and on-chip structure using build-up layer process
US20050127397A1 (en) * 2001-02-23 2005-06-16 Nitronex Corporation Gallium nitride materials including thermally conductive regions
US6538313B1 (en) * 2001-11-13 2003-03-25 National Semiconductor Corporation IC package with integral substrate capacitor
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
US20060286716A1 (en) * 2002-12-18 2006-12-21 K-Tec Devices Corp. Flip-chip mounting electronic component and method for producing the same, circuit board and method for producing the same, method for producing package
US7335994B2 (en) * 2003-01-27 2008-02-26 Micron Technology, Inc. Semiconductor component having multiple stacked dice
US20050002167A1 (en) * 2003-07-02 2005-01-06 John Hsuan Microelectronic package
US20050046041A1 (en) * 2003-08-29 2005-03-03 Advanced Semiconductor Engineering, Inc. Integrated circuit device with embedded passive component by flip-chip connection and method for manufacturing the same
US20050133916A1 (en) * 2003-12-17 2005-06-23 Stats Chippac, Inc Multiple chip package module having inverted package stacked over die
US20060027841A1 (en) * 2004-08-04 2006-02-09 Sharp Kabushiki Kaisha Stack type semiconductor apparatus package and manufacturing method thereof
US20070138572A1 (en) * 2005-12-15 2007-06-21 Atmel Corporation An electronics package with an integrated circuit device having post wafer fabrication integrated passive components

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8860195B2 (en) 2005-12-15 2014-10-14 Atmel Corporation Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US20090294957A1 (en) * 2005-12-15 2009-12-03 Lam Ken M Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US20070138572A1 (en) * 2005-12-15 2007-06-21 Atmel Corporation An electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US8258599B2 (en) 2005-12-15 2012-09-04 Atmel Corporation Electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US20080054428A1 (en) * 2006-07-13 2008-03-06 Atmel Corporation A stacked-die electronics package with planar and three-dimensional inductor elements
US7932590B2 (en) 2006-07-13 2011-04-26 Atmel Corporation Stacked-die electronics package with planar and three-dimensional inductor elements
US20110193192A1 (en) * 2006-07-13 2011-08-11 Atmel Corporation Stacked-Die Electronics Package with Planar and Three-Dimensional Inductor Elements
US8324023B2 (en) 2006-07-13 2012-12-04 Atmel Corporation Stacked-die electronics package with planar and three-dimensional inductor elements
US20110316160A1 (en) * 2006-10-20 2011-12-29 Infineon Technologies Ag Semiconductor Arrangement, Semiconductor Module, and Method for Connecting a Semiconductor Chip to a Ceramic Substrate
US9196562B2 (en) * 2006-10-20 2015-11-24 Infineon Technologies Ag Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate
US10161803B2 (en) 2010-07-27 2018-12-25 Flir Systems, Inc. Wafer level packaging of infrared camera detectors
US9513172B2 (en) 2010-07-27 2016-12-06 Flir Systems, Inc. Wafer level packaging of infrared camera detectors
US8743207B2 (en) * 2010-07-27 2014-06-03 Flir Systems Inc. Infrared camera architecture systems and methods
US9377363B2 (en) 2010-07-27 2016-06-28 Flir Systems, Inc. Infrared camera architecture systems and methods
US20120026337A1 (en) * 2010-07-27 2012-02-02 Flir Systems, Inc. Infrared camera architecture systems and methods
US8426963B2 (en) * 2011-01-18 2013-04-23 Delta Electronics, Inc. Power semiconductor package structure and manufacturing method thereof
US20120181706A1 (en) * 2011-01-18 2012-07-19 Jian-Hong Zeng Power semiconductor package structure and manufacturing method thereof
US10290618B2 (en) 2011-08-17 2019-05-14 Intersil Americas LLC Back-to-back stacked dies
US9524957B2 (en) 2011-08-17 2016-12-20 Intersil Americas LLC Back-to-back stacked dies
CN102956629A (en) * 2011-08-17 2013-03-06 英特赛尔美国有限公司 Back-to-back stacked dies
CN110211948A (en) * 2011-08-17 2019-09-06 英特赛尔美国有限公司 Back-to-back stacked chips
US9741591B2 (en) 2012-12-31 2017-08-22 Flir Systems, Inc. Wafer level packaging of microbolometer vacuum package assemblies
US10553454B2 (en) 2012-12-31 2020-02-04 Flir Systems, Inc. Wafer level packaging of microbolometer vacuum package assemblies
US10014276B2 (en) * 2015-02-25 2018-07-03 The United States Of America, As Represented By The Secretary Of The Navy Compensation of bondwires in the microwave regime
US20160247752A1 (en) * 2015-02-25 2016-08-25 United States Of America, As Represented By The Secretary Of The Navy Compensation Of Bondwires In The Microwave Regime
US20190088576A1 (en) * 2017-09-19 2019-03-21 Nxp Usa, Inc. Packaged integrated circuit having stacked die and method for therefor
US10446476B2 (en) * 2017-09-19 2019-10-15 Nxp Usa, Inc. Packaged integrated circuit having stacked die and method for therefor
US10734312B2 (en) 2018-07-18 2020-08-04 Nxp Usa, Inc. Packaged integrated circuit having stacked die and method for therefor
CN116845038A (en) * 2023-08-29 2023-10-03 之江实验室 Heat dissipation device for wafer-level processor and preparation method thereof

Also Published As

Publication number Publication date
US8860195B2 (en) 2014-10-14
US20090294957A1 (en) 2009-12-03

Similar Documents

Publication Publication Date Title
US8860195B2 (en) Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US9559029B2 (en) Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US7842607B2 (en) Semiconductor device and method of providing a thermal dissipation path through RDL and conductive via
US8072059B2 (en) Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US7727876B2 (en) Semiconductor device and method of protecting passivation layer in a solder bump process
US7667335B2 (en) Semiconductor package with passivation island for reducing stress on solder bumps
US6664644B2 (en) Semiconductor device and method for manufacturing the same
US8921983B2 (en) Semiconductor package and method of forming similar structure for top and bottom bonding pads
TWI518811B (en) Semiconductor device and method of forming bump structure with multi-layer ubm around bump formation area
US20130341789A1 (en) Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection
EP1941541B1 (en) Redistribution layer for wafer-level chip scale package and method therefor
US20090294899A1 (en) Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias
KR102362426B1 (en) Emi shielding for flip chip package with exposed die backside
US7772106B2 (en) Method of forming an inductor on a semiconductor wafer
US8568822B2 (en) Apparatus and method incorporating discrete passive components in an electronic package
US11062994B2 (en) Semiconductor device package and method of manufacturing the same
US9466577B2 (en) Semiconductor interconnect structure with stacked vias separated by signal line and method therefor
US10700029B2 (en) Semiconductor package device and method of manufacturing the same
US11127705B2 (en) Semiconductor structure and manufacturing method thereof
KR20210007870A (en) Semiconductor device and a method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: ATMEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAM, KEN M.;REEL/FRAME:017642/0440

Effective date: 20051213

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION