US20070141803A1 - Methods for making substrates and substrates formed therefrom - Google Patents

Methods for making substrates and substrates formed therefrom Download PDF

Info

Publication number
US20070141803A1
US20070141803A1 US11/505,668 US50566806A US2007141803A1 US 20070141803 A1 US20070141803 A1 US 20070141803A1 US 50566806 A US50566806 A US 50566806A US 2007141803 A1 US2007141803 A1 US 2007141803A1
Authority
US
United States
Prior art keywords
substrate
seed layer
layer
thermal expansion
expansion coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/505,668
Inventor
Alice Boussagol
Bruce Faure
Bruno Ghyselen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Assigned to S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A. reassignment S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FAURE, BRUCE, GHYSELEN, BRUNO, BOUSSAGOL, ALICE
Priority to PCT/EP2006/070109 priority Critical patent/WO2007071772A1/en
Priority to CN2006800478498A priority patent/CN101341580B/en
Priority to KR1020087014900A priority patent/KR20080078679A/en
Priority to EP06841567A priority patent/EP1979933A1/en
Priority to TW095148275A priority patent/TWI324357B/en
Publication of US20070141803A1 publication Critical patent/US20070141803A1/en
Priority to US11/840,696 priority patent/US7615468B2/en
Priority to US12/536,082 priority patent/US7839001B2/en
Priority to US12/914,194 priority patent/US7939428B2/en
Assigned to SOITEC reassignment SOITEC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to methods for making substrates and substrates for use in optics, electronics or opto-electronics and, in particular, substrates which may be used for making solar cells, light-emitting diodes and lasers.
  • a thin layer taken from a donor substrate is transferred onto a receiving supporting substrate to obtain substrates including a thin useful layer.
  • Useful layer is the layer of the substrate on which electronic components such as, for example, light-emitting diodes or other components may be made.
  • the thin layer is deposited on a receiving supporting substrate by a deposition technique.
  • This deposition technique may notably consist of epitaxy or chemical vapor deposition.
  • Such removal of the receiving support results in loss of materials, thereby putting a strain on the manufacturing costs of such substrates.
  • a method for making substrates which includes a useful thin layer method in which the receiving supporting substrate is removed in order to be recycled.
  • a useful thin layer method in which the receiving supporting substrate is removed in order to be recycled.
  • This method includes a step for transferring a seed layer on a receiving support by molecular adhesion at a bonding interface, a step for epitaxy of a useful layer on the seed layer and a step for applying stresses in order to lead to removal of the assembly (i.e., removal of the seed layer and of the useful layer from the receiving support at the bonding interface).
  • Seed layer is the material layer which allows development of the epitaxied useful layer.
  • the invention relates to a method for making substrates for optics, electronics, or opto-electronics which includes providing a donor substrate and a receiving substrate, wherein the receiving substrate has a thermal expansion coefficient; operably connecting the donor substrate to the receiving substrate; forming a seed layer on the receiving substrate, wherein the seed layer has a surface and a thermal expansion coefficient; and epitaxy of a useful layer on the seed layer, wherein the useful layer has a thermal expansion coefficient.
  • the thermal expansion coefficient of the receiving substrate is equal to or greater than the thermal expansion coefficient of the useful layer
  • the thermal expansion coefficient of the seed layer is about the same as the thermal expansion coefficient of the receiving substrate so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
  • the method for making substrates includes providing a donor substrate and a receiving support; forming a seed layer from the donor substrate; transferring the seed layer onto the receiving support; and forming a useful layer on the seed layer.
  • the thermal expansion coefficient of the receiving support is equal to or greater than the thermal expansion coefficient of the useful layer
  • the thermal expansion coefficient of the seed layer is about equal to the thermal expansion coefficient of the receiving support so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
  • the seed layer and the receiving support may substantially expand in the same way.
  • the receiving support may expand slightly less than the seed layer so that the seed layer may be placed under slight compression avoiding any deterioration of the seed layer.
  • the seed layer may consist of a material for which the thermal expansion coefficient is equal to (1+ ⁇ ) times that of the receiving support, with ⁇ of the order of 0.2, and preferably ⁇ equals 0.1.
  • the useful layer may consist of a material for which the thermal expansion coefficient may be larger than or equal to (1 ⁇ ′) times that of the receiving support, with a typical value of 0.2 for ⁇ ′.
  • the seed layer and/or the receiving support may be made of, for example, silicon, germanium, silicon carbide, GaN or sapphire.
  • the chemical composition of the seed layer advantageously, may be identical to that of the receiving support.
  • a composite substrate may be created using the method described herein.
  • the composite substrate may be used for optics, electronics, or opto-electronics,
  • the substrate may have at least one seed layer on a receiving support, and an epitaxied useful layer on the seed layer.
  • the thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer, and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support so that the seed layer and the receiving support-expand in substantially the same way to avoid stressing or deforming the seed layer.
  • FIG. 1 is a schematic illustration of the steps of an exemplary embodiment of a method for making a substrate.
  • FIG. 2 is a schematic illustration of the steps of an alternative exemplary embodiment of a method for making a substrate.
  • the method according to the invention includes a step for implanting atomic species at a determined depth in a donor substrate 1 in order to form a weakened area 2 .
  • the donor substrate may be boned upon or otherwise adhered onto a receiving substrate 3 by any appropriate means known in the art.
  • bonding may mean intimate contact of the donor substrate 1 with the receiving substrate 3 in order to join the donor substrate 1 and the receiving substrate 3 by molecular adhesion.
  • Bonding may be obtained according to various methods such as, for example, (1) having a surface of the donor substrate 1 come into direct contact with a surface of the receiving substrate; (2) forming a bonding layer in order to make a connecting layer on the surface of the donor substrate 1 , forming a bonding layer in order to make a second connecting layer on the surface of the receiving supporting substrate 3 and having the surfaces of the respective connecting layers of the donor substrate 1 and the donor substrate 3 come into contact with each other; and (3) forming a bonding layer on only one of both substrates.
  • the bonding layer may consist of, for example, an insulating layer or a dielectric layer.
  • the donor substrate 1 may be bonded onto the receiving substrate 3 by means of a bonding layer 4 deposited on the surface of the donor substrate and/or the receiving substrate 3 .
  • an annealing step may be applied at this stage for strengthening the bonding interface between the bonding layer 4 and the surface of the donor substrate 1 and/or the receiving substrate 3 . Nonetheless, bonding may be achieved according to any of the methods known to one skilled in the art.
  • a seed layer 5 may be detached from the donor substrate 1 at the weakened area 2 .
  • a useful layer 6 may be deposited on the surface of the seed layer 5 .
  • the useful layer 6 may be obtained by epitaxy, which is well known to one skilled in the art, according to step 300 .
  • the step 200 for implanting atomic species and for detaching the seed layer 5 corresponds to a SMART-CUT® method, a general description of which is found in the publication Silicon-On-Insulator Technology: Materials to VLSI, 2nd Edition of Jean-Pierre Colinge, Kluwer Academic Publishers, p. 50 and 51.
  • detachment of the seed layer 5 and of the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses, chemical etching, or a combination of at least two of these operations.
  • the seed layer 5 may consist of a material for which the thermal expansion coefficient is equal to (1+ ⁇ ) times that of the receiving support 3 , with ⁇ of the order of 0.2, and preferably ⁇ equals 0.1. It will however be observed that thermal expansion may vary with temperature, with the deposition technique, with the defects present inside the layers and also with the measurement techniques. Thus, when the structure is undergoing heat treatments (e.g., during detachment of the seed layer 5 and the useful layer 6 of the receiving substrate 3 ) the seed layer 5 and the receiving support 3 will substantially expand in the same way. The receiving support 3 will expand slightly less than the seed layer 5 so that the latter may be placed under slight compression, thereby avoiding deterioration of the seed layer 5 .
  • the useful layer 6 may consist of a material which has a thermal expansion coefficient which is larger than or equal to (1 ⁇ ′) times that of the receiving support 3 , with the value of ⁇ ′ between 0 and 0.8 and, preferably, between 0.2 and 0.3. Expansions of the different layers 5 , 6 and the receiving support 3 of the same order of magnitude during heat treatments may be obtained because of the closeness of the thermal expansion coefficients of the useful layer 6 , the seed layer 5 and the receiving support 3 . In this way, any risk of deterioration of the substrate or occurrence of a residual deflection of the final substrate may be avoided.
  • the seed layer 5 and/or the receiving support 3 may comprise a material such as, for example, silicon (e.g., ⁇ 111 ⁇ silicon), germanium, polycrystalline or monocrystalline silicon carbide, GaN, polycrystalline or monocrystalline AlN, and sapphire. Further, the chemical composition of the seed layer 5 may be identical with that of the receiving support 3 .
  • the method may also include steps for preparing the surface of the seed layer 5 .
  • These preparation steps may include, for example, polishing, annealing, smooth annealing operations (e.g., under hydrogen), annealing operations for strengthening the bond, sacrificial oxidization interface operations (i.e., for oxidizing and then removing the oxidized material), etching operations, etc.
  • Step 400 may lead to detachment at the bonding layer 4 of the assembly, consisting of the seed layer 5 and the useful layer 6 , from the receiving support 3 . If a self-supported substrate is desired, the assembly formed by the seed layer 5 and the useful layer 6 may only be able to be detached from the receiving support 3 if the thickness of the assembly is greater than or equal to 50 ⁇ m.
  • detachment may be accomplished by application of mechanical, thermal, electrostatic stresses; application of any type of etching (wet, dry, gas, etching, plasma etching, etc.) and/or application of any type of etching by irradiation such as laser irradiation (e.g., by chemical etchings at the bonding layer 4 ), or the like.
  • the receiving substrate 3 which may either be destroyed or recycled in order to reuse it during the making of a new substrate, may then be obtained on the one hand, and a structure consisting of the seed layer 5 and the useful layer 6 may be obtained on the other hand.
  • the useful layer 6 may be transferred onto a final supporting substrate 7 .
  • the final support 7 may be made of a material such as, for example, semi-conducting or semi-conductive materials (e.g., silicon, germanium, etc.), metals (e.g., copper), plastic materials and glasses. Since the resultant structure no longer undergoes any heat treatment, the final supporting substrate 7 may be made with any material which has a thermal expansion coefficient and/or a lattice parameter different from those of the useful layer 6 .
  • the useful layer 6 may be transferred onto the final supporting substrate 7 by bonding.
  • the bond may be obtained by applying a bonding layer 8 on one of the surfaces of the useful layer 6 and/or the final supporting substrate 7 . Similar to selecting the final substrate 7 , the bonding techniques applied in this step are not limited by temperature resistance, contaminations, the thermal expansion coefficient and/or the lattice parameter of the useful layer 6 .
  • the layer 8 used may comprise, for example, organic layers (e.g., insulating layers of the SiO 2 , Si 3 N 4 , or polyimides), conductive metal interfaces and seals (e.g., palladium silicide Pd 2 Si, tungsten silicide WSi 2 , SiAu, or PdIn).
  • the conductive interfaces may then provide the contact on the rear face of the layer.
  • the buried structure may consist of a triple junction based on amorphous silicon of the n-i-p type.
  • This buried structure may have a lower layer (i.e., a rear contact layer) consisting of metallization, such as silver (Ag) or aluminium (Al), on which a conducting transparent oxide may be deposited.
  • the rear contact layer on the one hand, may provide an electrical contact with which the triple junction solar cell may be connected and a rear mirror, on the other hand, allowing reflection of light which has not been absorbed by the solar cell.
  • the latter may consist of three amorphous silicon layers (of type n, i and p, respectively) successively deposited on the rear contact layer. It will be appreciated by those skilled in that art that when making LEDs, mirrors may also be buried in the bonding layer 8 .
  • the useful layer 6 and the seed layer 5 may be transferred onto the final supporting substrate 7 with or without the bonding layer 8 prior to removing the seed layer 5 .
  • atomic species may be implanted in the same way as previously discussed—at a determined depth of a donor substrate 1 —in order to form a weakened area 2 .
  • the donor substrate 1 in step 100 may then be adhered on a receiving substrate 3 by any appropriate means.
  • a seed layer 5 may be detached from the donor substrate 1 at the weakened area 2 .
  • a useful layer 6 may be deposited on the surface of the seed layer 5 . Detachment of the seed layer 5 and the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses and chemical etching, or a combination of at least two of these operations.
  • the seed layer 5 may originate from the thinning of the donor substrate (for example according to a BESOI type method) before depositing the useful layer 6 .
  • the final supporting substrate 7 may then be transferred onto the useful layer 6 by means of a bonding layer 8 . Stresses may be applied in order detach the structure, which may consist of the seed layer 5 , the useful layer 6 , the bonding layer 8 and the final supporting substrate 7 , from the receiving support 3 at the bonding layer 4 .
  • a receiving substrate 3 ready to be recycled, may be obtained on the one hand and a structure consisting of the seed layer 5 , the useful layer 6 , the bonding layer 8 and the final supporting substrate 7 may be obtained on the other hand.
  • the seed layer 5 may then be removed by any appropriate means in order to obtain the final substrate.
  • the substrates are intended for making solar cells (Example 1) and light-emitting diodes (Example 2). It should be noted, however, that the examples are not intended to be limiting as to the fields of application of the invention.
  • a weakened area 2 may be made by implanting atomic species at a determined depth in the donor substrate 1 which may be made of, for example, germanium (Ge).
  • the receiving substrate 3 which may also be made of Ge, may be bonded to the donor substrate 1 by means of a bonding layer 4 .
  • the bonding layer 4 preferably made of nitride or oxide, may be formed on the face of at least one of the donor 1 or receiving 3 substrates.
  • a seed layer 5 of Ge may be detached from the donor substrate 1 at the weakened area 2 using the SMART-CUT® method as described herein.
  • the seed layer 5 of Ge may have a thermal expansion coefficient (which is also noted as CTE) which varies from 4.6 to 6.67 10 ⁇ 6 for temperatures ranging from 25° C. to 600° C.
  • Detachment of the seed layer 5 and the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses and chemical etching, or a combination of at least two of these operations.
  • a useful gallium arsenide layer 6 may then be deposited on the surface of the seed layer 5 .
  • the CTE of AsGa may be from 5.00 to 7.4 10 ⁇ 6 for temperatures ranging from 25° C. to 600° C.
  • Different layers such as, for example, InP, AsGa, GaInP, InGaAs, InGaAlP, or InGaAsN epitaxied layers, may be successively deposited by epitaxy on the deposit of the AsGa layer in order to form an epitaxial stack for making junctions (e.g., triple junctions, quadruple junctions, etc.).
  • the useful layer 6 may have a crystalline quality at least equal to the crystalline quality which may be obtained by epitaxy on a massive Ge substrate.
  • the useful layer 6 and the seed layer 5 may then be transferred onto a final supporting substrate 7 .
  • the final support 7 may also be contacted with the epitaxial stack if the latter is made beforehand.
  • the final support 7 may be made of a material such as, for example, semi-conductors (e.g., silicon, germanium), plastic materials and glasses. Transfer of the useful layer 6 and the seed layer 5 onto the final supporting substrate 7 may be performed by bonding.
  • the bond may be performed using a bonding layer 8 made of, for example, insulating layers (e.g., SiO 2 , Si 3 N 4 , etc.), organic layers (e.g., polyimides), metal layers (e.g., palladium silicide Pd 2 Si and tungsten silicide WSi 2 ), and seals (e.g., SiAu, PdIn, etc.)
  • insulating layers e.g., SiO 2 , Si 3 N 4 , etc.
  • organic layers e.g., polyimides
  • metal layers e.g., palladium silicide Pd 2 Si and tungsten silicide WSi 2
  • seals e.g., SiAu, PdIn, etc.
  • the final supporting substrate 7 , the seed layer 5 and the useful layer 6 may then be detached by any appropriate means, for example, at the bonding layer 4 from the receiving support 3 .
  • the receiving support 3 may thereafter be recycled advantageously. This detachment may be obtained by applying stresses at the bonding interface such as, for example, mechanical stresses, thermal stresses, electrostatic stresses and stresses from laser irradiation. Thereafter, the seed layer may be removed in order to obtain the final substrate

Abstract

A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support.

Description

    FIELD OF THE INVENTION
  • The present invention relates to methods for making substrates and substrates for use in optics, electronics or opto-electronics and, in particular, substrates which may be used for making solar cells, light-emitting diodes and lasers.
    • BACKGROUND OF THE INVENTION
  • In the field of substrates for optics, electronics or opto-electronics, two main types of methods are well known for forming a thin layer on a supporting substrate. According to a first type of method, a thin layer taken from a donor substrate is transferred onto a receiving supporting substrate to obtain substrates including a thin useful layer. Useful layer is the layer of the substrate on which electronic components such as, for example, light-emitting diodes or other components may be made.
  • According to second type of method, the thin layer is deposited on a receiving supporting substrate by a deposition technique. This deposition technique may notably consist of epitaxy or chemical vapor deposition. Regardless of the type of method used for forming a useful layer on a receiving supporting substrate, in some instances it is necessary to remove at least one portion of the receiving support to obtain a final substrate including at least the useful layer. Such removal of the receiving support results in loss of materials, thereby putting a strain on the manufacturing costs of such substrates.
  • In order to find a remedy to this drawback, a method for making substrates has been devised which includes a useful thin layer method in which the receiving supporting substrate is removed in order to be recycled. Such a method is described in an alternative embodiment of U.S. Pat. No. 6,794,276, which describes a method for making substrates. This method includes a step for transferring a seed layer on a receiving support by molecular adhesion at a bonding interface, a step for epitaxy of a useful layer on the seed layer and a step for applying stresses in order to lead to removal of the assembly (i.e., removal of the seed layer and of the useful layer from the receiving support at the bonding interface). Seed layer is the material layer which allows development of the epitaxied useful layer.
  • In U.S. Pat. No. 6,794,276, certain specifications are required for allowing the seed layer to adapt to thermal expansions of the receiving support and the useful layer during heat treatments to which the substrate is subject. For this purpose, it is recommended that the seed layer has sufficiently small thickness, of the order of 0.5 microns, and preferably less than 1,000 Å. U.S. Pat. No. 6,794,276 also mentions the fact that the receiving support consists of a material for which the thermal expansion coefficient is 0.7 to 3 times larger than that of the useful layer. It is specified that the thermal expansion coefficient is the proportionality coefficient of the change in the length of a solid as a function of the initial length of the solid and of its change in temperature according to the following formula:

  • ΔL=αL 0 ΔT where α=thermal expansion coefficient
  • In an alternative embodiment, the method taught by U.S. Pat. No. 6,794,276 allows the receiving supporting substrate to be reused after its removal.
  • It is desirable to improve the method taught by U.S. Pat. No. 6,794,276. In particular, improvements are needed for reducing the risk of breaking the substrate, deteriorating, cracking the seed layer or the occurrence of a residual deflection of the final substrate making it unusable during the various heat treatments applied to the substrate. These improvements are now provided by the present invention.
    • SUMMARY OF THE INVENTION
  • The invention relates to a method for making substrates for optics, electronics, or opto-electronics which includes providing a donor substrate and a receiving substrate, wherein the receiving substrate has a thermal expansion coefficient; operably connecting the donor substrate to the receiving substrate; forming a seed layer on the receiving substrate, wherein the seed layer has a surface and a thermal expansion coefficient; and epitaxy of a useful layer on the seed layer, wherein the useful layer has a thermal expansion coefficient. Advantageously, the thermal expansion coefficient of the receiving substrate is equal to or greater than the thermal expansion coefficient of the useful layer, and the thermal expansion coefficient of the seed layer is about the same as the thermal expansion coefficient of the receiving substrate so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
  • In another embodiment, the method for making substrates includes providing a donor substrate and a receiving support; forming a seed layer from the donor substrate; transferring the seed layer onto the receiving support; and forming a useful layer on the seed layer. Again, the thermal expansion coefficient of the receiving support is equal to or greater than the thermal expansion coefficient of the useful layer, and the thermal expansion coefficient of the seed layer is about equal to the thermal expansion coefficient of the receiving support so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
  • Thus, during subsequent heat treatments which the structure will undergo, the seed layer and the receiving support may substantially expand in the same way. The receiving support may expand slightly less than the seed layer so that the seed layer may be placed under slight compression avoiding any deterioration of the seed layer.
  • In a preferred embodiment, the seed layer may consist of a material for which the thermal expansion coefficient is equal to (1+ε) times that of the receiving support, with ε of the order of 0.2, and preferably ε equals 0.1. Further, the useful layer may consist of a material for which the thermal expansion coefficient may be larger than or equal to (1±ε′) times that of the receiving support, with a typical value of 0.2 for ε′. The seed layer and/or the receiving support may be made of, for example, silicon, germanium, silicon carbide, GaN or sapphire. Moreover, the chemical composition of the seed layer, advantageously, may be identical to that of the receiving support.
  • A composite substrate may be created using the method described herein. The composite substrate may be used for optics, electronics, or opto-electronics, The substrate may have at least one seed layer on a receiving support, and an epitaxied useful layer on the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer, and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support so that the seed layer and the receiving support-expand in substantially the same way to avoid stressing or deforming the seed layer.
  • Other advantages and features will become better apparent from the description which follows of several alternative embodiments, given as non-limiting examples, of the method for making substrates according to the invention as well as of the substrate obtained by the method.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be better understood by reference to the following drawings, wherein like references numerals represent like elements. The drawings are merely exemplary to illustrate certain features that may be used singularly or in combination with other features and the present invention should not be limited to the embodiments shown.
  • FIG. 1 is a schematic illustration of the steps of an exemplary embodiment of a method for making a substrate; and
  • FIG. 2 is a schematic illustration of the steps of an alternative exemplary embodiment of a method for making a substrate.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • With reference to FIG. 1, the method according to the invention includes a step for implanting atomic species at a determined depth in a donor substrate 1 in order to form a weakened area 2. In step 100, the donor substrate may be boned upon or otherwise adhered onto a receiving substrate 3 by any appropriate means known in the art.
  • As referred to below, bonding may mean intimate contact of the donor substrate 1 with the receiving substrate 3 in order to join the donor substrate 1 and the receiving substrate 3 by molecular adhesion. Bonding may be obtained according to various methods such as, for example, (1) having a surface of the donor substrate 1 come into direct contact with a surface of the receiving substrate; (2) forming a bonding layer in order to make a connecting layer on the surface of the donor substrate 1, forming a bonding layer in order to make a second connecting layer on the surface of the receiving supporting substrate 3 and having the surfaces of the respective connecting layers of the donor substrate 1 and the donor substrate 3 come into contact with each other; and (3) forming a bonding layer on only one of both substrates.
  • In one embodiment, the bonding layer may consist of, for example, an insulating layer or a dielectric layer. In such an embodiment, the donor substrate 1 may be bonded onto the receiving substrate 3 by means of a bonding layer 4 deposited on the surface of the donor substrate and/or the receiving substrate 3. In addition, an annealing step may be applied at this stage for strengthening the bonding interface between the bonding layer 4 and the surface of the donor substrate 1 and/or the receiving substrate 3. Nonetheless, bonding may be achieved according to any of the methods known to one skilled in the art.
  • In step 200, a seed layer 5 may be detached from the donor substrate 1 at the weakened area 2. Thereafter, in step 300 a useful layer 6 may be deposited on the surface of the seed layer 5. In one preferred embodiment, the useful layer 6 may be obtained by epitaxy, which is well known to one skilled in the art, according to step 300. The step 200 for implanting atomic species and for detaching the seed layer 5 corresponds to a SMART-CUT® method, a general description of which is found in the publication Silicon-On-Insulator Technology: Materials to VLSI, 2nd Edition of Jean-Pierre Colinge, Kluwer Academic Publishers, p. 50 and 51. Those skilled in the art will appreciate that detachment of the seed layer 5 and of the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses, chemical etching, or a combination of at least two of these operations.
  • The seed layer 5 may consist of a material for which the thermal expansion coefficient is equal to (1+ε) times that of the receiving support 3, with ε of the order of 0.2, and preferably ε equals 0.1. It will however be observed that thermal expansion may vary with temperature, with the deposition technique, with the defects present inside the layers and also with the measurement techniques. Thus, when the structure is undergoing heat treatments (e.g., during detachment of the seed layer 5 and the useful layer 6 of the receiving substrate 3) the seed layer 5 and the receiving support 3 will substantially expand in the same way. The receiving support 3 will expand slightly less than the seed layer 5 so that the latter may be placed under slight compression, thereby avoiding deterioration of the seed layer 5.
  • The useful layer 6 may consist of a material which has a thermal expansion coefficient which is larger than or equal to (1±ε′) times that of the receiving support 3, with the value of ε′ between 0 and 0.8 and, preferably, between 0.2 and 0.3. Expansions of the different layers 5, 6 and the receiving support 3 of the same order of magnitude during heat treatments may be obtained because of the closeness of the thermal expansion coefficients of the useful layer 6, the seed layer 5 and the receiving support 3. In this way, any risk of deterioration of the substrate or occurrence of a residual deflection of the final substrate may be avoided.
  • The seed layer 5 and/or the receiving support 3 may comprise a material such as, for example, silicon (e.g., {111} silicon), germanium, polycrystalline or monocrystalline silicon carbide, GaN, polycrystalline or monocrystalline AlN, and sapphire. Further, the chemical composition of the seed layer 5 may be identical with that of the receiving support 3.
  • Between the steps for detaching 200 and for depositing 300 the useful layer, the method may also include steps for preparing the surface of the seed layer 5. These preparation steps may include, for example, polishing, annealing, smooth annealing operations (e.g., under hydrogen), annealing operations for strengthening the bond, sacrificial oxidization interface operations (i.e., for oxidizing and then removing the oxidized material), etching operations, etc.
  • Step 400 may lead to detachment at the bonding layer 4 of the assembly, consisting of the seed layer 5 and the useful layer 6, from the receiving support 3. If a self-supported substrate is desired, the assembly formed by the seed layer 5 and the useful layer 6 may only be able to be detached from the receiving support 3 if the thickness of the assembly is greater than or equal to 50 μm.
  • In order to perform the detachment, different techniques may be used. For example, detachment may be accomplished by application of mechanical, thermal, electrostatic stresses; application of any type of etching (wet, dry, gas, etching, plasma etching, etc.) and/or application of any type of etching by irradiation such as laser irradiation (e.g., by chemical etchings at the bonding layer 4), or the like. The receiving substrate 3, which may either be destroyed or recycled in order to reuse it during the making of a new substrate, may then be obtained on the one hand, and a structure consisting of the seed layer 5 and the useful layer 6 may be obtained on the other hand. It will be appreciated that for performing the detachment of the assembly (consisting of the seed layer 5 and the useful layer 6) from the receiving support 3 at the bonding layer 4, chemical etching may advantageously be used if the receiving substrate 3 is intended to be destroyed. On the other hand, if the receiving substrate 3 is intended to be recycled for reuse, mechanical stress or chemical etching of the bonding layer 4 may preferably be used, which provides full detachment of substrate 3. The seed layer may then be removed by any appropriate means known to those skilled in the art.
  • Thereafter, the useful layer 6 may be transferred onto a final supporting substrate 7. The final support 7 may be made of a material such as, for example, semi-conducting or semi-conductive materials (e.g., silicon, germanium, etc.), metals (e.g., copper), plastic materials and glasses. Since the resultant structure no longer undergoes any heat treatment, the final supporting substrate 7 may be made with any material which has a thermal expansion coefficient and/or a lattice parameter different from those of the useful layer 6.
  • In a preferred embodiment, the useful layer 6 may be transferred onto the final supporting substrate 7 by bonding. The bond may be obtained by applying a bonding layer 8 on one of the surfaces of the useful layer 6 and/or the final supporting substrate 7. Similar to selecting the final substrate 7, the bonding techniques applied in this step are not limited by temperature resistance, contaminations, the thermal expansion coefficient and/or the lattice parameter of the useful layer 6.
  • The layer 8 used may comprise, for example, organic layers (e.g., insulating layers of the SiO2, Si3N4, or polyimides), conductive metal interfaces and seals (e.g., palladium silicide Pd2Si, tungsten silicide WSi2, SiAu, or PdIn). The conductive interfaces may then provide the contact on the rear face of the layer.
  • Moreover, structures may be buried in this bonding layer 8 so that a rear junction contact of a triple junction may thereby be made for producing solar cells. In one embodiment, the buried structure may consist of a triple junction based on amorphous silicon of the n-i-p type. This buried structure may have a lower layer (i.e., a rear contact layer) consisting of metallization, such as silver (Ag) or aluminium (Al), on which a conducting transparent oxide may be deposited. The rear contact layer, on the one hand, may provide an electrical contact with which the triple junction solar cell may be connected and a rear mirror, on the other hand, allowing reflection of light which has not been absorbed by the solar cell. The latter may consist of three amorphous silicon layers (of type n, i and p, respectively) successively deposited on the rear contact layer. It will be appreciated by those skilled in that art that when making LEDs, mirrors may also be buried in the bonding layer 8.
  • In an alternative embodiment (not illustrated in FIG. 1), the useful layer 6 and the seed layer 5 may be transferred onto the final supporting substrate 7 with or without the bonding layer 8 prior to removing the seed layer 5.
  • Referring now to FIG. 2, atomic species may be implanted in the same way as previously discussed—at a determined depth of a donor substrate 1—in order to form a weakened area 2. The donor substrate 1 in step 100 may then be adhered on a receiving substrate 3 by any appropriate means. In step 200, a seed layer 5 may be detached from the donor substrate 1 at the weakened area 2. Thereafter, in step 300, a useful layer 6 may be deposited on the surface of the seed layer 5. Detachment of the seed layer 5 and the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses and chemical etching, or a combination of at least two of these operations.
  • In another alternative embodiment, the seed layer 5 may originate from the thinning of the donor substrate (for example according to a BESOI type method) before depositing the useful layer 6. The final supporting substrate 7 may then be transferred onto the useful layer 6 by means of a bonding layer 8. Stresses may be applied in order detach the structure, which may consist of the seed layer 5, the useful layer 6, the bonding layer 8 and the final supporting substrate 7, from the receiving support 3 at the bonding layer 4. A receiving substrate 3, ready to be recycled, may be obtained on the one hand and a structure consisting of the seed layer 5, the useful layer 6, the bonding layer 8 and the final supporting substrate 7 may be obtained on the other hand. The seed layer 5 may then be removed by any appropriate means in order to obtain the final substrate.
    • EXAMPLES
  • Two particular but non-limiting exemplary embodiments of a resultant substrate will be described hereafter with reference to FIG. 2. The substrates are intended for making solar cells (Example 1) and light-emitting diodes (Example 2). It should be noted, however, that the examples are not intended to be limiting as to the fields of application of the invention.
    • Example 1
  • According to this example, a weakened area 2 may be made by implanting atomic species at a determined depth in the donor substrate 1 which may be made of, for example, germanium (Ge). The receiving substrate 3, which may also be made of Ge, may be bonded to the donor substrate 1 by means of a bonding layer 4. The bonding layer 4, preferably made of nitride or oxide, may be formed on the face of at least one of the donor 1 or receiving 3 substrates.
  • As shown in step 200, a seed layer 5 of Ge may be detached from the donor substrate 1 at the weakened area 2 using the SMART-CUT® method as described herein. The seed layer 5 of Ge may have a thermal expansion coefficient (which is also noted as CTE) which varies from 4.6 to 6.67 10−6 for temperatures ranging from 25° C. to 600° C. Detachment of the seed layer 5 and the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses and chemical etching, or a combination of at least two of these operations.
  • As illustrated in step 300, a useful gallium arsenide layer 6 may then be deposited on the surface of the seed layer 5. The CTE of AsGa may be from 5.00 to 7.4 10−6 for temperatures ranging from 25° C. to 600° C. Different layers, such as, for example, InP, AsGa, GaInP, InGaAs, InGaAlP, or InGaAsN epitaxied layers, may be successively deposited by epitaxy on the deposit of the AsGa layer in order to form an epitaxial stack for making junctions (e.g., triple junctions, quadruple junctions, etc.). It will be appreciated that the useful layer 6 may have a crystalline quality at least equal to the crystalline quality which may be obtained by epitaxy on a massive Ge substrate.
  • The useful layer 6 and the seed layer 5 may then be transferred onto a final supporting substrate 7. It will be noted that the final support 7 may also be contacted with the epitaxial stack if the latter is made beforehand. The final support 7 may be made of a material such as, for example, semi-conductors (e.g., silicon, germanium), plastic materials and glasses. Transfer of the useful layer 6 and the seed layer 5 onto the final supporting substrate 7 may be performed by bonding. The bond may be performed using a bonding layer 8 made of, for example, insulating layers (e.g., SiO2, Si3N4, etc.), organic layers (e.g., polyimides), metal layers (e.g., palladium silicide Pd2Si and tungsten silicide WSi2), and seals (e.g., SiAu, PdIn, etc.)
  • The final supporting substrate 7, the seed layer 5 and the useful layer 6 may then be detached by any appropriate means, for example, at the bonding layer 4 from the receiving support 3. The receiving support 3 may thereafter be recycled advantageously. This detachment may be obtained by applying stresses at the bonding interface such as, for example, mechanical stresses, thermal stresses, electrostatic stresses and stresses from laser irradiation. Thereafter, the seed layer may be removed in order to obtain the final substrate
  • While the foregoing description and drawings represent the preferred embodiments of the present invention, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined in the accompanying claims. In particular, it will be clear to those skilled in the art that the present invention may be embodied in other specific forms, structures, arrangements, proportions, and with other elements, materials, and components, without departing from the spirit or essential characteristics thereof. One skilled in the art will appreciate that the invention may be used with many modifications of structure, arrangement, proportions, materials, and components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims, and not limited to the foregoing description.

Claims (30)

1. A method for making substrates comprising:
providing a donor substrate and a receiving substrate, wherein the receiving substrate has a thermal expansion coefficient;
operably connecting the donor substrate to the receiving substrate;
forming a seed layer on the receiving substrate, wherein the seed layer has a surface and a thermal expansion coefficient; and
epitaxy of a useful layer on the seed layer, wherein the useful layer has a thermal expansion coefficient;
wherein the thermal expansion coefficient of the receiving substrate is equal to or greater than the thermal expansion coefficient of the useful layer, and
wherein the thermal expansion coefficient of the seed layer is about the same as the thermal expansion coefficient of the receiving substrate so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
2. The method of claim 1 wherein the seed layer forms a surface portion of the donor substrate, the method further comprising forming a weakened area in the donor substrate beneath the seed layer and detaching the donor substrate from the seed layer at the weakened area so that the seed layer remains operably connected to the receiving substrate.
3. The method of claim 2, wherein the step of forming a weakened area comprises implanting atomic species into the donor substrate.
4. The method of claim 1, wherein the step of operably connecting the donor substrate to the receiving substrate includes forming a bonding layer between the seed layer and the receiving substrate.
5. The method of claim 4 further comprising preparing the surface of the seed layer, wherein the preparation step is selected from at least one of the group consisting of polishing, annealing, sacrificial oxidation interface operations and etching.
6. The method of claim 4 further comprising providing a supporting substrate of a material selected from the group consisting of a semi-conductor, metal, plastic and glass, and operably connecting the useful layer to the supporting substrate.
7. The method of claim 6 further comprising detaching the seed layer, the useful layer and the supporting substrate from the receiving substrate and subsequently removing the seed layer from the useful layer and the supporting substrate.
8. The method of claim 7 wherein the step of detaching comprises performing at least one of the operations selected from the groups consisting of heat treatment, application of stresses, irradiation and etching.
9. The method of claim 6, wherein the step of operably connecting the useful layer to the supporting substrate comprises forming a bonding layer between the useful layer and the supporting substrate, wherein the bonding layer is selected from the group consisting of insulating layers, organic layers, metal interfaces and seals.
10. The method of claim 10 further comprising burying a structure in the second bonding layer.
11. The method of claim 1 further comprising forming the seed layer from a material for which the thermal expansion coefficient is (1+ε) times the thermal expansion coefficient of the receiving substrate, and forming the useful layer from a material for which the thermal expansion coefficient is greater than or equal to (1±ε′) times the thermal expansion coefficient of the receiving substrate.
12. The method of claim 1 which further comprises forming at least one of the seed layer and the receiving substrate from a material selected from the group consisting of silicon, germanium, silicon carbide, GaN, AlN and sapphire, and optionally where the chemical composition of the seed layer and that of the receiving substrate are identical.
13. The method of claim 1 further comprising detaching the seed layer and the useful layer from the receiving substrate by performing at least one of the operations selected from the group consisting of heat treatment, application of mechanical, thermal or electrostatic stresses, irradiation and etching.
14. The method of claim 22 further comprising performing an operation selected from the group consisting of dry, wet, gas, chemical and plasma etching or irradiation using a laser.
15. The method of claim 1 further comprising removing the seed layer from the useful layer.
16. The method of claim 1 further comprising reusing the receiving substrate to make another substrate.
17. The method of claim 1, wherein the step of forming the seed layer comprises thinning the donor substrate after bringing the donor substrate into contact with the receiving substrate.
18. A method for making substrates comprising:
providing a donor substrate and a receiving support;
forming a seed layer from the donor substrate;
transferring the seed layer onto the receiving support;
forming a useful layer on the seed layer;
wherein the thermal expansion coefficient of the receiving support is equal to or greater than the thermal expansion coefficient of the useful layer, and
wherein the thermal expansion coefficient of the seed layer is about equal to the thermal expansion coefficient of the receiving support.
19. The method of claim 18 wherein forming the seed layer comprises inserting atomic species into the donor substrate and forming a weakened area beneath the seed layer.
20. The method of claim 18 wherein forming a useful layer comprises epitaxy of the useful layer on the seed layer.
21. The method of claim 18 wherein transferring the seed layer to the receiving support comprises bonding the donor substrate to the receiving support and detaching the seed layer and the useful layer from the receiving support.
22. The method of claim 21 further comprising removing the seed layer from the useful layer and transferring the useful layer onto a supporting substrate.
23. A substrate comprising:
a receiving support having a thermal expansion coefficient;
a seed layer having a thermal expansion coefficient, wherein the seed layer is operably connected to the receiving support; and
a useful layer having a thermal expansion coefficient, the useful layer being operably connected to the seed layer;
wherein the thermal expansion coefficient of the receiving support is greater than or equal to the thermal expansion coefficient of the useful layer, and
wherein the thermal expansion coefficient of the seed layer is about equal to the thermal expansion coefficient of the receiving support so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
24. The substrate of claim 23, wherein the seed layer is made of a material for which the thermal expansion coefficient is equal to (1+ε) times the thermal expansion coefficient of the receiving support.
25. The substrate of claim 23 wherein the useful layer is made of a material for which the thermal expansion coefficient is greater than or equal to (1±ε′) times the thermal expansion coefficient of the receiving support.
26. The substrate of claim 23, wherein the at least one of the seed layer and the receiving support is made of a material selected from the group consisting of silicon, germanium, silicon carbide, GaN, AlN and sapphire and optionally where the chemical composition of the seed layer and that of the receiving substrate are identical.
27. The substrate of claim 23 further comprising a supporting substrate comprising a material selected from the group consisting of semiconductors, plastic, glass and metal, and optionally including a bonding layer connecting the supporting substrate and the useful layer.
28. The substrate of claim 27 further comprising a structure buried in the bonding layer.
29. The substrate of claim 23 further comprising a bonding layer connecting the seed layer and the receiving support, wherein the bonding layer is comprised of a material selected from the group consisting of insulating layers, organic layers, metal interfaces and sealing layers.
30. The substrate of claim 23, wherein the seed layer and the useful layer has a thickness of at least 50 μm.
US11/505,668 2000-11-27 2006-08-16 Methods for making substrates and substrates formed therefrom Abandoned US20070141803A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
PCT/EP2006/070109 WO2007071772A1 (en) 2005-12-21 2006-12-21 Method for the manufacture of substrates, in particular for the optical, electronic or optoelectronic areas, and the substrate obtained in accordance with the said method
CN2006800478498A CN101341580B (en) 2005-12-21 2006-12-21 Method for the manufacture of substrates, in particular for the optical, electronic or optoelectronic areas, and the substrate obtained in accordance with the said method
KR1020087014900A KR20080078679A (en) 2005-12-21 2006-12-21 Method for the manufacture of substrates, in particular for the optical, electronic or optoelectronic areas, and the substrate obtained in accordance with the said method
EP06841567A EP1979933A1 (en) 2005-12-21 2006-12-21 Method for the manufacture of substrates, in particular for the optical, electronic or optoelectronic areas, and the substrate obtained in accordance with the said method
TW095148275A TWI324357B (en) 2005-12-21 2006-12-21 Method for the manufacture of substrates, in particular for the optical, electronic or optoelectronic areas, and the substrate obtained in accordance with the said method
US11/840,696 US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US12/536,082 US7839001B2 (en) 2000-11-27 2009-08-05 Methods for making substrates and substrates formed therefrom
US12/914,194 US7939428B2 (en) 2000-11-27 2010-10-28 Methods for making substrates and substrates formed therefrom

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0513045A FR2894990B1 (en) 2005-12-21 2005-12-21 PROCESS FOR PRODUCING SUBSTRATES, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED BY SAID PROCESS
FR05/13045 2005-12-21

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/883,437 Continuation-In-Part US7265029B2 (en) 2000-11-27 2004-07-01 Fabrication of substrates with a useful layer of monocrystalline semiconductor material

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/840,696 Continuation-In-Part US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US11/840,696 Continuation US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom

Publications (1)

Publication Number Publication Date
US20070141803A1 true US20070141803A1 (en) 2007-06-21

Family

ID=36648762

Family Applications (4)

Application Number Title Priority Date Filing Date
US11/505,668 Abandoned US20070141803A1 (en) 2000-11-27 2006-08-16 Methods for making substrates and substrates formed therefrom
US11/840,696 Expired - Lifetime US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US12/536,082 Expired - Lifetime US7839001B2 (en) 2000-11-27 2009-08-05 Methods for making substrates and substrates formed therefrom
US12/914,194 Active US7939428B2 (en) 2000-11-27 2010-10-28 Methods for making substrates and substrates formed therefrom

Family Applications After (3)

Application Number Title Priority Date Filing Date
US11/840,696 Expired - Lifetime US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US12/536,082 Expired - Lifetime US7839001B2 (en) 2000-11-27 2009-08-05 Methods for making substrates and substrates formed therefrom
US12/914,194 Active US7939428B2 (en) 2000-11-27 2010-10-28 Methods for making substrates and substrates formed therefrom

Country Status (7)

Country Link
US (4) US20070141803A1 (en)
EP (1) EP1979933A1 (en)
KR (1) KR20080078679A (en)
CN (1) CN101341580B (en)
FR (1) FR2894990B1 (en)
TW (1) TWI324357B (en)
WO (1) WO2007071772A1 (en)

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080261376A1 (en) * 2007-04-20 2008-10-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
US20080286952A1 (en) * 2007-05-18 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US20090098739A1 (en) * 2007-10-10 2009-04-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US20090111244A1 (en) * 2007-10-10 2009-04-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090117680A1 (en) * 2007-11-01 2009-05-07 Shunpei Yamazaki Method for manufacturing photoelectric conversion device
US20090194163A1 (en) * 2008-02-05 2009-08-06 Twin Creeks Technologies, Inc. Method to form a photovoltaic cell comprising a thin lamina
US20090194153A1 (en) * 2008-02-05 2009-08-06 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having low base resistivity and method of making
US20100032007A1 (en) * 2008-08-10 2010-02-11 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having a rear junction and method of making
US20100032010A1 (en) * 2008-08-10 2010-02-11 Twin Creeks Technologies, Inc. Method to mitigate shunt formation in a photovoltaic cell comprising a thin lamina
US20100031995A1 (en) * 2008-08-10 2010-02-11 Twin Creeks Technologies, Inc. Photovoltaic module comprising thin laminae configured to mitigate efficiency loss due to shunt formation
US20100087047A1 (en) * 2008-10-02 2010-04-08 Akihisa Shimomura Method for manufacturing soi substrate
US20100291756A1 (en) * 2008-01-30 2010-11-18 Siltronic Ag Method for the production of a semiconductor structure
US20100307572A1 (en) * 2009-06-09 2010-12-09 International Business Machines Corporation Heterojunction III-V Photovoltaic Cell Fabrication
US20100330777A1 (en) * 2009-06-24 2010-12-30 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate and method for manufacturing soi substrate
US20100330778A1 (en) * 2009-06-24 2010-12-30 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate and method for manufacturing soi substrate
US20110049588A1 (en) * 2009-08-25 2011-03-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof
US20110053345A1 (en) * 2009-08-25 2011-03-03 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate
US20110065263A1 (en) * 2009-08-25 2011-03-17 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate
US20110086492A1 (en) * 2009-10-09 2011-04-14 Semiconductor Energy Laboratory Co., Ltd. Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
US20110186958A1 (en) * 2010-02-03 2011-08-04 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and manufacturing method thereof
US8324086B2 (en) 2008-01-16 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor substrate by laser irradiation
US20130143336A1 (en) * 2010-09-10 2013-06-06 VerLASE TECHNOLOGIES LLC Methods of Fabricating Optoelectronic Devices Using Layers Detached from Semiconductor Donors and Devices Made Thereby
US8530336B2 (en) 2010-11-12 2013-09-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US8598013B2 (en) 2007-10-10 2013-12-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and semiconductor device
US8823127B2 (en) 2009-06-09 2014-09-02 International Business Machines Corporation Multijunction photovoltaic cell fabrication
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US10002763B2 (en) 2000-11-27 2018-06-19 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US20220393003A1 (en) * 2021-06-08 2022-12-08 Wafer Works Corporation Composite substrate and manufacturing method thereof
CN115863149A (en) * 2022-12-12 2023-03-28 中国科学院上海微系统与信息技术研究所 Preparation method of gallium oxide structure

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008526010A (en) * 2004-12-28 2008-07-17 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ Method for obtaining thin layers with low hole density
US9117966B2 (en) * 2007-09-24 2015-08-25 Solaero Technologies Corp. Inverted metamorphic multijunction solar cell with two metamorphic layers and homojunction top cell
JP2009141093A (en) * 2007-12-06 2009-06-25 Toshiba Corp Light emitting element and method of manufacturing the same
FR2926674B1 (en) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator METHOD FOR MANUFACTURING COMPOSITE STRUCTURE WITH STABLE BONDING OXIDE LAYER
JP5250321B2 (en) * 2008-07-04 2013-07-31 昭和電工株式会社 Method for producing seed crystal for silicon carbide single crystal growth and method for producing silicon carbide single crystal
TWI457984B (en) 2008-08-06 2014-10-21 Soitec Silicon On Insulator Relaxation of strained layers
EP2159836B1 (en) * 2008-08-25 2017-05-31 Soitec Stiffening layers for the relaxation of strained layers
FR2942910B1 (en) 2009-03-06 2011-09-30 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A HETEROSTRUCTURE TO REDUCE THE STRAIN STRENGTH OF THE DONOR SUBSTRATE
KR101119009B1 (en) * 2009-03-09 2012-03-14 한국과학기술연구원 Method of forming light emitting device with separation by ion implantation
FR2943174B1 (en) * 2009-03-12 2011-04-15 Soitec Silicon On Insulator ADAPTATION OF THE MESH PARAMETER OF A LAYER OF CONTAMINATED MATERIAL
US8633097B2 (en) * 2009-06-09 2014-01-21 International Business Machines Corporation Single-junction photovoltaic cell
US8580593B2 (en) 2009-09-10 2013-11-12 Micron Technology, Inc. Epitaxial formation structures and associated methods of manufacturing solid state lighting devices
US9012253B2 (en) * 2009-12-16 2015-04-21 Micron Technology, Inc. Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods
US8647962B2 (en) * 2010-03-23 2014-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging bond
FR2961948B1 (en) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator PROCESS FOR TREATING A COMPOUND MATERIAL PART
SG177816A1 (en) * 2010-07-15 2012-02-28 Soitec Silicon On Insulator Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
US8629426B2 (en) * 2010-12-03 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain stressor having enhanced carrier mobility manufacturing same
JP5696543B2 (en) * 2011-03-17 2015-04-08 セイコーエプソン株式会社 Manufacturing method of semiconductor substrate
JP2012230969A (en) * 2011-04-25 2012-11-22 Sumitomo Electric Ind Ltd GaN-BASED SEMICONDUCTOR DEVICE MANUFACTURING METHOD
FR2977069B1 (en) 2011-06-23 2014-02-07 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE USING TEMPORARY COLLAGE
RU2469433C1 (en) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Method for laser separation of epitaxial film or layer of epitaxial film from growth substrate of epitaxial semiconductor structure (versions)
KR101847941B1 (en) * 2012-02-08 2018-04-11 삼성전자주식회사 Semiconductor light emitting device and manufacturing method of the same
US9496279B2 (en) * 2012-02-29 2016-11-15 Kyocera Corporation Composite substrate
US9105561B2 (en) * 2012-05-14 2015-08-11 The Boeing Company Layered bonded structures formed from reactive bonding of zinc metal and zinc peroxide
FR3007891B1 (en) * 2013-06-28 2016-11-25 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A COMPOSITE STRUCTURE
WO2016205751A1 (en) * 2015-06-19 2016-12-22 QMAT, Inc. Bond and release layer transfer process
US9444019B1 (en) * 2015-09-21 2016-09-13 Epistar Corporation Method for reusing a substrate for making light-emitting device
CN106783998A (en) * 2016-12-16 2017-05-31 中国电子科技集团公司第五十五研究所 A kind of GaN high electron mobility transistor based on diamond substrate and preparation method thereof
CN110349843B (en) * 2019-07-26 2021-12-21 京东方科技集团股份有限公司 Thin film transistor, preparation method thereof, biological recognition device and display device
CN110600435A (en) * 2019-09-05 2019-12-20 方天琦 Multilayer composite substrate structure and preparation method thereof

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229305A (en) * 1992-02-03 1993-07-20 Motorola, Inc. Method for making intrinsic gettering sites in bonded substrates
US5374564A (en) * 1991-09-18 1994-12-20 Commissariat A L'energie Atomique Process for the production of thin semiconductor material films
US5759908A (en) * 1995-05-16 1998-06-02 University Of Cincinnati Method for forming SiC-SOI structures
US5869387A (en) * 1992-01-30 1999-02-09 Canon Kabushiki Kaisha Process for producing semiconductor substrate by heating to flatten an unpolished surface
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US5880491A (en) * 1997-01-31 1999-03-09 The United States Of America As Represented By The Secretary Of The Air Force SiC/111-V-nitride heterostructures on SiC/SiO2 /Si for optoelectronic devices
US5953662A (en) * 1996-04-30 1999-09-14 Ericsson, Inc. Dual home location registers in a mobile radio system
US5985687A (en) * 1996-04-12 1999-11-16 The Regents Of The University Of California Method for making cleaved facets for lasers fabricated with gallium nitride and other noncubic materials
US6020252A (en) * 1996-05-15 2000-02-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US6103597A (en) * 1996-04-11 2000-08-15 Commissariat A L'energie Atomique Method of obtaining a thin film of semiconductor material
US6114188A (en) * 1996-04-12 2000-09-05 Northeastern University Method of fabricating an integrated complex-transition metal oxide device
US6190998B1 (en) * 1996-05-15 2001-02-20 Commissariat A L'energie Atomique Method for achieving a thin film of solid material and applications of this method
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US6303468B1 (en) * 1997-08-12 2001-10-16 Commissariat A L'energie Atomique Method for making a thin film of solid material
US6328796B1 (en) * 1999-02-01 2001-12-11 The United States Of America As Represented By The Secretary Of The Navy Single-crystal material on non-single-crystalline substrate
US6426270B1 (en) * 1999-02-02 2002-07-30 Canon Kabushiki Kaisha Substrate processing method and method of manufacturing semiconductor substrate
US6534382B1 (en) * 1996-12-18 2003-03-18 Canon Kabushiki Kaisha Process for producing semiconductor article
US20030143772A1 (en) * 2002-01-30 2003-07-31 United Epitaxy Co., Ltd. High efficiency light emitting diode and method of making the same
US20030219959A1 (en) * 2000-11-27 2003-11-27 Bruno Ghyselen Methods for fabricating final substrates
US20030232487A1 (en) * 2002-06-11 2003-12-18 Fabrice Letertre Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US20040029359A1 (en) * 2000-11-27 2004-02-12 Fabrice Letertre Methods for fabricating a substrate
US6756286B1 (en) * 1997-12-30 2004-06-29 Commissariat A L'energie Atomique Method for transferring a thin film comprising a step of generating inclusions
US20040219959A1 (en) * 2003-05-01 2004-11-04 Ali Khayrallah Multiple antenna receiver
US6946317B2 (en) * 2003-05-27 2005-09-20 S.O.I.Tec Silicon On Insulator Technologies S.A. Method of fabricating heteroepitaxial microstructures
US7029993B1 (en) * 1999-08-20 2006-04-18 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for treating substrates for microelectronics and substrates obtained according to said method
US20070072324A1 (en) * 2005-09-27 2007-03-29 Lumileds Lighting U.S., Llc Substrate for growing a III-V light emitting device

Family Cites Families (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001864A (en) 1976-01-30 1977-01-04 Gibbons James F Semiconductor p-n junction solar cell and method of manufacture
US4255211A (en) 1979-12-31 1981-03-10 Chevron Research Company Multilayer photovoltaic solar cell with semiconductor layer at shorting junction interface
EP0193830A3 (en) 1980-04-10 1986-10-01 Massachusetts Institute Of Technology Solar cell device incorporating plural constituent solar cells
US4338480A (en) 1980-12-29 1982-07-06 Varian Associates, Inc. Stacked multijunction photovoltaic converters
US4612408A (en) 1984-10-22 1986-09-16 Sera Solar Corporation Electrically isolated semiconductor integrated photodiode circuits and method
IL79735A0 (en) 1985-09-09 1986-11-30 Hughes Aircraft Co Thin semiconductor structures
US4686323A (en) 1986-06-30 1987-08-11 The Standard Oil Company Multiple cell, two terminal photovoltaic device employing conductively adhered cells
US5217539A (en) 1991-09-05 1993-06-08 The Boeing Company III-V solar cells and doping processes
US5053083A (en) 1989-05-08 1991-10-01 The Board Of Trustees Of The Leland Stanford Junior University Bilevel contact solar cells
US5322572A (en) 1989-11-03 1994-06-21 The United States Of America As Represented By The United States Department Of Energy Monolithic tandem solar cell
US5019177A (en) 1989-11-03 1991-05-28 The United States Of America As Represented By The United States Department Of Energy Monolithic tandem solar cell
FR2690278A1 (en) 1992-04-15 1993-10-22 Picogiga Sa Multispectral photovoltaic component with cell stack, and production method.
FR2690279B1 (en) 1992-04-15 1997-10-03 Picogiga Sa MULTISPECTRAL PHOTOVOLTAUIC COMPONENT.
US5342453A (en) 1992-11-13 1994-08-30 Midwest Research Institute Heterojunction solar cell
US5376185A (en) 1993-05-12 1994-12-27 Midwest Research Institute Single-junction solar cells with the optimum band gap for terrestrial concentrator applications
DE69435205D1 (en) 1993-12-14 2009-05-28 Spectrolab Inc Thin semiconductor device and manufacturing method
US5479032A (en) 1994-07-21 1995-12-26 Trustees Of Princeton University Multiwavelength infrared focal plane array detector
SG65697A1 (en) * 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
KR100232886B1 (en) * 1996-11-23 1999-12-01 김영환 Soi wafer fabricating method
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6281426B1 (en) 1997-10-01 2001-08-28 Midwest Research Institute Multi-junction, monolithic solar cell using low-band-gap materials lattice matched to GaAs or Ge
US6482672B1 (en) 1997-11-06 2002-11-19 Essential Research, Inc. Using a critical composition grading technique to deposit InGaAs epitaxial layers on InP substrates
US5944913A (en) 1997-11-26 1999-08-31 Sandia Corporation High-efficiency solar cell and method for fabrication
FR2774214B1 (en) 1998-01-28 2002-02-08 Commissariat Energie Atomique PROCESS FOR PRODUCING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATOR AND IN PARTICULAR SiCOI
US6166318A (en) 1998-03-03 2000-12-26 Interface Studies, Inc. Single absorber layer radiated energy conversion device
FR2777116A1 (en) 1998-04-03 1999-10-01 Picogiga Sa SEMICONDUCTOR STRUCTURE OF PHOTOVOLTAIC COMPONENT
US6300557B1 (en) 1998-10-09 2001-10-09 Midwest Research Institute Low-bandgap double-heterostructure InAsP/GaInAs photovoltaic converters
US6239354B1 (en) 1998-10-09 2001-05-29 Midwest Research Institute Electrical isolation of component cells in monolithically interconnected modules
FR2787919B1 (en) 1998-12-23 2001-03-09 Thomson Csf PROCESS FOR PRODUCING A SUBSTRATE FOR GROWING A NITRIDE COMPOUND
US6881644B2 (en) * 1999-04-21 2005-04-19 Silicon Genesis Corporation Smoothing method for cleaved films made using a release layer
JP3657143B2 (en) 1999-04-27 2005-06-08 シャープ株式会社 Solar cell and manufacturing method thereof
US6252287B1 (en) 1999-05-19 2001-06-26 Sandia Corporation InGaAsN/GaAs heterojunction for multi-junction solar cells
US6340788B1 (en) 1999-12-02 2002-01-22 Hughes Electronics Corporation Multijunction photovoltaic cells and panels using a silicon or silicon-germanium active substrate cell for space and terrestrial applications
FR2816445B1 (en) 2000-11-06 2003-07-25 Commissariat Energie Atomique METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN LAYER ADHERING TO A TARGET SUBSTRATE
FR2840730B1 (en) * 2002-06-11 2005-05-27 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SUBSTRATE COMPRISING A LAYER UTILIZED IN MONOCRYSTALLINE SEMICONDUCTOR MATERIAL WITH IMPROVED PROPERTIES
US6815736B2 (en) 2001-02-09 2004-11-09 Midwest Research Institute Isoelectronic co-doping
US7019339B2 (en) 2001-04-17 2006-03-28 California Institute Of Technology Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby
US20050026432A1 (en) 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US7238622B2 (en) 2001-04-17 2007-07-03 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
FR2837625B1 (en) 2002-03-19 2004-09-17 Commissariat Energie Atomique MULTI-JUNCTION PHOTOVOLTAIC DEVICE WITH INDEPENDENT CELLS WITHOUT SHADING EFFECT AND METHOD FOR PRODUCING SUCH A DEVICE
US6660928B1 (en) 2002-04-02 2003-12-09 Essential Research, Inc. Multi-junction photovoltaic cell
US8067687B2 (en) 2002-05-21 2011-11-29 Alliance For Sustainable Energy, Llc High-efficiency, monolithic, multi-bandgap, tandem photovoltaic energy converters
US20060162768A1 (en) 2002-05-21 2006-07-27 Wanlass Mark W Low bandgap, monolithic, multi-bandgap, optoelectronic devices
US7071407B2 (en) 2002-10-31 2006-07-04 Emcore Corporation Method and apparatus of multiplejunction solar cell structure with high band gap heterojunction middle cell
US6951819B2 (en) 2002-12-05 2005-10-04 Blue Photonics, Inc. High efficiency, monolithic multijunction solar cells containing lattice-mismatched materials and methods of forming same
US7812249B2 (en) 2003-04-14 2010-10-12 The Boeing Company Multijunction photovoltaic cell grown on high-miscut-angle substrate
WO2005015638A1 (en) 2003-07-22 2005-02-17 Akzo Nobel N.V. Process for manufacturing a solar cell foil using a temporary substrate
US20050161078A1 (en) 2004-01-27 2005-07-28 Daniel Aiken Solar cell mechanical interconnection using direct wafer bonding
WO2005104192A2 (en) 2004-04-21 2005-11-03 California Institute Of Technology A METHOD FOR THE FABRICATION OF GaAs/Si AND RELATED WAFER BONDED VIRTUAL SUBSTRATES
WO2006015185A2 (en) 2004-07-30 2006-02-09 Aonex Technologies, Inc. GaInP/GaAs/Si TRIPLE JUNCTION SOLAR CELL ENABLED BY WAFER BONDING AND LAYER TRANSFER
US7846759B2 (en) 2004-10-21 2010-12-07 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
FR2878076B1 (en) 2004-11-17 2007-02-23 St Microelectronics Sa SLIMMING A SEMICONDUCTOR WAFER
US10374120B2 (en) 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
WO2007019277A2 (en) 2005-08-03 2007-02-15 California Institute Of Technology Method of forming semiconductor layers on handle substrates
US11211510B2 (en) 2005-12-13 2021-12-28 The Boeing Company Multijunction solar cell with bonded transparent conductive interlayer
US20070277874A1 (en) 2006-05-31 2007-12-06 David Francis Dawson-Elli Thin film photovoltaic structure
US8536445B2 (en) 2006-06-02 2013-09-17 Emcore Solar Power, Inc. Inverted metamorphic multijunction solar cells
US20080245409A1 (en) 2006-12-27 2008-10-09 Emcore Corporation Inverted Metamorphic Solar Cell Mounted on Flexible Film
US20080185038A1 (en) 2007-02-02 2008-08-07 Emcore Corporation Inverted metamorphic solar cell with via for backside contacts
WO2009005824A1 (en) 2007-07-03 2009-01-08 Microlink Devices, Inc. Thin film iii-v compound solar cell
US8916769B2 (en) 2008-10-01 2014-12-23 International Business Machines Corporation Tandem nanofilm interconnected semiconductor wafer solar cells
CA2744706C (en) 2008-11-26 2015-11-24 Microlink Devices, Inc. Solar cell with a backside via to contact the emitter layer
US7785989B2 (en) 2008-12-17 2010-08-31 Emcore Solar Power, Inc. Growth substrates for inverted metamorphic multijunction solar cells
JP2012516578A (en) 2009-01-28 2012-07-19 マイクロリンク デバイセズ， インク． High-efficiency III-V compound semiconductor solar cell device with oxidation window layer

Patent Citations (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5374564A (en) * 1991-09-18 1994-12-20 Commissariat A L'energie Atomique Process for the production of thin semiconductor material films
US5869387A (en) * 1992-01-30 1999-02-09 Canon Kabushiki Kaisha Process for producing semiconductor substrate by heating to flatten an unpolished surface
US5229305A (en) * 1992-02-03 1993-07-20 Motorola, Inc. Method for making intrinsic gettering sites in bonded substrates
US5759908A (en) * 1995-05-16 1998-06-02 University Of Cincinnati Method for forming SiC-SOI structures
US6103597A (en) * 1996-04-11 2000-08-15 Commissariat A L'energie Atomique Method of obtaining a thin film of semiconductor material
US6114188A (en) * 1996-04-12 2000-09-05 Northeastern University Method of fabricating an integrated complex-transition metal oxide device
US5985687A (en) * 1996-04-12 1999-11-16 The Regents Of The University Of California Method for making cleaved facets for lasers fabricated with gallium nitride and other noncubic materials
US5953662A (en) * 1996-04-30 1999-09-14 Ericsson, Inc. Dual home location registers in a mobile radio system
US6225192B1 (en) * 1996-05-15 2001-05-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US6020252A (en) * 1996-05-15 2000-02-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US6190998B1 (en) * 1996-05-15 2001-02-20 Commissariat A L'energie Atomique Method for achieving a thin film of solid material and applications of this method
US6534382B1 (en) * 1996-12-18 2003-03-18 Canon Kabushiki Kaisha Process for producing semiconductor article
US5880491A (en) * 1997-01-31 1999-03-09 The United States Of America As Represented By The Secretary Of The Air Force SiC/111-V-nitride heterostructures on SiC/SiO2 /Si for optoelectronic devices
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6303468B1 (en) * 1997-08-12 2001-10-16 Commissariat A L'energie Atomique Method for making a thin film of solid material
US6756286B1 (en) * 1997-12-30 2004-06-29 Commissariat A L'energie Atomique Method for transferring a thin film comprising a step of generating inclusions
US6328796B1 (en) * 1999-02-01 2001-12-11 The United States Of America As Represented By The Secretary Of The Navy Single-crystal material on non-single-crystalline substrate
US6426270B1 (en) * 1999-02-02 2002-07-30 Canon Kabushiki Kaisha Substrate processing method and method of manufacturing semiconductor substrate
US7029993B1 (en) * 1999-08-20 2006-04-18 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for treating substrates for microelectronics and substrates obtained according to said method
US6867067B2 (en) * 2000-11-27 2005-03-15 S.O.I. Tec Silicon On Insulator Technologies S.A. Methods for fabricating final substrates
US20040029359A1 (en) * 2000-11-27 2004-02-12 Fabrice Letertre Methods for fabricating a substrate
US20030219959A1 (en) * 2000-11-27 2003-11-27 Bruno Ghyselen Methods for fabricating final substrates
US6794276B2 (en) * 2000-11-27 2004-09-21 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for fabricating a substrate
US20050266626A1 (en) * 2000-11-27 2005-12-01 Bruce Faure Method of fabricating heteroepitaxial microstructures
US20040235268A1 (en) * 2000-11-27 2004-11-25 Fabrice Letertre Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US20050026394A1 (en) * 2000-11-27 2005-02-03 S.O.I.Tec Silicon On Insulator Technologies S.A., Methods for fabricating a substrate
US20030143772A1 (en) * 2002-01-30 2003-07-31 United Epitaxy Co., Ltd. High efficiency light emitting diode and method of making the same
US20030232487A1 (en) * 2002-06-11 2003-12-18 Fabrice Letertre Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US20040219959A1 (en) * 2003-05-01 2004-11-04 Ali Khayrallah Multiple antenna receiver
US6946317B2 (en) * 2003-05-27 2005-09-20 S.O.I.Tec Silicon On Insulator Technologies S.A. Method of fabricating heteroepitaxial microstructures
US20070072324A1 (en) * 2005-09-27 2007-03-29 Lumileds Lighting U.S., Llc Substrate for growing a III-V light emitting device

Cited By (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10002763B2 (en) 2000-11-27 2018-06-19 Soitec Fabrication of substrates with a useful layer of monocrystalline semiconductor material
US8193068B2 (en) 2007-04-20 2012-06-05 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
US20110136320A1 (en) * 2007-04-20 2011-06-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing soi substrate
US7897476B2 (en) * 2007-04-20 2011-03-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
US20080261376A1 (en) * 2007-04-20 2008-10-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
US20110076837A1 (en) * 2007-05-18 2011-03-31 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of soi substrate and manufacturing method of semiconductor device
US7820524B2 (en) * 2007-05-18 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US20080286952A1 (en) * 2007-05-18 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US8895407B2 (en) 2007-05-18 2014-11-25 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US8236668B2 (en) 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US20090111244A1 (en) * 2007-10-10 2009-04-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090098739A1 (en) * 2007-10-10 2009-04-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US8598013B2 (en) 2007-10-10 2013-12-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and semiconductor device
US8772128B2 (en) 2007-10-10 2014-07-08 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090117680A1 (en) * 2007-11-01 2009-05-07 Shunpei Yamazaki Method for manufacturing photoelectric conversion device
US7964429B2 (en) 2007-11-01 2011-06-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing photoelectric conversion device
US8324086B2 (en) 2008-01-16 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor substrate by laser irradiation
US20100291756A1 (en) * 2008-01-30 2010-11-18 Siltronic Ag Method for the production of a semiconductor structure
US8492243B2 (en) * 2008-01-30 2013-07-23 Siltronic Ag Method for the production of a semiconductor structure
US20090194163A1 (en) * 2008-02-05 2009-08-06 Twin Creeks Technologies, Inc. Method to form a photovoltaic cell comprising a thin lamina
US20090194153A1 (en) * 2008-02-05 2009-08-06 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having low base resistivity and method of making
US8129613B2 (en) 2008-02-05 2012-03-06 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having low base resistivity and method of making
US20100032010A1 (en) * 2008-08-10 2010-02-11 Twin Creeks Technologies, Inc. Method to mitigate shunt formation in a photovoltaic cell comprising a thin lamina
US8338209B2 (en) * 2008-08-10 2012-12-25 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having a rear junction and method of making
US20100031995A1 (en) * 2008-08-10 2010-02-11 Twin Creeks Technologies, Inc. Photovoltaic module comprising thin laminae configured to mitigate efficiency loss due to shunt formation
US20100032007A1 (en) * 2008-08-10 2010-02-11 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having a rear junction and method of making
US20100087047A1 (en) * 2008-10-02 2010-04-08 Akihisa Shimomura Method for manufacturing soi substrate
US8871610B2 (en) * 2008-10-02 2014-10-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US20100311250A1 (en) * 2009-06-09 2010-12-09 International Business Machines Corporation Thin substrate fabrication using stress-induced substrate spalling
US8450184B2 (en) * 2009-06-09 2013-05-28 International Business Machines Corporation Thin substrate fabrication using stress-induced spalling
US20100307572A1 (en) * 2009-06-09 2010-12-09 International Business Machines Corporation Heterojunction III-V Photovoltaic Cell Fabrication
US8823127B2 (en) 2009-06-09 2014-09-02 International Business Machines Corporation Multijunction photovoltaic cell fabrication
US8247261B2 (en) * 2009-06-09 2012-08-21 International Business Machines Corporation Thin substrate fabrication using stress-induced substrate spalling
US8278187B2 (en) 2009-06-24 2012-10-02 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments
US20100330777A1 (en) * 2009-06-24 2010-12-30 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate and method for manufacturing soi substrate
US20100330778A1 (en) * 2009-06-24 2010-12-30 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate and method for manufacturing soi substrate
US8404563B2 (en) 2009-06-24 2013-03-26 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate and method for manufacturing SOI substrate
US8354348B2 (en) 2009-08-25 2013-01-15 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US20110065263A1 (en) * 2009-08-25 2011-03-17 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate
US8426231B2 (en) 2009-08-25 2013-04-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device including a photoelectric conversion element
US8318588B2 (en) 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US20110053345A1 (en) * 2009-08-25 2011-03-03 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing soi substrate
US20110049588A1 (en) * 2009-08-25 2011-03-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof
US8288245B2 (en) 2009-10-09 2012-10-16 Semiconductor Energy Laboratory Co., Ltd. Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of SOI substrate
US20110086492A1 (en) * 2009-10-09 2011-04-14 Semiconductor Energy Laboratory Co., Ltd. Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
US20110186958A1 (en) * 2010-02-03 2011-08-04 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and manufacturing method thereof
US8476147B2 (en) 2010-02-03 2013-07-02 Semiconductor Energy Laboratory Co., Ltd. SOI substrate and manufacturing method thereof
US9269854B2 (en) * 2010-09-10 2016-02-23 VerLASE TECHNOLOGIES LLC Methods of fabricating optoelectronic devices using layers detached from semiconductor donors and devices made thereby
JP2013542589A (en) * 2010-09-10 2013-11-21 バーレイス テクノロジーズ エルエルシー Method of manufacturing an optoelectronic device using a layer separated from a semiconductor donor and device manufactured thereby
US9525150B2 (en) 2010-09-10 2016-12-20 VerLASE TECHNOLOGIES LLC Optoelectronic devices made using layers detached from inherently lamellar semiconductor donors
US20130143336A1 (en) * 2010-09-10 2013-06-06 VerLASE TECHNOLOGIES LLC Methods of Fabricating Optoelectronic Devices Using Layers Detached from Semiconductor Donors and Devices Made Thereby
US8530336B2 (en) 2010-11-12 2013-09-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US20220393003A1 (en) * 2021-06-08 2022-12-08 Wafer Works Corporation Composite substrate and manufacturing method thereof
US11600706B2 (en) * 2021-06-08 2023-03-07 Wafer Works Corporation Composite substrate and manufacturing method thereof
CN115863149A (en) * 2022-12-12 2023-03-28 中国科学院上海微系统与信息技术研究所 Preparation method of gallium oxide structure

Also Published As

Publication number Publication date
US7939428B2 (en) 2011-05-10
US20090289332A1 (en) 2009-11-26
KR20080078679A (en) 2008-08-27
TWI324357B (en) 2010-05-01
US20070287273A1 (en) 2007-12-13
CN101341580A (en) 2009-01-07
US7839001B2 (en) 2010-11-23
US20110039368A1 (en) 2011-02-17
TW200733194A (en) 2007-09-01
FR2894990B1 (en) 2008-02-22
WO2007071772A1 (en) 2007-06-28
CN101341580B (en) 2010-09-01
FR2894990A1 (en) 2007-06-22
EP1979933A1 (en) 2008-10-15
US7615468B2 (en) 2009-11-10

Similar Documents

Publication Publication Date Title
US20070141803A1 (en) Methods for making substrates and substrates formed therefrom
JP6650463B2 (en) Method of manufacturing high resistivity semiconductor-on-insulator wafer with charge trapping layer
US6350702B2 (en) Fabrication process of semiconductor substrate
US8481409B2 (en) Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate
KR100448423B1 (en) Method of producing semiconductor member
US20090311477A1 (en) Compliant Substrate In Particular For Hetero-Epitaxial Depositing
US20130294038A1 (en) Electronic device for radiofrequency or power applications and process for manufacturing such a device
US20030087503A1 (en) Process for production of semiconductor substrate
AU745315B2 (en) Method for manufacturing semiconductor article
JP2000349264A (en) Method for manufacturing, use and utilizing method of semiconductor wafer
JP2009516929A (en) Large area semiconductor on glass insulator
US8951887B2 (en) Process for fabricating a semiconductor structure employing a temporary bond
US20080102601A1 (en) Method for producing a semiconductor substrate
CN115023802A (en) Method for producing a composite structure comprising a thin layer of monocrystalline SiC on a carrier substrate made of SiC
US7695564B1 (en) Thermal management substrate
KR20220159960A (en) Method for manufacturing a composite structure comprising a thin layer made of single crystal SiC on a carrier substrate made of SiC
WO2008031809A1 (en) Process for making a gan substrate
JP3293767B2 (en) Semiconductor member manufacturing method
JP2023502571A (en) A process for making a composite structure comprising a thin layer of monocrystalline SiC on a carrier substrate made of SiC
US20240145294A1 (en) Method for manufacturing a silicon-carbide-based semiconductor structure and intermediate composite structure
US20240030061A1 (en) Donor substrate for the transfer of a thin layer and associated transfer method
JP2023528784A (en) Temporary strippable substrate for very high temperatures and process for transferring working layer from said substrate
TW202301554A (en) Method for producing a silicon carbide-based semiconductor structure and intermediate composite structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOUSSAGOL, ALICE;FAURE, BRUCE;GHYSELEN, BRUNO;REEL/FRAME:018377/0713;SIGNING DATES FROM 20060816 TO 20060901

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: SOITEC, FRANCE

Free format text: CHANGE OF NAME;ASSIGNOR:S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES;REEL/FRAME:027800/0911

Effective date: 20110906