US20070148817A1 - Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components - Google Patents
Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components Download PDFInfo
- Publication number
- US20070148817A1 US20070148817A1 US11/708,917 US70891707A US2007148817A1 US 20070148817 A1 US20070148817 A1 US 20070148817A1 US 70891707 A US70891707 A US 70891707A US 2007148817 A1 US2007148817 A1 US 2007148817A1
- Authority
- US
- United States
- Prior art keywords
- conductive
- jacket
- disposing
- substrate
- contact pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B33—ADDITIVE MANUFACTURING TECHNOLOGY
- B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
- B33Y80/00—Products made by additive manufacturing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/742—Apparatus for manufacturing bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B33—ADDITIVE MANUFACTURING TECHNOLOGY
- B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
- B33Y30/00—Apparatus for additive manufacturing; Details thereof or accessories therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/1155—Selective modification
- H01L2224/11552—Selective modification using a laser or a focussed ion beam [FIB]
- H01L2224/11554—Stereolithography, i.e. solidification of a pattern defined by a laser trace in a photosensitive resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates generally to conductive structures for use with semiconductor device components, such as flip-chip type semiconductor devices, including chip-scale packages. Particularly, the present invention pertains to complementarily configured and located conductive structures on a semiconductor device and another substrate to which the semiconductor device is to be connected. The invention also relates to methods of fabricating the conductive structures and, more particularly, to the use of stereolithography to fabricate at least a portion of the conductive structures.
- Some types of semiconductor devices such as flip-chip type semiconductor devices, including flip-chip type dice and ball grid array (BGA) packages (including chip-scale packages, or CSPs), can be connected to higher level substrates by orienting these semiconductor devices face down over the higher level substrate.
- the contact pads of such semiconductor devices are typically connected directly to corresponding contact pads of the higher level substrate by solder balls.
- solders that are known in the art to be useful in connecting semiconductor devices face down to higher level substrates include, but are not limited to, lead-tin (Pb/Sn) solder, silver-nickel (Ag/Ni) solder, copper, gold, and conductive or conductor-filled polymers.
- Pb/Sn solder lead-tin solder
- Ag/Ni silver-nickel solder
- copper gold
- conductive or conductor-filled polymers conductive or conductor-filled polymers.
- 95/5 type Pb/Sn solder bumps i.e., solder having about 95% by weight lead and about 5% by weight tin
- CSPs chip-scale packages
- a quantity of solder paste having a higher melting temperature such as 63/37 type Pb/Sn solder, can be applied to the contact pad of the higher level substrate to facilitate bonding of the solder bump thereto.
- the 95/5 type Pb/Sn solder and the 63/37 type Pb/Sn solder are heated to bond the solder bump to a contact pad of the substrate, the 95/5 type Pb/Sn solder, which has a lower melting temperature, softens first.
- the gravitational or compressive forces holding the semiconductor device in position over the higher level substrate can cause the softened 95/5 type Pb/Sn solder bump to flatten, pushing the solder laterally outward onto portions of the surface of the semiconductor device that surround the contact pad to which the solder bump is secured.
- solder balls when solder balls are reflowed to connect a semiconductor device to a substrate, a phenomenon referred to as “outgassing” occurs, which can damage a semiconductor device proximate to the solder balls.
- relatively high temperatures are required to reflow even low temperature solders, such as 95/5 type Pb/Sn solders.
- the reflow temperatures can damage package components, such as packaging or encapsulant materials, and even features of the semiconductor die being connected to the substrate.
- Assemblies that include semiconductor devices connected face down to higher level substrates are subjected to thermal cycling during further processing, testing thereof, and in normal use.
- the solder balls thereof are also exposed to wide ranges of temperatures, causing the solder balls to expand when heated and contract when cooled.
- Solder balls have a very different coefficient of thermal expansion than the primary materials of the semiconductor device and the substrate between which the solder balls are disposed.
- the amount that the solder balls expand and contract differs significantly from the amount of expansion and contraction of the semiconductor device and the substrate.
- repeated variations in temperatures can cause solder fatigue, which can reduce the strength of the solder balls, cause the solder balls to fail, and diminish the reliability of the solder balls.
- Thermal cycling can also alter the conformations of the conductive structures.
- solder ball The likelihood that a solder ball will be damaged by thermal cycling is particularly high when the solder ball spreads over and contacts the surface of the semiconductor device or the higher level substrate surrounding the contact pad.
- the solder ball loses some of its ability to dissipate heat and, therefore, can be exposed to the full range of temperatures that can occur during thermal cycling.
- flattened solder balls and solder balls that contact regions of the surface of a semiconductor device that surround the contact pads thereof are particularly susceptible to the types of damage that can be caused by thermal cycling of the semiconductor device.
- solder balls In an attempt to increase the reliability with which solder balls connect semiconductor devices face down to higher level substrates, resins have been applied to semiconductor devices to form collars around the bases of the solder balls protruding from the semiconductor devices. These resinous supports laterally contact the bases of the solder balls to enhance the reliability thereof.
- the resinous supports are applied to a semiconductor device after solder balls have been secured to the contact pads of the semiconductor device and before the semiconductor device is connected face down to a higher level substrate.
- the shapes of solder balls can change when bonded to the contact pads of a substrate. If the shapes of the solder balls change, the solder balls can fail to maintain contact with the resinous supports, which could thereby fail to protect or enhance the reliability of the solder balls.
- solder balls in connecting a semiconductor device face down to higher level substrates is also somewhat undesirable from the standpoint that, due to their generally spherical shapes, solder balls consume a great deal of area, or “real estate,” on a semiconductor device. Thus, solder balls can unduly limit the minimum spacing between the adjacent contact pads of a semiconductor device and, thus, the minimum pitch of the contact pads on the semiconductor device.
- conductive structures have been used to connect semiconductor devices, including those with relatively tight contact pad pitches, to substrates.
- these alternative conductive structures include pillars of conductive elastomer or conductor filled epoxy. When such conductive pillars are secured to the contact pads of a semiconductor device, however, the conductive materials from which these conductive structures are fabricated can bleed. This may cause the material to flow onto regions of the semiconductor device surrounding the contact pad, which may cause parasitic capacitance or even electrical shorts when adjacent conductive structures bleed into contact with each other or a conductive structure bleeds onto an adjacent contact pad.
- the inventors are not aware of any art that discloses reinforced, self-aligning conductive structures that facilitate the connection of a semiconductor device to a substrate while preventing conductive material from bleeding or flowing over the edges of contact pads to which the conductive structures are secured. Moreover, the inventors are not aware of methods that can be used to fabricate such reinforced conductive structures.
- stereolithography also known as “layered manufacturing”
- layered manufacturing has evolved to a degree where it is employed in many industries.
- stereolithography involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software.
- the model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object.
- a complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
- stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries. This is followed by selective consolidation or fixation of the material to at least a partially consolidated, or semisolid, state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer of the object to be fabricated.
- the unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer.
- thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object.
- resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material.
- various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
- stereolithography An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
- stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, pre-existing object or component to create a larger product.
- stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other, pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results is required.
- the inventor is not aware of the use of stereolithography in the fabrication of conductive structures protruding from the contact pads of semiconductor devices, such as flip-chip type semiconductor devices or chip-scale packages.
- conventional stereolithography apparatus and methods fail to address the difficulties of precisely locating and orienting a number of pre-existing components for stereolithographic application of material thereto without the use of mechanical alignment techniques or to otherwise assuring precise, repeatable placement of components.
- the present invention includes a reinforced, self-aligning conductive structure.
- the conductive structure includes interconnectable male and female members, each having a conductive center and a dielectric jacket formed from a thermally stable resin surrounding the conductive center.
- the female member of the reinforced, self-aligning conductive structure is secured to or fabricated on a contact pad of one of a semiconductor device and a substrate, while the male member is secured to or fabricated on a corresponding contact pad of the other one of the substrate and the semiconductor device.
- Each of the male and female members include an outer dielectric support component that contains a quantity of conductive material in contact with the contact pad over which each of the members is disposed.
- the female member has a recess configured complementarily to at least an end of the male member so as to receive the end of the male member.
- the invention includes a method for joining the conductive centers of an assembled male member and female member.
- the conductive material of each of the male and female members is preferably a thermally curable polymer.
- the material of at least one of the conductive centers is at least partially uncured.
- the material of the conductive centers can be fully cured to form an integral conductive center between a contact pad of the semiconductor device and a corresponding contact pad of the substrate.
- curing the conductive material of the male and female members following assembly thereof secures the semiconductor device to the substrate.
- conductive centers of each of the male and female members can be employed as the conductive centers of each of the male and female members.
- the conductive centers of an interconnected male member and female member can be formed into an integral conductive center by reflowing the material of the conductive centers.
- a conductive structure incorporating teachings of the present invention surrounds the periphery of a contact pad exposed at the surface of a semiconductor device or substrate to confine the conductive material over the contact pad and to prevent the conductive material from bleeding or flowing onto portions of the surface of the semiconductor device or substrate that surround the contact pad.
- the present invention includes a method for fabricating the reinforced conductive structure according to the present invention.
- a computer-controlled, 3-D CAD initiated process known as “stereolithography” or “layered manufacturing” is used to fabricate the jacket of both the male and female members.
- stereolithography or “layered manufacturing” is used to fabricate the jacket of both the male and female members.
- each jacket is formed as either a single layer or a series of superimposed, contiguous, mutually adhered layers of material.
- the stereolithographic method of fabricating the jackets of the present invention preferably includes the use of a machine vision system to locate the semiconductor devices or substrates on which the jackets are to be fabricated, as well as the features or other components on or associated with the semiconductor devices or substrates (e.g., contact pads, conductive traces, etc.).
- the use of a machine vision system directs the alignment of a stereolithography system with each semiconductor device or substrate for material disposition purposes. Accordingly, the semiconductor devices or substrates need not be precisely mechanically aligned with any component of the stereolithography system to practice the stereolithographic embodiment of the method of the present invention.
- the jackets to be fabricated or positioned upon and secured to a semiconductor device component in accordance with the invention are fabricated using precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser under control of a computer and responsive to input from a machine vision system, such as a pattern recognition system, to fix or cure selected regions of a layer of a liquid photopolymer material disposed on the semiconductor device or substrate.
- a machine vision system such as a pattern recognition system
- the jackets may be fabricated either separately from the semiconductor device or substrate to which they are to be secured or directly on the semiconductor device or substrate. If the jackets are fabricated directly on the semiconductor device or substrate, they may be fabricated around pre-formed quantities of conductive material protruding from the contact pads of the semiconductor device or substrate. Alternatively, the jackets may be fabricated around or over the peripheries of contact pads of the semiconductor device or substrate with the contact pads being exposed therethrough. Conductive material may then be disposed in the jackets and against the contact pads exposed therethrough.
- a quantity of unconsolidated (e.g., particulate, molten, or uncured liquid) conductive or conductor-filled material is disposed in the centers of the jackets.
- stereolithography may also be used to form the conductive centers of the male and female members from an electrically conductive photopolymer. If stereolithography is used to fabricate the conductive centers, the conductive center of at least one of a corresponding pair of members is preferably left at least partially unconsolidated so as to facilitate the subsequent formation of an integral conductive center through the conductive structure.
- FIG. 1 is a perspective view of a semiconductor device having male members of conductive structures protruding from the contact pads thereof and a carrier substrate having corresponding female members of the conductive structures protruding from the contact pads thereof;
- FIG. 2 is an enlarged partial perspective view of a male member on the semiconductor device of FIG. 1 ;
- FIG. 3 is an enlarged partial perspective view of a female member on the substrate of FIG. 1 ;
- FIG. 4 is a bottom plan view of the semiconductor device of FIG. 1 ;
- FIG. 5 is a bottom plan view of the substrate of FIG. 1 ;
- FIG. 6 is a cross-sectional view depicting the semiconductor device and the substrate of FIG. 1 in an assembled relationship with the male members and the female members interconnected;
- FIG. 7 is a cross-sectional view depicting a semiconductor device and a substrate having another embodiment of the male and female members of the conductive structure in communication with a contact pad thereof;
- FIG. 8 is a cross-sectional view depicting another embodiment of the conductive structure, with the male and female members thereof secured to corresponding contact pads of a semiconductor device and a substrate;
- FIG. 9 is a cross-sectional view depicting yet another embodiment of the conductive structure, with the male and female members thereof secured to corresponding contact pads of a semiconductor device and a substrate;
- FIG. 10 is a perspective view of a portion of a wafer having a plurality of semiconductor devices thereon, depicting female members of the conductive structures being fabricated around each of the contact pads of the semiconductor devices at the wafer level;
- FIG. 11 is a schematic representation of an exemplary stereolithography apparatus that can be employed in the method of the present invention to fabricate the jacket of a male member of a conductive structure of the present invention.
- FIG. 12 is a partial cross-sectional side view of a semiconductor device disposed on a platform of a stereolithographic apparatus for the formation of jackets of a male member of a conductive structure around the contact pads of the semiconductor device.
- Semiconductor device 10 is a flip-chip type device, such as a flip-chip die or a ball grid array package, or a flip-chip type chip-scale package having contact pads 12 ( FIG. 6 ) on a surface 14 thereof that can each be bonded to corresponding contact pads 22 ( FIG. 6 ) of a surface 24 of substrate 20 by way of conductive structures 30 .
- Each conductive structure 30 has a separate, interconnectable male member 40 and female member 50 . As illustrated, male members 40 are secured to and protrude from contact pads 12 of semiconductor device 10 , while female members 50 are secured to and protrude from contact pads 22 of substrate 20 .
- male members 40 each include a dielectric jacket 42 with an aperture 44 extending through the length thereof.
- Aperture 44 is filled with a quantity of conductive material, referred to herein as a conductive center 46 of male member 40 .
- aperture 44 is completely filled with conductive material.
- Jacket 42 and aperture 44 are configured to contain the material of conductive center 46 over a contact pad 12 and to, therefore, prevent the material of conductive center 46 from bleeding or flowing off of contact pads 12 and onto the surrounding areas of surface 14 .
- Jacket 42 also electrically insulates the lateral periphery of conductive center 46 .
- FIGS. 3 and 6 illustrate female members 50 , each of which has a dielectric jacket 52 with an aperture 54 extending through the length thereof.
- jacket 52 and aperture 54 are configured to contain the conductive material of conductive center 56 over a contact pad 22 of substrate 20 and to prevent the material of conductive center 56 from bleeding or flowing off of contact pads 22 and onto surrounding areas of surface 24 .
- Jacket 52 also electrically insulates the lateral surfaces of conductive center 56 .
- aperture 54 is preferably only partially filled with conductive material to form a conductive center 56 of female member 50 .
- An upper portion 58 of aperture 54 which is preferably not filled with conductive material, is configured to matingly receive at least an end portion of male member 40 .
- Upper portion 58 is also referred to herein as a receptacle.
- Conductive structure 30 ′ has a male member 40 ′, illustrated as being secured over a contact pad 12 of semiconductor device 10 , and a female member 50 ′, which, as illustrated, is secured to a contact pad 22 of substrate 20 .
- outer ledge 48 defines a minimum length of conductive structure 30 ′ and a minimum distance between an assembled semiconductor device 10 and substrate 20 .
- upper portion 58 ′ of aperture 54 ′ can have a larger periphery than the remainder of aperture 54 ′, with an internal ledge 55 being formed at the junction between upper portion 58 ′ and the remainder of aperture 54 ′.
- Internal ledge 55 acts as a stop for male member 40 ′ during insertion thereof into aperture 54 ′ and prevents male member 40 ′ from being inserted too far into aperture 54 ′ of female member 50 ′.
- Internal ledge 55 may also be used as a line of demarcation to identify an optimum level for filling aperture 54 ′ with conductive material so as to facilitate an electrical communication between a contact pad 12 of semiconductor device 10 and a corresponding contact pad 22 of substrate 20 while avoiding the use of an excessive quantity of conductive material as male member 40 ′ and female member 50 ′ are interconnected.
- FIG. 8 illustrates another embodiment of a conductive structure 30 ′′ according to the present invention, wherein the larger end of a frustoconically shaped or otherwise tapered male member 40 ′′ thereof is secured to a contact pad 22 of substrate 20 and the female member 50 ′′ thereof is secured to a contact pad 12 of semiconductor device 10 .
- Female member 50 ′′ has an aperture 54 ′′ configured to receive at least an end portion 43 ′′ of the jacket 42 ′′ of male member 40 ′′.
- the tapering of the outer surface of jacket 42 ′′ facilitates self-alignment of male member 40 ′′ and female member 50 ′′ when semiconductor device 10 and substrate 20 are not precisely and accurately aligned.
- jacket 42 ′′ may be tapered and aperture 54 ′′ sized so as to permit male member 40 ′′ to insert only a predetermined, specific distance into aperture 54 ′′ of female member 50 ′′ and, thus, define a minimum length of conductive structure 30 ′′, as well as a minimum assembled distance between semiconductor device 10 and substrate 20 .
- FIG. 9 Yet another embodiment of a conductive structure 30 ′′′ according to the present invention is illustrated in FIG. 9 .
- the male and female members 40 ′′′, 50 ′′′, respectively, of conductive structure 30 ′′′ each have substantially cylindrical shapes.
- Female member 50 ′′′ has an aperture 54 ′′′ with an inner surface and an end remote from substrate 20 to which female member 50 ′′′ is secured that tapers outwardly toward a periphery of female member 50 ′′′.
- conductive structure 30 ′′′ has a substantially cylindrical shape.
- FIG. 10 a wafer 72 with a plurality of semiconductor devices 10 thereon is illustrated.
- Each semiconductor device 10 which has yet to be singulated, or diced, from wafer 72 , has female members 50 of conductive structures 30 secured to the contact pads 12 (see FIG. 8 ) thereof.
- Each semiconductor device 10 on wafer 72 is separated from adjacent semiconductor devices 10 by a street 74 .
- jackets of the male and female members of the conductive structures including jackets 42 , 42 ′, 42 ′′, 52 , 52 ′, 52 ′′, are preferably substantially simultaneously fabricated on or secured to a collection of semiconductor devices 10 or substrates 20 , such as prior to singulating semiconductor dice from a wafer 72
- the jackets of each of the members of the conductive structures can also be fabricated on or secured to collections of individual semiconductor devices 10 or substrates 20 , or to individual semiconductor devices 10 or substrates 20 .
- the jackets can be substantially simultaneously fabricated on or secured to a collection of different types of semiconductor devices 10 or substrates 20 .
- the jackets of both members of the conductive structures of the present invention can be fabricated directly on semiconductor devices 10 or substrates 20 .
- the jackets can be fabricated separately from semiconductor devices 10 or substrates 20 , then secured thereto as known in the art, such as by the use of a suitable adhesive.
- the jackets are preferably fabricated from a photo-curable polymer, or “photopolymer,” by stereolithographic processes. When fabricated directly on a semiconductor device 10 or substrate 20 , the jackets can be made either before or after preformed conductive centers 46 , 56 are connected to contact pads 12 of semiconductor device 10 or to contact pads 22 of substrate 20 .
- the ensuing description is limited to an explanation of a method of fabricating jackets 52 on a semiconductor device 10 prior to placing conductive material in contact with contact pads 12 of semiconductor device 10 .
- the method described herein is also useful for fabricating the jackets of other embodiments of the female member of a conductive structure according to the present invention on one or more semiconductor devices or substrates, as well as for fabricating the jackets of any embodiment of a male member of a conductive structure that incorporates teachings of the present invention on one or more semiconductor devices or substrates.
- FIG. 11 schematically depicts various components and operation of an exemplary stereolithography apparatus 80 to facilitate the reader's understanding of the technology employed in implementation of the method of the present invention, although those of ordinary skill in the art will understand and appreciate that apparatus of other designs and manufacture may be employed in practicing the method of the present invention.
- the preferred, basic stereolithography apparatus for implementation of the method of the present invention, as well as operation of such apparatus, are described in great detail in United States patents assigned to 3D Systems, Inc., of Valencia, Calif., such patents including, without limitation, U.S. Pat. Nos.
- a 3-D CAD drawing of an object to be fabricated in the form of a data file is placed in the memory of a computer 82 controlling the operation of apparatus 80 if computer 82 is not a CAD computer in which the original object design is effected.
- an object design may be effected in a first computer in an engineering or research facility and the data files transferred via wide or local area network, tape, disc, CD-ROM, or otherwise, as known in the art, to computer 82 of apparatus 80 for object fabrication.
- the data is preferably formatted in an STL (for STereoLithography) file, STL being a standardized format employed by a majority of manufacturers of stereolithography equipment. Fortunately, the format has been adopted for use in many solid-modeling CAD programs, so translation from another internal geometric database format is often unnecessary.
- STL file the boundary surfaces of an object are defined as a mesh of interconnected triangles.
- Apparatus 80 also includes a reservoir 84 (which may comprise a removable reservoir interchangeable with others containing different materials) of an unconsolidated material 86 to be employed in fabricating the intended object.
- the unconsolidated material 86 is a liquid, photo-curable polymer, or “photopolymer,” that cures in response to light in the UV wavelength range.
- the surface level 88 of material 86 is automatically maintained at an extremely precise, constant magnitude by devices known in the art responsive to output of sensors within apparatus 80 and preferably under control of computer 82 .
- a support platform or elevator 90 precisely vertically movable in fine, repeatable increments in direction 116 responsive to control of computer 82 , is located for movement downward into and upward out of material 86 in reservoir 84 .
- An object may be fabricated directly on platform 90 or on a substrate disposed on platform 90 .
- the substrate may be positioned on platform 90 and secured thereto by way of one or more base supports 122 (see FIG. 12 ).
- Such base supports 122 may be fabricated before or simultaneously with the stereolithographic fabrication of one or more objects on platform 90 or a substrate disposed thereon.
- These supports 122 may support, or prevent lateral movement of, the substrate or object being formed relative to a surface 100 of platform 90 .
- Supports 122 may also provide a perfectly horizontal reference plane for fabrication of one or more objects thereon, as well as facilitate the removal of a substrate or formed object from platform 90 following the stereolithographic fabrication of one or more objects on the substrate.
- supports 122 can preclude inadvertent contact of recoater blade 102 , to be described in greater detail below, with surface 100 of platform 90 .
- Apparatus 80 has a UV wavelength range laser plus associated optics and galvanometers (collectively identified as laser 92 ) for controlling the scan of laser beam 96 in the X-Y plane across platform 90 .
- Laser 92 has associated therewith a mirror 94 to reflect beam 96 downwardly as beam 98 toward surface 100 of platform 90 .
- Beam 98 is traversed in a selected pattern in the X-Y plane, that is to say, in a plane parallel to surface 100 , by initiation of the galvanometers under control of computer 82 to at least partially cure, by impingement thereon, selected portions of material 86 disposed over surface 100 to at least a partially consolidated (e.g., semisolid) state.
- the use of mirror 94 lengthens the path of the laser beam, effectively doubling same, and provides a more vertical beam 98 than would be possible if the laser 92 itself were mounted directly above platform surface 100 , thus enhancing resolution.
- data from the STL files resident in computer 82 is manipulated to build an object, such as jacket 52 , illustrated in FIGS. 1, 3 , and 5 , or base supports 122 , one layer at a time.
- the data mathematically representing one or more of the objects to be fabricated are divided into subsets, each subset representing a slice or layer of the object.
- the division of data is effected by mathematically sectioning the 3-D CAD model into at least one layer, a single layer or a “stack” of such layers representing the object.
- Each slice may be from about 0.0001 to about 0.0300 inch thick. As mentioned previously, a thinner slice promotes higher resolution by enabling better reproduction of fine vertical surface features of the object or objects to be fabricated.
- supports 122 may be programmed as a separate STL file from the other objects to be fabricated.
- the primary STL file for the object or objects to be fabricated and the STL file for base support(s) 122 are merged.
- the operational parameters for apparatus 80 are set to adjust the size (diameter if circular) of the laser light beam used to cure material 86 .
- computer 82 automatically checks and, if necessary, adjusts by means known in the art, the surface level 88 of material 86 in reservoir 84 to maintain same at an appropriate focal length for laser beam 98 .
- U.S. Pat. No. 5,174,931 referenced above and previously incorporated herein by reference, discloses one suitable level control system.
- the height of mirror 94 may be adjusted responsive to a detected surface level 88 to cause the focal point of laser beam 98 to be located precisely at the surface of material 86 at surface level 88 if level 88 is permitted to vary, although this approach is more complex.
- Platform 90 may then be submerged in material 86 in reservoir 84 to a depth equal to the thickness of one layer or slice of the object to be formed, and the liquid surface level 88 is readjusted as required to accommodate material 86 displaced by submergence of platform 90 .
- Laser 92 is then activated so laser beam 98 will scan unconsolidated (e.g., liquid or powdered) material 86 disposed over surface 100 of platform 90 to at least partially consolidate (e.g., polymerize to at least a semisolid state) material 86 at selected locations, defining the boundaries of a first layer 122 A of base support 122 and filling in solid portions thereof.
- Platform 90 is then lowered by a distance equal to thickness of second layer 122 B, and laser beam 98 is scanned over selected regions of the surface of material 86 to define and fill in the second layer while simultaneously bonding the second layer to the first. The process may then be repeated as often as necessary, layer by layer, until base support 122 is completed.
- Platform 90 is then moved relative to mirror 94 to form any additional base supports 122 on platform 90 or a substrate disposed thereon or to fabricate objects upon platform 90 , base support 122 , or a substrate, as provided in the control software.
- the number of layers required to erect support 122 or one or more other objects to be formed depends upon the height of the object or objects to be formed and the desired layer thickness 108 , 110 .
- the layers of a stereolithographically fabricated structure with a plurality of layers may have different thicknesses.
- a recoater blade 102 is employed, the process sequence is somewhat different.
- surface 100 of platform 90 is lowered into unconsolidated (e.g., liquid) material 86 below surface level 88 a distance greater than a thickness of a single layer of material 86 to be cured, then raised above surface level 88 until platform 90 , a substrate disposed thereon, or a structure being formed on either platform 90 or a substrate thereon, is precisely one layer's thickness below blade 102 .
- Blade 102 then sweeps horizontally over platform 90 or (to save time) at least over a portion thereof on which one or more objects are to be fabricated to remove excess material 86 and leave a film of precisely the desired thickness.
- Platform 90 is then lowered so that the surface of the film and material level 88 are coplanar and the surface of the unconsolidated material 86 is still.
- Laser 92 is then initiated to scan with laser beam 98 and define the first layer 130 .
- the process is repeated, layer by layer, to define each succeeding layer 130 and simultaneously bond same to the next lower layer 130 until all of the layers of the object or objects to be fabricated are completed.
- a layer of unconsolidated (e.g., liquid) material 86 may be formed on surface 100 of support platform 90 , on a substrate disposed on platform 90 , or on one or more objects being fabricated by lowering platform 90 to flood material 86 over surface 100 , over a substrate disposed thereon, or over the highest completed layer of the object or objects being formed, then raising platform 90 and horizontally traversing a so-called “meniscus” blade horizontally over platform 90 to form a layer of unconsolidated material having the desired thickness over platform 90 , the substrate, or each of the objects being formed.
- Laser 92 is then initiated and a laser beam 98 scanned over the layer of unconsolidated material to define at least the boundaries of the solid regions of the next higher layer of the object or objects being fabricated.
- Yet another alternative to layer preparation of unconsolidated (e.g., liquid) material 86 is to merely lower platform 90 to a depth equal to that of a layer of material 86 to be scanned, and to then traverse a combination flood bar and meniscus bar assembly horizontally over platform 90 , a substrate disposed on platform 90 , or one or more objects being formed to substantially concurrently flood material 86 thereover and to define a precise layer thickness of material 86 for scanning.
- unconsolidated (e.g., liquid) material 86 is to merely lower platform 90 to a depth equal to that of a layer of material 86 to be scanned, and to then traverse a combination flood bar and meniscus bar assembly horizontally over platform 90 , a substrate disposed on platform 90 , or one or more objects being formed to substantially concurrently flood material 86 thereover and to define a precise layer thickness of material 86 for scanning.
- a commercially available stereolithography apparatus operating generally in the manner as that described above with respect to apparatus 80 of FIG. 11 is preferably employed, but with further additions and modifications as hereinafter described for practicing the method of the present invention.
- the SLA-250/50HR, SLA-5000 and SLA-7000 stereolithography systems are suitable for modification.
- Photopolymers believed to be suitable for use in practicing the present invention include Cibatool SL 5170 and SL 5210 resins for the SLA-250/50HR system, Cibatool SL 5530 resin for the SLA-5000 and 7000 systems, and Cibatool SL 7510 resin for the SLA-7000 system. All of these photopolymers are available from Ciba Specialty Chemicals Inc.
- the layer thickness of material 86 to be formed may be on the order of about 0.0001 to 0.0300 inch, with a high degree of uniformity. It should be noted that different material layers may have different heights so as to form a structure of a precise, intended total height or to provide different material thicknesses for different portions of the structure.
- the size of the laser beam “spot” impinging on the surface of material 86 to consolidate (e.g., cure) same may be on the order of 0.001 inch to 0.008 inch.
- Resolution is preferably ⁇ 0.0003 inch in the X-Y plane (parallel to surface 100 ) over at least a 0.5 inch ⁇ 0.25 inch field from a center point, permitting a high resolution scan effectively across a 1.0 inch ⁇ 0.5 inch area.
- the longer and more effectively vertical the path of laser beam 96 / 98 the greater the achievable resolution.
- apparatus 80 useful in the method of the present invention includes a camera 140 which is in communication with computer 82 and preferably located, as shown, in close proximity to optics and mirror 94 located above surface 100 of support platform 90 .
- Camera 140 may be any one of a number of commercially available cameras, such as capacitive-coupled discharge (CCD) cameras available from a number of vendors.
- Suitable circuitry as required for adapting the output of camera 140 for use by computer 82 may be incorporated in a board 142 installed in computer 82 , which is programmed, as known in the art, to respond to images generated by camera 140 and processed by board 142 .
- Camera 140 and board 142 may together comprise a so-called “machine vision system” and, specifically, a “pattern recognition system” (PRS), operation of which will be described briefly below for a better understanding of the present invention.
- a self-contained machine vision system available from a commercial vendor of such equipment may be employed.
- such systems are available from Cognex Corporation of Natick, Mass.
- the apparatus of the Cognex BGA Inspection PackageTM or the SMD Placement Guidance PackageTM may be adapted to the present invention, although it is believed that the MVS-8000TM product family and the Checkpoint® product line, the latter employed in combination with Cognex PatMaxTM software, may be especially suitable for use in the present invention.
- a data file representative of the size, configuration, thickness and surface topography of, for example, a particular type and design of semiconductor device 10 or other substrate upon which one or more jackets 52 are to be mounted is placed in the memory of computer 82 .
- jackets 52 are configured to be interconnected with complementary jackets 42 (see FIGS. 1 and 6 ) of male members 40 on another substrate, a data file representative of the substrate to which male members 42 are to be secured and the features thereof, as well as a data file representative of male members 40 , may be placed in memory.
- One or more semiconductor devices 10 , wafers 72 (see FIG. 10 ), or other substrates may be placed on surface 100 of platform 90 for fabrication of one or more dielectric jackets 52 around contact pads 12 thereof. If one or more semiconductor devices 10 , wafers 72 , or other substrates are to be held on or supported above platform 90 by stereolithographically formed base supports 122 , one or more layers of material 86 are sequentially disposed on surface 100 and selectively altered by use of laser 92 to form base supports 122 .
- Camera 140 is then activated to locate the position and orientation of each semiconductor device 10 , including those on a wafer 72 (see FIG. 10 ), or other substrate upon which one or more dielectric jackets 52 are to be fabricated.
- the features of each semiconductor device 10 , wafer 72 , or other substrate are compared with those in the data file residing in memory, the locational and orientational data for each semiconductor device 10 , wafer 72 , or other substrate then also being stored in memory.
- the data file representing the design, size, shape and topography for each semiconductor device 10 or other substrate may be used at this juncture to detect physically defective or damaged semiconductor devices 10 or other substrates prior to fabricating jackets 52 thereon or before conducting further processing or assembly of semiconductor device 10 or other substrates.
- each semiconductor device 10 or other substrate can be deleted from the process of fabricating jackets 52 , from further processing, or from assembly with other components.
- data files for more than one type (size, thickness, configuration, surface topography) of each semiconductor device 10 or other substrate may be placed in computer memory and computer 82 programmed to recognize not only the locations and orientations of each semiconductor device 10 or other substrate, but also the type of semiconductor device 10 or other substrate at each location upon platform 90 so that material 86 may be at least partially consolidated by laser beam 98 in the correct pattern and to the height required to define jackets 52 in the appropriate, desired locations on each semiconductor device 10 or other substrate.
- wafer 72 or the one or more semiconductor devices 10 or other substrates on platform 90 may then be submerged partially below the surface level 88 of liquid material 86 to a depth greater than the thickness of a first layer of material 86 to be at least partially consolidated (e.g., cured to at least a semisolid state) to form the lowest layer 130 of each dielectric jacket 52 at the appropriate location or locations on each semiconductor device 10 or other substrate, then raised to a depth equal to the layer thickness, surface 88 of material 86 being allowed to become calm.
- Photopolymers that are useful as material 86 exhibit a desirable dielectric constant, low shrinkage upon cure, are of sufficient (i.e., semiconductor grade) purity, exhibit good adherence to other semiconductor device materials, and have a similar coefficient of thermal expansion (CTE) to the material of conductive centers 46 , 56 ( FIGS. 1-6 ) (e.g., solder or other metal or metal alloy, conductive resin, or conductive elastomer).
- CTE coefficient of thermal expansion
- the CTE of material 86 is sufficiently similar to that of the material of conductive centers 46 , 56 to prevent undue stressing thereof during thermal cycling of semiconductor device 10 or substrate 20 in testing, subsequent processing, and subsequent normal operation.
- Exemplary photopolymers exhibiting these properties are believed to include, but are not limited to, the above-referenced resins from Ciba Specialty Chemicals Inc.
- One area of particular concern in determining resin suitability is the substantial absence of mobile ions and, specifically, fluorides.
- Laser 92 is then activated and scanned to direct beam 98 , under control of computer 82 , toward specific locations of surface 88 relative to each semiconductor device 10 or other substrate to effect the aforementioned partial cure of material 86 to form a first layer 52 A of each jacket 52 .
- Platform 90 is then lowered into reservoir 84 and raised a distance equal to the desired thickness of another layer 52 B of each jacket 52 , and laser 92 is activated to add another layer 52 B to each jacket 52 under construction. This sequence continues, layer by layer, until each of the layers of jackets 52 have been completed.
- the first layer of a dielectric jacket 52 is identified by numeral 52 A, and the second layer is identified by numeral 52 B.
- the first layer of base support 122 is identified by numeral 122 A and the second layer thereof is identified by numeral 122 B.
- both base support 122 and jacket 52 have only two layers. Jackets 52 with any number of layers are, however, within the scope of the present invention.
- Each layer 52 A, 52 B of a dielectric jacket 52 is preferably built by first defining any internal and external object boundaries of that layer with laser beam 98 , then hatching solid areas of jacket 52 located within the object boundaries with laser beam 98 .
- An internal boundary of a layer may comprise aperture 54 , a through-hole, a void, or a recess in jacket 52 , for example. If a particular layer includes a boundary of a void in the object above or below that layer, then laser beam 98 is scanned in a series of closely-spaced, parallel vectors so as to develop a continuous surface, or skin, with improved strength and resolution. The time it takes to form each layer depends upon the geometry thereof, the surface tension and viscosity of material 86 , and the thickness of that layer.
- dielectric jackets 52 may each be formed as a partially cured outer skin extending above surface 14 of semiconductor device 10 or above surface 24 of substrate 20 and forming a dam within which unconsolidated material 86 can be contained. This may be particularly useful where the jackets 52 protrude a relatively high distance 60 from surface 14 .
- support platform 90 may be submerged so that material 86 enters the area within the dam, raised above surface level 88 , and then laser beam 98 activated and scanned to at least partially cure material 86 residing within the dam or, alternatively, to merely cure a “skin” comprising the surface of dielectric jackets 52 , a final cure of the material of the jackets 52 being effected subsequently by broad-source UV radiation in a chamber or by thermal cure in an oven.
- jackets 52 of extremely precise dimensions may be formed of material 86 by apparatus 80 in minimal time.
- dielectric jackets 52 ′′ depicted in FIG. 8
- some of material 86 may be located in shadowed areas 53 (see FIG. 8 ).
- laser beam 98 is directed substantially vertically downwardly toward surface 88 of material 86
- material 86 located in shadowed regions 53 will not be contacted or altered by laser beam 98 .
- the unconsolidated material 86 in shadowed areas 53 will become trapped therein as material 86 adjacent to and laterally outward from shadowed areas 53 is at least partially consolidated and as jacket 52 is built up around conductive center 56 ′′.
- Such trapped, unconsolidated material 86 will eventually cure due to the cross-linking initiated in the outwardly adjacent photopolymer, and the cure can be subsequently accelerated as known in the art, such as by a thermal cure.
- platform 90 is elevated above surface level 88 of material 86 and platform 90 is removed from apparatus 80 , along with any substrate (e.g., semiconductor device 10 , wafer 72 (see FIG. 10 ), or other substrate) disposed thereon and any stereolithographically fabricated structures, such as jackets 52 .
- any substrate e.g., semiconductor device 10 , wafer 72 (see FIG. 10 ), or other substrate
- unconsolidated material 86 e.g., excess uncured liquid
- Each semiconductor device 10 , wafer 72 , or other substrate is removed from platform 90 , such as by cutting the substrate free of base supports 122 .
- base supports 122 may be configured to readily release semiconductor devices 10 , wafers 72 , or other substrates.
- a solvent may be employed to release base supports 122 from platform 90 .
- release and solvent materials are known in the art. See, for example, U.S. Pat. No. 5,447,822 referenced above and previously incorporated herein by reference.
- Jackets 52 and semiconductor device 10 or substrate 20 may also be cleaned by use of known solvents that will not substantially degrade, deform, or damage jackets 52 or a substrate to which jackets 52 are secured.
- jackets 52 may then require postcuring.
- Jackets 52 may have regions of unconsolidated material contained within a boundary or skin thereof or in a shadowed area 53 (see FIGS. 8 and 9 ), or material 86 may be only partially consolidated (e.g., polymerized or cured) and exhibit only a portion (typically 40% to 60%) of its fully consolidated strength.
- Postcuring to completely harden jackets 52 may be effected in another apparatus projecting UV radiation in a continuous manner over jackets 52 or by thermal completion of the initial, UV-initiated partial cure.
- each jacket 52 on each specific semiconductor device 10 or other substrate may vary, again responsive to output of camera 140 or one or more additional cameras 144 , 146 , or 148 , shown in broken lines, detecting the protrusion of unusually high (or low) preformed, preplaced conductive centers 56 which could affect the desired distance that jackets 52 will protrude from surface 14 .
- the lateral extent (i.e., diameter or width) of each preplaced conductive center may be recognized and the girth of the outer boundary of each jacket 52 adjusted accordingly.
- laser 92 is again activated to at least partially cure material 86 residing on each semiconductor device 10 or other substrate to form the layer or layers of each jacket 52 .
- FIGS. 11 and 12 illustrate the stereolithographic fabrication of jackets 52 on a substrate, such as a semiconductor device 10 , a wafer 72 ( FIG. 10 ), or another substrate, including a plurality of semiconductor devices 10 or other substrates
- jackets 52 can be fabricated separately from a substrate, then secured to a substrate by known processes, such as by the use of a suitable adhesive material.
- dielectric jackets 52 are particularly advantageous since a large number of jackets 52 may be fabricated in a short time, the jacket height and position are computer controlled to be extremely precise, wastage of unconsolidated material 86 is minimal, solder coverage of passivation materials is avoided, and the stereolithography method requires minimal handling of semiconductor devices 10 , wafers 72 , or other substrates.
- Stereolithography is also an advantageous method of fabricating dielectric jackets 52 according to the present invention since stereolithography can be conducted at substantially ambient temperature, the small spot size and rapid traverse of laser beam 98 resulting in negligible thermal stress upon semiconductor devices 10 , wafers 72 , or other substrates, as well as on the features thereof.
- the stereolithography fabrication process may also advantageously be conducted at the wafer level or on multiple substrates, saving fabrication time and expense.
- the stereolithography method of the present invention recognizes specific semiconductor devices 10 or other substrates 20 , variations between individual substrates are accommodated. Accordingly, when the stereolithography method of the present invention is employed, jackets 52 can be simultaneously fabricated on different types of semiconductor devices 10 or other substrates, as well as on both semiconductor devices 10 and other substrates.
- Exemplary methods include, but are not limited to, the use of photoresist materials to form the reinforcement structures and fabrication of the reinforcement structure from dielectric materials using known semiconductor device patterning (e.g., mask and etch) processes.
- conductive centers 46 , 56 of members 40 , 50 can be preformed or formed after dielectric jackets 42 , 52 , respectively, have been secured to one of semiconductor device 10 and substrate 20 .
- Preformed conductive centers 46 , 56 can be made by known processes, such as by molding quantities of conductive material into a desired shape, then secured to a contact pad 12 , 22 of a semiconductor device 10 or substrate 20 , respectively, by known processes, such as by thermal bonding.
- conductive centers 46 , 56 are formed after dielectric jackets 42 , 52 have been secured to contact pads 12 of semiconductor device 10 or to contact pads 22 of substrate 20 , conductive material is disposed in each aperture 44 , 54 in jackets 42 , 52 .
- conductive material is placed into apertures 44 , 54 .
- solder can be disposed in apertures 44 , 54 by submerging jackets 42 , 52 in a solder bath, after which the solder may be allowed to harden and the conductive members secured to contact pads.
- solder paste or a preformed solder brick can be disposed in apertures 44 , 54 , then subsequently reflowed to form conductive centers 46 , 56 .
- Conductive thermoplastic materials can similarly be disposed in apertures 44 , 54 in a melted state, then cooled to form conductive centers 46 , 56 .
- particles of thermoplastic conductive material can be placed in apertures 44 , 54 and heated and cooled to form conductive centers 46 , 56 . Such heating and cooling may be effected either before or after male member 40 and female member 50 are interconnected.
- Thermally curable conductive resins can also be disposed in apertures 44 , 54 in an uncured or partially uncured state, then heated to cure the conductive resin and to form conductive centers 46 , 56 .
- the conductive center 46 , 56 of at least one of a pair of male and female members 40 , 50 is left uncured or at least partially uncured until after male member 40 and female member 50 have been interconnected so as to allow for the full curing of the conductive resin and the formation of an integral conductive center extending through conductive structure 30 .
- semiconductor device 10 is connected to substrate 20 by aligning male members 40 protruding from semiconductor device 10 with corresponding female members 50 on substrate 20 .
- the ends of male members 40 are then inserted into upper portion 58 of apertures 54 of their corresponding female members 50 such that the conductive centers 46 and 56 of male member 40 and female member 50 , respectively, can communicate with one another.
- male member 40 may alternatively be secured to substrate 20 and female member 50 may alternatively be secured to semiconductor device 10 .
- a single, integral conductive center can then be formed by bonding conductive centers 46 and 56 .
- conductive centers 46 and 56 are formed from a thermally curable conductive resin, at least one of conductive centers 46 , 56 is left at least partially uncured until male member 40 and female member 50 are interconnected.
- the conductive material of conductive center 46 , 56 can then be heated to a sufficient curing temperature so as to bond conductive center 46 to conductive center 56 .
- conductive centers 46 and 56 comprise a thermoplastic conductive elastomer, a solder, a metal, or a metal alloy
- conductive centers 46 and 56 are heated to a sufficient temperature to wet or reflow the conductive material thereof and, thereby, to bond each conductive center 46 , 56 to its corresponding contact pad 12 , 22 and to bond conductive center 46 to conductive center 56 .
Abstract
A method for fabricating an electrical interconnection element, or conductive structure, includes disposing a jacket of a first member of the electrical interconnection element laterally around a contact of a semiconductor device structure and introducing conductive material into the jacket. The jacket, which may be electrically insulative, may include a plurality of adjacent, mutually adhered regions. Such regions may be formed by programmed material consolidation processes, such as stereolithography, in which material is selectively consolidated in a manner controlled by a program. The first member is configured to interconnect with a second member of the electrical interconnection element, which may be secured to and electrically communicate with a contact of another semiconductor device component.
Description
- This application is a divisional of application Ser. No. 09/590,646, filed Jun. 8, 2000, pending. The disclosure of the previously referenced U.S. patent application referenced is hereby incorporated by reference in its entirety.
- 1. Field of the Invention
- The present invention relates generally to conductive structures for use with semiconductor device components, such as flip-chip type semiconductor devices, including chip-scale packages. Particularly, the present invention pertains to complementarily configured and located conductive structures on a semiconductor device and another substrate to which the semiconductor device is to be connected. The invention also relates to methods of fabricating the conductive structures and, more particularly, to the use of stereolithography to fabricate at least a portion of the conductive structures.
- 2. State of the Art
- Some types of semiconductor devices, such as flip-chip type semiconductor devices, including flip-chip type dice and ball grid array (BGA) packages (including chip-scale packages, or CSPs), can be connected to higher level substrates by orienting these semiconductor devices face down over the higher level substrate. The contact pads of such semiconductor devices are typically connected directly to corresponding contact pads of the higher level substrate by solder balls.
- Examples of solders that are known in the art to be useful in connecting semiconductor devices face down to higher level substrates include, but are not limited to, lead-tin (Pb/Sn) solder, silver-nickel (Ag/Ni) solder, copper, gold, and conductive or conductor-filled polymers. For example, 95/5 type Pb/Sn solder bumps (i.e., solder having about 95% by weight lead and about 5% by weight tin) have been used in flip-chip and ball grid array type attachments, including chip-scale packages (CSPs).
- When 95/5 type Pb/Sn solder bumps are employed as conductive structures to form a direct connection between a contact pad of a semiconductor device and a contact pad of a higher level substrate, a quantity of solder paste having a higher melting temperature, such as 63/37 type Pb/Sn solder, can be applied to the contact pad of the higher level substrate to facilitate bonding of the solder bump thereto. As the 95/5 type Pb/Sn solder and the 63/37 type Pb/Sn solder are heated to bond the solder bump to a contact pad of the substrate, the 95/5 type Pb/Sn solder, which has a lower melting temperature, softens first. Thus, the gravitational or compressive forces holding the semiconductor device in position over the higher level substrate can cause the softened 95/5 type Pb/Sn solder bump to flatten, pushing the solder laterally outward onto portions of the surface of the semiconductor device that surround the contact pad to which the solder bump is secured.
- Further, when solder balls are reflowed to connect a semiconductor device to a substrate, a phenomenon referred to as “outgassing” occurs, which can damage a semiconductor device proximate to the solder balls. Moreover, relatively high temperatures are required to reflow even low temperature solders, such as 95/5 type Pb/Sn solders. The reflow temperatures can damage package components, such as packaging or encapsulant materials, and even features of the semiconductor die being connected to the substrate.
- Assemblies that include semiconductor devices connected face down to higher level substrates are subjected to thermal cycling during further processing, testing thereof, and in normal use. As these assemblies undergo thermal cycling, the solder balls thereof are also exposed to wide ranges of temperatures, causing the solder balls to expand when heated and contract when cooled. Solder balls have a very different coefficient of thermal expansion than the primary materials of the semiconductor device and the substrate between which the solder balls are disposed. Thus, the amount that the solder balls expand and contract differs significantly from the amount of expansion and contraction of the semiconductor device and the substrate. As a result, repeated variations in temperatures can cause solder fatigue, which can reduce the strength of the solder balls, cause the solder balls to fail, and diminish the reliability of the solder balls. Thermal cycling can also alter the conformations of the conductive structures.
- The likelihood that a solder ball will be damaged by thermal cycling is particularly high when the solder ball spreads over and contacts the surface of the semiconductor device or the higher level substrate surrounding the contact pad. The solder ball loses some of its ability to dissipate heat and, therefore, can be exposed to the full range of temperatures that can occur during thermal cycling. Thus, flattened solder balls and solder balls that contact regions of the surface of a semiconductor device that surround the contact pads thereof are particularly susceptible to the types of damage that can be caused by thermal cycling of the semiconductor device.
- Furthermore, when solder balls contact regions of the semiconductor device that surround the contact pads to which the solder balls are secured, undesirable parasitic capacitance can occur.
- In an attempt to increase the reliability with which solder balls connect semiconductor devices face down to higher level substrates, resins have been applied to semiconductor devices to form collars around the bases of the solder balls protruding from the semiconductor devices. These resinous supports laterally contact the bases of the solder balls to enhance the reliability thereof. The resinous supports are applied to a semiconductor device after solder balls have been secured to the contact pads of the semiconductor device and before the semiconductor device is connected face down to a higher level substrate. As those of skill in the art are aware, however, the shapes of solder balls can change when bonded to the contact pads of a substrate. If the shapes of the solder balls change, the solder balls can fail to maintain contact with the resinous supports, which could thereby fail to protect or enhance the reliability of the solder balls.
- The use of solder balls in connecting a semiconductor device face down to higher level substrates is also somewhat undesirable from the standpoint that, due to their generally spherical shapes, solder balls consume a great deal of area, or “real estate,” on a semiconductor device. Thus, solder balls can unduly limit the minimum spacing between the adjacent contact pads of a semiconductor device and, thus, the minimum pitch of the contact pads on the semiconductor device.
- Other types of conductive structures have been used to connect semiconductor devices, including those with relatively tight contact pad pitches, to substrates. Examples of these alternative conductive structures include pillars of conductive elastomer or conductor filled epoxy. When such conductive pillars are secured to the contact pads of a semiconductor device, however, the conductive materials from which these conductive structures are fabricated can bleed. This may cause the material to flow onto regions of the semiconductor device surrounding the contact pad, which may cause parasitic capacitance or even electrical shorts when adjacent conductive structures bleed into contact with each other or a conductive structure bleeds onto an adjacent contact pad.
- The use of other conductive structures which have more desirable shapes, such as pillars, or columns, and mushroom-type shapes, and consume less conductive material than solder balls, to connect semiconductor devices face down to higher level substrates, has been limited since these taller and thinner conductive structures are typically made from materials that do not retain their shapes upon being bonded to the contact pads of a higher level substrate or in thermal cycling of the semiconductor device.
- The inventors are not aware of any art that discloses reinforced, self-aligning conductive structures that facilitate the connection of a semiconductor device to a substrate while preventing conductive material from bleeding or flowing over the edges of contact pads to which the conductive structures are secured. Moreover, the inventors are not aware of methods that can be used to fabricate such reinforced conductive structures.
- In the past decade, a manufacturing technique termed “stereolithography,” also known as “layered manufacturing,” has evolved to a degree where it is employed in many industries.
- Essentially, stereolithography, as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
- The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries. This is followed by selective consolidation or fixation of the material to at least a partially consolidated, or semisolid, state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer of the object to be fabricated. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which can be fixed and the minimum thickness of a layer that can be generated. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
- An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
- In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, pre-existing object or component to create a larger product.
- However, to the inventors' knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other, pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results is required. In particular, the inventor is not aware of the use of stereolithography in the fabrication of conductive structures protruding from the contact pads of semiconductor devices, such as flip-chip type semiconductor devices or chip-scale packages. Furthermore, conventional stereolithography apparatus and methods fail to address the difficulties of precisely locating and orienting a number of pre-existing components for stereolithographic application of material thereto without the use of mechanical alignment techniques or to otherwise assuring precise, repeatable placement of components.
- The present invention includes a reinforced, self-aligning conductive structure. The conductive structure includes interconnectable male and female members, each having a conductive center and a dielectric jacket formed from a thermally stable resin surrounding the conductive center.
- In one embodiment, the female member of the reinforced, self-aligning conductive structure is secured to or fabricated on a contact pad of one of a semiconductor device and a substrate, while the male member is secured to or fabricated on a corresponding contact pad of the other one of the substrate and the semiconductor device. Each of the male and female members include an outer dielectric support component that contains a quantity of conductive material in contact with the contact pad over which each of the members is disposed. The female member has a recess configured complementarily to at least an end of the male member so as to receive the end of the male member. Upon connection of the female and male members, the conductive center portions of the members contact each other to place the corresponding contact pads of the semiconductor device and the substrate in electrical communication with each other.
- According to another aspect, the invention includes a method for joining the conductive centers of an assembled male member and female member. The conductive material of each of the male and female members is preferably a thermally curable polymer. Preferably, the material of at least one of the conductive centers is at least partially uncured. Once the male and female members have been assembled, the material of the conductive centers can be fully cured to form an integral conductive center between a contact pad of the semiconductor device and a corresponding contact pad of the substrate. In addition, curing the conductive material of the male and female members following assembly thereof secures the semiconductor device to the substrate.
- Alternatively, other conductive materials, such as solders, metals, or metal alloys, can be employed as the conductive centers of each of the male and female members. The conductive centers of an interconnected male member and female member can be formed into an integral conductive center by reflowing the material of the conductive centers.
- A conductive structure incorporating teachings of the present invention surrounds the periphery of a contact pad exposed at the surface of a semiconductor device or substrate to confine the conductive material over the contact pad and to prevent the conductive material from bleeding or flowing onto portions of the surface of the semiconductor device or substrate that surround the contact pad.
- According to another aspect, the present invention includes a method for fabricating the reinforced conductive structure according to the present invention. In a preferred embodiment of the method, a computer-controlled, 3-D CAD initiated process known as “stereolithography” or “layered manufacturing” is used to fabricate the jacket of both the male and female members. When stereolithographic processes are employed, each jacket is formed as either a single layer or a series of superimposed, contiguous, mutually adhered layers of material.
- The stereolithographic method of fabricating the jackets of the present invention preferably includes the use of a machine vision system to locate the semiconductor devices or substrates on which the jackets are to be fabricated, as well as the features or other components on or associated with the semiconductor devices or substrates (e.g., contact pads, conductive traces, etc.). The use of a machine vision system directs the alignment of a stereolithography system with each semiconductor device or substrate for material disposition purposes. Accordingly, the semiconductor devices or substrates need not be precisely mechanically aligned with any component of the stereolithography system to practice the stereolithographic embodiment of the method of the present invention.
- In a preferred embodiment, the jackets to be fabricated or positioned upon and secured to a semiconductor device component in accordance with the invention are fabricated using precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser under control of a computer and responsive to input from a machine vision system, such as a pattern recognition system, to fix or cure selected regions of a layer of a liquid photopolymer material disposed on the semiconductor device or substrate.
- The jackets may be fabricated either separately from the semiconductor device or substrate to which they are to be secured or directly on the semiconductor device or substrate. If the jackets are fabricated directly on the semiconductor device or substrate, they may be fabricated around pre-formed quantities of conductive material protruding from the contact pads of the semiconductor device or substrate. Alternatively, the jackets may be fabricated around or over the peripheries of contact pads of the semiconductor device or substrate with the contact pads being exposed therethrough. Conductive material may then be disposed in the jackets and against the contact pads exposed therethrough.
- Following the fabrication of a hollow jacket, a quantity of unconsolidated (e.g., particulate, molten, or uncured liquid) conductive or conductor-filled material is disposed in the centers of the jackets. Alternatively, stereolithography may also be used to form the conductive centers of the male and female members from an electrically conductive photopolymer. If stereolithography is used to fabricate the conductive centers, the conductive center of at least one of a corresponding pair of members is preferably left at least partially unconsolidated so as to facilitate the subsequent formation of an integral conductive center through the conductive structure.
- Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.
-
FIG. 1 is a perspective view of a semiconductor device having male members of conductive structures protruding from the contact pads thereof and a carrier substrate having corresponding female members of the conductive structures protruding from the contact pads thereof; -
FIG. 2 is an enlarged partial perspective view of a male member on the semiconductor device ofFIG. 1 ; -
FIG. 3 is an enlarged partial perspective view of a female member on the substrate ofFIG. 1 ; -
FIG. 4 is a bottom plan view of the semiconductor device ofFIG. 1 ; -
FIG. 5 is a bottom plan view of the substrate ofFIG. 1 ; -
FIG. 6 is a cross-sectional view depicting the semiconductor device and the substrate ofFIG. 1 in an assembled relationship with the male members and the female members interconnected; -
FIG. 7 is a cross-sectional view depicting a semiconductor device and a substrate having another embodiment of the male and female members of the conductive structure in communication with a contact pad thereof; -
FIG. 8 is a cross-sectional view depicting another embodiment of the conductive structure, with the male and female members thereof secured to corresponding contact pads of a semiconductor device and a substrate; -
FIG. 9 is a cross-sectional view depicting yet another embodiment of the conductive structure, with the male and female members thereof secured to corresponding contact pads of a semiconductor device and a substrate; -
FIG. 10 is a perspective view of a portion of a wafer having a plurality of semiconductor devices thereon, depicting female members of the conductive structures being fabricated around each of the contact pads of the semiconductor devices at the wafer level; -
FIG. 11 is a schematic representation of an exemplary stereolithography apparatus that can be employed in the method of the present invention to fabricate the jacket of a male member of a conductive structure of the present invention; and -
FIG. 12 is a partial cross-sectional side view of a semiconductor device disposed on a platform of a stereolithographic apparatus for the formation of jackets of a male member of a conductive structure around the contact pads of the semiconductor device. - With reference to
FIGS. 1 and 4 -6, asemiconductor device assembly 10, including asemiconductor device 10 and asubstrate 20, is shown.Semiconductor device 10 is a flip-chip type device, such as a flip-chip die or a ball grid array package, or a flip-chip type chip-scale package having contact pads 12 (FIG. 6 ) on asurface 14 thereof that can each be bonded to corresponding contact pads 22 (FIG. 6 ) of asurface 24 ofsubstrate 20 by way ofconductive structures 30. - Each
conductive structure 30 has a separate, interconnectablemale member 40 andfemale member 50. As illustrated,male members 40 are secured to and protrude fromcontact pads 12 ofsemiconductor device 10, whilefemale members 50 are secured to and protrude fromcontact pads 22 ofsubstrate 20. - Referring now to
FIGS. 2 and 6 ,male members 40 each include adielectric jacket 42 with anaperture 44 extending through the length thereof.Aperture 44 is filled with a quantity of conductive material, referred to herein as aconductive center 46 ofmale member 40. Preferably,aperture 44 is completely filled with conductive material.Jacket 42 andaperture 44 are configured to contain the material ofconductive center 46 over acontact pad 12 and to, therefore, prevent the material ofconductive center 46 from bleeding or flowing off ofcontact pads 12 and onto the surrounding areas ofsurface 14.Jacket 42 also electrically insulates the lateral periphery ofconductive center 46. -
FIGS. 3 and 6 illustratefemale members 50, each of which has adielectric jacket 52 with anaperture 54 extending through the length thereof. As withmale member 40,jacket 52 andaperture 54 are configured to contain the conductive material ofconductive center 56 over acontact pad 22 ofsubstrate 20 and to prevent the material ofconductive center 56 from bleeding or flowing off ofcontact pads 22 and onto surrounding areas ofsurface 24.Jacket 52 also electrically insulates the lateral surfaces ofconductive center 56. Unlikeaperture 44 ofmale member 40,aperture 54 is preferably only partially filled with conductive material to form aconductive center 56 offemale member 50. Anupper portion 58 ofaperture 54, which is preferably not filled with conductive material, is configured to matingly receive at least an end portion ofmale member 40.Upper portion 58 is also referred to herein as a receptacle. - Turning to
FIG. 7 , an alternative embodiment of aconductive structure 30′ incorporating teachings of the present invention is illustrated.Conductive structure 30′ has amale member 40′, illustrated as being secured over acontact pad 12 ofsemiconductor device 10, and afemale member 50′, which, as illustrated, is secured to acontact pad 22 ofsubstrate 20. - As illustrated, the periphery of the
end portion 43′ ofjacket 42′ is smaller than the periphery of the remainder ofjacket 42′, with anouter ledge 48 being formed at the junction betweenend portion 43′ and the remainder, orbase portion 45′, ofjacket 42′. Whenmale member 40′ is interconnected withfemale member 50′, a complementarily configuredupper portion 58′ ofaperture 54′ receivesend portion 43′ ofmale member 40′ andledge 48 prevents further insertion ofmale member 40′ intoaperture 54′ offemale member 50′. Thus,outer ledge 48 defines a minimum length ofconductive structure 30′ and a minimum distance between an assembledsemiconductor device 10 andsubstrate 20. - With continued reference to
FIG. 7 , in addition tomale member 40′ including anouter ledge 48, or alternatively thereto,upper portion 58′ ofaperture 54′ can have a larger periphery than the remainder ofaperture 54′, with aninternal ledge 55 being formed at the junction betweenupper portion 58′ and the remainder ofaperture 54′.Internal ledge 55 acts as a stop formale member 40′ during insertion thereof intoaperture 54′ and preventsmale member 40′ from being inserted too far intoaperture 54′ offemale member 50′.Internal ledge 55 may also be used as a line of demarcation to identify an optimum level for fillingaperture 54′ with conductive material so as to facilitate an electrical communication between acontact pad 12 ofsemiconductor device 10 and acorresponding contact pad 22 ofsubstrate 20 while avoiding the use of an excessive quantity of conductive material asmale member 40′ andfemale member 50′ are interconnected. -
FIG. 8 illustrates another embodiment of aconductive structure 30″ according to the present invention, wherein the larger end of a frustoconically shaped or otherwise taperedmale member 40″ thereof is secured to acontact pad 22 ofsubstrate 20 and thefemale member 50″ thereof is secured to acontact pad 12 ofsemiconductor device 10.Female member 50″ has anaperture 54″ configured to receive at least anend portion 43″ of thejacket 42″ ofmale member 40″. The tapering of the outer surface ofjacket 42″ facilitates self-alignment ofmale member 40″ andfemale member 50″ whensemiconductor device 10 andsubstrate 20 are not precisely and accurately aligned. In addition,jacket 42″ may be tapered andaperture 54″ sized so as to permitmale member 40″ to insert only a predetermined, specific distance intoaperture 54″ offemale member 50″ and, thus, define a minimum length ofconductive structure 30″, as well as a minimum assembled distance betweensemiconductor device 10 andsubstrate 20. - Yet another embodiment of a
conductive structure 30′″ according to the present invention is illustrated inFIG. 9 . The male andfemale members 40′″, 50′″, respectively, ofconductive structure 30′″ each have substantially cylindrical shapes. The outer surface of thejacket 42′″ ofend 43′″ ofmale member 40′″, remote fromsemiconductor device 10 to whichmale member 40′″ is secured, tapers inwardly toward the center ofmale member 40′″.Female member 50′″ has anaperture 54′″ with an inner surface and an end remote fromsubstrate 20 to whichfemale member 50′″ is secured that tapers outwardly toward a periphery offemale member 50′″. The tapered ends 43′″, 53′″ ofmale member 40′″ andfemale member 50′″, respectively, are complementarily configured, thereby facilitating the receipt ofend 43′″ byend 53′″. Accordingly, upon interconnection ofmale member 40′″ andfemale member 50′″,conductive structure 30′″ has a substantially cylindrical shape. - Turning now to
FIG. 10 , awafer 72 with a plurality ofsemiconductor devices 10 thereon is illustrated. Eachsemiconductor device 10, which has yet to be singulated, or diced, fromwafer 72, hasfemale members 50 ofconductive structures 30 secured to the contact pads 12 (seeFIG. 8 ) thereof. Eachsemiconductor device 10 onwafer 72 is separated fromadjacent semiconductor devices 10 by astreet 74. - While the jackets of the male and female members of the conductive structures according to the present invention, including
jackets semiconductor devices 10 orsubstrates 20, such as prior to singulating semiconductor dice from awafer 72, the jackets of each of the members of the conductive structures can also be fabricated on or secured to collections ofindividual semiconductor devices 10 orsubstrates 20, or toindividual semiconductor devices 10 orsubstrates 20. As another alternative, the jackets can be substantially simultaneously fabricated on or secured to a collection of different types ofsemiconductor devices 10 orsubstrates 20. - The jackets of both members of the conductive structures of the present invention can be fabricated directly on
semiconductor devices 10 orsubstrates 20. Alternatively, the jackets can be fabricated separately fromsemiconductor devices 10 orsubstrates 20, then secured thereto as known in the art, such as by the use of a suitable adhesive. - The jackets are preferably fabricated from a photo-curable polymer, or “photopolymer,” by stereolithographic processes. When fabricated directly on a
semiconductor device 10 orsubstrate 20, the jackets can be made either before or after preformedconductive centers pads 12 ofsemiconductor device 10 or to contactpads 22 ofsubstrate 20. - For simplicity, the ensuing description is limited to an explanation of a method of fabricating
jackets 52 on asemiconductor device 10 prior to placing conductive material in contact withcontact pads 12 ofsemiconductor device 10. As should be appreciated by those of skill in the art, however, the method described herein is also useful for fabricating the jackets of other embodiments of the female member of a conductive structure according to the present invention on one or more semiconductor devices or substrates, as well as for fabricating the jackets of any embodiment of a male member of a conductive structure that incorporates teachings of the present invention on one or more semiconductor devices or substrates. -
FIG. 11 schematically depicts various components and operation of anexemplary stereolithography apparatus 80 to facilitate the reader's understanding of the technology employed in implementation of the method of the present invention, although those of ordinary skill in the art will understand and appreciate that apparatus of other designs and manufacture may be employed in practicing the method of the present invention. The preferred, basic stereolithography apparatus for implementation of the method of the present invention, as well as operation of such apparatus, are described in great detail in United States patents assigned to 3D Systems, Inc., of Valencia, Calif., such patents including, without limitation, U.S. Pat. Nos. 4,575,330; 4,929,402; 4,996,010; 4,999,143; 5,015,424; 5,058,988; 5,059,021; 5,059,359; 5,071,337; 5,076,974; 5,096,530; 5,104,592; 5,123,734; 5,130,064; 5,133,987; 5,141,680; 5,143,663; 5,164,128; 5,174,931; 5,174,943; 5,182,055; 5,182,056; 5,182,715; 5,184,307; 5,192,469; 5,192,559; 5,209,878; 5,234,636; 5,236,637; 5,238,639; 5,248,456; 5,256,340; 5,258,146; 5,267,013; 5,273,691; 5,321,622; 5,344,298; 5,345,391; 5,358,673; 5,447,822; 5,481,470; 5,495,328; 5,501,824; 5,554,336; 5,556,590; 5,569,349; 5,569,431; 5,571,471; 5,573,722; 5,609,812; 5,609,813; 5,610,824; 5,630,981; 5,637,169; 5,651,934; 5,667,820; 5,672,312; 5,676,904; 5,688,464; 5,693,144; 5,695,707; 5,711,911; 5,776,409; 5,779,967; 5,814,265; 5,850,239; 5,854,748; 5,855,718; 5,855,836; 5,885,511; 5,897,825; 5,902,537; 5,902,538; 5,904,889; 5,943,235; and 5,945,058. The disclosure of each of the foregoing patents is hereby incorporated herein by this reference. - With continued reference to
FIG. 11 and as noted above, a 3-D CAD drawing of an object to be fabricated in the form of a data file is placed in the memory of acomputer 82 controlling the operation ofapparatus 80 ifcomputer 82 is not a CAD computer in which the original object design is effected. In other words, an object design may be effected in a first computer in an engineering or research facility and the data files transferred via wide or local area network, tape, disc, CD-ROM, or otherwise, as known in the art, tocomputer 82 ofapparatus 80 for object fabrication. - The data is preferably formatted in an STL (for STereoLithography) file, STL being a standardized format employed by a majority of manufacturers of stereolithography equipment. Fortunately, the format has been adopted for use in many solid-modeling CAD programs, so translation from another internal geometric database format is often unnecessary. In an STL file, the boundary surfaces of an object are defined as a mesh of interconnected triangles.
-
Apparatus 80 also includes a reservoir 84 (which may comprise a removable reservoir interchangeable with others containing different materials) of anunconsolidated material 86 to be employed in fabricating the intended object. In the currently preferred embodiment, theunconsolidated material 86 is a liquid, photo-curable polymer, or “photopolymer,” that cures in response to light in the UV wavelength range. Thesurface level 88 ofmaterial 86 is automatically maintained at an extremely precise, constant magnitude by devices known in the art responsive to output of sensors withinapparatus 80 and preferably under control ofcomputer 82. A support platform orelevator 90, precisely vertically movable in fine, repeatable increments indirection 116 responsive to control ofcomputer 82, is located for movement downward into and upward out ofmaterial 86 inreservoir 84. - An object may be fabricated directly on
platform 90 or on a substrate disposed onplatform 90. When the object is to be fabricated on a substrate disposed onplatform 90, the substrate may be positioned onplatform 90 and secured thereto by way of one or more base supports 122 (seeFIG. 12 ). Such base supports 122 may be fabricated before or simultaneously with the stereolithographic fabrication of one or more objects onplatform 90 or a substrate disposed thereon. These supports 122 may support, or prevent lateral movement of, the substrate or object being formed relative to asurface 100 ofplatform 90.Supports 122 may also provide a perfectly horizontal reference plane for fabrication of one or more objects thereon, as well as facilitate the removal of a substrate or formed object fromplatform 90 following the stereolithographic fabrication of one or more objects on the substrate. Moreover, where a so-called “recoater”blade 102 is employed to form a layer of material onplatform 90 or a substrate disposed thereon, supports 122 can preclude inadvertent contact ofrecoater blade 102, to be described in greater detail below, withsurface 100 ofplatform 90. -
Apparatus 80 has a UV wavelength range laser plus associated optics and galvanometers (collectively identified as laser 92) for controlling the scan oflaser beam 96 in the X-Y plane acrossplatform 90.Laser 92 has associated therewith amirror 94 to reflectbeam 96 downwardly asbeam 98 towardsurface 100 ofplatform 90.Beam 98 is traversed in a selected pattern in the X-Y plane, that is to say, in a plane parallel tosurface 100, by initiation of the galvanometers under control ofcomputer 82 to at least partially cure, by impingement thereon, selected portions ofmaterial 86 disposed oversurface 100 to at least a partially consolidated (e.g., semisolid) state. The use ofmirror 94 lengthens the path of the laser beam, effectively doubling same, and provides a morevertical beam 98 than would be possible if thelaser 92 itself were mounted directly aboveplatform surface 100, thus enhancing resolution. - Referring now to
FIGS. 11 and 12 , data from the STL files resident incomputer 82 is manipulated to build an object, such asjacket 52, illustrated inFIGS. 1, 3 , and 5, or base supports 122, one layer at a time. Accordingly, the data mathematically representing one or more of the objects to be fabricated are divided into subsets, each subset representing a slice or layer of the object. The division of data is effected by mathematically sectioning the 3-D CAD model into at least one layer, a single layer or a “stack” of such layers representing the object. Each slice may be from about 0.0001 to about 0.0300 inch thick. As mentioned previously, a thinner slice promotes higher resolution by enabling better reproduction of fine vertical surface features of the object or objects to be fabricated. - When one or more base supports 122 are to be stereolithographically fabricated, supports 122 may be programmed as a separate STL file from the other objects to be fabricated. The primary STL file for the object or objects to be fabricated and the STL file for base support(s) 122 are merged.
- Before fabrication of a first layer for a
support 122 or an object is commenced, the operational parameters forapparatus 80 are set to adjust the size (diameter if circular) of the laser light beam used to curematerial 86. In addition,computer 82 automatically checks and, if necessary, adjusts by means known in the art, thesurface level 88 ofmaterial 86 inreservoir 84 to maintain same at an appropriate focal length forlaser beam 98. U.S. Pat. No. 5,174,931, referenced above and previously incorporated herein by reference, discloses one suitable level control system. Alternatively, the height ofmirror 94 may be adjusted responsive to a detectedsurface level 88 to cause the focal point oflaser beam 98 to be located precisely at the surface ofmaterial 86 atsurface level 88 iflevel 88 is permitted to vary, although this approach is more complex.Platform 90 may then be submerged inmaterial 86 inreservoir 84 to a depth equal to the thickness of one layer or slice of the object to be formed, and theliquid surface level 88 is readjusted as required to accommodatematerial 86 displaced by submergence ofplatform 90.Laser 92 is then activated solaser beam 98 will scan unconsolidated (e.g., liquid or powdered)material 86 disposed oversurface 100 ofplatform 90 to at least partially consolidate (e.g., polymerize to at least a semisolid state)material 86 at selected locations, defining the boundaries of afirst layer 122A ofbase support 122 and filling in solid portions thereof.Platform 90 is then lowered by a distance equal to thickness ofsecond layer 122B, andlaser beam 98 is scanned over selected regions of the surface ofmaterial 86 to define and fill in the second layer while simultaneously bonding the second layer to the first. The process may then be repeated as often as necessary, layer by layer, untilbase support 122 is completed.Platform 90 is then moved relative to mirror 94 to form any additional base supports 122 onplatform 90 or a substrate disposed thereon or to fabricate objects uponplatform 90,base support 122, or a substrate, as provided in the control software. The number of layers required to erectsupport 122 or one or more other objects to be formed depends upon the height of the object or objects to be formed and the desiredlayer thickness - If a
recoater blade 102 is employed, the process sequence is somewhat different. In this instance,surface 100 ofplatform 90 is lowered into unconsolidated (e.g., liquid)material 86 below surface level 88 a distance greater than a thickness of a single layer ofmaterial 86 to be cured, then raised abovesurface level 88 untilplatform 90, a substrate disposed thereon, or a structure being formed on eitherplatform 90 or a substrate thereon, is precisely one layer's thickness belowblade 102.Blade 102 then sweeps horizontally overplatform 90 or (to save time) at least over a portion thereof on which one or more objects are to be fabricated to removeexcess material 86 and leave a film of precisely the desired thickness.Platform 90 is then lowered so that the surface of the film andmaterial level 88 are coplanar and the surface of theunconsolidated material 86 is still.Laser 92 is then initiated to scan withlaser beam 98 and define thefirst layer 130. The process is repeated, layer by layer, to define each succeedinglayer 130 and simultaneously bond same to the nextlower layer 130 until all of the layers of the object or objects to be fabricated are completed. A more detailed discussion of this sequence and apparatus for performing same is disclosed in U.S. Pat. No. 5,174,931, previously incorporated herein by reference. - As an alternative to the above approach to preparing a layer of
material 86 for scanning withlaser beam 98, a layer of unconsolidated (e.g., liquid)material 86 may be formed onsurface 100 ofsupport platform 90, on a substrate disposed onplatform 90, or on one or more objects being fabricated by loweringplatform 90 toflood material 86 oversurface 100, over a substrate disposed thereon, or over the highest completed layer of the object or objects being formed, then raisingplatform 90 and horizontally traversing a so-called “meniscus” blade horizontally overplatform 90 to form a layer of unconsolidated material having the desired thickness overplatform 90, the substrate, or each of the objects being formed.Laser 92 is then initiated and alaser beam 98 scanned over the layer of unconsolidated material to define at least the boundaries of the solid regions of the next higher layer of the object or objects being fabricated. - Yet another alternative to layer preparation of unconsolidated (e.g., liquid)
material 86 is to merelylower platform 90 to a depth equal to that of a layer ofmaterial 86 to be scanned, and to then traverse a combination flood bar and meniscus bar assembly horizontally overplatform 90, a substrate disposed onplatform 90, or one or more objects being formed to substantially concurrentlyflood material 86 thereover and to define a precise layer thickness ofmaterial 86 for scanning. - All of the foregoing approaches to liquid material flooding and layer definition and apparatus for initiation thereof are known in the art and are not material to the practice of the present invention, therefore, no further details relating thereto will be provided herein.
- In practicing the present invention, a commercially available stereolithography apparatus operating generally in the manner as that described above with respect to
apparatus 80 ofFIG. 11 is preferably employed, but with further additions and modifications as hereinafter described for practicing the method of the present invention. For example and not by way of limitation, the SLA-250/50HR, SLA-5000 and SLA-7000 stereolithography systems, each offered by 3D Systems, Inc., of Valencia, Calif., are suitable for modification. Photopolymers believed to be suitable for use in practicing the present invention include Cibatool SL 5170 and SL 5210 resins for the SLA-250/50HR system, Cibatool SL 5530 resin for the SLA-5000 and 7000 systems, and Cibatool SL 7510 resin for the SLA-7000 system. All of these photopolymers are available from Ciba Specialty Chemicals Inc. - By way of example and not limitation, the layer thickness of
material 86 to be formed, for purposes of the invention, may be on the order of about 0.0001 to 0.0300 inch, with a high degree of uniformity. It should be noted that different material layers may have different heights so as to form a structure of a precise, intended total height or to provide different material thicknesses for different portions of the structure. The size of the laser beam “spot” impinging on the surface ofmaterial 86 to consolidate (e.g., cure) same may be on the order of 0.001 inch to 0.008 inch. Resolution is preferably ±0.0003 inch in the X-Y plane (parallel to surface 100) over at least a 0.5 inch×0.25 inch field from a center point, permitting a high resolution scan effectively across a 1.0 inch×0.5 inch area. Of course, it is desirable to have substantially this high a resolution across the entirety ofsurface 100 ofplatform 90 to be scanned bylaser beam 98, such area being termed the “field of exposure,” and being substantially coextensive with the vision field of a machine vision system employed in the apparatus of the invention as explained in more detail below. The longer and more effectively vertical the path oflaser beam 96/98, the greater the achievable resolution. - Referring again to
FIG. 11 , it should be noted thatapparatus 80 useful in the method of the present invention includes acamera 140 which is in communication withcomputer 82 and preferably located, as shown, in close proximity to optics andmirror 94 located abovesurface 100 ofsupport platform 90.Camera 140 may be any one of a number of commercially available cameras, such as capacitive-coupled discharge (CCD) cameras available from a number of vendors. Suitable circuitry as required for adapting the output ofcamera 140 for use bycomputer 82 may be incorporated in aboard 142 installed incomputer 82, which is programmed, as known in the art, to respond to images generated bycamera 140 and processed byboard 142.Camera 140 andboard 142 may together comprise a so-called “machine vision system” and, specifically, a “pattern recognition system” (PRS), operation of which will be described briefly below for a better understanding of the present invention. Alternatively, a self-contained machine vision system available from a commercial vendor of such equipment may be employed. For example, and without limitation, such systems are available from Cognex Corporation of Natick, Mass. For example, the apparatus of the Cognex BGA Inspection Package™ or the SMD Placement Guidance Package™ may be adapted to the present invention, although it is believed that the MVS-8000™ product family and the Checkpoint® product line, the latter employed in combination with Cognex PatMax™ software, may be especially suitable for use in the present invention. - It is noted that a variety of machine vision systems are in existence, examples of which and their various structures and uses are described, without limitation, in U.S. Pat. Nos. 4,526,646; 4,543,659; 4,736,437; 4,899,921; 5,059,559; 5,113,565; 5,145,099; 5,238,174; 5,463,227; 5,288,698; 5,471,310; 5,506,684; 5,516,023; 5,516,026; and 5,644,245. The disclosure of each of the immediately foregoing patents is hereby incorporated by this reference.
- In order to facilitate fabrication of one or more
dielectric jackets 52 in accordance with the method of the present invention withapparatus 80, a data file representative of the size, configuration, thickness and surface topography of, for example, a particular type and design ofsemiconductor device 10 or other substrate upon which one ormore jackets 52 are to be mounted, is placed in the memory ofcomputer 82. Also, asjackets 52 are configured to be interconnected with complementary jackets 42 (seeFIGS. 1 and 6 ) ofmale members 40 on another substrate, a data file representative of the substrate to whichmale members 42 are to be secured and the features thereof, as well as a data file representative ofmale members 40, may be placed in memory. - One or
more semiconductor devices 10, wafers 72 (seeFIG. 10 ), or other substrates may be placed onsurface 100 ofplatform 90 for fabrication of one or moredielectric jackets 52 aroundcontact pads 12 thereof. If one ormore semiconductor devices 10,wafers 72, or other substrates are to be held on or supported aboveplatform 90 by stereolithographically formed base supports 122, one or more layers ofmaterial 86 are sequentially disposed onsurface 100 and selectively altered by use oflaser 92 to form base supports 122. -
Camera 140 is then activated to locate the position and orientation of eachsemiconductor device 10, including those on a wafer 72 (seeFIG. 10 ), or other substrate upon which one or moredielectric jackets 52 are to be fabricated. The features of eachsemiconductor device 10,wafer 72, or other substrate are compared with those in the data file residing in memory, the locational and orientational data for eachsemiconductor device 10,wafer 72, or other substrate then also being stored in memory. It should be noted that the data file representing the design, size, shape and topography for eachsemiconductor device 10 or other substrate may be used at this juncture to detect physically defective or damagedsemiconductor devices 10 or other substrates prior to fabricatingjackets 52 thereon or before conducting further processing or assembly ofsemiconductor device 10 or other substrates. Accordingly, such damaged ordefective semiconductor devices 10 or other substrates can be deleted from the process of fabricatingjackets 52, from further processing, or from assembly with other components. It should also be noted that data files for more than one type (size, thickness, configuration, surface topography) of eachsemiconductor device 10 or other substrate may be placed in computer memory andcomputer 82 programmed to recognize not only the locations and orientations of eachsemiconductor device 10 or other substrate, but also the type ofsemiconductor device 10 or other substrate at each location uponplatform 90 so thatmaterial 86 may be at least partially consolidated bylaser beam 98 in the correct pattern and to the height required to definejackets 52 in the appropriate, desired locations on eachsemiconductor device 10 or other substrate. - Continuing with reference to
FIGS. 11 and 12 ,wafer 72 or the one ormore semiconductor devices 10 or other substrates onplatform 90 may then be submerged partially below thesurface level 88 ofliquid material 86 to a depth greater than the thickness of a first layer ofmaterial 86 to be at least partially consolidated (e.g., cured to at least a semisolid state) to form thelowest layer 130 of eachdielectric jacket 52 at the appropriate location or locations on eachsemiconductor device 10 or other substrate, then raised to a depth equal to the layer thickness,surface 88 ofmaterial 86 being allowed to become calm. Photopolymers that are useful asmaterial 86 exhibit a desirable dielectric constant, low shrinkage upon cure, are of sufficient (i.e., semiconductor grade) purity, exhibit good adherence to other semiconductor device materials, and have a similar coefficient of thermal expansion (CTE) to the material ofconductive centers 46, 56 (FIGS. 1-6 ) (e.g., solder or other metal or metal alloy, conductive resin, or conductive elastomer). Preferably, the CTE ofmaterial 86 is sufficiently similar to that of the material ofconductive centers semiconductor device 10 orsubstrate 20 in testing, subsequent processing, and subsequent normal operation. Exemplary photopolymers exhibiting these properties are believed to include, but are not limited to, the above-referenced resins from Ciba Specialty Chemicals Inc. One area of particular concern in determining resin suitability is the substantial absence of mobile ions and, specifically, fluorides. -
Laser 92 is then activated and scanned to directbeam 98, under control ofcomputer 82, toward specific locations ofsurface 88 relative to eachsemiconductor device 10 or other substrate to effect the aforementioned partial cure ofmaterial 86 to form afirst layer 52A of eachjacket 52.Platform 90 is then lowered intoreservoir 84 and raised a distance equal to the desired thickness of anotherlayer 52B of eachjacket 52, andlaser 92 is activated to add anotherlayer 52B to eachjacket 52 under construction. This sequence continues, layer by layer, until each of the layers ofjackets 52 have been completed. - In
FIG. 12 , the first layer of adielectric jacket 52 is identified by numeral 52A, and the second layer is identified by numeral 52B. Likewise, the first layer ofbase support 122 is identified by numeral 122A and the second layer thereof is identified by numeral 122B. As illustrated, bothbase support 122 andjacket 52 have only two layers.Jackets 52 with any number of layers are, however, within the scope of the present invention. - Each
layer dielectric jacket 52 is preferably built by first defining any internal and external object boundaries of that layer withlaser beam 98, then hatching solid areas ofjacket 52 located within the object boundaries withlaser beam 98. An internal boundary of a layer may compriseaperture 54, a through-hole, a void, or a recess injacket 52, for example. If a particular layer includes a boundary of a void in the object above or below that layer, thenlaser beam 98 is scanned in a series of closely-spaced, parallel vectors so as to develop a continuous surface, or skin, with improved strength and resolution. The time it takes to form each layer depends upon the geometry thereof, the surface tension and viscosity ofmaterial 86, and the thickness of that layer. - Alternatively,
dielectric jackets 52 may each be formed as a partially cured outer skin extending abovesurface 14 ofsemiconductor device 10 or abovesurface 24 ofsubstrate 20 and forming a dam within whichunconsolidated material 86 can be contained. This may be particularly useful where thejackets 52 protrude a relativelyhigh distance 60 fromsurface 14. In this instance,support platform 90 may be submerged so thatmaterial 86 enters the area within the dam, raised abovesurface level 88, and thenlaser beam 98 activated and scanned to at least partially curematerial 86 residing within the dam or, alternatively, to merely cure a “skin” comprising the surface ofdielectric jackets 52, a final cure of the material of thejackets 52 being effected subsequently by broad-source UV radiation in a chamber or by thermal cure in an oven. In this manner,jackets 52 of extremely precise dimensions may be formed ofmaterial 86 byapparatus 80 in minimal time. - When
dielectric jackets 52″, depicted inFIG. 8 , are being fabricated on a substrate, such assemiconductor device 10, having aconductive center 56″ already secured to thecontact pads 12 thereof, some ofmaterial 86 may be located in shadowed areas 53 (seeFIG. 8 ). Aslaser beam 98 is directed substantially vertically downwardly towardsurface 88 ofmaterial 86,material 86 located in shadowedregions 53 will not be contacted or altered bylaser beam 98. Nonetheless, theunconsolidated material 86 in shadowedareas 53 will become trapped therein asmaterial 86 adjacent to and laterally outward from shadowedareas 53 is at least partially consolidated and asjacket 52 is built up aroundconductive center 56″. Such trapped,unconsolidated material 86 will eventually cure due to the cross-linking initiated in the outwardly adjacent photopolymer, and the cure can be subsequently accelerated as known in the art, such as by a thermal cure. - Once
dielectric jackets 52, or at least the outer skins thereof, have been fabricated,platform 90 is elevated abovesurface level 88 ofmaterial 86 andplatform 90 is removed fromapparatus 80, along with any substrate (e.g.,semiconductor device 10, wafer 72 (seeFIG. 10 ), or other substrate) disposed thereon and any stereolithographically fabricated structures, such asjackets 52. Excess, unconsolidated material 86 (e.g., excess uncured liquid) may be manually removed fromplatform 90, from any substrate disposed thereon, and fromjackets 52. Eachsemiconductor device 10,wafer 72, or other substrate is removed fromplatform 90, such as by cutting the substrate free of base supports 122. Alternatively, base supports 122 may be configured to readily releasesemiconductor devices 10,wafers 72, or other substrates. As another alternative, a solvent may be employed to release base supports 122 fromplatform 90. Such release and solvent materials are known in the art. See, for example, U.S. Pat. No. 5,447,822 referenced above and previously incorporated herein by reference. -
Jackets 52 andsemiconductor device 10 orsubstrate 20 may also be cleaned by use of known solvents that will not substantially degrade, deform, ordamage jackets 52 or a substrate to whichjackets 52 are secured. - As noted previously,
jackets 52 may then require postcuring.Jackets 52 may have regions of unconsolidated material contained within a boundary or skin thereof or in a shadowed area 53 (seeFIGS. 8 and 9 ), ormaterial 86 may be only partially consolidated (e.g., polymerized or cured) and exhibit only a portion (typically 40% to 60%) of its fully consolidated strength. Postcuring to completely hardenjackets 52 may be effected in another apparatus projecting UV radiation in a continuous manner overjackets 52 or by thermal completion of the initial, UV-initiated partial cure. - It should be noted that the height, shape, or placement of each
jacket 52 on eachspecific semiconductor device 10 or other substrate may vary, again responsive to output ofcamera 140 or one or moreadditional cameras conductive centers 56 which could affect the desired distance thatjackets 52 will protrude fromsurface 14. Likewise, the lateral extent (i.e., diameter or width) of each preplaced conductive center may be recognized and the girth of the outer boundary of eachjacket 52 adjusted accordingly. In any case,laser 92 is again activated to at least partially curematerial 86 residing on eachsemiconductor device 10 or other substrate to form the layer or layers of eachjacket 52. - Although
FIGS. 11 and 12 illustrate the stereolithographic fabrication ofjackets 52 on a substrate, such as asemiconductor device 10, a wafer 72 (FIG. 10 ), or another substrate, including a plurality ofsemiconductor devices 10 or other substrates,jackets 52 can be fabricated separately from a substrate, then secured to a substrate by known processes, such as by the use of a suitable adhesive material. - The use of a stereolithographic process as exemplified above to fabricate
dielectric jackets 52 is particularly advantageous since a large number ofjackets 52 may be fabricated in a short time, the jacket height and position are computer controlled to be extremely precise, wastage ofunconsolidated material 86 is minimal, solder coverage of passivation materials is avoided, and the stereolithography method requires minimal handling ofsemiconductor devices 10,wafers 72, or other substrates. - Stereolithography is also an advantageous method of fabricating
dielectric jackets 52 according to the present invention since stereolithography can be conducted at substantially ambient temperature, the small spot size and rapid traverse oflaser beam 98 resulting in negligible thermal stress uponsemiconductor devices 10,wafers 72, or other substrates, as well as on the features thereof. - The stereolithography fabrication process may also advantageously be conducted at the wafer level or on multiple substrates, saving fabrication time and expense. As the stereolithography method of the present invention recognizes
specific semiconductor devices 10 orother substrates 20, variations between individual substrates are accommodated. Accordingly, when the stereolithography method of the present invention is employed,jackets 52 can be simultaneously fabricated on different types ofsemiconductor devices 10 or other substrates, as well as on bothsemiconductor devices 10 and other substrates. - Of course, other known methods can also be used to fabricate the jackets of the conductive structures of the present invention. Exemplary methods include, but are not limited to, the use of photoresist materials to form the reinforcement structures and fabrication of the reinforcement structure from dielectric materials using known semiconductor device patterning (e.g., mask and etch) processes.
- Referring again to
FIGS. 1-9 , as disclosed previously herein,conductive centers members dielectric jackets semiconductor device 10 andsubstrate 20. Preformedconductive centers contact pad semiconductor device 10 orsubstrate 20, respectively, by known processes, such as by thermal bonding. - When conductive centers 46, 56 are formed after
dielectric jackets pads 12 ofsemiconductor device 10 or to contactpads 22 ofsubstrate 20, conductive material is disposed in eachaperture jackets apertures - When a solder, metal, or metal alloy is used to form
conductive centers dielectric jackets jackets apertures jackets conductive centers apertures conductive centers - Conductive thermoplastic materials can similarly be disposed in
apertures conductive centers apertures conductive centers male member 40 andfemale member 50 are interconnected. - Thermally curable conductive resins can also be disposed in
apertures conductive centers conductive center female members male member 40 andfemale member 50 have been interconnected so as to allow for the full curing of the conductive resin and the formation of an integral conductive center extending throughconductive structure 30. - Referring again to
FIGS. 1 and 6 ,semiconductor device 10 is connected tosubstrate 20 by aligningmale members 40 protruding fromsemiconductor device 10 with correspondingfemale members 50 onsubstrate 20. The ends ofmale members 40 are then inserted intoupper portion 58 ofapertures 54 of their correspondingfemale members 50 such that theconductive centers male member 40 andfemale member 50, respectively, can communicate with one another. As noted previously herein,male member 40 may alternatively be secured tosubstrate 20 andfemale member 50 may alternatively be secured tosemiconductor device 10. - A single, integral conductive center can then be formed by bonding
conductive centers conductive centers conductive centers male member 40 andfemale member 50 are interconnected. The conductive material ofconductive center conductive center 46 toconductive center 56. Whenconductive centers conductive centers conductive center corresponding contact pad conductive center 46 toconductive center 56. - While the present invention has been disclosed in terms of certain preferred embodiments, those of ordinary skill in the art will recognize and appreciate that the invention is not so limited. Additions, deletions and modifications to the disclosed embodiments may be effected without departing from the scope of the invention as claimed herein. Similarly, features from one embodiment may be combined with those of another while remaining within the scope of the invention.
Claims (50)
1. A method for fabricating an electrical interconnection element for use with a semiconductor device structure, comprising:
providing at least one substrate having at least one contact pad exposed at a surface thereof; and
disposing at least a first member of an electrical interconnection element over the at least one contact pad, the first member having a conductive center and an insulative jacket configured to laterally contain material of the conductive center over the at least one contact pad, the first member being configured to connect with a complementary second member of the electrical interconnection element.
2. The method of claim 1 , wherein disposing at least the first member comprises securing the jacket to the at least one substrate with at least a portion of the at least one contact pad being exposed therethrough.
3. The method of claim 2 , further comprising:
disposing the conductive center in communication with the at least one contact pad after securing the jacket.
4. The method of claim 3 , wherein disposing the conductive center comprises disposing at least partially unconsolidated conductive material in communication with the at least one contact pad.
5. The method of claim 4 , wherein disposing at least partially unconsolidated conductive material comprises disposing at least partially uncured conductive resin in communication with the at least one contact pad.
6. The method of claim 4 , wherein disposing at least partially unconsolidated conductive material comprises disposing at least one of a solder paste, a molten solder, a metal, or a metal alloy, in communication with the at least one contact pad.
7. The method of claim 4 , wherein disposing at least partially unconsolidated conductive material comprises disposing an at least partially melted conductive elastomer in communication with the at least one contact pad.
8. The method of claim 3 , wherein disposing the conductive center comprises disposing a preformed conductive center in communication with the at least one contact pad.
9. The method of claim 1 , wherein disposing at least the first member comprises positioning the jacket around a conductive center secured to the at least one contact pad.
10. The method of claim 1 , wherein disposing at least the first member comprises fabricating the jacket on the surface.
11. The method of claim 10 , wherein fabricating comprises fabricating the jacket from a photopolymer.
12. The method of claim 3 , wherein fabricating comprises fabricating the jacket as at least two adjacent, mutually adhered regions.
13. The method of claim 1 , wherein providing comprises providing at least one semiconductor device.
14. The method of claim 13 , wherein providing comprises providing at least one semiconductor wafer with a plurality of semiconductor dice.
15. The method of claim 13 , wherein providing comprises providing at least one of a ball grid array package and a chip-scale package.
16. The method of claim 1 , wherein providing comprises providing at least one carrier substrate.
17. The method of claim 1 , wherein disposing comprises securing the jacket to the surface.
18. The method of claim 17 , further comprising:
prior to disposing, fabricating the jacket to have at least two adjacent, mutually adhered regions.
19. The method of claim 18 , wherein fabricating comprises fabricating at least one of the at least two regions from a photopolymer material.
20. A method for fabricating a semiconductor device component, comprising:
providing at least one substrate with at least one contact pad exposed at a surface thereof; and
sequentially forming at least one region of at least one jacket of a first member of a conductive structure on the surface around the at least one contact pad, the at least one jacket having an aperture formed through the length thereof and configured to laterally contain conductive material over the at least one contact pad, the at least one jacket configured to interconnect with a jacket of a second member of the conductive structure.
21. The method of claim 20 , wherein sequentially forming comprises forming the at least one region from a photopolymer.
22. The method of claim 20 , wherein providing comprises providing at least one semiconductor device.
23. The method of claim 22 , wherein providing comprises providing at least one wafer including a plurality of semiconductor dice.
24. The method of claim 22 , wherein providing comprises providing at least one of a ball grid array package and a chip-scale package.
25. The method of claim 20 , wherein providing comprises providing at least one carrier substrate.
26. The method of claim 20 , wherein sequentially forming comprises forming the aperture to have a larger periphery at an upper portion thereof than at a base portion thereof.
27. The method of claim 26 , wherein forming comprises forming an inner ledge between the upper portion and the base portion.
28. The method of claim 26 , wherein forming comprises forming at least a portion of a wall of the aperture to taper inwardly from the upper portion to the base portion.
29. The method of claim 20 , wherein sequentially forming comprises forming the at least one jacket to have an outer surface with a smaller periphery at an end thereof than at a base portion thereof.
30. The method of claim 29 , wherein forming comprises forming an outer ledge on the outer surface between the end and the base portion.
31. The method of claim 29 , wherein forming comprises forming at least a portion of the outer surface to taper outwardly from the end to the base portion.
32. The method of claim 31 , wherein forming comprises forming the at least one jacket to have a frustoconical configuration.
33. The method of claim 20 , further comprising:
disposing conductive material in the aperture.
34. The method of claim 33 , wherein disposing comprises substantially filling the aperture with the conductive material.
35. The method of claim 33 , wherein disposing comprises partially filling the aperture with the conductive material.
36. The method of claim 35 , wherein sequentially forming comprises forming the aperture to receive at least an end of the second member.
37. The method of claim 33 , wherein disposing comprises disposing at least partially unconsolidated conductive material in the aperture.
38. The method of claim 37 , wherein disposing comprises disposing at least partially uncured conductive resin in the aperture.
39. The method of claim 37 , wherein disposing at least partially unconsolidated conductive material comprises disposing at least one of a solder paste, a molten solder, a metal, and a metal alloy in the aperture.
40. The method of claim 37 , wherein disposing at least partially unconsolidated conductive material comprises disposing an at least partially melted conductive elastomer in the aperture.
41. The method of claim 20 , further comprising:
securing a preformed conductive center to the at least one contact pad.
42. The method of claim 41 , wherein securing the preformed conductive center is effected before the sequentially forming.
43. The method of claim 41 , wherein securing the preformed conductive center is effected after the sequentially forming.
44. A method for fabricating a semiconductor device component, comprising:
placing at least one substrate with contact pads in a horizontal plane;
recognizing a location and orientation of the at least one substrate; and
fabricating at least one jacket of a first member of a conductive structure by selectively consolidating material of the at least one jacket in a manner controlled by a program, the first member comprising at least one region of at least semisolid material on a surface of the at least one substrate, the at least one jacket around at least one contact pad of the contact pads, the at least one jacket protruding from the surface so as to laterally contain conductive material of a conductive center of the first member over at least a portion of the at least one contact pad, the first member being configured to connect with a complementarily configured second member of the conductive structure.
45. The method of claim 44 , further comprising:
storing data including at least one physical parameter of the at least one substrate and of the at least one jacket in computer memory, and using the stored data in conjunction with a machine vision system to recognize the location and orientation of the at least one substrate.
46. The method of claim 45 , further including, in computer memory, at least one physical parameter of the at least one contact pad around which the at least one jacket is to be fabricated.
47. The method of claim 45 , further including, in computer memory, at least one parameter of another substrate component with which the at least one substrate is to be assembled.
48. The method of claim 45 , further comprising:
using the stored data, in conjunction with the machine vision system, to effect fabricating the at least one jacket.
49. The method of claim 44 , further comprising:
recognizing a location of the at least one contact pad.
50. The method of claim 44 , further including securing the at least one substrate to a carrier prior to placing the at least one substrate in the horizontal plane.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/708,917 US20070148817A1 (en) | 2000-06-08 | 2007-02-20 | Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/590,646 US7557452B1 (en) | 2000-06-08 | 2000-06-08 | Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same |
US11/708,917 US20070148817A1 (en) | 2000-06-08 | 2007-02-20 | Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/590,646 Division US7557452B1 (en) | 2000-06-08 | 2000-06-08 | Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070148817A1 true US20070148817A1 (en) | 2007-06-28 |
Family
ID=38194351
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/590,646 Expired - Fee Related US7557452B1 (en) | 2000-06-08 | 2000-06-08 | Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same |
US11/708,917 Abandoned US20070148817A1 (en) | 2000-06-08 | 2007-02-20 | Methods for fabricating reinforced, self-aligning conductive structures for semiconductor device components |
US11/709,046 Abandoned US20070148818A1 (en) | 2000-06-08 | 2007-02-20 | Electrical connection methods employing corresponding, insulator-coated members of interconnection elements |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/590,646 Expired - Fee Related US7557452B1 (en) | 2000-06-08 | 2000-06-08 | Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/709,046 Abandoned US20070148818A1 (en) | 2000-06-08 | 2007-02-20 | Electrical connection methods employing corresponding, insulator-coated members of interconnection elements |
Country Status (1)
Country | Link |
---|---|
US (3) | US7557452B1 (en) |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080251948A1 (en) * | 2005-09-22 | 2008-10-16 | Chipmos Technologies Inc. | Chip package structure |
US20080268572A1 (en) * | 2005-09-22 | 2008-10-30 | Chipmos Technologies Inc. | Chip package |
US20090127704A1 (en) * | 2007-11-20 | 2009-05-21 | Fujitsu Limited | Method and System for Providing a Reliable Semiconductor Assembly |
US20100072631A1 (en) * | 2008-09-25 | 2010-03-25 | Commissariat A L'energie Atomique | Connection by fitting together two soldered inserts |
US20100151624A1 (en) * | 2005-09-22 | 2010-06-17 | Chipmos Technologies Inc. | Fabricating process of a chip package structure |
US20100219716A1 (en) * | 2009-02-27 | 2010-09-02 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Micro device having a movable structure |
US20140075747A1 (en) * | 2011-06-30 | 2014-03-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Connecting component equipped with hollow inserts |
US20150048504A1 (en) * | 2013-08-19 | 2015-02-19 | Ambit Microsystems (Zhongshan) Ltd. | Package assembly for chip and method of manufacturing same |
EP2943048A1 (en) * | 2014-05-05 | 2015-11-11 | Lockheed Martin Corporation | Board integrated interconnect |
EP2341583B1 (en) * | 2008-10-21 | 2017-05-31 | Asahi Denka Kenkyusho Co., Ltd. | Female connector, male connector assembled thereto, and electric/electronic apparatus using the connectors |
EP3326816A1 (en) * | 2016-11-29 | 2018-05-30 | CSEM Centre Suisse d'Electronique et de Microtechnique SA - Recherche et Développement | A process for reversibly connecting at least two elements with 3d printed connectors |
JP2019050348A (en) * | 2017-09-07 | 2019-03-28 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Printed circuit board |
US20190131260A1 (en) * | 2017-10-30 | 2019-05-02 | Micron Technology, Inc. | 3DI Solder Cup |
FR3119048A1 (en) * | 2021-01-21 | 2022-07-22 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | INTERCONNECTION WITH AME |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060064773A1 (en) * | 2004-06-28 | 2006-03-23 | Pioneer Hi-Bred International, Inc. | Cell cycle polynucleotides and polypeptides and methods of use |
US7262495B2 (en) * | 2004-10-07 | 2007-08-28 | Hewlett-Packard Development Company, L.P. | 3D interconnect with protruding contacts |
TWI393226B (en) * | 2004-11-04 | 2013-04-11 | Taiwan Semiconductor Mfg | Nanotube-based filler |
JP5074738B2 (en) * | 2006-10-24 | 2012-11-14 | リンテック株式会社 | Spacer sheet for composite semiconductor device and method for manufacturing composite semiconductor device |
US8211752B2 (en) * | 2007-11-26 | 2012-07-03 | Infineon Technologies Ag | Device and method including a soldering process |
US20100019185A1 (en) * | 2008-07-22 | 2010-01-28 | Honeywell International Inc. | Electrically conductive bonding means for device components |
US8309396B2 (en) * | 2009-01-26 | 2012-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for 3D integrated circuit stacking |
US20110169158A1 (en) * | 2010-01-14 | 2011-07-14 | Qualcomm Incorporated | Solder Pillars in Flip Chip Assembly |
US20110309481A1 (en) * | 2010-06-18 | 2011-12-22 | Rui Huang | Integrated circuit packaging system with flip chip mounting and method of manufacture thereof |
US8692390B2 (en) * | 2011-02-18 | 2014-04-08 | Chipbond Technology Corporation | Pyramid bump structure |
US8531040B1 (en) * | 2012-03-14 | 2013-09-10 | Honeywell International Inc. | Controlled area solder bonding for dies |
TWI488273B (en) * | 2012-07-18 | 2015-06-11 | Chipbond Technology Corp | Manufacturing method of semiconductor and semiconductor structure thereof |
JPWO2014033977A1 (en) * | 2012-08-29 | 2016-08-08 | パナソニックIpマネジメント株式会社 | Semiconductor device |
US9627347B2 (en) * | 2012-09-24 | 2017-04-18 | National Institute Of Advanced Industrial Science And Technology | Method of manufacturing semiconductor device and semiconductor device manufacturing apparatus |
US9773724B2 (en) * | 2013-01-29 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and semiconductor device packages |
JP6221499B2 (en) * | 2013-08-19 | 2017-11-01 | 富士通株式会社 | Electronic device and method of manufacturing electronic device |
TWI563606B (en) * | 2014-01-29 | 2016-12-21 | Siliconware Precision Industries Co Ltd | Package substrate as well as manufacturing method thereof and semiconductor package as well as manufacturing method thereof |
JP6476871B2 (en) * | 2014-05-22 | 2019-03-06 | 株式会社村田製作所 | Circuit board, power storage device, battery pack and electronic device |
US9711474B2 (en) * | 2014-09-24 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure with polymeric layer and manufacturing method thereof |
CN105448862B (en) * | 2014-09-29 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and preparation method thereof |
DE112016003737T5 (en) * | 2015-08-18 | 2018-05-03 | Mitsubishi Electric Corporation | SEMICONDUCTOR DEVICE |
JP6593447B2 (en) * | 2015-10-13 | 2019-10-23 | 株式会社村田製作所 | Resin substrate, component mounting resin substrate, resin substrate manufacturing method, component mounting resin substrate manufacturing method |
US9714012B1 (en) | 2016-01-22 | 2017-07-25 | International Business Machines Corporation | Power source element replacement during vehicle operation |
US9764703B2 (en) * | 2016-01-22 | 2017-09-19 | International Business Machines Corporation | Power source element detection and monitoring |
KR20170143125A (en) | 2016-06-20 | 2017-12-29 | 삼성전자주식회사 | Memory device including memory cell for generating reference voltage |
US10276539B1 (en) * | 2017-10-30 | 2019-04-30 | Micron Technology, Inc. | Method for 3D ink jet TCB interconnect control |
CN109979833A (en) * | 2019-03-10 | 2019-07-05 | 复旦大学 | A kind of quick room temperature micro convex point bonding method based on nested structure and annealing |
Citations (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173220A (en) * | 1991-04-26 | 1992-12-22 | Motorola, Inc. | Method of manufacturing a three-dimensional plastic article |
US5264061A (en) * | 1992-10-22 | 1993-11-23 | Motorola, Inc. | Method of forming a three-dimensional printed circuit assembly |
US5278442A (en) * | 1991-07-15 | 1994-01-11 | Prinz Fritz B | Electronic packages and smart structures formed by thermal spray deposition |
US5411400A (en) * | 1992-09-28 | 1995-05-02 | Motorola, Inc. | Interconnect system for a semiconductor chip and a substrate |
US5418471A (en) * | 1994-01-26 | 1995-05-23 | Emulation Technology, Inc. | Adapter which emulates ball grid array packages |
US5484314A (en) * | 1994-10-13 | 1996-01-16 | Micron Semiconductor, Inc. | Micro-pillar fabrication utilizing a stereolithographic printing process |
US5545367A (en) * | 1992-04-15 | 1996-08-13 | Soane Technologies, Inc. | Rapid prototype three dimensional stereolithography |
US5646442A (en) * | 1994-09-16 | 1997-07-08 | Yamaichi Electronics Co., Ltd. | Contact structure for IC socket |
US5705117A (en) * | 1996-03-01 | 1998-01-06 | Delco Electronics Corporaiton | Method of combining metal and ceramic inserts into stereolithography components |
US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
US5932891A (en) * | 1997-08-28 | 1999-08-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with test terminal and IC socket |
US5940679A (en) * | 1995-01-06 | 1999-08-17 | Matsushita Electric Industrial Co., Ltd. | Method of checking electric circuits of semiconductor device and conductive adhesive for checking usage |
US5959845A (en) * | 1997-09-18 | 1999-09-28 | International Business Machines Corporation | Universal chip carrier connector |
US6007349A (en) * | 1996-01-04 | 1999-12-28 | Tessera, Inc. | Flexible contact post and post socket and associated methods therefor |
US6251488B1 (en) * | 1999-05-05 | 2001-06-26 | Optomec Design Company | Precision spray processes for direct write electronic components |
US6259962B1 (en) * | 1999-03-01 | 2001-07-10 | Objet Geometries Ltd. | Apparatus and method for three dimensional model printing |
US6268574B1 (en) * | 1999-04-29 | 2001-07-31 | Rudolph R. Edens | Electrical and pneumatic lock-out device |
US6391251B1 (en) * | 1999-07-07 | 2002-05-21 | Optomec Design Company | Forming structures from CAD solid models |
US20020171177A1 (en) * | 2001-03-21 | 2002-11-21 | Kritchman Elisha M. | System and method for printing and supporting three dimensional objects |
US6506671B1 (en) * | 2000-06-08 | 2003-01-14 | Micron Technology, Inc. | Ring positionable about a periphery of a contact pad, semiconductor device components including same, and methods for positioning the ring around a contact pad |
US6524346B1 (en) * | 1999-02-26 | 2003-02-25 | Micron Technology, Inc. | Stereolithographic method for applying materials to electronic component substrates and resulting structures |
US6525408B2 (en) * | 2000-06-08 | 2003-02-25 | Micron Technology, Inc. | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
US20030043360A1 (en) * | 2001-08-30 | 2003-03-06 | Farnworth Warren M. | Methods and apparatus for stereolithographic processing of components and assemblies |
US20030151167A1 (en) * | 2002-01-03 | 2003-08-14 | Kritchman Eliahu M. | Device, system and method for accurate printing of three dimensional objects |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01136357A (en) * | 1987-11-24 | 1989-05-29 | Mitsubishi Electric Corp | Package for integrated circuit |
JPH0547984A (en) * | 1991-08-20 | 1993-02-26 | Nec Corp | Socket type package |
US5329423A (en) * | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
US5772451A (en) * | 1993-11-16 | 1998-06-30 | Form Factor, Inc. | Sockets for electronic components and methods of connecting to electronic components |
US5993554A (en) | 1998-01-22 | 1999-11-30 | Optemec Design Company | Multiple beams and nozzles to increase deposition rate |
US6583354B2 (en) * | 1999-04-27 | 2003-06-24 | International Business Machines Corporation | Method of reforming reformable members of an electronic package and the resultant electronic package |
-
2000
- 2000-06-08 US US09/590,646 patent/US7557452B1/en not_active Expired - Fee Related
-
2007
- 2007-02-20 US US11/708,917 patent/US20070148817A1/en not_active Abandoned
- 2007-02-20 US US11/709,046 patent/US20070148818A1/en not_active Abandoned
Patent Citations (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173220A (en) * | 1991-04-26 | 1992-12-22 | Motorola, Inc. | Method of manufacturing a three-dimensional plastic article |
US5278442A (en) * | 1991-07-15 | 1994-01-11 | Prinz Fritz B | Electronic packages and smart structures formed by thermal spray deposition |
US5545367A (en) * | 1992-04-15 | 1996-08-13 | Soane Technologies, Inc. | Rapid prototype three dimensional stereolithography |
US5411400A (en) * | 1992-09-28 | 1995-05-02 | Motorola, Inc. | Interconnect system for a semiconductor chip and a substrate |
US5264061A (en) * | 1992-10-22 | 1993-11-23 | Motorola, Inc. | Method of forming a three-dimensional printed circuit assembly |
US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
US5418471A (en) * | 1994-01-26 | 1995-05-23 | Emulation Technology, Inc. | Adapter which emulates ball grid array packages |
US5646442A (en) * | 1994-09-16 | 1997-07-08 | Yamaichi Electronics Co., Ltd. | Contact structure for IC socket |
US5484314A (en) * | 1994-10-13 | 1996-01-16 | Micron Semiconductor, Inc. | Micro-pillar fabrication utilizing a stereolithographic printing process |
US5940679A (en) * | 1995-01-06 | 1999-08-17 | Matsushita Electric Industrial Co., Ltd. | Method of checking electric circuits of semiconductor device and conductive adhesive for checking usage |
US6007349A (en) * | 1996-01-04 | 1999-12-28 | Tessera, Inc. | Flexible contact post and post socket and associated methods therefor |
US5705117A (en) * | 1996-03-01 | 1998-01-06 | Delco Electronics Corporaiton | Method of combining metal and ceramic inserts into stereolithography components |
US5932891A (en) * | 1997-08-28 | 1999-08-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with test terminal and IC socket |
US5959845A (en) * | 1997-09-18 | 1999-09-28 | International Business Machines Corporation | Universal chip carrier connector |
US20030102566A1 (en) * | 1999-02-26 | 2003-06-05 | Farnworth Warren M. | Stereolithographic method for applying materials to electronic component substrates and resulting structures |
US6524346B1 (en) * | 1999-02-26 | 2003-02-25 | Micron Technology, Inc. | Stereolithographic method for applying materials to electronic component substrates and resulting structures |
US6259962B1 (en) * | 1999-03-01 | 2001-07-10 | Objet Geometries Ltd. | Apparatus and method for three dimensional model printing |
US6268574B1 (en) * | 1999-04-29 | 2001-07-31 | Rudolph R. Edens | Electrical and pneumatic lock-out device |
US6251488B1 (en) * | 1999-05-05 | 2001-06-26 | Optomec Design Company | Precision spray processes for direct write electronic components |
US6391251B1 (en) * | 1999-07-07 | 2002-05-21 | Optomec Design Company | Forming structures from CAD solid models |
US6882049B2 (en) * | 2000-06-08 | 2005-04-19 | Micron Technology, Inc. | Support ring for use with a contact pad and semiconductor device components including the same |
US6525408B2 (en) * | 2000-06-08 | 2003-02-25 | Micron Technology, Inc. | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
US7109106B2 (en) * | 2000-06-08 | 2006-09-19 | Micron Technology, Inc. | Methods for providing support for conductive structures protruding from semiconductor device components |
US6548897B2 (en) * | 2000-06-08 | 2003-04-15 | Micron Technology, Inc. | Ring positionable about a periphery of a contact pad, semiconductor device components including same, and methods for positioning the ring around a contact pad |
US6569753B1 (en) * | 2000-06-08 | 2003-05-27 | Micron Technology, Inc. | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
US20030098499A1 (en) * | 2000-06-08 | 2003-05-29 | Salman Akram | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pad, semiconductor device components including same, and methods for fabricating same |
US6506671B1 (en) * | 2000-06-08 | 2003-01-14 | Micron Technology, Inc. | Ring positionable about a periphery of a contact pad, semiconductor device components including same, and methods for positioning the ring around a contact pad |
US6911735B2 (en) * | 2000-06-08 | 2005-06-28 | Micron Technology, Inc. | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
US20030203612A1 (en) * | 2000-06-08 | 2003-10-30 | Salman Akram | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same |
US6902995B2 (en) * | 2000-06-08 | 2005-06-07 | Micron Technology, Inc. | Ring positionable about a periphery of a contact pad, semiconductor device components including same, and methods for positioning the ring around a contact pad |
US20020171177A1 (en) * | 2001-03-21 | 2002-11-21 | Kritchman Elisha M. | System and method for printing and supporting three dimensional objects |
US20040142058A1 (en) * | 2001-08-30 | 2004-07-22 | Farnworth Warren M. | Apparatus and methods for use in stereolithographic processing of components and assemblies |
US6911173B2 (en) * | 2001-08-30 | 2005-06-28 | Micron Technology, Inc. | Methods for stereolithographic processing of components and assemblies |
US20030043360A1 (en) * | 2001-08-30 | 2003-03-06 | Farnworth Warren M. | Methods and apparatus for stereolithographic processing of components and assemblies |
US20030151167A1 (en) * | 2002-01-03 | 2003-08-14 | Kritchman Eliahu M. | Device, system and method for accurate printing of three dimensional objects |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7960214B2 (en) | 2005-09-22 | 2011-06-14 | Chipmos Technologies Inc. | Chip package |
US20080268572A1 (en) * | 2005-09-22 | 2008-10-30 | Chipmos Technologies Inc. | Chip package |
US20080251948A1 (en) * | 2005-09-22 | 2008-10-16 | Chipmos Technologies Inc. | Chip package structure |
US20100151624A1 (en) * | 2005-09-22 | 2010-06-17 | Chipmos Technologies Inc. | Fabricating process of a chip package structure |
US7981725B2 (en) | 2005-09-22 | 2011-07-19 | Chipmos Technologies Inc. | Fabricating process of a chip package structure |
US7847414B2 (en) | 2005-09-22 | 2010-12-07 | Chipmos Technologies Inc. | Chip package structure |
US20090127704A1 (en) * | 2007-11-20 | 2009-05-21 | Fujitsu Limited | Method and System for Providing a Reliable Semiconductor Assembly |
US8487428B2 (en) * | 2007-11-20 | 2013-07-16 | Fujitsu Limited | Method and system for providing a reliable semiconductor assembly |
US20100072631A1 (en) * | 2008-09-25 | 2010-03-25 | Commissariat A L'energie Atomique | Connection by fitting together two soldered inserts |
EP2175485A3 (en) * | 2008-09-25 | 2011-06-01 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Connection between two soldered inserts and method of manufacturing the same |
US8093728B2 (en) | 2008-09-25 | 2012-01-10 | Commissariat A L'energie Atomique | Connection by fitting together two soldered inserts |
FR2936359A1 (en) * | 2008-09-25 | 2010-03-26 | Commissariat Energie Atomique | CONNECTION BY EMBOITEMENT OF TWO INSERTS WELDED. |
EP2341583B1 (en) * | 2008-10-21 | 2017-05-31 | Asahi Denka Kenkyusho Co., Ltd. | Female connector, male connector assembled thereto, and electric/electronic apparatus using the connectors |
US20100219716A1 (en) * | 2009-02-27 | 2010-09-02 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Micro device having a movable structure |
US8368196B2 (en) * | 2009-02-27 | 2013-02-05 | Kabushiki Kaisha Toyota Chuo Kenkyusho | Micro device having a movable structure |
US20140075747A1 (en) * | 2011-06-30 | 2014-03-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Connecting component equipped with hollow inserts |
US10002842B2 (en) | 2011-06-30 | 2018-06-19 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method of producing a hybridized device including microelectronic components |
US20150048504A1 (en) * | 2013-08-19 | 2015-02-19 | Ambit Microsystems (Zhongshan) Ltd. | Package assembly for chip and method of manufacturing same |
US9386693B2 (en) | 2014-05-05 | 2016-07-05 | Lockheed Martin Corporation | Board integrated interconnect |
EP2943048A1 (en) * | 2014-05-05 | 2015-11-11 | Lockheed Martin Corporation | Board integrated interconnect |
JP2015213162A (en) * | 2014-05-05 | 2015-11-26 | ロッキード マーティン コーポレイションLockheed Martin Corporation | Board integrated interconnect |
KR20150126778A (en) * | 2014-05-05 | 2015-11-13 | 록히드 마틴 코포레이션 | Board integrated interconnect |
KR102045596B1 (en) | 2014-05-05 | 2019-11-15 | 록히드 마틴 코포레이션 | Board integrated interconnect |
EP3326816A1 (en) * | 2016-11-29 | 2018-05-30 | CSEM Centre Suisse d'Electronique et de Microtechnique SA - Recherche et Développement | A process for reversibly connecting at least two elements with 3d printed connectors |
JP2019050348A (en) * | 2017-09-07 | 2019-03-28 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Printed circuit board |
US20190131260A1 (en) * | 2017-10-30 | 2019-05-02 | Micron Technology, Inc. | 3DI Solder Cup |
US10483221B2 (en) * | 2017-10-30 | 2019-11-19 | Micron Technology, Inc. | 3DI solder cup |
US10964654B2 (en) | 2017-10-30 | 2021-03-30 | Micron Technology Inc. | 3DI solder cup |
US11532578B2 (en) | 2017-10-30 | 2022-12-20 | Micron Technology, Inc. | 3DI solder cup |
FR3119048A1 (en) * | 2021-01-21 | 2022-07-22 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | INTERCONNECTION WITH AME |
Also Published As
Publication number | Publication date |
---|---|
US7557452B1 (en) | 2009-07-07 |
US20070148818A1 (en) | 2007-06-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7557452B1 (en) | Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same | |
US7169693B2 (en) | Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same | |
US7109106B2 (en) | Methods for providing support for conductive structures protruding from semiconductor device components | |
US6630365B2 (en) | Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures | |
US7041533B1 (en) | Stereolithographic method for fabricating stabilizers for semiconductor devices | |
US7189600B2 (en) | Methods for fabricating stiffeners for flexible substrates | |
US20060189005A1 (en) | Methods for fabricating semiconductor devices so as to stabilize the same when contact-bearing surfaces thereof face over test substrates |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |