US20070176288A1 - Solder wall structure in flip-chip technologies - Google Patents
Solder wall structure in flip-chip technologies Download PDFInfo
- Publication number
- US20070176288A1 US20070176288A1 US11/275,867 US27586706A US2007176288A1 US 20070176288 A1 US20070176288 A1 US 20070176288A1 US 27586706 A US27586706 A US 27586706A US 2007176288 A1 US2007176288 A1 US 2007176288A1
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- United States
- Prior art keywords
- solder
- semiconductor chip
- wall
- solder bumps
- module substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 101
- 238000005516 engineering process Methods 0.000 title description 4
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 32
- 239000000919 ceramic Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 238000005272 metallurgy Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 4
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 229910002092 carbon dioxide Inorganic materials 0.000 description 4
- 239000001569 carbon dioxide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Definitions
- the present invention relates to flip-chip technologies, and more specifically, to a solder wall structure in flip-chip technologies.
- solder bumps are formed on top of a chip to help bond the chip to a ceramic substrate. These solder bumps may be corroded by carbon dioxide and water vapor of the surrounding ambient environment. Therefore, there is a need for a structure (and a method for forming the same), in which the solder bumps are not corroded by carbon dioxide and water vapor of the surrounding ambient.
- the present invention provides a semiconductor structure, comprising (a) a first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
- the present invention also provides a semiconductor fabrication method, comprising providing a first semiconductor chip; forming N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and forming a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
- the present invention also provides a semiconductor structure, comprising (a) a first semiconductor chip comprising a crack stop on a perimeter of the first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps, and such that the first solder wall is overlapping the crack stop; and (d) a module substrate coupled to the first solder wall and the N solder bumps
- FIGS. 1A-1G illustrate a fabrication method for forming a semiconductor structure, in accordance with embodiments of the present invention.
- FIG. 1F i shows a top-down view of the semiconductor structure of FIG. 1F , in accordance with embodiments of the present invention.
- FIG. 1G i shows a top-down view of a semiconductor chip after it is cut from the semiconductor structure of FIG. 1G , in accordance with embodiments of the present invention.
- FIG. 2 illustrates a fabrication method for forming a module, in accordance with embodiments of the present invention.
- FIGS. 1A-1G illustrate a fabrication method for forming a semiconductor structure 100 , in accordance with embodiments of the present invention. More specifically, with reference to FIG. 1A , in one embodiment, the fabrication of the semiconductor structure 100 starts with a semiconductor chip 102 and a dicing channel region 104 .
- the semiconductor chip 102 comprises multiple interconnect layers 106 a , 106 b , 106 c , and 106 d . There may be additional device layers in a silicon substrate of the semiconductor chip 102 beneath and coupled to the interconnect layer 106 d , but these additional device layers and the silicon substrate are not shown for simplicity. In the embodiment described above, there are only four interconnect layers 106 a , 106 b , 106 c , and 106 d . In general, the semiconductor chip 102 can have N interconnect layers, wherein N is a positive integer.
- the top interconnect layer 106 a of the semiconductor chip 102 includes (i) a dielectric layer 110 a , (ii) an electrically conducting line 120 a (comprising copper (Cu) in one embodiment) embedded in the dielectric layer 110 a , and (iii) a metal region 122 a (comprising Cu in one embodiment) embedded in the dielectric layer 110 a .
- the interconnect layers 106 b , 106 c , and 106 d comprise dielectric layers 110 b , 110 c , and 110 d , electrically conducting lines 120 b , 120 c , and 120 d (comprising Cu in one embodiment), and metal regions 122 b , 122 c , and 122 d (comprising Cu in one embodiment), respectively.
- the metal regions 122 a , 122 b , 122 c , and 122 d run on a perimeter of the semiconductor chip 102 and form a crack stop 122 surrounding the semiconductor chip 102 .
- the crack stop 122 is to prevent cracking from propagating from the dicing channel region 104 to the semiconductor chip 102 during a chip dicing process. It should be noted that from FIG. 1B to FIG. 1G , a bottom part of the structure 100 , which comprises the interconnect layers 106 b , 106 c , and 106 d , is omitted for simplicity, the only top interconnect layer 106 a is shown.
- portions of the dielectric layer 110 a are removed so as to create a hole 124 and a trench 126 such that top surfaces 125 and 127 of the Cu line 120 a and the crack stop 122 , respectively, are exposed to the surrounding ambient.
- the trench 126 runs along the crack stop 122 of the chip 102 .
- a bond pad 130 (comprising aluminum (Al) in one embodiment) is formed on top of the Cu line 120 a and the dielectric layer 110 a such that the Al bond pad 130 is electrically coupled to the Cu line 120 a .
- a wall base 132 (comprising Al in one embodiment) is formed on top of the crack stop 122 and the dielectric layer 110 a such that the Al wall base 132 is in direct physical contact with the crack stop 122 .
- the Al bond pad 130 and the Al wall base 132 can be simultaneously formed by (a) forming an Al layer (not shown) on the entire structure 100 , and then (b) directionally and selectively etching back the Al layer stopping at the dielectric layer 110 a .
- the directional and selective etching in step (b) may be performed using a traditional lithographic and etching process such that what remains of the Al layer after the etching are the Al bond pad 130 and the Al wall base 132 (as shown in FIG. 1B ).
- the Al wall base 132 runs along the crack stop 122 of the chip 102 (i.e. the Al wall base 132 runs on the perimeter of the semiconductor chip 102 ).
- a patterned support/interface layer 140 (comprising polyimide in one embodiment) is formed on top of the entire structure 100 of FIG. 1B .
- the patterned support/interface layer 140 comprises a hole 142 and a trench 146 such that (i) a top surface 144 of the Al bond pad 130 is exposed to the surrounding ambient environment via the hole 142 and (ii) a top surface 148 of the Al wall base 132 is exposed to the surrounding ambient environment via the trench 146 .
- the trench 146 runs along the Al wall base 132 of the chip 102 (i.e. the trench 146 runs on the perimeter of the semiconductor chip 102 ).
- the patterned support/interface layer 140 is formed using a photosensitive method. More specifically, the patterned support/interface layer 140 is formed by (i) spin-applying a polyimide film (not shown) on the structure 100 of FIG. 1B , (ii) then curing the polyimide film at a high temperature, (iii) then exposing the polyimide film to light through a mask (not shown) in a photo stepper lithographic tool (not shown), (iv) and then developing the polyimide film so as to form the patterned support/interface layer 140 .
- polyimide is a photosensitive polymer. In general, other photosensitive polymers may be used instead of polyimide.
- a bump limiting metallurgy (BLM) film 150 is formed on top of the entire structure 100 of FIG. 1C by, illustratively, sputter deposition or plating or a combination of sputter deposition and plating.
- a patterned photo-resist layer 160 is formed on top of the BLM film 150 .
- the patterned photo-resist layer 160 is formed by using a conventional lithographic process.
- the patterned photo-resist layer 160 comprises (i) a hole 162 aligned with the hole 142 and (ii) a trench 166 aligned with the trench 146 such that top surfaces 164 and 168 of the BLM film 150 are exposed to the surrounding ambient environment via the hole 162 and the trench 166 , respectively.
- the holes 142 and 162 can be collectively referred to as a hole 142 , 162 .
- the trenches 146 and 166 can be collectively referred to as a trench 146 , 166 .
- the trench 146 , 166 runs on the perimeter of the semiconductor chip 102 .
- a solder bump 170 (comprising a mixture of lead (Pb) and tin (Sn) in one embodiment) and a solder wall 172 (comprising a mixture of Pb and Sn in one embodiment) are simultaneously formed in the hole 142 , 162 and the trench 146 , 166 , respectively, by, illustratively, electroplating. More specifically, in one embodiment, the structure 100 is submerged in a solution (not shown) containing tin and lead ions. The BLM film 150 is electrically coupled to the cathode of an external dc (direct current) power supply (not shown), while the solution is electrically coupled to the anode of the dc supply.
- dc direct current
- solder wall 172 runs along the trench 146 , 166 (i.e. the solder wall 172 runs on the perimeter of the semiconductor chip 102 ).
- the patterned photo-resist layer 160 and portions of the BLM film 150 are removed by wet etching, RIE etching, or electro-etch, resulting in the solder bump 170 , the solder wall 172 , and BLM regions 150 of the structure 100 of FIG. 1F .
- FIG. 1F i shows a top-down view of the structure 100 of FIG. 1F , in accordance with embodiments of the present invention.
- the solder bump 170 and the solder wall 172 of FIG. 1F are reflowed at a high temperature, resulting in structure 100 of FIG. 1G .
- the solder bump 170 and the solder wall 172 of FIG. 1F are reflowed by subjecting them to a temperature lower than 400° C.
- the chip dicing process is performed wherein a blade (not shown) can be used to cut through the dicing channel region 104 , resulting in the separated semiconductor chip 102 in FIG. 1G i.
- FIG. 1G i shows a top-down view of the chip 102 after it is cut from the structure 100 of FIG. 1G , in accordance with embodiments of the present invention.
- the chip 102 can have multiple solder bumps 170 (similar to the solder bump 170 of FIG. 1G ). In one embodiment, these multiple solder bumps 170 and the solder wall 172 can be formed simultaneously using the fabrication process described above in FIGS. 1A-1G .
- the chip 102 is flipped upside down and bonded to a module substrate 180 (comprising ceramic in one embodiment), resulting in a module 200 in FIG. 2 .
- the multiple solder bumps 170 are bonded one-to-one to multiple substrate bump pads 182 of the ceramic module substrate 180
- the solder wall 172 is bonded to a substrate wall pad 184 of the ceramic module substrate 180 .
- the chip 102 in FIG. 2 is a cross-section view along a line 2 - 2 in FIG. 1G i.
- other chips can be bonded to the same ceramic module substrate 180 in a similar manner so as to form the multi-chip module 200 .
- the solder bumps 170 of the chip 102 are isolated from carbon dioxide and water vapor of the surrounding ambient environment by the chip 102 , the ceramic module substrate 180 , and the solder wall 172 .
Abstract
Description
- 1. Technical Field
- The present invention relates to flip-chip technologies, and more specifically, to a solder wall structure in flip-chip technologies.
- 2. Related Art
- In typical flip-chip technologies, solder bumps are formed on top of a chip to help bond the chip to a ceramic substrate. These solder bumps may be corroded by carbon dioxide and water vapor of the surrounding ambient environment. Therefore, there is a need for a structure (and a method for forming the same), in which the solder bumps are not corroded by carbon dioxide and water vapor of the surrounding ambient.
- The present invention provides a semiconductor structure, comprising (a) a first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
- The present invention also provides a semiconductor fabrication method, comprising providing a first semiconductor chip; forming N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; and forming a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
- The present invention also provides a semiconductor structure, comprising (a) a first semiconductor chip comprising a crack stop on a perimeter of the first semiconductor chip; (b) N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer; (c) a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps, and such that the first solder wall is overlapping the crack stop; and (d) a module substrate coupled to the first solder wall and the N solder bumps
- Therefore, there is a need for a structure (and a method for forming the same), in which the solder bumps are not corroded by carbon dioxide and water vapor of the surrounding ambient.
-
FIGS. 1A-1G illustrate a fabrication method for forming a semiconductor structure, in accordance with embodiments of the present invention. -
FIG. 1F i shows a top-down view of the semiconductor structure ofFIG. 1F , in accordance with embodiments of the present invention. -
FIG. 1G i shows a top-down view of a semiconductor chip after it is cut from the semiconductor structure ofFIG. 1G , in accordance with embodiments of the present invention. -
FIG. 2 illustrates a fabrication method for forming a module, in accordance with embodiments of the present invention. -
FIGS. 1A-1G illustrate a fabrication method for forming asemiconductor structure 100, in accordance with embodiments of the present invention. More specifically, with reference toFIG. 1A , in one embodiment, the fabrication of thesemiconductor structure 100 starts with asemiconductor chip 102 and adicing channel region 104. Thesemiconductor chip 102 comprisesmultiple interconnect layers semiconductor chip 102 beneath and coupled to theinterconnect layer 106 d, but these additional device layers and the silicon substrate are not shown for simplicity. In the embodiment described above, there are only fourinterconnect layers semiconductor chip 102 can have N interconnect layers, wherein N is a positive integer. - In one embodiment, the
top interconnect layer 106 a of thesemiconductor chip 102 includes (i) adielectric layer 110 a, (ii) an electrically conductingline 120 a (comprising copper (Cu) in one embodiment) embedded in thedielectric layer 110 a, and (iii) ametal region 122 a (comprising Cu in one embodiment) embedded in thedielectric layer 110 a. Similarly, theinterconnect layers dielectric layers lines metal regions metal regions semiconductor chip 102 and form acrack stop 122 surrounding thesemiconductor chip 102. In one embodiment, thecrack stop 122 is to prevent cracking from propagating from thedicing channel region 104 to thesemiconductor chip 102 during a chip dicing process. It should be noted that fromFIG. 1B toFIG. 1G , a bottom part of thestructure 100, which comprises theinterconnect layers top interconnect layer 106 a is shown. - Next, with reference to
FIG. 1B , in one embodiment, portions of thedielectric layer 110 a are removed so as to create ahole 124 and atrench 126 such thattop surfaces Cu line 120 a and thecrack stop 122, respectively, are exposed to the surrounding ambient. In one embodiment, thetrench 126 runs along thecrack stop 122 of thechip 102. - Next, in one embodiment, a bond pad 130 (comprising aluminum (Al) in one embodiment) is formed on top of the
Cu line 120 a and thedielectric layer 110 a such that theAl bond pad 130 is electrically coupled to theCu line 120 a. In one embodiment, a wall base 132 (comprising Al in one embodiment) is formed on top of thecrack stop 122 and thedielectric layer 110 a such that theAl wall base 132 is in direct physical contact with thecrack stop 122. Illustratively, theAl bond pad 130 and theAl wall base 132 can be simultaneously formed by (a) forming an Al layer (not shown) on theentire structure 100, and then (b) directionally and selectively etching back the Al layer stopping at thedielectric layer 110 a. The directional and selective etching in step (b) may be performed using a traditional lithographic and etching process such that what remains of the Al layer after the etching are theAl bond pad 130 and the Al wall base 132 (as shown inFIG. 1B ). In one embodiment, the Alwall base 132 runs along thecrack stop 122 of the chip 102 (i.e. theAl wall base 132 runs on the perimeter of the semiconductor chip 102). - Next, with reference to
FIG. 1C , in one embodiment, a patterned support/interface layer 140 (comprising polyimide in one embodiment) is formed on top of theentire structure 100 ofFIG. 1B . In one embodiment, the patterned support/interface layer 140 comprises ahole 142 and atrench 146 such that (i) atop surface 144 of the Albond pad 130 is exposed to the surrounding ambient environment via thehole 142 and (ii) atop surface 148 of theAl wall base 132 is exposed to the surrounding ambient environment via thetrench 146. In one embodiment, thetrench 146 runs along the Alwall base 132 of the chip 102 (i.e. thetrench 146 runs on the perimeter of the semiconductor chip 102). - In one embodiment, the patterned support/
interface layer 140 is formed using a photosensitive method. More specifically, the patterned support/interface layer 140 is formed by (i) spin-applying a polyimide film (not shown) on thestructure 100 ofFIG. 1B , (ii) then curing the polyimide film at a high temperature, (iii) then exposing the polyimide film to light through a mask (not shown) in a photo stepper lithographic tool (not shown), (iv) and then developing the polyimide film so as to form the patterned support/interface layer 140. It should be noted that polyimide is a photosensitive polymer. In general, other photosensitive polymers may be used instead of polyimide. - Next, with reference to
FIG. 1D , in one embodiment, a bump limiting metallurgy (BLM)film 150 is formed on top of theentire structure 100 ofFIG. 1C by, illustratively, sputter deposition or plating or a combination of sputter deposition and plating. - Next, with reference to
FIG. 1E , in one embodiment, a patterned photo-resist layer 160 is formed on top of the BLMfilm 150. In one embodiment, the patterned photo-resist layer 160 is formed by using a conventional lithographic process. In one embodiment, the patterned photo-resistlayer 160 comprises (i) ahole 162 aligned with thehole 142 and (ii) atrench 166 aligned with thetrench 146 such thattop surfaces 164 and 168 of theBLM film 150 are exposed to the surrounding ambient environment via thehole 162 and thetrench 166, respectively. It should be noted that theholes hole trenches trench trench semiconductor chip 102. - Next, in one embodiment, a solder bump 170 (comprising a mixture of lead (Pb) and tin (Sn) in one embodiment) and a solder wall 172 (comprising a mixture of Pb and Sn in one embodiment) are simultaneously formed in the
hole trench structure 100 is submerged in a solution (not shown) containing tin and lead ions. TheBLM film 150 is electrically coupled to the cathode of an external dc (direct current) power supply (not shown), while the solution is electrically coupled to the anode of the dc supply. Under the electric field created in the solution by the dc power supply, tin and lead ions in the solution arrive at the exposedsurfaces 164 and 168 of theBLM film 150 and deposit there forming thesolder bump 170 and thesolder wall 172, respectively, as shown inFIG. 1E . In one embodiment, thesolder wall 172 runs along thetrench 146,166 (i.e. thesolder wall 172 runs on the perimeter of the semiconductor chip 102). - Next, in one embodiment, the patterned photo-resist
layer 160 and portions of the BLM film 150 (that are not protected by thesolder bump 170 and the solder wall 172) are removed by wet etching, RIE etching, or electro-etch, resulting in thesolder bump 170, thesolder wall 172, andBLM regions 150 of thestructure 100 ofFIG. 1F . -
FIG. 1F i shows a top-down view of thestructure 100 ofFIG. 1F , in accordance with embodiments of the present invention. - Next, in one embodiment, the
solder bump 170 and thesolder wall 172 ofFIG. 1F are reflowed at a high temperature, resulting instructure 100 ofFIG. 1G . Illustratively, thesolder bump 170 and thesolder wall 172 ofFIG. 1F are reflowed by subjecting them to a temperature lower than 400° C. - Next, in one embodiment, the chip dicing process is performed wherein a blade (not shown) can be used to cut through the dicing
channel region 104, resulting in the separatedsemiconductor chip 102 inFIG. 1G i.FIG. 1G i shows a top-down view of thechip 102 after it is cut from thestructure 100 ofFIG. 1G , in accordance with embodiments of the present invention. It should be noted that thechip 102 can have multiple solder bumps 170 (similar to thesolder bump 170 ofFIG. 1G ). In one embodiment, thesemultiple solder bumps 170 and thesolder wall 172 can be formed simultaneously using the fabrication process described above inFIGS. 1A-1G . - Next, with reference to
FIG. 2 , in one embodiment, thechip 102 is flipped upside down and bonded to a module substrate 180 (comprising ceramic in one embodiment), resulting in amodule 200 inFIG. 2 . In one embodiment, themultiple solder bumps 170 are bonded one-to-one to multiplesubstrate bump pads 182 of theceramic module substrate 180, whereas thesolder wall 172 is bonded to asubstrate wall pad 184 of theceramic module substrate 180. It should be noted that thechip 102 inFIG. 2 is a cross-section view along a line 2-2 inFIG. 1G i. - In one embodiment, other chips (not shown, but similar to the
chip 102 ofFIG. 1G i) can be bonded to the sameceramic module substrate 180 in a similar manner so as to form themulti-chip module 200. - In summary, after the
chip 102 is bonded to theceramic module substrate 180, the solder bumps 170 of thechip 102 are isolated from carbon dioxide and water vapor of the surrounding ambient environment by thechip 102, theceramic module substrate 180, and thesolder wall 172. - While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.
Claims (20)
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