US20070204200A1 - High reliability memory module with a fault tolerant address and command bus - Google Patents
High reliability memory module with a fault tolerant address and command bus Download PDFInfo
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- US20070204200A1 US20070204200A1 US11/741,314 US74131407A US2007204200A1 US 20070204200 A1 US20070204200 A1 US 20070204200A1 US 74131407 A US74131407 A US 74131407A US 2007204200 A1 US2007204200 A1 US 2007204200A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
Definitions
- FIGS. 4A and 4B are schematic views of the ECC/ Parity register, shown in FIG. 3A ;
- Receiver 47 has an input coupled to the reset (/RST) signal line 37 .
- the inputs 35 a and 35 b (CEK 0 , CEK 1 ) 36 a and 36 ba (ODT 0 , ODT 1 ) are provided from the memory interface chip 18 and are not associated with the Chip Select (CS) inputs 33 a and 33 b , and signal from source 37 (/RST) driving amplifier 47 is an asynchronous reset input and, when low, resets all the primary latches 70 a through 70 e , 71 , 72 a through 72 n , 73 , 74 , 75 a , 75 b , 76 a , 76 b and all the secondary latches 92 a through 92 n , 93 , 94 , 95 a , 95 b , 96 a and 96 b thereby forcing the outputs low.
- This signal from source 37 ( /RST) also resets the error bus registers and error lines from the
- any double bit error will also be detected (as well as many other errors that are not correctable), and will be reported on the /Error (UE) error line (driven low for two clocks) and in the error bus registers if this error is the first since a Reset is issued.
- UE Error
- CS 0 - 1 are not included in the ECC logic, the propagation delay of the CS output signals will track the signals included in the ECC logic (1 additional clock of latency)
- each of these contacts is provided with a first contact on a first side of the DIMM and a redundant contact directly opposite the first contact on the opposite side of the DIMM.
- the voltage reference source 28 is applied via contact or pin 1 on the front side of the DIMM it is also applied via contact or pin 139 on the back side of the DIMM with contact 1 being direct opposite contact 139 .
- the SDA signal is applied via contact or pin 135 on the front side of the DIMM and also via the contact or pin 273 on the back side of the DIMM and the SCL signal is applied via contact or pin 136 on the front side of the DIMM and also via contact or pin 274 on the back side of the DIMM.
- unused ECC check bit inputs can be held at a low level, i.e., “0” thus ensuring that these inputs are at a known and quiescent state.
Abstract
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
Description
- This application is a continuation of U. S. patent application Ser. No. 10/413,605 filed Apr. 14, 2003, the contents of which are incorporated by reference herein in their entirety.
- This invention relates generally a high-reliability memory module with a fault tolerant address and command bus for use as a main memory that will achieve the degree of fault-tolerance and self-healing necessary for autonomic computing systems.
- Memory modules are well known to the prior art and have been and are presently being used in practical applications such as in computers and other equipment using solid state memories.
- Broadly speaking, currently available main memories offer bandwidths in the range of 1.6 to 2.6 GB/s, and although some memories provide for limited data path error correction most offer no means of any error correction. Furthermore, memory modules for server products usually include redrive logic for address and command inputs, and clock re-synchronization and redrive circuitry to ensure accurate clock timings at each device on the memory assembly. Although these solutions provide systems with the ability to achieve the specified bandwidth objectives, the overall quantity and types of failures in the memory subsystem, outside the data path itself, has actually increased due to the added circuitry associated with each memory device. Simultaneously, as servers are more widely utilized in business, many server applications simply cannot accept periodic unplanned system outages caused by failed memory modules. Thus the emphasis and need of improved overall system reliability is increasing dramatically and requires a comprehensive system solution that includes both a high degree of fault tolerance and overall reliability.
- The present invention provides such a comprehensive system solution that includes the high degree of fault tolerance and the overall differentiated system reliability long desired in the server market.
- Other possible solutions, such as memory mirroring, symbol slicing and extensive forms of fault rejection and redundancy, provide enhanced memory subsystem reliability, but, due to negative impacts such as increased cost, power, and reduced performance, have been considered only for niche applications where price is not of high importance as these subsystem quality enhancements are very expensive to implement. Therefore solutions suitable for the low or midrange server markets have not been available.
- Consequently the industry has long sought a simple, relatively inexpensive and reliable solution that provides differentiated product quality, that provides an adequate level of asset-protection that does not endanger the reliability of the system through the use of reduced-function memory assemblies and yet is cost competitive.
- The present invention is directed to a high reliability memory controller/interface module, provided with a high degree of compatibility with industry-standard solutions, capable of meeting the desired performance and reliability requirements and interfacing with the presently available memory modules, as well as with existing or enhanced support devices. The present invention accomplishes all these ends, resulting in an enhanced reliability memory solution at low cost.
- An object of the present invention is a 28 bit 1:2 register, intended for use with Dual line Memory Modules (DIMMs) having Dynamic Random Access Memory chips thereon. The register of the present invention has added thereto error correction code (ECC) logic to correct single bit errors on the command or address bus, and permit continuous memory operation independent of the existence of these errors.
- Another object of the present invention is to include in such DIMMs error latches and an error reporting mode whereby the system may interrogate the device to determine the error condition thereby allowing accurate fault determination and preventive maintenance—thereby reducing unplanned system outages.
- A further object of the present invention is to include redundant contacts on all connectors/DIMM interconnects that would otherwise be considered single points of failure whereby an intermittent or permanent contact failure would result in an unplanned system outage.
- Still another object of the present invention is to provide the DIMM with key operational features such as chip select gating of key inputs and programmable delay for un-gated inputs, thereby reducing module power and offering increased operational flexibility.
- A further object of the invention is to provide a DIMM that can be readily utilized in presently available controllers in a manner most applicable to the market needs.
- Another further object of the present invention is to have a DIMM that uses connectors similar to those presently in use so that prior art contacts, molds, handlers and related production tools can continue to be used such that the modules can be more cheaply produced with additional density while providing value-added reliability, and other value-add attributes, such as a higher memory packaging density with minimal additional production costs.
- The DIMM of the present invention is comprised of a printed circuit board having a front side and a back side and a plurality of dynamic random access memories (DRAMs) or synchronous dynamic random access memories (SDRAMs) affixed to both the front surface and the back surface. On a first edge of the front surface of said board there is provided one hundred and thirty eight (138) contacts for connecting circuitry, external to the card, to the SDRAMS and related devices on the DIMM and on the same first edge on the rear side of the card there is provided an additional one hundred and thirty eight (138) external circuitry connecting contacts so that the board has a total of two hundred and seventy six (276) external circuitry connecting contacts thereon. The contact means provided on the front and the back sides of the printed circuit card provide for electrically connecting the external circuitry to the SDRAMs in a direct or indirect maimer.
- Still another further object of the present invention is to provide a server memory structure having a dual inline memory module or DIMM provided with selective redundant contacts, a phase lock loop, 2 or 32K bit serial electronically erasable programmable read only memory (EE PROM) and a 28 bit, 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting register, read via an independent bus, and real time error lines for both correctable errors and uncorrectable error conditions. More particularly the server of the present invention comprises a novel DIMM provided with a new and unique ECC/ Parity Register coupled to the
memory interface chip 18 which is in turn coupled to the Memory controller orprocessor 19 such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. - Still another object of the invention is to provide for detecting if the module installed in the server can monitor the address and control bus integrity, correct errors on the address and control bus, report errors and log and counts errors.
- Still an other object of the invention is to provide for Parity error reporting in which the parity signal is delivered one cycle after the address and command to which it applies, and the error line be driven low two clocks after the address and command bits are driven to the DRAMs from the register on the DIMM. After holding the error line low for only 2 clock cycles, the driver can be disabled and the output permitted to return to an undriven state (high impedance) thus allowing this line to be shared by multiple modules.
- Still further the invention provides means for and a method for adjusting the propagation delay, fox signals on the memory module that are not included in the ECC circuitry, such that the signals can be selectively re-driven within one or two clock cycles.
- Still further the present invention permits operation of the memory module in parity mode, such that unused ECC check bit inputs are held at a low level thus ensuring that these inputs are at a known and quiescent state.
- Still further the present invention provides for reducing the probability of Single Point of Failures occurring by providing selected signals with redundant contacts directly on the opposite side of the DIMM from the original function contact thereby reducing the probability of a contact failure resulting in an unplanned system outage.
- Even further the present invention provides for operating a module of the present invention consistent with conventional non-ECC protected modules, by removing the secondary registers (post-ECC) from the delay path by setting the /ECC Mode control pin to a high level.
- These objects, features and advantages of the present invention will be become further apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings wherein:
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FIG. 1 is a block diagram of a typical server memory arrangement. -
FIG. 2 is a block diagram of the enhanced server memory arrangement of the present invention; -
FIGS. 3A and 3B are plan views respectively of the front and back of the two hundred and seventy six (276) pin dual inline memory module (DIMM) of the present invention; -
FIGS. 4A and 4B are schematic views of the ECC/ Parity register, shown inFIG. 3A ; -
FIG. 5 is a block diagram of the single error correction/ double error detection error correction code (SEC/DED ECC) circuit ofFIG. 4B ; -
FIG. 6 describes, in H-matrix form, the preferred ECC code selected for the module ofFIG. 3 ; -
FIGS. 7A, 7B and 7C show the designated contacts or pin connections for the DIMM ofFIGS. 3A and 3B ; and -
FIG. 8 shows the timing diagram used with the present invention. - A full appreciation of the features and advantages of the present invention can best be gained by reference to the drawings and more particularly to the figures where:
FIG. 1 is a block diagram of a typical server memory arrangement;FIG. 2 is a block diagram of the enhanced server memory arrangement of the present invention;FIGS. 3A and 3B are plan views respectively of the front and back of the 276 contact dual inline memory module (DIMM) of the present invention;FIGS. 4A and 4B are schematic views of the register, parity and error correction circuits shown inFIGS. 3A and 3B ;FIG. 5 is a block diagram of the single error correction/double error detection error correction code (SEC/DED ECC) circuit ofFIG. 4B ;FIG. 6 describes, in H-matrix, form the preferred ECC code selected for the module ofFIG. 3A ;FIGS. 7A, 7B and 7C show the designated pin connections for the DIMM ofFIGS. 3A and 3B andFIG. 8 shows the timing diagram used with the present invention. - In
FIG. 1 there is illustrated, in schematic form, a block diagram of a typical server memory arrangement as might be found in any currently available server which can employ a plurality of dual inline memory modules (DIMMs). It should be understood that many such DIMMs would be used in actual practice but for ease of illustration only one prior art DIMM 10 is shown inFIG. 1 DIMM 10 is a printed circuit card on which there is provided a plurality of either synchronous dynamic random access memories or dynamic randomaccess memories circuits 11, herein after collectively referred to as DRAM. EachDRAM 11 on theDIMM 10 has a plurality of output pins that are coupled, via the printed circuitry on the DIMM to the contacts on the DIMM and theses contacts are further coupled, via adata line 15, to amemory interface chip 18 and to a memory controller orprocessor 19. Each DRAM on the DIMM is further, coupled via such DIMM contacts, to aregister 12 and to a phase lockedloop circuit 14 on the DIMM. The phase locked loop 14 (PLL) is connected viaclock line 17 to thememory interface chip 18. Theregister 12 is also coupled to thememory interface chip 18 via an address and command (cmd)bus 16. Thememory interface chip 18 is coupled to thememory controller 19 via thedata line 15, address andcommand line 16 andClock line 17. It should be understood that although only one such DIMM is shown in this figure that in actuality the server would contain many such DMMs. Such other DIMMs would be coupled in a like maimer to thememory interface chip 18 andmemory controller 19 via data, address and command lines. Since such servers and their operation are so well known to those skilled in the art, further description of such servers and their operation is not deemed necessary. - Turning now to
FIGS. 2, 3A , 3B, 4A, 4B, 5 and 8 the enhanced server memory arrangement of the present invention will be described. - In
FIG. 2 there is illustrated, in schematic form, a block diagram of a server memory arrangement employing the present invention. In thisFIG. 2 the server comprises anovel DIMM 20 provided with a novel ECC/Parity Register chip 21 coupled to thememory interface chip 18 which is in turn coupled to the memory controller orprocessor 19. It should be understood that thechip 21 need not include both the ECC function and the parity function. For example, thechip 21 could have just the ECC function alone or just the parity function alone and still operate in accordance with the present invention. More specifically, as shown in thisFIG. 2 , thememory interface chip 18 sends and receives data from the DIMMs via thedata line 15 and sends address and commands vialine 16. Thememory interface chip 18 then sends and receives data, via line. 15, to the DRAMs and sends address and command information to theregister chip 21 via add/cmd line 16 and check bits for error correction purposes to the ECC/Parity register chip 21 vialine 25. -
FIGS. 3A and 3B show respectively the front and back views of thenovel DIMM 20 of the present invention. Generally speaking DIMMs are printed circuit cards designed to carry a plurality ofDRAMs 22 thereon and the DRAM output pins (not shown) are connected via the printed circuit to selectedconnectors 23 along the edge of both the back and front sides of the card and are often provided with a single indexing key ornotch 9 on the connector edge. The use and manufacture of such DIMMs is well known and need not be further described herein. The DIMM of the present invention however is novel and is designed to address several of the most significant contributors to unplanned and often catastrophic system outages encountered in the prior art DIMMs. The improvements in the DIMM of the present invention are realized especially by enlarging the length ofDIMM 20 to between 149 mm and 153 mm. Nominally theDIMM 20 is 151.35 mm (5.97 inches) long and its width is 30.48 mm (1.2 inches). The width of the DIMM is not critical and the DIMM need only be wide enough to accommodate the DRAMs installed thereon. The length of the DIMM however must be such that theDIMM 20 can accommodate additional signal contacts, up to 138, as well as up to thirty-sixDRAMs 26 having a body size up to 14 mm by 21 mm and have a locating key or notch 9 a distance of between 82.675 mm from one end of the DIMM and 68.675 mm from the other end of the DIMM as shown. Again it should be understood that these dimensions are nominal and may vary plus or minus 3 mm in various implementations. The DIMM can also be provided with additional notches 9 a and 9 b on each side, i.e., the shorter edges of theDIMM 20. These dimensions permit the DIMM, of the invention, to accommodate placing up to eighteen DRAMs on the front surface and up to an additional eighteen such DRAMs on the rear surface. Further, as shown inFIG. 3A , on the front of eachDIMM 20, in addition to the DRAMs, there is positioned a phase lockedloop chip 24 and the novel ECC/Parity Register chip 21 of the present invention. This novel ECC/Parity Register chip 21 will be further described below and in detail in conjunction withFIGS. 4A and 4B . It should be understood that the phase locked loop chip can be eliminated if its circuitry is provided on theregister chip 21. - This new, improved, larger
sized DIMM 20, shown in theseFIGS. 3A and 3B , also achieves a further significant improvement in the interconnect failure rate for the larger size of the module permits the connector system to accommodate two hundred and seventy-six contacts or pins 23. These pins are numbered and coupled to respective inputs as shown inFIGS. 7 a, 7 b, and 7 c. Contact or pin number one (1) is identified and shown inFIG. 3A ascontact 23A and is on the left hand side of the front side of theDIMM 20 and is positioned approximately 5.175 mm from the left edge of theDIMM 20 and 77.5 mm from the center of thenotch 9. Contact or pin number one hundred and thirty-eight (138) is identified and shown inFIG. 3A ascontact 23B and is on the right hand side of the front side of theDIMM 20 and is positioned approximately 5.175 mm from the right edge of theDIMM 20 and approximately 63.5 mm from the center of thenotch 9. Contact or pin number one hundred and thirty-nine (139) is identified and shown inFIG. 3B ascontact 23C and is directly opposite contact number one 23A and is also positioned approximately 5.175 mm from the left edge of theDIMM 20 and is also 77.5 mm from the center of thenotch 9. Contact or pin number two hundred and seventy-six (276) is identified in shown inFIG. 3B ascontact 23D and is directly opposite contact number one hundred and thirty-eight 23B and is also positioned approximately 5.175 mm from the right edge of theDIMM 20 and 63.5 mm from the center of thenotch 9. The greater size of thisDIMM 20 also accommodates the inclusion the new and a larger ECC/Parity register 21 required by the present invention. Because the two hundred and seventy-six contacts or pins 23 on this larger DIMM are more than sufficient to meet the needs of all the circuitry on the DIMM this means that the DIMM provides extra or redundant contacts. These extra or redundant contacts or pins 23 can now be used to provide additional protection for certain selected signal or voltage lines, for which error correction is not possible. The present invention by providing such redundant contacts effectively eliminates concerns such as contact failures on clock inputs, CS, CKE, and ODT inputs, Vref inputs, and other signals not protected by ECC. Other benefits include the elimination or reduction of concerns regarding power supply noise and/or voltage drops due to scarcity of voltage (VDD) contacts in the data region as well providing additional ground pins in the address/control region on theDIMM 20. The larger contact count of the present invention also permits theDIMM 20 to be wired such that they are consistent with prior art DIMMs. Theadditional contacts 23 also permit the inclusion of ECC check bits, associated with address and command inputs, allowing for real-time system monitoring of faults associated with these inputs, as well as system interrogation of fault counts and attributes. These faults would result in catastrophic system outages in conventional prior art systems using the smaller prior art DIMMs. - It should be understood that although only one
DIMM 21 is shown in theFIGS. 1 and 2 that, in actuality, the server would contain many such DIMMs. As noted above, theDIMM 21, of the present invention, is provided with a plurality ofSDRAMs 22, a phase lockedloop circuit 24 and the ECC/Parity register 21. The ECC/Parity register 21 onDIMM 20 includes unique error correction code (ECC) circuitry that is coupled to thememory interface chip 18 vialine 25 to provide even greater significant reliability enhancement to such servers. The inclusion of this new, improved error correction code (ECC) circuitry results in a significant reduction in interconnect failure. -
FIGS. 4A and 4B together comprise a schematic view of the novel ECC/Parity register 21 onDIMM 20 where, for clarity in description, it is shown as comprised of two distinct sections 21 a and 21 b.FIG. 4A shows theenhanced function 28 bit 1:2 register segment 21 a of the present invention andFIG. 4B shows the error correction code circuit segment 21 b. The error correction code circuit ECC segment 21 b, shown inFIG. 4B , corrects for single bit errors and thus permits continuous memory operation independent of the existence of these errors. This ECC segment also includes a parity operating mode circuitry together and error reporting circuitry. The novel ECC/Parity register 21 onDIMM 20 thus provides leading-edge performance and reliability and key operational features different from and unavailable from the prior art while retaining timing requirements generally consistent with theJEDEC 14 bit 1:2 DDR II register. - More particularly, the register segment 21 a contains a plurality of so called differential bit receivers 40 a through, 40 e, 41, 42 a through 42 n, 43, 44, 45 a, 45 b, 46 a and 46 b and a
single amplifier 47. Each of these differential receivers 40 a through 40 e, 41, 42 a through 42 n, 43, 44, 45 a, 45 b, 46 a and 46 b has two inputs and a single output. One of the inputs of each differential receiver 40 a through, 40 e, 41, 42 a through 42 n, 43, 44, 45 a, 45 b, 46 a and 46 b is coupled to areference voltage source 28. The second input of the each of the differential receivers 40 a through, 40 e, 41, 42 a through 42 n, 43, 44, 45 a, 45 b, 46 a and 46 b are coupled torespective inputs 30 a through, 30 e, 31, 32 a through 32 n, 33 a, 33 b, 34, 35 a, 35 b, 36 a and 36 b. - Receiver set 40 a through 40 e is comprised of five receivers of which only the first and the
last receivers 40 a and 40 e are shown. Receivers 40 a through 40 e have their second inputs respectively coupled to respectivecheck bit lines 30 a through 30 e and their outputs connected through respectiveprimary multiplexers 60 a through 60 e to the inputs of respectiveprimary latches 70 a through 70 e. Typically the check bit lines are contained in a bus that contains a set of five such check bit lines. However, for simplification of the drawing and ease of description only, Fig, 4 a shows only the first and the lastcheck bit lines 30 a and 30 e of the set and the first and last of the receivers 40 a through 40 e. It being understood that each receiver in the set 40 a through 40 e has one of its respective inputs coupled to a respective one of a set of check bitinput lines 30 a through 30 e and its output to a respective one of a set of three input multiplexers and thence to a respective one of a set of three input primary latches. - The second input of the
differential receiver 41 is coupled to acheck bit 0/Parity_in signal line 30. - Receiver set 42 a through 42 n is comprised of twenty two receivers coupled to a data line bus typically containing twenty two
data lines 32 a through 32 n. However, for simplification of the drawing and ease of description only, FIG, 4 a shows only the first and thelast data lines receivers 42 a through 42 n are shown in the drawing. Thefirst receiver 42 a is shown as having its first input coupled to data bitline 32 a and its output coupled to the first input ofmultiplexer 62 a whose output is coupled to a first input ofprimary latch 72 a and thelast receiver 42 n is shown as having its first input coupled to data bitline 32 n and its output coupled to the first input ofmultiplexer 62 n whose output is coupled to a first input of primary latch 72 n. Each respective receiver in set 42 a through 42 n has an input coupled to a respective one of data lines inset 32 a through 32 n and their outputs connected through respectiveprimary multiplexers 42 a through 42 n to the inputs of respectiveprimary latches 62 a through 62 n. All the primary multiplexers and latches in the set 42 a through 42 n are identical to those shown connected toreceivers memory interface chip 18 inFIG. 2 and are re-driven only when one or more of theinputs - As previously noted, the second input of the
differential receiver 41 is coupled to acheck bit 0/Parity13 insignal line 30. The output of thedifferential receiver 41 is coupled to an input ofmultiplexer 61 whose output is coupled to aprimary latch 71. Thecheck bit 0/Parity13 in signal is interpreted as an ECC check bit from the memory controller or as a parity bit depending on the setting of ECC mode input 136 (FIG. 4B )Clock inputs 131 are fed to all the primary latches 70 a through 70 e, 71, 72 a through 72 n, 73, 74, 75 a, 75 b, 76 a and 76 b. The Check bits 1-5 atinputs 30 a through 30 e are in a don't care state when the register is being operated in parity mode and will be held low. When these inputs are operated in parity mode, a parity in signal will be provided on theCheck bit 0/Parity13 insignal line 30 and maintain odd parity across thedata inputs 32 a through 32 n, at the rising edge of the clock signal (CK) atinput 131 that immediately follows the rising edge ofclock 131 that occurred simultaneously with the associateddata inputs 32 a through 32 n. - The second inputs of the
differential receivers differential receivers primary latches select NAND gate 63. The output ofNAND gate 63 is coupled to the selection input of themultiplexers 60 a through 60 e, 61 and 62 a through 62 n. These lines initiate DRAM address/command decodes and as such at least one will be low when a valid address/command signal is present and the register can be programmed to redrive all the data inputs when at least one chip select input (CS0, /CS1) 33 a, 33 b is low. The third input of thisNAND gate 63 is coupled to CS gate enablecircuit 34 which can be set low to causemultiplexers 60 a through 60 e to pass signals fromreceivers 32 a through 32 n independent of the levels oninputs - The output of
differential receiver lines FIG. 4B ) whose output is coupled to theerror logic circuit 100 also shown inFIG. 4 b. -
Receiver 45 a has an input coupled to the clock enablesignal source 35 a (CKE0) and an output coupled to theprimary latch 75 a. -
Receiver 45 b has an input coupled to the clock enablesignal sources 35 b (CKE0) and an output coupled to theprimary latch 75 b. -
Receiver 46 a has an input coupled to the on die termination linesignal input line 36 a (ODT0) and an output coupled to theprimary latch 76 a. -
Receiver 46 b has an input coupled to the on die terminationline signal line 36 b (ODT1) and an output coupled to theprimary latch 76 b. -
Receiver 47 has an input coupled to the reset (/RST)signal line 37. Theinputs memory interface chip 18 and are not associated with the Chip Select (CS)inputs amplifier 47 is an asynchronous reset input and, when low, resets all the primary latches 70 a through 70 e, 71, 72 a through 72 n, 73, 74, 75 a, 75 b, 76 a, 76 b and all the secondary latches 92 a through 92 n, 93, 94, 95 a, 95 b, 96 a and 96 b thereby forcing the outputs low. This signal from source 37 ( /RST) also resets the error bus registers and error lines from theerror logic circuit 100. - Coupled to the above described register of
FIG. 4A is the unique error correction code circuit arrangement ofFIG. 4B . - In
FIG. 4B , module location identification is provided to errorlogic circuit 100 which is more fully described in conjunction withFIG. 6 below. This module location identification is provided to errorlogic circuit 100 throughreceivers error logic circuit 100. The signals from sources (SA0, SA1, SA2) 78 a, 78 b and 78 c define the DIMM address which is then reported on the error bus when requested by the system. Thiserror logic circuit 100 is controlled by a signal from theNAND gate 175 when either of the DRAM chip select signal sources (/CS0) 33 a and (/CS1) 33 b are active. Theerror logic circuit 100 further has areset signal source 180 coupled thereto. - Also included in the error correction code circuit of
FIG. 4 b is a SEC/DED ECC circuit 90 which is more fully described in conjunction withFIG. 5 below. Coupled to this SEC/DED ECC circuit are the outputs ofprimary latches 70 a through 70 e, 71 and 72 a through 72 n. This SEC/DED ECC circuit 90 provides threeoutputs error logic circuit 100. These outputs are: a correctable error (CE)line 109, an uncorrectable error (UE)line 110 and a parityerror bit line 111 fed to theerror logic circuit 100 which provides outputs regarding correctable and uncorrectable errors onoutput lines logic error circuit 100 also provides an Error Bus (Inter Integrated circuit or IIC) 122 for external collection of error information such as error type, DIMM address, error count and status of the 28 input and internally generated syndrome bits at the time of the first fail. The information remains latched until a reset command is written tobus 122 or /RST input 37 is switched low. The selected IIC protocol allows unique byte addressing of the nine registers, consistent with the present industry standard protocol for serial program decode electronic erasable programmable read only memory (SPD EEPROM) and is well known to the art. - This SEC/
DED ECC circuit 90 also has data bit outputs coupled through secondary latches 92 a through 92 n to a first input of all the output or secondary multiplexers 102 a through 102 n. The output of register latches 72 a through 72 n labeled BYPASS are directly connected to the second input of the output or secondary multiplexers 102 a through 102 n thereby allowing the SEC/DED ECC circuit 90 to be bypassed depending on theECC mode input 123. - The output of the primary or register latches 73, 74, 75 a, 75 b, 76 a and 76 b are all coupled to a first input of secondary or output latches 93, 94, 95 a, 95 b, 96 a and 96 b and through these
secondary latches secondary multiplexers primary latches secondary multiplexers secondary latches Delay CKE input 124 and /ECC mode input 123. - A control circuit comprised of a
differential register 130 that has a first input coupled to aCK signal input 131, a second input coupled to a /CK signal input 132 and its output coupled to a second input all the primary latches 70 a through 70 e, 71, 72 a through 72 n, 73, 74, 75 a, 75 b, 76 a and 76 b and to the second input of all the output or secondary latches 92 a through 92 n, 93, 94, 95 a, 95 b, 96 a and 96 b and to theerror logic circuit 100 vialine 88. The /ECCmode signal source 135 is coupled to a selection third input of secondary multiplexers 102 a through 102 n, 103 and 104 and to theerror logic circuit 100. The output orsecondary multiplexers source 124 of /Delay, CKE13 ODT signals. - The ECC code selected for this module is a single error correction/ double error detection (SEC/DED) code and is shown in the H-Matrix depicted in
FIG. 6 . The use of this SEC/DED code ensures that all single errors associated with the address and control bits are detected and corrected and that all double bit errors are detected. It should be noted that interconnect failures almost exclusively begin as single point fails, with other failures possibly occurring over time dependent or independent of the root cause of the initial fail. - In summary the present invention describes unique DIMM having an enhanced 28 bit 1:2 register with added error correction code logic (ECC) incorporated therein for correcting single bit errors while permitting continuous memory operation independent of the existence of these errors. A parity operating mode is also provided, in conjunction with error reporting circuitry to permit the system to interrogate the device to determine the error condition.
- The above described 28 bit 1:2 register of the present invention provides key operational features, which differ from existing register designs intended for memory module applications and includes: Error detection and correction on key inputs; programmable delay for un-gated inputs; parity mode; reset circuitry; error reporting and identification and reporting of the DIMM address.
- CS gating of key inputs, e.g., /CS0 and /CS1, is provided as a means of reducing device power for the internal latches which will only be updated when one or both of the chip select CS) inputs are active low (and chip select gate enable tied high) at the rising edge of the system clock. The twenty two chip select-gated signals associated with this function include addresses continuously re-driven at the rising edge of every clock depending on the state of chip select. However, the chip select gating function can be disabled by tying the chip select gate enable input low thereby enabling all internal latches to be updated on every rising edge of clock.
- Programmable delay for un-gated inputs (/Delay CKE-ODT) associated with CKE and ODT (DRAM signals), the inputs will be latched and re-driven on each rising edge of the clock signal (CLK,) independent of the state of the chip select (CS) signals. However, since some controllers may be designed with limited flexibility regarding latency for these signals vs chip select (CS), address (Addr), row address strobe (RAS), column address strobe (CAS) and write enable (WE), a delay block can be selected to re-align the timing relationships which are offset by 1 clock when the error correction code circuitry (ECC) is enabled.
- ECC Mode (/ECC Mode low): For all inputs gated by CS, on-chip SEC/DED ECC logic is enabled and the signal received on CHK0/Parity in is received as
check bit 0 when /ECC Mode input is low. This ECC logic will operate across 28 inputs (22 ‘CS-gated inputs and the 6 check bits) and will correct all single bit errors and detect all double bit errors present on the twenty two chip select gated data inputs. If a correctable error is detected, /Error (CE) will be driven low for two clocks and errors will be counted and latched in the error bus registers for the 28 inputs if this is the first error since a reset is issued. Any double bit error will also be detected (as well as many other errors that are not correctable), and will be reported on the /Error (UE) error line (driven low for two clocks) and in the error bus registers if this error is the first since a Reset is issued. Although CS0-1 are not included in the ECC logic, the propagation delay of the CS output signals will track the signals included in the ECC logic (1 additional clock of latency) - In addition to the above ECC mode, the same twenty two chip select gated data signals can be operated in ‘parity mode (/ECC Mode high), whereby the signal received on CHK0/Parity in line is received as parity to the register one clock pulse later than the chip select gated data inputs. The received parity bit is then compared to the parity calculated across these same inputs by the register parity logic to verify that the information has not been corrupted. The twenty two chip select gated data signals will be latched and re-driven on the first clock pulse and any error will be reported two clock pulses later via the uncorrectable /Error (UE) line (driven low for two clock pulses) and in the Error Bus Registers. No correction of errors will be completed in this mode. The convention of parity, in this application, is odd parity (odd numbers of 1's across data and parity inputs equals valid parity).
- The /RST signal input is used to clear all internal latches (including the error registers), and all outputs will be driven low quickly except the error lines which will be driven high.
- Error reporting circuitry is included to permit external monitoring of DIMM operation. Two open-drain outputs are available to permit multiple modules to share a common signal line for reporting an error that occurred during a valid command (/CS=low) cycle (consistent with the re-driven signals). These two outputs are driven low for two clocks to allow the memory controller time to sense the error. /Error (CE) indicates that a correctable error occurred and was corrected by the ECC logic, /Error (UE) indicates that an uncorrectable error occurred and depending on the mode selected is an uncorrectable ECC error or a parity error. Note that the timing of/Error (UE) is different in parity mode vs. ECC mode.
- In addition, an error bus (9 registers that can be read and reset via an IIC bus) is available to permit the device to be interrogated for additional error information, such as the error type (correctable, uncorrectable or parity error), error count and the memory card location (via the SA0-2 address pins which are conventionally wired only to the separate serial program decode (SPD) electronic erasable programmable read only memory (EE PROM). Other information is also available for diagnostics such as the signals received by the register (address/command, control signals, check bits, parity bit) when a chip select (CS) is active low and the associated syndrome bits so that they can be decoded to determine which of the 28 input signals (22 ‘CS-gated
plus 6 check bits) or internal ECC logic failed. These registers will contain information about the first fail, and the error counter will continue to increment until it is reset or reaches the full count (64K). All registers can be reset by writing the reset error bus command on the IIC bus, or via the /RST pin. - In addition to the use of the ECC structure defined above (included in both the memory interface chip and the register on the DIMM), redundant contacts are included on the module pinout to effectively eliminate other possible SPOF (single-point-of-failure) contributors in the interconnect system. Contacts that cannot be protected by the ECC structure described above, for various reasons, include the following: voltage reference (Vref), Clocks, Chip Selects (CS), CKEs, ODTs, VSS /VDD contacts or pins, Error lines, data input on the IIC bus (SDA), data clock on the IIC bus (SCL) and related signals. In the present invention each of these contacts is provided with a first contact on a first side of the DIMM and a redundant contact directly opposite the first contact on the opposite side of the DIMM. For example if the
voltage reference source 28 is applied via contact orpin 1 on the front side of the DIMM it is also applied via contact or pin 139 on the back side of the DIMM withcontact 1 being direct opposite contact 139. Similarly the SDA signal is applied via contact or pin 135 on the front side of the DIMM and also via the contact or pin 273 on the back side of the DIMM and the SCL signal is applied via contact or pin 136 on the front side of the DIMM and also via contact or pin 274 on the back side of the DIMM. A full description of the contact or pin assignment matrix for the present invention is shown inFIGS. 7A, 7B and 7C. The specific contact placement is selected to maximize fault tolerance. By providing such opposite redundant contacts, problems caused, for example, by a slight bowing of the DIMM will cause low contact pressure on a contact on one side of DIMM but high pressure on the opposing contact. In such cases good signal flow will always be assured when such redundant and opposing contacts, as discussed above, are used. These opposing and redundant contacts will also facilitate board wiring by minimizing wiring congestion for this solution also permits in-line wiling. The following chart is a listing of the DIMM locations of a few of these contacts.NOMINAL CONTACT SIDE of DISTANCE FROM DIRECTION SIGNAL Or PIN # DIMM KEY FROM KEY CS0 86 FRONT 11.495 mm RIGHT CS0 224 BACK 11.495 mm LEFT CS1 91 FRONT 16.495 mm RIGHT CS1 229 BACK 16.495 mm LEFT CKE0 65 FRONT 13.505 mm LEFT CKE0 203 BACK 13.505 mm RIGHT CKE1 62 FRONT 16.505 mm LEFT CKE1 200 BACK 16.505 mm RIGHT RAS 222 BACK 9.495 mm LEFT CAS 87 FRONT 12.495 mm RIGHT WE 84 FRONT 9.495 mm RIGHT CK0 77 FRONT 2.495 mm RIGHT CK0 215 BACK 2.495 mm LEFT CK0B 78 FRONT 3.495 mm RIGHT CK0B 216 BACK 3.495 mm LEFT - The ECC function adds a single clock pulse delay (at planned operating frequencies) to the DIMM register performance, which may be of concern to some performance-optimized applications. As such, two additional modes are included on the module that permits the system user to tradeoff performance and reliability. In Parity Mode, the memory interface chip or controller would generate a single parity bit in conjunction with providing the full address and command field to the module. The module would re-drive the address and command bits, to the DRAMs, in the next cycle-rather than adding the additional cycle required in ECC mode. Any error on the address and command bus would be reported to the system at a later time, and the potential for recovery from the fail would be small hence this option is undesirable for many applications. The last mode would be to simply operate the memory in a mode with no parity bits and no ECC bits, with neither the added delay due to ECC nor any means to detect a fault on the address/command bus as per the prior art convention now used for these modules.
-
FIG. 5 is a block diagram of the SEC/DED ECC circuit ofFIG. 4B . The twenty twodata inputs 32 a through 32 n via the twenty twolatches 72 a through 72 n and lines 82 a through 82 n are fed both to a checkbit generator circuit 230 and a first input of a parity generator/checker circuit 231. The parity generator/checker circuit 231 further has a second input coupled to the parity insignal source 31 viaprimary latch 71 andoutput line 81 and depending on the state of the parity input signal oninput 31 sends a parity error signal (PERR) onoutput line 111 to theerror logic circuit 100. - Meanwhile the check
bit generator circuit 230 is transferring the twenty two inputted data signals to a first input of asyndrome bit generator 232 whose second input is coupled to thecheck bit inputs 30 a through 30 e through thelines 80 a through 80 e coming from the primary latches 70 a through 70 e. - The
Syndrome bit generator 232 then transfers the twenty two data signals to a first input of a syndrome bit decoder and the six check bits to theerror generator 235 which determines if there are either correctable or uncorrectable errors in the received data and provides the appropriate correctable error or uncorrectable error signal to theerror logic circuit 100 via eitherline data correction circuit 234. In the correction circuit the syndrome bits are selectively X ored with the data inputs consistent with the H-matrix, shown inFIG. 6 , with any single bit errors in the data field inverted to correct the error. - The
Error Logic block 100 consists of 3 major elements (not shown) which are an error counter, a status register block that contains a plurality of status registers, and an IIC logic block all of which are interconnected through common logic circuits. All of these blocks as well as the interconnecting logic circuits are common and readily available circuits known to those skilled in the art. - More specifically, the error counter is a 16-bit counter that increments as it receives errors inputs (CE, UE or Parity) from the SEC/
DED ECC 90. This error counter continues to count errors (until it reaches its full count) even while the status registers are being read out on the IIC bus. - The status register block includes, in the present case, nine eight bit register sets (0-8) which contain information on the data input (DO-21) signals, the check bit signals (C0-5 and Parity In) signals received from the
memory controller 19 as well as signals from the memory module 20 (FCC/Parity Mode, SAO-2), the error count, and the syndrome bits (S0-5) which are calculated by the SEC/DED ECC 90. - The IIC Logic block consists of the necessary logic to support the “IIC Bus Specifications Version 2.1 January 2000 Standard”. In this case the register is an IIC slave where the register is addressed by the DIMM address input range sources (SA0, SA1, SA2) 78 a, 78 b and 78 c and responds to several IIC bus commands-reset, read from the nine (9) Status Registers and the test mode.
- The miscellaneous logic circuits interconnecting the above described error counter, status register block and IIC logic block include logic circuits designed to reset the error counters and the nine (9) status registers from either the external reset signal (/RST)
source 37 or an internal power-on reset, to load the contents of the nine status registers and logic (including a set of shadow registers) that the IIC logic will send out onto the IIC bus when a IIC bus read occurs, along with some control logic to drive the correctable error (CE) and uncorrectable error (UE) lines out if such an error occurs. - The error bus that comprises nine (9) registers that can be read and reset via an IIC bus) permits the device to be interrogated for additional error information, such as the error type (correctable, uncorrectable or parity error), error count and the memory card location (via the SA0-2 address pins, also shared by the separate SPD EPROM). Other information is also available for diagnostics such as the signals received by the register (address/command, control signals, check bits, parity bit) associated with a CS is active low and the syndrome bits so that they can be decoded to determine, in the case of a failure, which of the 28 input signals (22 ‘CS-gated
plus 6 check bits) failed. These registers will contain information about the first fail, and the error counter will continue to increment until it is reset or reaches the full count (64K). All registers can be reset by writing the Reset Error Bus command on the IIC bus. - The Byte 0: Status Register is the general status bit register that can be read to determine the type of error, the mode and the address of the DIMM (same as the DIMM SPD address).
Byte 0: Status Register. Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0RFU 0DIMM DIMM DIMM Mode Parity ECCerror ECCerror Address SA2 Address Address 1= ECC Error 1= UE 1= CE SA1 SA0 0= Pty 1=PERR -
Bytes 1 and 2: Error Counter. - The 16 bit error counter will count up to 64K errors (FFFF hex) based on any error (CE, UE or Parity Error).
Byte 1 is the LSB audbyte 2 is the MSB of the error counter. Once the 16- bit counter has counted up to all ones, it will stay all 1's until the error bus is reset. The error counter register will not increment during a IIC read operation but will continue to count errors if they occur.Byte 1 (LSB) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0E7 E6 E5 E4 E3 E2 E1 E0 -
Byte 2 (MSB) Bit 7Bit 6Bit 5Bit 4Bit 3Bit2 Bit 1 Bit 0E15 E14 E13 E12 E11 E1O E9 E8 - Bytes 3-7: Data Registers.
- Bytes 3-7 show the polarity of all 28 signals of the addresses and commands plus the check bits and parity bit that were received at the time of the first fail.
Byte 3: Data Register A (DO-7) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0D7 D6 D5 D4 D3 D2 D1 D0 -
Byte 4: Data Register B (D8-15) Bit 7Bit 6Bit 5Bit 4Bit 3Bit2 Bit 1 Bit 0D15 D14 D13 D12 D11 D10 D9 D8 -
Byte 5: Data Register C (D16-21, CSO-1) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0CS1 CS0 D21 D20 D19 D18 D17 D16 -
Byte 6: Data Register D (CKE0-1, ODT0-1) Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0RFU RFU 0 RFU 0RFU 0ODT1 ODT0 CKE1 CKE0 0 -
Byte 7: Check Bit (CO-5) and Parity Register Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0RFU RFU 0 Check 5Check Check Check Check Check 0 Bit 4Bit 3Bit 2Bit 1Bit 0/Pty In - Byte 8: Syndrome Register
-
Byte 8 shows the syndrome bits associated with the first error. These can be decoded to determine which of the 22 ‘CS-gated signals or 6 Check Bits caused the fail. Bytes 3-7 show the polarity of all input signals at the time of the fail.FIG. 8 shows the timing diagram used with the present invention.Byte 8: Syndrome Bit (0-5) Register Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0RFU 0RFU 0Syndrome Syndrome Syndrome Syndrome Syndrome Syndrome Bit 5 Bit 4Bit 3Bit 2Bit 1Bit 0 - All the information necessary for one skilled in the art to design this
error logic block 100 is included in the H- Matrix shown inFIG. 6 where D0 through D21 indicate refer to the data bits, C0 through C5 refer to the check bits and S0 through S5 refer to the syndrome bits. In order to detect if the module installed in the server can properly monitor the address and control bus integrity, correct errors on the address and control bus, report errors and log and counts errors it is necessary that the DIMM error bus be functional and correctly accessed using the industry IIC protocol and the SA0-2 bits such that the DIMM can provide a byte of data which includesByte 0 discussed above. This is achieved by echoing back the SA 0-2 bits onbits Byte 0 and having bit 3 (the ECC flag bit) at a “1” or high level. This proves a unique signature. If the match does not occur the module is incapable of monitoring the address and control bus integrity, correcting errors on the address and control bus, reporting errors or logging and counting detected errors - Parity error reporting in the present invention is realized by delivering the parity signal one cycle after the address and command to which it applies, and driving the error line low, i.e., “0” two clock cycles after the address and command bits are driven to the DRAMs from the memory interface chip if an error is detected. After holding the error line low for only 2 clock cycles, the driver will be disabled and the output permitted to return to an undriven state (high impedance) allowing this line to be shared by multiple modules.
- The invention also provides a means for and a method for adjusting the propagation delay for signals on the memory module that are not included in the ECC circuitry such that the signals can be selectively re-driven within one or two clock cycles. This results in a significant increase in module operating speed.
- Moreover by operating the memory module in parity mode, unused ECC check bit inputs can be held at a low level, i.e., “0” thus ensuring that these inputs are at a known and quiescent state.
- Finally the module of the invention may be operated as if it were a conventional non-ECC protected module, by effective removing the secondary registers (post-ECC) from the delay path by setting the /ECC Mode control pin to a high level, i.e. “1 ”.
- In summary, the present invention is an
enhanced function 28 bit 1:2 register, intended for use on main memory modules. The register, of the present invention, adds ECC logic to correct single bit errors and permit continuous memory operation independent of the existence of these errors. A parity operating mode is also provided, in conjunction with error reporting circuitry to permit the system to interrogate the device to determine the error condition. - The present invention also provides CS gating of key inputs (/CS0, CS1, CS Gate Enable). As a means to reduce device power, the register's internal latches will only be updated when one or both of the CS inputs are active low (and CS Gate Enable tied high) at the rising edge of clock. The 22 CS-gated signals associated with this function include addresses (addr 0:15, BA 0:2). RAS, CAS, WE-with the remaining signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they are independent of CS. The CS gating function can be disabled by tying CS Gate Enable low enabling all internal latches to be updated on every rising edge of clock.
- Programmable delay for un-gated inputs (/Delay CKE-ODT) is also provided. For the pins associated with CKE and ODT (DRAM signals), the inputs will be latched and re-driven on each rising edge of CLK, independent of the state of the chip select (CS). However, since some controllers may be designed with limited flexibility regarding latency for these signals vs CS, Addr, RAS, CAS and WE. a delay block can be selected to re-align the timing relationships which are offset by one clock cycle when the error correction code is enabled.
- Also for all inputs gated by CS, the on-chip SEC/DED ECC logic is enabled and the signal received on CHK0/Parity In is received as
check bit 0 via a programming pin (/ECC Mode low). This ECC logic will operate across 28 inputs (22 CS-gated inputs and the 6 check bits), and will correct all single bit errors present on the 22 CS-gated inputs. /Error (CE) will be driven low for two clocks and errors will be counted and latched in the Error Bus Registers for the 28 inputs. Any double bit error will also be detected (as well as any error that is not correctable), and will be reported on the /Error (UE) error line (driven low for two clocks) and in the Error Bus Registers. Although CS0-1 are not included in the ECC logic, the propagation delay of the CS output signals will track the signals included in the ECC logic (1 additional clock of latency). - In addition to the above ECC mode, the same 22 CS-gated signals can be operated in ‘parity mode (/ECC Mode high), whereby the signal received on CHK0/Parity In is received as parity to the
register 1 clock later than the CS-gated inputs. The received parity bit is then compared to the parity calculated across these same inputs by the register parity logic to verify that the information has not been corrupted. The 22 ‘CS-gated signals will be latched and re-driven on the first clock and any error will be reported two clocks later via the /Error (UE) line (driven low for two clocks) and in the Error Bus Registers. No correction of errors will be completed in this mode. The convention of parity is odd parity (odd numbers of 1's across data and parity inputs equals valid parity). - The /RST pin is used to clear all internal latches (including the error registers), and all outputs will be driven low quickly except the error lines which will be driven high.
- The error reporting circuitry, of the present invention is included to permit external monitoring of device operation. Two open-drain outputs are available to permit multiple modules to share a common signal pin for reporting an error that occurred during a valid command (/CS=low) cycle (consistent with the re-driven signals). These two outputs are driven low for two clocks to allow the memory controller time to sense the error. /Error (CE) indicates that a correctable error occurred and was corrected by the ECC logic. /Error (UE) indicates that an uncorrectable error occurred and depending on the mode selected is an uncorrectable ECC error or a parity error. Note that the timing of UE is different in parity mode vs. ECC mode.
- In addition, the error bus, (the nine registers discussed above that can be read and reset via an IIC bus) is available to permit the device to be interrogated for additional error information, such as the error type (correctable, uncorrectable or parity error), error count and the memory card location (via the SA0-2 address pins, also shared by the separate SPD EPROM). Other information is also available for diagnostics such as the signals received by the register (address/command, control signals. check bits, parity bit) when a CS is active low and the syndrome bits so that they can be decoded to determine which of the 28 input signals (22 CS-gated
plus 6 check bits) failed. These registers will contain information about the first fail, and the error counter will continue to increment until it is reset or reaches the full count (64K). All registers can be reset by writing the Reset Error Bus command on the IIC bus. - This completes the description of the preferred embodiment of the invention. Since changes may be made in the above construction without departing from the scope of the invention described herein, it is intended that all the matter contained in the above description or shown in the accompanying drawings shall be interpreted in an illustrative and not in a limiting sense. Thus other alternatives and modifications will now become apparent to those skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.
Claims (27)
1. A dual in-line memory module (DIMM) comprising:
a rectangular printed circuit board having a first side and a second side, a length of between 148.35 and 154.35 millimeters (mm) and first and second ends having a width smaller than said length;
a first plurality of connector locations on said first side extending along a first edge of said board that extends the length of the board;
a second plurality of connector locations on said second side extending on said first edge of said board;
a locating key having its center positioned on said first edge and located between 79.675 mm and 86 mm from said first end of said card and located between 65.675 and 71.675 mm from said second end of said card.
2. The DIMM of claim 1 wherein there is further provided on one or more of said first and second sides:
multiple dynamic random access memories (DRAMs);
a phase lock loop circuit; and
a 28 bit 1 to 2 register circuit having error correction code (ECC) across data inputs, parity checking, and a real time error line for reporting both correctable errors and uncorrectable error conditions.
3. The DIMM of claim 1 wherein there is further provided on one or more of said first and second sides:
multiple DRAMs;
a phase lock loop circuit; and
a 28 bit 1 to 2 register circuit having error correction code (ECC) across data inputs and a real time error line for reporting both correctable errors and uncorrectable error conditions.
4. The DIMM of claim 2 wherein there are 22 data inputs to the register ECC circuitry.
5. The DIMM of claim 1 wherein said multiple DRAMs are mounted on said first side of said printed circuit board.
6. The DIMM of claim 1 wherein said multiple DRAMs are mounted on said second side of said printed circuit board.
7. The DIMM of claim 1 wherein the output pins of said multiple DRAMS are connected to selected ones of said connector locations on said board.
8. The DIMM of claim 1 wherein the first edge of the first side of said board has one hundred and thirty-eight (138) connector locations and an identical plurality of connector locations on the said first edge of the second side of said board for a total of two hundred and seventy-six (276) contacts on said board.
9. The DIMM of claim 1 wherein selected contacts on said first side surface are coupled to selected contacts on said second side to provide redundant contacts for selected signals.
10. The DIMM of claim 1 wherein;
a selected number of said contacts on said first side are commonly connected to a selected number of contacts on said second side to provide said card with a selected number of redundant contacts, and the DIMM further comprises:
a plurality of DRAMs on one or more of said first and second sides;
a 2 or 32K bit serial EE PROM and a 28 bit 1 to 2 register circuit chip having ECC, a multi-byte fault reporting register, read via an independent bus, and real time error lines for both correctable errors and uncorrectable error conditions; and
a phase lock loop circuit coupled to said DRAMs and to said register circuit chip.
11. The DIMM of claim 1 wherein;
a selected number of said contacts on said first side are commonly connected to a selected number of contacts on said second side to provide said card with a selected number of redundant contacts, and the DIMM further comprises:
a plurality of DRAMs on one or more of said first and second sides;
a 2 or 32K bit serial EE PROM and a 28 bit 1 to 2 register circuit chip having parity checking, a multi-byte fault reporting register, read via an independent bus, and real time error lines for both correctable errors and uncorrectable error conditions; and
a phase lock loop circuit coupled to said DRAMs and to said register circuit chip.
12. The DIMM of claim 1 wherein selected contacts CS1, CKE0, CKE1, RAS, CAS, WE, CK0, and CK0B are positioned at selected nominal distances from the key on said first edge of said DIMM as follows:
13. A dual in-line memory module (DIMM) comprising:
a rectangular printed circuit board having a first side and a second side, a length of between 146 and 156 millimeters (mm) and first and second ends having a width smaller than said length;
a first plurality of connector locations on said first side extending along a first edge of said board that extends the length of the board;
a second plurality of connector locations on said second side extending on said first edge of said board;
a locating key having its center positioned on said first edge and located between 79 and 89 mm from said first end of said card and located between 63 and 73 mm from said second end of said card.
14. The DIMM of claim 13 wherein there is further provided on one or more of said first and second sides:
multiple dynamic random access memories (DRAMs);
a phase lock loop circuit; and
a 28 bit 1 to 2 register circuit having error correction code (ECC) across data inputs, parity checking, and a real time error line for reporting both correctable errors and uncorrectable error conditions.
15. The DIMM of claim 13 wherein there is further provided on one or more of said first and second sides:
multiple DRAMs;
a phase lock loop circuit; and
a 28 bit 1 to 2 register circuit having error correction code (ECC) across data inputs and a real time error line for reporting both correctable errors and uncorrectable error conditions.
16. The DIMM of claim 14 wherein there are 22 data inputs to the register ECC circuitry.
17. The DIMM of claim 13 wherein said multiple DRAMs are mounted on said first side of said printed circuit board.
18. The DIMM of claim 13 wherein said multiple DRAMs are mounted on said second side of said printed circuit board.
19. The DIMM of claim 13 wherein the output pins of said multiple DRAMS are connected to selected ones of said connector locations on said board.
20. The DIMM of claim 13 wherein the first edge of the first side of said board has one hundred and thirty-eight (138) connector locations and an identical plurality of connector locations on the said first edge of the second side of said board for a total of two hundred and seventy-six (276) contacts on said board.
21. The DIMM of claim 13 wherein selected contacts on said first side surface are coupled to selected contacts on said second side to provide redundant contacts for selected signals.
22. The DIMM of claim 13 wherein;
a selected number of said contacts on said first side are commonly connected to a selected number of contacts on said second side to provide said card with a selected number of redundant contacts, and the DIMM further comprises:
a plurality of DRAMs on one or more of said first and second sides;
a 2 or 32K bit serial EE PROM and a 28 bit 1 to 2 register circuit chip having ECC, a multi-byte fault reporting register, read via an independent bus, and real time error lines for both correctable errors and uncorrectable error conditions; and
a phase lock loop circuit coupled to said DRAMs and to said register circuit chip.
23. The DIMM of claim 13 wherein;
a selected number of said contacts on said first side are commonly connected to a selected number of contacts on said second side to provide said card with a selected number of redundant contacts, and the DIMM further comprises:
a plurality of DRAMs on one or more of said first and second sides;
a 2 or 32K bit serial EE PROM and a 28 bit 1 to 2 register circuit chip having parity checking, a multi-byte fault reporting register, read via an independent bus, and real time error lines for both correctable errors and uncorrectable error conditions; and
a phase lock loop circuit coupled to said DRAMs and to said register circuit chip.
24. The DIMM of claim 13 wherein selected contacts CS1, CKE0, CKE1, RAS, CAS, WE, CK0, and CK0B are positioned at selected nominal distances from the key on said first edge of said DIMM as follows:
25. A dual in-line memory module (DIMM) comprising:
a rectangular printed circuit board having a first side and a second side, a length of about 151.25 millimeters (mm) and first and second ends having a width smaller than said length;
a first plurality of connector locations on said first side extending along a first edge of said board that extends the length of the board;
a second plurality of connector locations on said second side extending on said first edge of said board;
a locating key having its center positioned on said first edge and located at a distance of about 82.68 mm from said first end of said card and located at a distance of about 68.68 mm from said second end of said card.
26. A dual in-line memory module (DIMM) comprising:
a rectangular printed circuit board having a first side and a second side, a length of about 149.15 millimeters (mm) and first and second ends having a width smaller than said length;
a first plurality of connector locations on said first side extending along a first edge of said board that extends the length of the board;
a second plurality of connector locations on said second side extending on said first edge of said board;
a locating key having its center positioned on said first edge and located at a distance of about 81.58 mm from said first end of said card and located at a distance of about 67.58 mm from said second end of said card.
27. A dual in-line memory module (DIMM) comprising:
a rectangular printed circuit board having a first side and a second side, a length of about 151.35 millimeters (mm) and first and second ends having a width smaller than said length;
a first plurality of connector locations on said first side extending along a first edge of said board that extends the length of the board;
a second plurality of connector locations on said second side extending on said first edge of said board;
a locating key having its center positioned on said first edge and located at a distance of about 85.67 mm from said first end of said card and located at a distance of about 65.675 mm from said second end of said card.
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US7234099B2 (en) | 2007-06-19 |
US8489936B2 (en) | 2013-07-16 |
WO2004090723A2 (en) | 2004-10-21 |
TWI320853B (en) | 2010-02-21 |
KR20060004917A (en) | 2006-01-16 |
CN1768330A (en) | 2006-05-03 |
KR20070087176A (en) | 2007-08-27 |
US20070204201A1 (en) | 2007-08-30 |
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KR100843871B1 (en) | 2008-07-03 |
US7761771B2 (en) | 2010-07-20 |
US7380179B2 (en) | 2008-05-27 |
CN100392610C (en) | 2008-06-04 |
US20040205433A1 (en) | 2004-10-14 |
US7363533B2 (en) | 2008-04-22 |
US20060242541A1 (en) | 2006-10-26 |
US20060190780A1 (en) | 2006-08-24 |
WO2004090723A3 (en) | 2005-05-12 |
TW200506398A (en) | 2005-02-16 |
KR100834366B1 (en) | 2008-06-02 |
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