US20070205515A1 - Device having a redundant structure - Google Patents
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- US20070205515A1 US20070205515A1 US11/746,508 US74650807A US2007205515A1 US 20070205515 A1 US20070205515 A1 US 20070205515A1 US 74650807 A US74650807 A US 74650807A US 2007205515 A1 US2007205515 A1 US 2007205515A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to an interconnect structure, e.g., a damascene interconnect, for integrated circuits with improved reliability and improved electromigration properties.
- fatwire structure is a wiring layout laid out with a metal line having thicker height and wider width, e.g., thickness and pitch of 2 ⁇ , 4 ⁇ , 6 ⁇ , etc. of a thin wire, minimum ground rules dimensions.
- reliability of fatwire structures with a larger pitch becomes worse than in a thin wire structure.
- This inconsistent reliability is due to the fatwire structure.
- fatwire failure generally occurs at the top of the metal line, i.e., near the surface of the stripe, and/or at the bottom of the interlevel via.
- the bottom of the via may not fully contact the sidewall liner.
- the liner is too thin to sustain all the current density of the fatwire.
- FIGS. 1-4 A conventional process for forming a dual damascene line is shown in FIGS. 1-4 .
- a trench 12 is formed in a substrate 11 into which a metal, e.g., copper or aluminum, is provided, e.g., via electroplating, in order to form metal line Mx and at least one via Vx.
- a metal e.g., copper or aluminum
- Substrate 11 may be, e.g., Si0 2 , a low K organic material, a PCVD low dielectric material or other suitable material having a thickness of 400 to 2500 angstroms, metal line Mx may have a thickness in a range between 0.4-1.0 micron and a width of 0.2 to 1.0 micron, and via Vx may have a depth of 0.4 to 1.0 micron from the bottom of Mx and a diameter of 0.2 to 0.4 micron.
- substrate 11 may optionally be covered by a hardmask layer 13 , which can be, e.g., a PCVD oxide, SiCNH, SiC, Si 3 N 4 , or other suitable material.
- metal Mx is patterned by removing excess metal from the upper surface of substrate 11 or optional hardmask 13 , e.g., through chemical mechanical polishing, to form a smooth upper surface.
- a cap layer 14 is applied over the top of substrate 11 /hardmask 13 and metal line Mx.
- Cap layer 14 can be, e.g., SiN x , SiCNH, or other suitable cap layer material for metal line Mx, and have a thickness of 200-1000 angstroms.
- a substrate or interlevel layer 15 is deposited onto cap layer 14 .
- Interlayer 15 like substrate 11 , can be, e.g., Si0 2 , a low K organic material, a PCVD low k-dielectric material or other suitable material having a thickness of 4000 (1 ⁇ ) to 24000 (6 ⁇ ).
- a hardmask layer 16 can be deposited onto the surface of interlevel layer 15 .
- Hardmask layer 16 can be, e.g., a PCVD oxide, SiCNH, or other suitable material with a thickness of 300-2000 angstroms.
- a dual damascene trench 17 is formed in interlevel layer 15 and optional hardmask 16 .
- Trench 17 which is formed by, e.g., lithography and etching, is composed of two portions: a first portion 18 extending to a depth of 0.6-2 micron from the surface of interlevel layer 15 /hardmask 16 and a second portion 19 extending from first portion 18 down through cap layer 14 to contact metal line Mx.
- a metal e.g., copper
- liner 20 is deposited in trench 17 , and more particularly liner 20 , in order to form metal line MQ in portion 18 of trench 17 and via VL in portion 19 of trench 17 .
- wiring lines are patterned by removing excess metal from metal line MQ from the upper surface of substrate 15 or optional hardmask 16 , e.g., through chemical mechanical polishing, to achieve a smooth upper surface with a metal stripe.
- the present invention is directed to a method of fabricating a device.
- the method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.
- the present invention is directed to a device that includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line.
- the instant invention is directed to a method for fabricating an interconnect structure.
- the method includes forming a trench in a substrate, depositing metal in the trench, forming a second trench in the metal, depositing a redundant liner in the second trench, and depositing metal in the second trench.
- the invention is directed to a method of forming a redundant device that includes forming a redundant liner to divide a metal line of dual damascene line.
- FIGS. 1-4 illustrate a conventional formation of a dual damascene line (prior arts).
- FIGS. 5-10 illustrate the formation of a redundant fatwire from the conventional dual damascene line depicted in FIG. 4 in accordance with the features of the present invention.
- the invention relates to a process for forming a wire from a conventional dual damascene line.
- the formed fatwire eliminates the line opens and improves reliability (electromigration) by providing a longer lifetime and tighter sigma than conventional fatwire structures.
- the fatwire structure includes a thin redundant liner in the fatwire interconnect structure to isolate voids from underneath the via and to prevent such voids from propagating upward above the redundant liner. As a result, upward propagation of voids into the upper part of the metal layer is prevented.
- the via opening is etched through the redundant liner, which increases the mechanical strength of the interconnect and essentially eliminates any thermal cycle and/or stress migration effects. Further, the depth of the via improves performance against the electromigration effects by increasing contact surface around the via.
- the present invention increases the reliability of the conventional dual damascene line shown in FIG. 4 by using a redundant line.
- a blanket reactive ion etch (RIE) or a blanket wet etch is performed on the metal stripe, e.g., copper, to remove a portion of the thickness of metal line MQ to form metal line MQ′.
- the portion of barrier layer 20 lying adjacent the removed thickness is not removed, such that a trench 21 is formed between facing portions of barrier layer 20 and between an upper surface of metal line MQ′ and the upper surface of interlevel layer 15 /hardmask 16 .
- Trench 21 can be up to one-half of the thickness of metal line MQ, may be at least 100 angstroms, and preferably, is between 10-30% of the thickness of metal line MQ.
- a barrier layer (redundant liner) 22 is deposited onto the surface of interlevel layer 15 /hardmask 16 , as well as into and along the sides of trench 21 .
- Barrier layer 22 can have a thickness of 50-500 angstroms, preferably 50-100 angstroms, and be formed of, e.g., Ta, TaN, W, Ti, TiN, or other suitable material to act as a diffusion barrier layer for the metal to be deposited in barrier layer 22 .
- layer 22 can be formed from one or more of the identified materials.
- a metal e.g., copper, is deposited into trench 21 , and more particularly into barrier layer 22 , in order to form metal line MQ′′.
- a wiring line is patterned by removing excess metal from metal line MQ′ and portions of barrier layer 22 from the upper surface of substrate 15 or optional hardmask 16 , e.g., through chemical mechanical polishing, to achieve a smooth upper surface with a metal stripe.
- barrier layer 22 forms a redundant layer in the middle of the fatwire, i.e., between metal lines MQ′ and MQ′′.
- a cap layer 24 is applied over the top of substrate 15 /hardmask 16 and the metal stripe patterned from metal line MQ′′.
- Cap layer 24 can be, e.g., SiNx, SiCNH, or other suitable cap layer material for metal line Mx, and have a thickness of 200-1000 angstroms.
- a substrate or interlevel layer 25 is deposited onto cap layer 24 .
- Interlayer 25 like substrates 11 and 15 , can be, e.g., Si0 2 , a low K organic material, a PCVD low k-dielectric material or other suitable material having a thickness of 5000 to 24000 angstroms.
- an optional hardmask layer (not shown) can be deposited onto the surface of interlevel layer 25 in the manner set forth above.
- a trench 27 is formed in interlevel layer 25 , e.g., by lithography and etching, and is composed of two portions: a first portion 28 extending to a depth of 0.6-2 microns from the surface of interlevel layer 25 and a second portion 29 extending from first portion 28 down through at least barrier (redundant) layer 22 in order to create the desired redundance.
- a layer (liner) is deposited into trench 27 , followed by deposition of metal into trench 27 , or more specifically, into the liner within trench 27 , in order to form metal line LN and via VQ, as shown in FIG. 10 .
- metal line LN can be etched so that a redundant liner can be placed within the etched portion, and then deposited with metal.
- the wiring line can be patterned by chemical mechanical polishing to provide a smooth surface and metal strip. This procedure can be repeated a number of time, e.g., 8-9 times, depending upon the particular interconnect design.
- via VQ is etched through cap layer 24 , barrier layer 22 , and into MQ′.
- via VQ can be, e.g., a depth deeper than one-half the thickness of the fatwire.
- barrier layer 22 additionally forms a redundant layer between metal lines MQ′ and LN.
- barrier layer 22 will prevent any voids from underneath via VQ from propagating upward to metal line MQ′′. Further, the depth of via VQ will improve performance by increasing the contact surface around via V 2 , and improve reliability by having a longer lifetime and tighter sigma.
- This type of interconnect in which the via VQ is deep into the fatwire will make the structure mechanically stronger, and, therefore, less prone to thermal cycle or stress migration failures due to the expansion or contraction of metal and the interlevel low k-dielectrics.
- the circuit as described above is part of the design for an integrated circuit chip.
- the chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly.
- the stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer.
- the photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Abstract
Description
- The present application is a divisional of U.S. patent application Ser. No. 11/164,223 filed Nov. 15, 2005, the disclosure of which is expressly incorporated by reference herein in its entirety.
- The present invention relates to an interconnect structure, e.g., a damascene interconnect, for integrated circuits with improved reliability and improved electromigration properties.
- According to the known art, “fatwire” structure is a wiring layout laid out with a metal line having thicker height and wider width, e.g., thickness and pitch of 2×, 4×, 6×, etc. of a thin wire, minimum ground rules dimensions. However, with regard to electromigration effects, reliability of fatwire structures with a larger pitch becomes worse than in a thin wire structure. This inconsistent reliability is due to the fatwire structure. In this regard, fatwire failure generally occurs at the top of the metal line, i.e., near the surface of the stripe, and/or at the bottom of the interlevel via. In the known structure, the bottom of the via may not fully contact the sidewall liner. Moreover, even when the via contacts the sidewall liner, the liner is too thin to sustain all the current density of the fatwire.
- A conventional process for forming a dual damascene line is shown in
FIGS. 1-4 . In particular, atrench 12 is formed in asubstrate 11 into which a metal, e.g., copper or aluminum, is provided, e.g., via electroplating, in order to form metal line Mx and at least one via Vx.Substrate 11 may be, e.g., Si02, a low K organic material, a PCVD low dielectric material or other suitable material having a thickness of 400 to 2500 angstroms, metal line Mx may have a thickness in a range between 0.4-1.0 micron and a width of 0.2 to 1.0 micron, and via Vx may have a depth of 0.4 to 1.0 micron from the bottom of Mx and a diameter of 0.2 to 0.4 micron. Moreover,substrate 11 may optionally be covered by ahardmask layer 13, which can be, e.g., a PCVD oxide, SiCNH, SiC, Si3N4, or other suitable material. Moreover, the portion ofhardmask 13 overtrench 12 removed during the formation oftrench 12 is filled with metal Mx. Further, metal line Mx is patterned by removing excess metal from the upper surface ofsubstrate 11 oroptional hardmask 13, e.g., through chemical mechanical polishing, to form a smooth upper surface. - In a next production step, a
cap layer 14 is applied over the top ofsubstrate 11/hardmask 13 and metal line Mx.Cap layer 14 can be, e.g., SiNx, SiCNH, or other suitable cap layer material for metal line Mx, and have a thickness of 200-1000 angstroms. A substrate orinterlevel layer 15 is deposited ontocap layer 14.Interlayer 15, likesubstrate 11, can be, e.g., Si02, a low K organic material, a PCVD low k-dielectric material or other suitable material having a thickness of 4000 (1×) to 24000 (6×). Optionally, ahardmask layer 16 can be deposited onto the surface ofinterlevel layer 15.Hardmask layer 16 can be, e.g., a PCVD oxide, SiCNH, or other suitable material with a thickness of 300-2000 angstroms. - In a next step in the conventional process, as shown in
FIG. 2 , adual damascene trench 17 is formed ininterlevel layer 15 andoptional hardmask 16.Trench 17, which is formed by, e.g., lithography and etching, is composed of two portions: afirst portion 18 extending to a depth of 0.6-2 micron from the surface ofinterlevel layer 15/hardmask 16 and asecond portion 19 extending fromfirst portion 18 down throughcap layer 14 to contact metal line Mx. - As illustrated in
FIG. 3 , aliner 20 is deposited intotrench 17 in order to form a barrier layer having a thickness of 50-500 angstroms.Liner 20 can be, e.g., Ta, TaN, W, Ti, TiN, or a combination of Ta, TaN, Ti, TiN, W or with other suitable material to act as a barrier layer for the metal to be deposited inliner 20. Moreover,liner 20 can be formed from one or more of the identified materials. - As noted above, and shown in
FIG. 4 , a metal, e.g., copper, is deposited intrench 17, and more particularlyliner 20, in order to form metal line MQ inportion 18 oftrench 17 and via VL inportion 19 oftrench 17. Further, in accordance with the conventional process, wiring lines are patterned by removing excess metal from metal line MQ from the upper surface ofsubstrate 15 oroptional hardmask 16, e.g., through chemical mechanical polishing, to achieve a smooth upper surface with a metal stripe. - The present invention is directed to a method of fabricating a device. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.
- Moreover, the present invention is directed to a device that includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line.
- The instant invention is directed to a method for fabricating an interconnect structure. The method includes forming a trench in a substrate, depositing metal in the trench, forming a second trench in the metal, depositing a redundant liner in the second trench, and depositing metal in the second trench.
- Still further, the invention is directed to a method of forming a redundant device that includes forming a redundant liner to divide a metal line of dual damascene line.
-
FIGS. 1-4 illustrate a conventional formation of a dual damascene line (prior arts); and -
FIGS. 5-10 illustrate the formation of a redundant fatwire from the conventional dual damascene line depicted inFIG. 4 in accordance with the features of the present invention. - The invention relates to a process for forming a wire from a conventional dual damascene line. According to the invention, the formed fatwire eliminates the line opens and improves reliability (electromigration) by providing a longer lifetime and tighter sigma than conventional fatwire structures.
- According to the invention, the fatwire structure includes a thin redundant liner in the fatwire interconnect structure to isolate voids from underneath the via and to prevent such voids from propagating upward above the redundant liner. As a result, upward propagation of voids into the upper part of the metal layer is prevented.
- The via opening is etched through the redundant liner, which increases the mechanical strength of the interconnect and essentially eliminates any thermal cycle and/or stress migration effects. Further, the depth of the via improves performance against the electromigration effects by increasing contact surface around the via.
- The present invention increases the reliability of the conventional dual damascene line shown in
FIG. 4 by using a redundant line. In particular, as illustrated inFIG. 5 , a blanket reactive ion etch (RIE) or a blanket wet etch is performed on the metal stripe, e.g., copper, to remove a portion of the thickness of metal line MQ to form metal line MQ′. However, the portion ofbarrier layer 20 lying adjacent the removed thickness is not removed, such that atrench 21 is formed between facing portions ofbarrier layer 20 and between an upper surface of metal line MQ′ and the upper surface ofinterlevel layer 15/hardmask 16.Trench 21 can be up to one-half of the thickness of metal line MQ, may be at least 100 angstroms, and preferably, is between 10-30% of the thickness of metal line MQ. - After formation of
trench 21, a barrier layer (redundant liner) 22, as shown inFIG. 6 , is deposited onto the surface ofinterlevel layer 15/hardmask 16, as well as into and along the sides oftrench 21.Barrier layer 22 can have a thickness of 50-500 angstroms, preferably 50-100 angstroms, and be formed of, e.g., Ta, TaN, W, Ti, TiN, or other suitable material to act as a diffusion barrier layer for the metal to be deposited inbarrier layer 22. Moreover,layer 22 can be formed from one or more of the identified materials. Thereafter, a metal, e.g., copper, is deposited intotrench 21, and more particularly intobarrier layer 22, in order to form metal line MQ″. - As shown in
FIG. 7 , a wiring line is patterned by removing excess metal from metal line MQ′ and portions ofbarrier layer 22 from the upper surface ofsubstrate 15 oroptional hardmask 16, e.g., through chemical mechanical polishing, to achieve a smooth upper surface with a metal stripe. Thus,barrier layer 22 forms a redundant layer in the middle of the fatwire, i.e., between metal lines MQ′ and MQ″. - In a next production step, as illustrated in
FIG. 8 , acap layer 24 is applied over the top ofsubstrate 15/hardmask 16 and the metal stripe patterned from metal line MQ″.Cap layer 24 can be, e.g., SiNx, SiCNH, or other suitable cap layer material for metal line Mx, and have a thickness of 200-1000 angstroms. A substrate orinterlevel layer 25 is deposited ontocap layer 24.Interlayer 25, likesubstrates interlevel layer 25 in the manner set forth above. - As illustrated in
FIG. 9 , atrench 27 is formed ininterlevel layer 25, e.g., by lithography and etching, and is composed of two portions: afirst portion 28 extending to a depth of 0.6-2 microns from the surface ofinterlevel layer 25 and asecond portion 29 extending fromfirst portion 28 down through at least barrier (redundant)layer 22 in order to create the desired redundance. Subsequently, a layer (liner) is deposited intotrench 27, followed by deposition of metal intotrench 27, or more specifically, into the liner withintrench 27, in order to form metal line LN and via VQ, as shown inFIG. 10 . Moreover, a portion of metal line LN can be etched so that a redundant liner can be placed within the etched portion, and then deposited with metal. The wiring line can be patterned by chemical mechanical polishing to provide a smooth surface and metal strip. This procedure can be repeated a number of time, e.g., 8-9 times, depending upon the particular interconnect design. - In this manner, via VQ is etched through
cap layer 24,barrier layer 22, and into MQ′. Thus, via VQ can be, e.g., a depth deeper than one-half the thickness of the fatwire. Moreover,barrier layer 22 additionally forms a redundant layer between metal lines MQ′ and LN. - As a result of this construction,
barrier layer 22 will prevent any voids from underneath via VQ from propagating upward to metal line MQ″. Further, the depth of via VQ will improve performance by increasing the contact surface around via V2, and improve reliability by having a longer lifetime and tighter sigma. This type of interconnect, in which the via VQ is deep into the fatwire will make the structure mechanically stronger, and, therefore, less prone to thermal cycle or stress migration failures due to the expansion or contraction of metal and the interlevel low k-dielectrics. - The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- Moreover, the above-described method is used in the fabrication of integrated circuit chips.
- While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.
Claims (8)
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US11/746,508 US20070205515A1 (en) | 2005-11-15 | 2007-05-09 | Device having a redundant structure |
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US11/164,223 US7279411B2 (en) | 2005-11-15 | 2005-11-15 | Process for forming a redundant structure |
US11/746,508 US20070205515A1 (en) | 2005-11-15 | 2007-05-09 | Device having a redundant structure |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090127711A1 (en) * | 2007-11-15 | 2009-05-21 | International Business Machines Corporation | Interconnect structure and method of making same |
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Also Published As
Publication number | Publication date |
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CN1967804A (en) | 2007-05-23 |
US7279411B2 (en) | 2007-10-09 |
US20070111497A1 (en) | 2007-05-17 |
CN100452347C (en) | 2009-01-14 |
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