US20070257349A1 - Leaded Package Integrated Circuit Stacking - Google Patents
Leaded Package Integrated Circuit Stacking Download PDFInfo
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- US20070257349A1 US20070257349A1 US11/774,846 US77484607A US2007257349A1 US 20070257349 A1 US20070257349 A1 US 20070257349A1 US 77484607 A US77484607 A US 77484607A US 2007257349 A1 US2007257349 A1 US 2007257349A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/05—Flexible printed circuits [FPCs]
- H05K2201/056—Folded around rigid support or component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09445—Pads for connections not located at the edge of the PCB, e.g. for flexible circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
There is provided a stacked IC module including first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages, and a flexible circuit disposed in part between the first and second leaded packages, wherein the flexible is folded back on itself to create an arcuate connective field that is compressed to have conformity with the plural leads of the first and second leaded packages.
Description
- This application is a continuation of U.S. patent application Ser. No. 11/248,662 filed Oct. 11, 2005, which is incorporated by reference.
- This invention relates to stacking leaded integrated circuit devices. More particularly, this invention relates to stacks of leaded integrated circuits and associated flex circuitry.
- A variety of systems and techniques are known for stacking packaged integrated circuits. Some techniques are devised for stacking chip-scale packaged devices (CSPs) while other systems and methods are better directed to leaded packages which exhibit a set of leads extending from at least one lateral side of a typically rectangular package.
- Memory devices are packaged in both chip-scale (CSP) and leaded packages. However, techniques for stacking CSP devices are typically not optimum for stacking leaded devices. Although CSP devices are gaining market share, in many areas integrated circuits continue to be packaged in high volumes in leaded packages. For example, the well-known flash memory integrated circuit is typically packaged in leaded packages with fine-pitched leads emergent from one or both sides of a package. A common package for flash memory is a fine pitch thin small outline package commonly known as the TSOP. Flash circuitry in TSOP packaging typically differs from common TSOP-packaged DSRAMs in that flash TSOPs typically exhibit fine pitch leads emergent from the shorter pair of the lateral sides of the package while DRAM TSOPs typically exhibit leads emergent from the longer pair of sides of the package.
- The assignees of the present invention, Staktek Group L.P., has developed a wide variety of techniques, systems and designs for stacks and stacking with both leaded and CSP devices. In leaded package stacking, Staktek Group L.P. has developed rail bus systems that interconnect the leads of stacked leaded IC devices by use of rails. The present assignee also owns, for example, U.S. Pat. No. 6,572,387 issued Jun. 3, 2003 and U.S. patent application Ser. No. 10/449,242 published as Pub. No. 2003/0203663 A1 which disclose and claim various techniques and apparatus related to stacking leaded packages.
- Many other techniques have been developed that use various means for interconnecting the leads of the stacked devices. For example, U.S. Pat. No. 4,696,525 to Coller et al. teaches a socket connector for coupling adjacent devices in a stacked configuration to one another. The socket has external conductors that interconnect leads from like, adjacent devices to one another. Sockets, however, are limited in several respects. They are not versatile in their ability to implement complex interconnections. In addition, such sockets, which have relatively thick, plastic bodies, act as heat insulators between adjoining upper and lower (major) package surfaces, which can inhibit the module's overall ability to dissipate heat.
- Although the art has many techniques for stacking leaded devices, a new system and method for stacking leaded package devices is a welcome development. Accordingly, the present application discloses improved systems and methods for electrically and thermally coupling adjacent integrated circuit devices in stacked modules.
- The present invention provides a system and method for electrically and thermally coupling adjacent IC packages to one another in a stacked configuration. A flex circuit having an interconnective pattern is inserted between ICs to be stacked. A part of the flex circuit emerges from between the ICs and provides a connective field that provides plural contact areas that connect to respective leads of the ICs. Thus, the flex does not require discrete leads which must be individually aligned with the individual leads of the constituent ICs employed in the stack. The principle may be employed to aggregate two or more contact areas for respective connection to leads of constituent ICs but is most profitably employed with a continuous connective field that provides contact areas for many leads of the ICs.
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FIG. 1A depicts one embodiment of a flex circuit that may be employed in accordance with a preferred embodiment of the present invention. -
FIG. 1B depicts an embodiment of a flex circuit in accordance with an embodiment of the present invention. -
FIG. 2 depicts an enlargement of the area marked “A” inFIG. 1B . -
FIG. 3 depicts another aspect of a flex circuit in accordance with a preferred embodiment of the present invention. -
FIG. 4 depicts an enlargement of the area marked “B” inFIG. 3 . -
FIG. 5 is an exploded view of a stacked module devised in accordance with a preferred embodiment of the present invention. -
FIG. 6 is a perspective view of a stacked module devised in accordance with a preferred embodiment of the present invention. -
FIG. 7 is a depiction of an enlarged area marked “C” fromFIG. 6 . -
FIG. 8 is a side view of a stacked module in accordance with a preferred embodiment of the present invention. -
FIG. 9 depicts an enlarged view of the area marked “D” inFIG. 8 . -
FIG. 10 depicts an enlarged view of a part of the area marked “E” inFIG. 9 . -
FIG. 11 is a view of a stacked module in accordance with a preferred embodiment of the present invention. -
FIG. 12 is another side view of a stacked module in accordance with an alternative preferred embodiment of the present invention. -
FIG. 13 is depicts an enlarged view of the area marked “F” inFIG. 12 . -
FIG. 14 is a perspective view of a stacked module in accordance with an alternative preferred embodiment of the present invention. -
FIG. 15 is a side view of a stacked module in accordance with another alternative preferred embodiment of the present invention. -
FIG. 16 is a depiction of an enlarged view of the area marked “H” inFIG. 15 . -
FIG. 17 is a perspective view of a stacked module in accordance with another alternative preferred embodiment of the present invention. -
FIG. 1A depicts a cross-sectional view of a part of one embodiment of a flex circuit that may be employed in accordance with a preferred embodiment of the present invention. Depictedflex circuit 12 is an exemplar flex circuit embodiment that may be employed in accordance with the present invention in stacked modules comprised of leaded packaged integrated circuits. Depictedexemplar flex circuit 12 exhibits at least oneconnective field 19 which before inclusion in a module, typically will exhibit a loop-like or arcuate shape but may exhibit other shapes. An arcuate shape such as the one depicted as an example in typically deformed to be more adapted with the shape of the leads of the constituent ICs of a module in compliance with a preferred embodiment of a method for devising a stacked IC module in accordance with the present invention. The cross-section ofFIG. 1A further depicts adhesive 18 disposed along at least a part offlex circuit 12 for adherence to ICs whenflex circuit 12 is employed in a module. -
FIG. 1B is another depiction of aflex circuit 12 that may be employed to advantage in accordance with some preferred embodiments of the present invention.Flex circuit 12 is comprised of two layers, one of which is asubstrate layer 16 and the other of which layers is a conductive layer 14L which providesplural contact areas 14 of the more than oneconnective fields 19 as shown.Plural contact areas 14 are held in spaced apart relation by their adherence onsubstrate layer 16. Typically,connective field 19 is configured in a loop-like or arcuate configuration. Whenflex circuit 12 is disposed between ICs in a module, the leads of the ICs then make contact withconnective field 19 and typically deformconnective field 19 through compression to encourage adaptation of the shape ofconnective field 19 to the configuration of the leads. Thus, the arcuate configuration ofconnective field 19 improves contact between thecontact areas 14 with the respective leads of the constituent ICs of the module.Connective field 19 could, however, be devised in any shape so long as it exhibitsplural contact areas 14 for contact with at least two respective leads from an integrated circuit (packaged) of the module to be created. An another example,connective field 19 could be more of a folded structure that exhibitsplural contact areas 14 spaced apart laterally as part of a contiguous structure to allow the single structure of the flex circuit to be used to position a plurality of contact areas adjacent to a plurality of package leads in typically a one-to-one correspondence but it is advantageous in typical embodiments to haveconnective field 19 take a natural arcuate shape beforeflex circuit 12 is included in a module. Further the connective field need not be a closed loop. By havingplural contact areas 14,connective field 19 allowsplural contact areas 14 to be aligned with their respective leads in a stacked module thus avoiding the more difficult task of aligning individually each discrete lead from a flex circuit with the associated lead from ICs of the stacked module. -
Flex circuit 12 may have more than two layers but is shown withlayers 14L and 16 as an efficient and simple construction that may be employed in devising modules in accordance with preferred embodiments of the present invention. As those of skill will appreciate, flex circuitry with more than two layers may readily be employed particularly where especially complex electrical connections are required.Adhesive 18 is shown onflex circuit 12 and anoptional form 17 is shown withinconnective field 19.Adhesive 18 may also be disposed onICs 20 and/or 22 in addition to or instead of onflex circuit 12 when constructing a module in accordance with some embodiments of the present invention.Optional form 17 is preferably an elastomer to provide a ready preformed shape for configuration of aconnective field 19 and encourage compressive forces to enhance contact betweencontact areas 14 and leads ofICs -
Flex circuit 12 is shown with substantiallyplanar portion 12A that resides between ICs in a stacked module devised in accordance with some embodiments of the present invention. Anoptional portion 12B offlex circuit 12 is also resident between ICs in a stacked module and typically resides beneath a part ofportion 12A. - Conductive layer 14L and connect
areas 14 are preferably comprised of copper although any conductive material may be employed for such purposes. A more preferred copper layer would be thin and ductile copper deposited uponsubstrate layer 16 that is preferably a polyimide. An etched copper or other conductive material may also be used as a conductive layer 14L but a conductive layer 14L deposited on a substrate would be preferred. -
FIG. 2 depicts an enlargement of the area marked “A” inFIG. 1 . Contactareas 14 are shown in spaced apart relation onsubstrate layer 16.Thin film adhesive 18 is shown onflex circuit 12. Those of skill will recognize thatthin film adhesive 18 is not required but a thin film adhesive is a well understood method for adheringflex circuit 12 inmodule 10 as later depicted and preferred adhesives will have thermal conductivity properties to enhance the thermal conduction between the ICs in a module. -
FIG. 3 depicts another aspect ofexemplar flex circuit 12 in accordance with a preferred embodiment of the present invention. As shown inFIG. 3 ,flex circuit 12 exhibits connectivefield 19 and a part offlex circuit 12 identified as 12B is disposed underupper portion 12A offlex circuit 12 in the depicted embodiment offlex circuit 12. Other flex circuits may be employed with preferred modules in accordance with alternative embodiments of the present invention where an overlap of apart -
FIG. 4 depicts an enlargement of the area marked “B” inFIG. 3 showing in more detail a part ofconnective field 19 and thecontact areas 14 that provide connective facility between the flex circuit and the leads of constituent ICs of a module devised in accordance with a preferred embodiment. -
FIG. 5 is an exploded view of an exemplar stackedmodule 10 devised in accordance with a preferred embodiment of the present invention.Exemplar module 10 is comprised of upperleaded IC 20 and lowerleaded IC 22. The present invention may be employed with other circuitry besides and in addition to flash memory including, just as non-limiting examples, DRAMs, FPGAs, system stacks that include logic and memory and communications or graphics modules. It should be noted therefore, that there the depicted profile forICs lower ICs ICs module 10 in accord with the present invention need not have only two ICs as the invention may be employed to devise astacked module 10 with two or more ICs as those of skill will understand after appreciating this disclosure. -
Flex circuit 12 is disposed betweenICs components flex circuit 12 andICs connective field 19 is preferably compressed to have conformity with the configurations of the leads of the constituent ICs thus improving contact betweencontact areas 14 and respective leads. Those of skill will recognize thatflex circuit 12 may be constructed in two pieces with one piece for each ofconnective fields 19 and such a construction, although less than preferred, should be understood to be within the scope of the present invention. Further, identified adhesive 18 may be applied to theICs 20 and/or 22 in addition to or in place of its disposition onflex circuit 12 but that use of a thin file adhesive onflex circuit 12 is preferred for efficient construction. - When
ICs flex circuit 12 between, portions ofcontact areas 14 exposed around parts ofconnective fields 19 are preferably disposed in contact withleads 24 ofICs appropriate contact areas 14 is preferably realized whileconnective field 19 deforms in compliance with the configurations of the constituent IC leads. Solder as shown in later Figs. is then preferably employed between leads andcontact areas 14. A module could be built in accordance with an embodiment in which no solder was employed and compression between leads 24 andflex circuit 12 was the sole realization of the contact betweencontact areas 14 andrespective leads 24 but as those of skill will recognize, such a construction would not be preferred. Further, a module in accordance with an alternative embodiment could be devised in which thecontact areas 14 do not touch the respective leads but await realization of electrical contact with solder or other conductive attachment. Other forms of bonding other than solder betweencontact areas 14 and leads 24 may also be employed (such as brazing or welding for example) but soldering techniques are well understood and adapted for use in large scale manufacturing. -
FIG. 6 is a perspective view of amodule 10 showingICs connective field 19 offlex circuit 12 havingcontact areas 14 in contact with respective ones of the leads ofICs ICs sides leads 24 emergent from at least one of said sides with the particular configurations of IC shown having leads emergent from two opposite sides of the respective package. Upper surface 29 andlower surface 30 of the ICs are also identified inFIG. 6 . Those of skill will recognize that the identified “sides” need not be perpendicular to respective upper andlower surfaces 29 and 30 ofICs -
FIG. 6 illustrates that, in devising a module in accordance with the present invention, some embodiments may be constructed with the assistance of amechanical fixture 25 andfixture 25 andmodule 10 may be brought together (see force FA) to correlateconnective field 19 offlex circuit 12 withleads 24 ofICs contact areas 14 ofconnective field 19 offlex circuit 12 by pushing on either leads or the flex as the case may be. As those of skill will recognize, embodiments of the present invention assist in avoidance of what would otherwise be difficult registration and correlation between discrete leads from a flex circuit and individual leads 24 ofICs -
FIG. 7 shows greater detail of the area marked “C” inFIG. 6 and shows thatICs adhesive layers 18 and parts offlex circuit 12 that lie betweenICs Connective field 19 offlex circuit 12 aboutoptional form 17 showscontact areas 14 in contact withleads 24 ofICs substrate layer 16, which is preferably a dielectric layer such as polyimide for example, is shown betweencontact areas 14 and preferably holdscontact areas 14 in spaced apart relation. There is shown a one-to-one correspondence betweenindividual contact areas 14 and individual respective leads ofICs wider contact area 14 may be in contact with two or more side-by-side leads 24 of an IC if the electrical connections require such a configuration. -
FIG. 8 is a side view of amodule 10 devised in accordance with a preferred embodiment of the present invention.Module 10 includesICs flex circuit 12 in part between saidICs Flex circuit 12 is shown withconnective field 19 aboutform 17. Examples ofmodule 10 in a variety of different profiles may be devised in compliance with the present invention and the methods of thepresent invention modules 10 may be devised to present profiles in compliance with a variety of application requirements. -
FIG. 9 is an enlarged depiction of a cross-section through the area marked “D” inFIG. 8 .Flex circuit 12 is shown disposed withportion 12A betweenICs Flex circuit 12 emerges from the ICs to provideconnective field 19 which has as earlier shown,plural contact areas 14 for connection to leads 24. In the depicted embodiment,flex circuit 12 after transit throughconnective field 19 then re-enters betweenICs portion 12B which is in the depicted embodiment disposed beneathportion 12A.Solder 26 is shown inFIG. 9 and is employed to secure electrical connection betweenrespective contact areas 14 and respective leads 24. -
FIG. 10 is an enlarged depiction of the area marked “E” inFIG. 9 and illustrates in cross-sectionexemplar flex circuit 12 with conductive layer 14L andsubstrate layer 16. -
FIG. 11 illustrates an end view ofmodule 10 illustratingconnective field 19 along leads 24 ofICs ICs module 10 is devised with TSOP DRAMs, the depiction ofFIG. 11 is more an exemplification of a side view ofmodule 10. -
FIG. 12 is a side view of amodule 10 devised in accordance with an alternative preferred embodiment of the present invention. In depictedmodule 10 ofFIG. 12 ,flex circuit 12 exhibits aconnective field 19 that provides more area forcontact areas 14 to be in contact withleads 24 ofICs ICs flex circuit 12. This is shown in greater detail inFIG. 13 , which is an enlarged depiction of the area marked with “F” inFIG. 12 . -
FIG. 13 illustratesconnective field 19 of flex circuit 12 (without use of a form 17) and by extension,contact areas 14 disposed in proximal compression withrespective leads 24 ofupper IC 20 andlower IC 22. It will be noted that in the depicted embodiment,flex circuit 12 emerges from betweenICs ICs -
FIG. 14 is a perspective view of amodule 10 that illustrates the continuous nature ofconnective field 19 across more than one contact area for connection with more than onelead 24 thus avoiding the use of separated leads to realize connections between respective leads ofICs ICs -
FIG. 15 illustrates a stackedmodule 10 in accordance with an alternative preferred embodiment of the present invention. Unlike earlier depicted embodiments, the embodiment ofmodule 10 depicted inFIG. 15 employsflex circuit 12 to provideconnective field 19 but does not exhibit a return of apart 12B offlex circuit 12 to the area in betweenICs flex circuit 12 identified as portion 12C is adhered to thebottom surface 30 oflower IC 22 with adhesive 18 as shown in greater detail inFIG. 16 . -
FIG. 16 is an enlarged depiction of the area marked “H” inFIG. 15 . As illustrated,flex circuit 12 emerges from betweenIC 20 andIC 22 and exhibitsconnective field 19 but is disposed so as to be proximal to the lower side offeet 28 of respective leads 24 ofICs flex circuit 12 is disposed along a portion oflower surface 30 of lower IC22. -
FIG. 17 is a perspective view of a stackedmodule 10 in accordance with an alternative preferred embodiment of the present invention as shown in earlierFIGS. 15 and 16 . - Although the present invention has been described in detail, it will be apparent to those skilled in the art that many embodiments taking a variety of specific forms and reflecting changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. Therefore, the described embodiments illustrate but do not restrict the scope of the claims.
Claims (18)
1. A stacked IC module comprising:
first and second leaded packages in stacked disposition, each of the first and second leaded packages having plural leads emergent along at least one side of each of the respective leaded packages; and
a flexible circuit disposed in part between the first and second leaded packages, wherein the flexible is folded back on itself to create an arcuate connective field that is compressed to have conformity with the plural leads of the first and second leaded packages.
2. The stacked IC module of claim 1 , wherein the arcuate connective field is compressed to form a planar contact with the plural leads of both the first and second leaded packages.
3. The stacked IC module of claim 1 , wherein the flexible circuit is bonded to itself in the portion of the flexible circuit that is folded back.
4. The attached IC module of claim 3 , wherein the flexible circuit is bonded to itself with a non-conductive adhesive.
5. The stacked IC module of claim 1 , in which the first and second leaded packages include flash memory circuitry.
6. The stacked IC module of claim 1 , in which the connective field is disposed about a form.
7. The stacked IC module of claim 6 , in which the form is comprised of elastomer.
8. A leaded package interconnection system comprising:
a flexible circuit folded back upon itself to form an arcuate connection field, wherein the arcuate connective field, wherein the arcuate connection field is configured to deform in shape when the flexible circuit is disposed between two leaded packages.
9. The leaded package interconnection system of claim 8 , wherein the flexible circuit is bonded to itself to form the arcuate connection field.
10. The leaded package interconnection system of claim 8 , comprising an elastomer form disposed within the arcuate connection field.
11. The leaded package interconnection system of claim 8 , wherein the arcuate connection field is configured to form a planar connection with leads emergent from the two leaded packages.
12. The leaded package interconnection system of claim 8 , comprising the two leaded packages.
13. The leaded package interconnection system of claim 8 , wherein the flexible circuit is folded back on itself on both ends of the flexible circuit.
14. A stacked IC module construction method comprising:
providing a flex circuit that exhibits at least one connective field configured in an arcuate shape;
providing first and second leaded ICs, the first and second leaded ICs each having leads emergent from at least one side; and
disposing together, the first and second ICs with the flex circuit between to deform the connective field to be conformal with the leads of the first and second leaded ICs to realize contact between selected contact areas of the at least one connective field and selected ones of the leads of the first and second ICs.
15. The method of claim 14 , comprising disposing an adhesive between at least one of the first and second ICs and the flex circuit.
16. The method of claim 14 , in which the first and second ICs are each memory circuits in leaded packages.
17. The method of claim 14 , in which the flex circuit exhibits two connective fields each of which includes plural contact areas and the flex circuit is comprised of at least two layers with a first of the two layers being comprised of copper and the second of the two layers being comprised of a dielectric.
18. The method of claim 17 , in which the layer comprised of copper is deposited on the layer comprised of the dielectric.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/774,846 US20070257349A1 (en) | 2005-10-11 | 2007-07-09 | Leaded Package Integrated Circuit Stacking |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/248,662 US7259452B2 (en) | 2005-10-11 | 2005-10-11 | Leaded package integrated circuit stacking |
US11/774,846 US20070257349A1 (en) | 2005-10-11 | 2007-07-09 | Leaded Package Integrated Circuit Stacking |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/248,662 Continuation US7259452B2 (en) | 2005-10-11 | 2005-10-11 | Leaded package integrated circuit stacking |
Publications (1)
Publication Number | Publication Date |
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US20070257349A1 true US20070257349A1 (en) | 2007-11-08 |
Family
ID=37910434
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/248,662 Active US7259452B2 (en) | 2005-10-11 | 2005-10-11 | Leaded package integrated circuit stacking |
US11/774,846 Abandoned US20070257349A1 (en) | 2005-10-11 | 2007-07-09 | Leaded Package Integrated Circuit Stacking |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/248,662 Active US7259452B2 (en) | 2005-10-11 | 2005-10-11 | Leaded package integrated circuit stacking |
Country Status (2)
Country | Link |
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US (2) | US7259452B2 (en) |
WO (1) | WO2007044019A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US7446403B2 (en) * | 2006-06-14 | 2008-11-04 | Entorian Technologies, Lp | Carrier structure stacking system and method |
US8225475B2 (en) * | 2008-12-10 | 2012-07-24 | Omnetics Connector Corporation | Alignment device for fine pitch connector leads |
KR20220051470A (en) * | 2020-10-19 | 2022-04-26 | 삼성전자주식회사 | Semiconductor package and method of fabricating the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6313998B1 (en) * | 1999-04-02 | 2001-11-06 | Legacy Electronics, Inc. | Circuit board assembly having a three dimensional array of integrated circuit packages |
US6572387B2 (en) * | 1999-09-24 | 2003-06-03 | Staktek Group, L.P. | Flexible circuit connector for stacked chip module |
US6608763B1 (en) * | 2000-09-15 | 2003-08-19 | Staktek Group L.P. | Stacking system and method |
US20060050592A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Compact module system and method |
-
2005
- 2005-10-11 US US11/248,662 patent/US7259452B2/en active Active
- 2005-10-28 WO PCT/US2005/039307 patent/WO2007044019A1/en active Application Filing
-
2007
- 2007-07-09 US US11/774,846 patent/US20070257349A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6313998B1 (en) * | 1999-04-02 | 2001-11-06 | Legacy Electronics, Inc. | Circuit board assembly having a three dimensional array of integrated circuit packages |
US6572387B2 (en) * | 1999-09-24 | 2003-06-03 | Staktek Group, L.P. | Flexible circuit connector for stacked chip module |
US6608763B1 (en) * | 2000-09-15 | 2003-08-19 | Staktek Group L.P. | Stacking system and method |
US20060050592A1 (en) * | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Compact module system and method |
Also Published As
Publication number | Publication date |
---|---|
US20070080470A1 (en) | 2007-04-12 |
WO2007044019A1 (en) | 2007-04-19 |
US7259452B2 (en) | 2007-08-21 |
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Owner name: STAKTEK GROUP L.P., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WEHRLY, JAMES DOUGLAS;ROPER, DAVID L.;REEL/FRAME:019666/0058 Effective date: 20051011 |
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STCB | Information on status: application discontinuation |
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