US20070259461A1 - Semiconductor wafer examination method and semiconductor chip manufacturing method - Google Patents

Semiconductor wafer examination method and semiconductor chip manufacturing method Download PDF

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Publication number
US20070259461A1
US20070259461A1 US11/775,449 US77544907A US2007259461A1 US 20070259461 A1 US20070259461 A1 US 20070259461A1 US 77544907 A US77544907 A US 77544907A US 2007259461 A1 US2007259461 A1 US 2007259461A1
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conducted
wafer
inspecting
electrode
semiconductor
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US11/775,449
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Hideki Yuzawa
Kazuhiro Kijima
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Seiko Epson Corp
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Seiko Epson Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2868—Complete testing stations; systems; procedures; software aspects
    • G01R31/287—Procedures; Software aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2881—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to environmental aspects other than temperature, e.g. humidity or vibrations

Definitions

  • the present invention relates to a semiconductor wafer examination method by wafer probing, and a semiconductor chip manufacturing method.
  • a semiconductor wafer formed with a plurality of semiconductor chips is subjected to an electric examination on a semiconductor chip basis so that screening is performed to find any defective piece.
  • Such an examination includes a probe examination by probing.
  • the wafer is generally diced so that chips are formed. This thus may cause a failure to some semiconductor devices of the semiconductor chips if heat and pressure act on the electrodes of the semiconductor chips in the subsequent process of semiconductor chip implementation, for example.
  • a failure detection is no sooner than semiconductor chip implementation, e.g., during the package check.
  • An advantage of some aspects of the invention is to provide a semiconductor wafer examination method with which screening is performed at an earlier stage with high accuracy to find any possible failure.
  • Another advantage of some aspects of the invention is to provide a semiconductor chip manufacturing method using the examination method of the invention.
  • the invention is directed to a semiconductor wafer examination method that includes: a step of preparing a wafer formed with a chip area for use as a semiconductor chip; a first probe examination in which the wafer is examined by probing; a step of pressing an electrode of the wafer with a pressure member having a flat surface; and a second probe examination in which the wafer is examined by probing.
  • any failure that is highly likely to occur to a semiconductor wafer e.g., at the time of semiconductor chip implementation, can be detected in advance so that screening can be performed with better reliability. This favorably leads to the reduction of failure occurrence so that the resulting semiconductor chip can be high in reliability.
  • the electrode in the step of pressing the electrode, the electrode can be heated.
  • an upper surface of the electrode in the step of pressing the electrode, an upper surface of the electrode can be made flat.
  • the pressure member can use a bonding tool.
  • a semiconductor device in the chip area, can be formed below the electrode.
  • the invention is also directed to a semiconductor chip manufacturing method that includes: a step of preparing a wafer formed with a chip area for use as a semiconductor chip; a first probe examination in which the wafer is examined by probing; a step of pressing an electrode of the wafer with a pressure member having a flat surface; a second probe examination in which the wafer is examined by probing; and a step of forming the semiconductor chip by dicing the wafer.
  • the resulting semiconductor chip manufactured by such an examination method can be less likely to cause a failure.
  • FIG. 1 is a diagram showing the procedure in an embodiment of the invention.
  • FIG. 2 is a diagram showing process operations in the embodiment of the invention.
  • FIG. 3 is another diagram showing the process operations in the embodiment of the invention.
  • FIG. 4 is a diagram showing the partial configuration of a semiconductor wafer in the embodiment of the invention.
  • FIG. 1 is a diagram for illustrating a semiconductor wafer examination method of the embodiment.
  • FIG. 2 is a cross sectional diagram schematically showing a process of the semiconductor wafer examination method.
  • FIG. 3 is a schematic plan view of a wafer being an examination object.
  • FIG. 4 is a schematic cross sectional view of a part of a chip area.
  • a wafer is prepared for examination use. As shown in FIGS. 2 and 3 , this wafer is configured by a semiconductor substrate 10 formed with a plurality of chip areas 12 , which serve as semiconductor chips after wafer dicing.
  • the chip areas 12 are provided with an integrated circuit that is not shown.
  • the integrated circuit is not specifically defined by configuration, and may include an active element such as transistor or a passive element such as resistor, coil, or capacitor.
  • the chip areas 12 are each provided with electrodes 14 for connection use.
  • the electrode 14 can be electrically connected to the inside of each corresponding chip area 12 .
  • the term electrode 14 may include any other electrodes not electrically connected to the chip areas 12 .
  • the electrode 14 may be configured to include a pad 16 , and a bump 18 formed on the pad 16 .
  • the bump 18 may be a gold bump, or a nickel bump with gold plating.
  • the wafer is examined in the procedure of FIG. 1 .
  • the wafer is first examined using a probe device by probing, i.e., a first probe examination (S 1 ).
  • the probe examination is not specifically defined in manner, and any known technique will be adopted.
  • the electrodes 14 formed to the chip areas 12 of the semiconductor wafer are brought in contact with a probe needle of a probe card for voltage application of a predetermined level from the probe needle.
  • the chip areas 12 are then examined electrically using a tester, e.g., continuity test.
  • the probe needle is brought in contact with the electrodes 14 on the basis of the chip area 12 or of a plurality of chip areas 12 so that the chip areas 12 can be examined sequentially as indicated by an arrow of FIG. 3 , for example.
  • the electrodes 14 of the wafer are then pressed with a pressure member (S 2 ).
  • a pressure member 20 having a flat surface 22 is moved downward with the flat surface 22 facing down, and the flat surface 22 is brought in contact with the upper surfaces of the electrodes 14 .
  • the pressure member 20 is then moved downward again to press the electrodes 14 for application thereto of a predetermined level of pressure. If a user wants to check the influence as a result of heating of the electrodes 14 , the electrodes are to be pressed while the pressure member 20 is being heated.
  • the electrodes 14 are pressed against the wiring section of the substrate while being heated using a bonding tool. If a user wants to check the resulting influence, the electrodes 14 may be pressed and heated in the process b with more strict requirements for implementation so that the influence can be checked with better reliability.
  • COG Process b Load on 30 MPa 45 MPa Electrodes 14 Temperature 300 degrees 300 to of Electrodes 14 or lower 350 degrees
  • the pressurization/heating operation in the process b can be applied on the basis of the chip area 12 or of a plurality of chip areas 12 .
  • the bump 18 of each of the electrodes 14 is made flat on the upper surface.
  • the pressure member 20 is not specifically restrictive as long as being adjustable at least for pressurization, preferably, being adjustable for both pressurization and heating.
  • the pressure member 20 may serve also as a bonding tool for use for a collective connection between the wiring section of the substrate and the electrodes of the semiconductor chips.
  • the wafer is then examined by probing, i.e., a second probe examination (S 3 ), similarly to the first probe examination.
  • This probe examination enables to detect any failure occurred as a result of the probe examination, i.e., in the pressurization operation in the process b, or the pressurization/heating operation therein.
  • the examination technique of this embodiment is applicable to a semiconductor wafer with semiconductor chips of a general type.
  • the examination technique is useful also to examine a semiconductor wafer including a semiconductor unit of the following type.
  • the semiconductor device is formed with semiconductor devices such as MIS (Metal Insulator Semiconductor) transistor 30 also below the electrode 14 .
  • the semiconductor substrate 10 is formed with a device isolation insulation layer 20 .
  • the device isolation insulation layer 20 can be formed by STI (Shallow Trench Isolation), LOCOS (Local Oxidation of Silicon), semi-recessed LOCOS, and others.
  • the device isolation insulation layer 20 of FIG. 4 is the one formed by STI.
  • the MIS transistor 30 is formed in an area 10 A directly below the electrode 14 .
  • an MIS transistor 40 is provided similarly to the area 10 A.
  • the MIS transistor 30 is configured to include a gate insulation layer 32 , a gate electrode 34 provided on the gate insulation layer 32 , and an impurity region 36 formed to the semiconductor substrate 10 .
  • the impurity region 36 serves as a source or drain region.
  • the MIS transistor 40 is configured similarly to the MIS transistor 30 , including a gate insulation layer 42 , a gate electrode 44 , and an impurity region 46 .
  • the gate electrodes 34 and 44 are each configured by a polysilicon layer, a polycide layer, or others.
  • the MIS transistors 30 and 40 may each include a sidewall insulation layer.
  • a reference numeral 14 denotes a wiring layer.
  • inter-layer insulation layers 50 and 60 are so formed in this order as to cover the MIS transistors 30 and 40 .
  • the inter-layer insulation layers 50 and 60 are each made of a known general material.
  • a wiring layer 52 of a predetermined pattern is formed, and an electrical connection is established by a contact layer 54 between the wiring layer 52 and the impurity region 36 of the MIS transistor 30 .
  • the inter-layer insulation layer 60 is formed thereon with the pad 16 .
  • the pad 16 establishes an electrical connection by the wiring layer 52 and a contact layer 64 .
  • the pad 16 is formed by a metal such as aluminum or copper.
  • the semiconductor unit may be also formed with a passivation layer 70 , which is formed with an aperture 72 from which at least a part of the pad 16 is exposed.
  • the aperture 72 may be so formed as to expose therefrom only the center portion of the pad 16 . That is, the passivation layer 70 may be so formed as to cover the peripheral portion of the pad 16 .
  • the passivation layer 70 may be formed by SiO 2 , SiN, polyimide resin, or others.
  • the aperture 72 is formed with the bump 18 , i.e., the bump 18 is formed on the exposure surface of the pad 16 .
  • the bump 18 is so formed as to reach over the passivation layer 70 .
  • the bump 18 is formed by a single or a plurality of layers, and is made of a metal such as gold, nickel, or copper.
  • the bump 18 is not specifically defined by outer shape, and may be formed rectangular (including square and rectangle), or formed circular. The outer dimension of the bump 18 may be smaller than that of the pad 16 . With this being the case, the bump 18 may be formed only in an area overlapping the pad 16 .
  • a barrier layer may be formed at the bottom of the bump 18 .
  • the barrier layer may serve to prevent material dissipation for both the pad 16 and the bump 18 .
  • the barrier layer may be formed by a single or a plurality of layers, and may be formed by sputtering.
  • the barrier layer may be also made to improve the adhesion between the pad 16 and the bump 18 .
  • the barrier layer may include a titanium tungsten (TiW) layer.
  • TiW titanium tungsten
  • the top surface of the barrier layer may be an electroplated metal layer, e.g., Au layer, for deposition of the bump 18 .
  • the MIS transistor 30 is formed below the electrode 14 , if the electrode 14 is pressurized and heated when being connected to any other component, not only the electrode 14 but also the components therebelow are affected thereby. As a result, this easily leads to failures of the devices compared with a case where the electrode 14 is formed therebelow with no device such as MIS transistor. With the examination method of this embodiment, however, the processes b and c enable to detect failures being highly likely to occur as a result of semiconductor chip implementation even prior to the implementation. This is surely applicable to a case where no MIS transistor is formed below the electrode 14 .
  • the wafer is diced by any known dicing technique so that semiconductor chips can be formed.
  • any failures that are highly likely to occur as a result of semiconductor chip implementation can be detected beforehand, e.g., in the form of semiconductor wafer, so that screening can be performed with better reliability with respect to the resulting semiconductor chips.
  • This favorably reduces the failure frequency of the semiconductor chips for use, and the resulting semiconductor chips can be increased in reliability.
  • Such characteristics are considered advantageous especially with a semiconductor wafer in which devices such as MIS transistors are formed below the electrodes.
  • the upper surfaces of the electrodes 14 are pressed, preferably, pressed and heated so that the upper surface of the bump 18 of each of the electrodes 14 can be made flat.
  • the bump 18 can be flat enough, and the electrodes 14 are highly reliable in terms of connection.
  • the invention includes any configuration substantially the same as the configurations described in the embodiment, e.g., configurations leading to the same functions, methods, and results, or configurations leading to the same objects and effects.
  • the invention also includes any configuration in which a component(s) are changed if not essential.
  • the invention also includes any configuration leading to the same effects or achieving the same objects as those described in the embodiment.
  • the invention also includes any configuration in which any known technique is taken into consideration for the configurations described in the embodiment.

Abstract

A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 11/458,781 filed on Jul. 20, 2006, which claims the benefit of Japanese Patent Application No. 2005-214218, filed Jul. 25, 2005. The disclosures of the above applications are incorporated herein by reference.
    • BACKGROUND
  • 1. Technical Field
  • The present invention relates to a semiconductor wafer examination method by wafer probing, and a semiconductor chip manufacturing method.
  • 2. Related Art
  • In the process of manufacturing a semiconductor chip, a semiconductor wafer formed with a plurality of semiconductor chips is subjected to an electric examination on a semiconductor chip basis so that screening is performed to find any defective piece. Such an examination includes a probe examination by probing. After the wafer is subjected to the probe examination, the wafer is generally diced so that chips are formed. This thus may cause a failure to some semiconductor devices of the semiconductor chips if heat and pressure act on the electrodes of the semiconductor chips in the subsequent process of semiconductor chip implementation, for example. With the previous general semiconductor chip manufacturing method, such a failure detection is no sooner than semiconductor chip implementation, e.g., during the package check.
    • SUMMARY
  • An advantage of some aspects of the invention is to provide a semiconductor wafer examination method with which screening is performed at an earlier stage with high accuracy to find any possible failure.
  • Another advantage of some aspects of the invention is to provide a semiconductor chip manufacturing method using the examination method of the invention.
  • The invention is directed to a semiconductor wafer examination method that includes: a step of preparing a wafer formed with a chip area for use as a semiconductor chip; a first probe examination in which the wafer is examined by probing; a step of pressing an electrode of the wafer with a pressure member having a flat surface; and a second probe examination in which the wafer is examined by probing.
  • With such a semiconductor wafer examination method according to some aspects of the invention, any failure that is highly likely to occur to a semiconductor wafer, e.g., at the time of semiconductor chip implementation, can be detected in advance so that screening can be performed with better reliability. This favorably leads to the reduction of failure occurrence so that the resulting semiconductor chip can be high in reliability.
  • With the semiconductor wafer examination method according to some aspects of the invention, in the step of pressing the electrode, the electrode can be heated.
  • With the semiconductor wafer examination method according to some aspects of the invention, in the step of pressing the electrode, an upper surface of the electrode can be made flat.
  • With the semiconductor wafer examination method according to some aspects of the invention, the pressure member can use a bonding tool.
  • With the semiconductor wafer examination method according to some aspects of the invention, in the chip area, a semiconductor device can be formed below the electrode.
  • The invention is also directed to a semiconductor chip manufacturing method that includes: a step of preparing a wafer formed with a chip area for use as a semiconductor chip; a first probe examination in which the wafer is examined by probing; a step of pressing an electrode of the wafer with a pressure member having a flat surface; a second probe examination in which the wafer is examined by probing; and a step of forming the semiconductor chip by dicing the wafer.
  • With the semiconductor chip manufacturing method according to some aspects of the invention, the resulting semiconductor chip manufactured by such an examination method can be less likely to cause a failure.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
  • FIG. 1 is a diagram showing the procedure in an embodiment of the invention.
  • FIG. 2 is a diagram showing process operations in the embodiment of the invention.
  • FIG. 3 is another diagram showing the process operations in the embodiment of the invention.
  • FIG. 4 is a diagram showing the partial configuration of a semiconductor wafer in the embodiment of the invention.
    • DESCRIPTION OF EXEMPLARY EMBODIMENT
  • In the below, an exemplary embodiment of the invention is described by referring to the accompanying drawings. FIG. 1 is a diagram for illustrating a semiconductor wafer examination method of the embodiment. FIG. 2 is a cross sectional diagram schematically showing a process of the semiconductor wafer examination method. FIG. 3 is a schematic plan view of a wafer being an examination object. FIG. 4 is a schematic cross sectional view of a part of a chip area.
  • In the embodiment, a wafer is prepared for examination use. As shown in FIGS. 2 and 3, this wafer is configured by a semiconductor substrate 10 formed with a plurality of chip areas 12, which serve as semiconductor chips after wafer dicing. The chip areas 12 are provided with an integrated circuit that is not shown. The integrated circuit is not specifically defined by configuration, and may include an active element such as transistor or a passive element such as resistor, coil, or capacitor.
  • The chip areas 12 are each provided with electrodes 14 for connection use. The electrode 14 can be electrically connected to the inside of each corresponding chip area 12. The term electrode 14 may include any other electrodes not electrically connected to the chip areas 12. As shown in FIG. 4, the electrode 14 may be configured to include a pad 16, and a bump 18 formed on the pad 16. With this being the case, the bump 18 may be a gold bump, or a nickel bump with gold plating.
  • The wafer is examined in the procedure of FIG. 1.
  • a. The wafer is first examined using a probe device by probing, i.e., a first probe examination (S1). The probe examination is not specifically defined in manner, and any known technique will be adopted. As an exemplary probe examination, as shown in FIG. 3, the electrodes 14 formed to the chip areas 12 of the semiconductor wafer are brought in contact with a probe needle of a probe card for voltage application of a predetermined level from the probe needle. The chip areas 12 are then examined electrically using a tester, e.g., continuity test. In such a probe examination, the probe needle is brought in contact with the electrodes 14 on the basis of the chip area 12 or of a plurality of chip areas 12 so that the chip areas 12 can be examined sequentially as indicated by an arrow of FIG. 3, for example.
  • b. The electrodes 14 of the wafer are then pressed with a pressure member (S2). In this process, as shown in FIG. 2, a pressure member 20 having a flat surface 22 is moved downward with the flat surface 22 facing down, and the flat surface 22 is brought in contact with the upper surfaces of the electrodes 14. The pressure member 20 is then moved downward again to press the electrodes 14 for application thereto of a predetermined level of pressure. If a user wants to check the influence as a result of heating of the electrodes 14, the electrodes are to be pressed while the pressure member 20 is being heated.
  • For example, when a semiconductor chip is mounted on a substrate, generally, the electrodes 14 are pressed against the wiring section of the substrate while being heated using a bonding tool. If a user wants to check the resulting influence, the electrodes 14 may be pressed and heated in the process b with more strict requirements for implementation so that the influence can be checked with better reliability.
  • For example, for reference purposes, described now are exemplary requirements for COG (Chip On Glass) implementation and for the process b. Note here that these requirements share the same moving-down speed of the pressure member 20 and the time for the pressing operation.
    COG Process b
    Load on 30 MPa 45 MPa
    Electrodes
    14
    Temperature 300 degrees 300 to
    of Electrodes 14 or lower 350 degrees
  • The pressurization/heating operation in the process b can be applied on the basis of the chip area 12 or of a plurality of chip areas 12. After the process b, the bump 18 of each of the electrodes 14 is made flat on the upper surface.
  • The pressure member 20 is not specifically restrictive as long as being adjustable at least for pressurization, preferably, being adjustable for both pressurization and heating. The pressure member 20 may serve also as a bonding tool for use for a collective connection between the wiring section of the substrate and the electrodes of the semiconductor chips.
  • c. The wafer is then examined by probing, i.e., a second probe examination (S3), similarly to the first probe examination. This probe examination enables to detect any failure occurred as a result of the probe examination, i.e., in the pressurization operation in the process b, or the pressurization/heating operation therein.
  • The examination technique of this embodiment is applicable to a semiconductor wafer with semiconductor chips of a general type. The examination technique is useful also to examine a semiconductor wafer including a semiconductor unit of the following type.
  • As shown in FIG. 4, the semiconductor device is formed with semiconductor devices such as MIS (Metal Insulator Semiconductor) transistor 30 also below the electrode 14. More specifically, in this semiconductor unit, the semiconductor substrate 10 is formed with a device isolation insulation layer 20. The device isolation insulation layer 20 can be formed by STI (Shallow Trench Isolation), LOCOS (Local Oxidation of Silicon), semi-recessed LOCOS, and others. The device isolation insulation layer 20 of FIG. 4 is the one formed by STI. In an area 10A directly below the electrode 14, the MIS transistor 30 is formed. Also in an area 10B not directly below the electrode 14, an MIS transistor 40 is provided similarly to the area 10A. The MIS transistor 30 is configured to include a gate insulation layer 32, a gate electrode 34 provided on the gate insulation layer 32, and an impurity region 36 formed to the semiconductor substrate 10. The impurity region 36 serves as a source or drain region. The MIS transistor 40 is configured similarly to the MIS transistor 30, including a gate insulation layer 42, a gate electrode 44, and an impurity region 46. The gate electrodes 34 and 44 are each configured by a polysilicon layer, a polycide layer, or others. Although not shown in FIG. 4, the MIS transistors 30 and 40 may each include a sidewall insulation layer. In FIG. 4, a reference numeral 14 denotes a wiring layer.
  • Over the MIS transistors 30 and 40, inter-layer insulation layers 50 and 60 are so formed in this order as to cover the MIS transistors 30 and 40. The inter-layer insulation layers 50 and 60 are each made of a known general material. On the inter-layer insulation layer 50, a wiring layer 52 of a predetermined pattern is formed, and an electrical connection is established by a contact layer 54 between the wiring layer 52 and the impurity region 36 of the MIS transistor 30.
  • The inter-layer insulation layer 60 is formed thereon with the pad 16. The pad 16 establishes an electrical connection by the wiring layer 52 and a contact layer 64. The pad 16 is formed by a metal such as aluminum or copper. The semiconductor unit may be also formed with a passivation layer 70, which is formed with an aperture 72 from which at least a part of the pad 16 is exposed. The aperture 72 may be so formed as to expose therefrom only the center portion of the pad 16. That is, the passivation layer 70 may be so formed as to cover the peripheral portion of the pad 16. The passivation layer 70 may be formed by SiO2, SiN, polyimide resin, or others.
  • The aperture 72 is formed with the bump 18, i.e., the bump 18 is formed on the exposure surface of the pad 16. In this semiconductor unit, the bump 18 is so formed as to reach over the passivation layer 70. The bump 18 is formed by a single or a plurality of layers, and is made of a metal such as gold, nickel, or copper. The bump 18 is not specifically defined by outer shape, and may be formed rectangular (including square and rectangle), or formed circular. The outer dimension of the bump 18 may be smaller than that of the pad 16. With this being the case, the bump 18 may be formed only in an area overlapping the pad 16.
  • Although not shown, a barrier layer may be formed at the bottom of the bump 18. The barrier layer may serve to prevent material dissipation for both the pad 16 and the bump 18. The barrier layer may be formed by a single or a plurality of layers, and may be formed by sputtering. The barrier layer may be also made to improve the adhesion between the pad 16 and the bump 18. The barrier layer may include a titanium tungsten (TiW) layer. When such a barrier layer is formed by a plurality of layers, the top surface of the barrier layer may be an electroplated metal layer, e.g., Au layer, for deposition of the bump 18.
  • With such a semiconductor unit as shown in FIG. 4, because the MIS transistor 30 is formed below the electrode 14, if the electrode 14 is pressurized and heated when being connected to any other component, not only the electrode 14 but also the components therebelow are affected thereby. As a result, this easily leads to failures of the devices compared with a case where the electrode 14 is formed therebelow with no device such as MIS transistor. With the examination method of this embodiment, however, the processes b and c enable to detect failures being highly likely to occur as a result of semiconductor chip implementation even prior to the implementation. This is surely applicable to a case where no MIS transistor is formed below the electrode 14.
  • After such an examination method, the wafer is diced by any known dicing technique so that semiconductor chips can be formed.
  • According to the embodiment, the following effects can be characteristically achieved.
  • First of all, with the examination method of the embodiment, any failures that are highly likely to occur as a result of semiconductor chip implementation can be detected beforehand, e.g., in the form of semiconductor wafer, so that screening can be performed with better reliability with respect to the resulting semiconductor chips. This favorably reduces the failure frequency of the semiconductor chips for use, and the resulting semiconductor chips can be increased in reliability. Such characteristics are considered advantageous especially with a semiconductor wafer in which devices such as MIS transistors are formed below the electrodes.
  • Secondly, with the examination method of the embodiment, in the process b, the upper surfaces of the electrodes 14 are pressed, preferably, pressed and heated so that the upper surface of the bump 18 of each of the electrodes 14 can be made flat. As such, in the resulting semiconductor chips, the bump 18 can be flat enough, and the electrodes 14 are highly reliable in terms of connection.
  • While the invention has been described in detail, the foregoing description is in all aspects not restrictive, and it is understood that numerous other modifications and variations can be devised. For example, the invention includes any configuration substantially the same as the configurations described in the embodiment, e.g., configurations leading to the same functions, methods, and results, or configurations leading to the same objects and effects. The invention also includes any configuration in which a component(s) are changed if not essential. The invention also includes any configuration leading to the same effects or achieving the same objects as those described in the embodiment. The invention also includes any configuration in which any known technique is taken into consideration for the configurations described in the embodiment.

Claims (26)

1. A method of manufacturing a semiconductor device, the method comprising:
preparing a wafer;
firstly inspecting the wafer;
the firstly inspecting being conducted for processes which follow the firstly inspecting.
2. The method according to claim 1,
the wafer including a semiconductor chip, the semiconductor chip including a transistor and an electrode, the electrode being disposed above a part of the transistor.
3. The method according to claim 2,
the semiconductor chip including an insulating layer formed above the transistor; and
the electrode being formed above the insulating layer.
4. The method according to claim 3,
the electrode including at least a pad, the pad being formed on the insulating layer.
5. The method according to claim 4,
the electrode including a bump, the bump being formed on the pad.
6. The method according to claim 5,
the bump being formed within the pad in a plan view.
7. The method according to claim 6,
the pad including aluminum or cupper; and
the bump including gold or nickel.
8. The method according to claim 1,
the firstly inspecting being a first electrical inspection.
9. The method according to claim 1,
the firstly inspecting being conducted by contacting a first needle to the electrode.
10. The method according to claim 1,
the firstly inspecting being conducted by firstly probing.
11. The method according to claim 1,
the firstly inspecting being conducted by using a first probe card.
12. The method according to claim 1,
the processes including a pressing or a heating.
13. The method according to claim 12,
the pressing or the heating being conducted by a pressure member or a bonding tool.
14. The method according to claim 12,
the pressing being conducted by about 45 MPa.
15. The method according to claim 12,
the heating being conducted by 300 to 350 degrees.
16. The method according to claim 12,
the pressing or the heating being conducted in a first condition that being more strict than a second condition of a mounting.
17. The method according to claim 12,
the pressing or the heating being conducted in a first condition that being more strict than a second condition of a mounting, the second condition being about 30 MPa.
18. The method according to claim 12,
the pressing or the heating being conducted in a first condition that being more strict than a second condition of a mounting, the second condition being less than or equal to about 300 degrees.
19. The method according to claim 16,
the mounting being a COG mounting.
20. The method according to claim 1,
the processes including a secondly inspecting.
21. The method according to claim 20,
the secondly inspecting being a second electrical inspection.
22. The method according to claim 20,
the secondly inspecting being conducted by contacting a second needle to the electrode.
23. The method according to claim 20,
the secondly inspecting being conducted by secondly probing.
24. The method according to claim 20,
the secondly inspecting being conducted by using a second probe card.
25. The method according to claim 17,
the mounting being a COG mounting.
26. The method according to claim 18,
the mounting being a COG mounting.
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US20070259458A1 (en) 2007-11-08
US20070254388A1 (en) 2007-11-01
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US20070018675A1 (en) 2007-01-25
US7598730B2 (en) 2009-10-06

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