US20070262435A1 - Three-dimensional packaging scheme for package types utilizing a sacrificial metal base - Google Patents

Three-dimensional packaging scheme for package types utilizing a sacrificial metal base Download PDF

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Publication number
US20070262435A1
US20070262435A1 US11/380,477 US38047706A US2007262435A1 US 20070262435 A1 US20070262435 A1 US 20070262435A1 US 38047706 A US38047706 A US 38047706A US 2007262435 A1 US2007262435 A1 US 2007262435A1
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United States
Prior art keywords
wirebond pads
conducting contact
mounting area
base layer
tunnels
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Abandoned
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US11/380,477
Inventor
Ken Lam
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Atmel Corp
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Atmel Corp
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Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to US11/380,477 priority Critical patent/US20070262435A1/en
Assigned to ATMEL CORPORATION reassignment ATMEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAM, KEN M.
Priority to US11/557,879 priority patent/US7564137B2/en
Priority to PCT/US2007/067315 priority patent/WO2007127739A2/en
Priority to CNA200780014844XA priority patent/CN101432868A/en
Priority to TW096114978A priority patent/TW200807683A/en
Publication of US20070262435A1 publication Critical patent/US20070262435A1/en
Priority to US12/479,407 priority patent/US7927918B2/en
Priority to US12/683,357 priority patent/US7981796B2/en
Abandoned legal-status Critical Current

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Definitions

  • the invention relates to a three-dimensional stackable semiconductor package, and more particularly, to a three-dimensional stackable semiconductor package for package types having a sacrificial metal base.
  • the chips include more bonding pads (or terminal pads), and thus packages for the chips have more external terminals (or leads).
  • a conventional plastic package that has its leads along the perimeter of the package must accommodate a large number of leads, the footprint of the package increases.
  • a goal in many electronic systems is to minimize an overall size of the systems.
  • pin pitch (or lead pitch) of the package must decrease.
  • a pin pitch of less than about 0.4 mm gives rise to many technical concerns. For example, trimming of a package having a pin pitch less than 0.4 mm requires expensive trimming tools, and the leads are prone to bending during handling of the package.
  • surface-mounting of such packages demands a costly and complicated surface-mounting process due to a required critical alignment step.
  • a micro ball grid array package ( ⁇ BGA) and a bump, chip carrier (BCC) are examples of the chip scale packages.
  • the ⁇ BGA package includes a polyimide tape on which a conductive pattern is formed and employs a totally different manufacturing process from a conventional plastic packaging.
  • the bump chip carrier package includes a substrate having grooves formed around a central portion of a top surface of a copper alloy plate and an electroplating layer formed in the grooves. Accordingly, chip scale packages use specialized packaging materials and processes that increase package manufacturing costs.
  • FIGS. 1A through 1C illustrate plan and cross-sectional views of a conventional apparatus for manufacturing leadless BCC packages.
  • a conventional metal carrier matrix array 101 has an upper surface 103 , which includes an encapsulating matrix 105 with a plurality of sawing lines 107 .
  • the cross-sectional view of FIG. 13 includes a plurality of bump pads 109 and a plurality of die pads 111 formed on the upper surface 103 of the metal carrier 101 by plating.
  • Back surfaces of integrated circuit dice 113 are attached to corresponding die pads 111 , and a plurality of bonding wires 115 connect a plurality of bonding pads 117 on active surfaces of the dice 113 to corresponding bump pads 109 .
  • a encapsulant 119 encapsulates the encapsulating matrix 105 including the dice 113 and the bonding wires 115 .
  • the bump pads 109 and the die pads 111 are exposed from the bottom surface 121 of the encapsulant 119 . Then, the encapsulant 119 is singulated by sawing along the sawing lines 107 to form a plurality of individual BCC packages.
  • a integrated circuit package that uses conventional packaging materials and processes can only be accessed for electrical interconnection, for example, to a printed circuit board, by the bump pads on the bottom surface 121 of the package. Consequently, what is needed to provide for a higher density of integrated circuit packaging into a given printed circuit board footprint is a means of allowing the integrated circuit packages to be stacked, one atop another.
  • the present invention is an apparatus and a method for packaging semiconductor devices.
  • the apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation volume surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating. The filled tunnels extend bottom contact pads to an uppermost portion of the encapsulated area.
  • the sacrificial metal base strip serves as a plating bus and is etch-removed after plating.
  • the filled tunnels allow components to be stacked in a three-dimensional configuration.
  • the invention may be applied to multiple dice or combinations of circuits and dice within stackable packages. Each of the stackable packages may then be stacked three-dimensionally while not increasing an overall footprint size of a mounting area on, for example, a printed circuit board.
  • the present invention is thus, in one exemplary embodiment, a semiconductor package matrix.
  • the semiconductor package matrix includes a plurality of three-dimensional stackable semiconductor packages arranged side-by-side in an array within the matrix and separated by kerf regions. The kerf regions are located at an outermost periphery of each of the plurality of three-dimensional stackable semiconductor packages.
  • Each of the plurality of three-dimensional stackable semiconductor packages includes an area for mounting an integrated circuit die and/or one or more discrete electrical components and a plurality of wirebond pads substantially coplanar with a die mounting area.
  • Each of the plurality of wirebond pads allows a bonding wire to provide electrical communication from either the integrated circuit die and/or the one or more discrete electrical components to outside of the packaged device.
  • a mold cap has a lowermost portion and an uppermost portion.
  • the lowermost portion is at a level substantially coplanar with the die mounting area and the plurality of wirebond pads.
  • the mold cap has a plurality of conducting contact tunnels, each of which is associated and arranged to be in electrical communication with a corresponding one of the plurality of wirebond pads once a conducting material fills the conducting contact tunnel.
  • the plurality of conducting contact tunnels extend from an uppermost portion of the plurality of wirebond pads to the uppermost portion of the mold cap.
  • the present invention is also a method of packaging a semiconductor device (or plurality of devices within a single package).
  • An exemplary embodiment of the method includes mounting an electrical component to a die mounting area and securing a plurality of bond wires from a plurality of bond pads on the electrical component to corresponding ones of a plurality of wirebond pads.
  • a mold cavity is provided which has a plurality of conducting contact tunnels. The contact tunnels are arranged such that the plurality of conducting contact tunnels are disposed over the plurality of wirebond pads.
  • the electrical component and the bond wires are encapsulated with a mold compound, substantially filling the mold cavity.
  • the plurality of conducting contact tunnels are then filled with an electrically conductive material.
  • FIGS. 1A-1C show a bumped chip carrier of the prior art.
  • FIGS. 2A-2E show exemplary cross-sections of stackable integrated circuit die and discrete component carriers in accord with the present invention.
  • a cross-sectional view of a potentially-stackable integrated circuit die and discrete component carriers includes a sacrificial metal base strip 201 , a plurality of die mounting areas 203 , and a plurality of wirebond pads 205 .
  • a plurality of integrated circuit dice 207 are mounted to corresponding ones of the plurality of die mounting areas 203 .
  • the plurality of integrated circuit dice 207 may also be discrete components (not shown) or a combination of integrated circuit dice and discrete components mounted to a plurality of die mounting areas.
  • the sacrificial metal base layer may be constructed from an electrically conducting non-metallic material such as, for example, polypropylene with embedded carbon particles or a polymer strip overplated with metal.
  • the plurality of dice 207 each include a plurality of bonding pads 209 . Once the plurality of dice 207 are mounted, a plurality of bonding wires 211 are used to electrically connect the plurality of bonding pads 209 to selected ones of the plurality of wirebond pads 205 .
  • the plurality of wirebond pads 205 , dice 207 , and bonding wires 211 are typically encapsulated in a molding compound.
  • the molding compound is introduced into a molding cavity (not shown) by a mold gate located at an edge of the sacrificial metal base strip 201 .
  • the molding compound is typically a polymeric precursor comprised of an epoxy base material filled with silica and anhydrides, requiring thermal energy for curing to form a polymeric encapsulant 215 .
  • the encapsulant 215 protects the fragile plurality of bonding wires 211 and their associated electrical connections, as well as the plurality of dice 207 .
  • tubes are located above each of the plurality of wirebond pads 205 , thus forming tunnels 213 after the encapsulant 215 is poured and formed.
  • the tubes may be formed by placing pins or other structures either into the mold or added afterwards (e.g., machined or welded into place into a mold cavity). Streets 217 indicate where the saw kerf is to run during a subsequent dicing operation.
  • the tunnels 213 have been filled with a conductor to produce a plurality of conducting metal contacts 219 .
  • the sacrificial metal base strip 201 provides electrical continuity required for an electrolytic plating process so the plurality of conducting metal contacts 219 (e.g., copper) can be fabricated by filling the tunnels 213 ( FIG. 2A ). Copper, or virtually any other metal, used for fabricating the plurality of conducting metal contacts 219 may then optionally be capped with, for example, nickel-gold alloy caps or another noble metal.
  • the plurality of conducting metal contacts 219 may be fabricated by, for example, plating with materials such as tungsten or tantalum into the tunnels 213 .
  • a conductive epoxy or polymer may be used to fill the tunnels 213 . The conductive epoxy is then cured in place.
  • the sacrificial metal base strip 201 is then etch removed ( FIG. 2C ) by processes known in the art.
  • Die mounting areas and wirebond pads may be plated with, for example, gold-nickel-gold or palladium-gold such that only the alloy bonding areas are left intact after etch.
  • the dice are then singulated ( FIG. 2D ), for example, by a die saw or laser, producing a first 251 and a second 253 packaged product.
  • the singulated first 251 and second 253 packaged products are mechanically stacked.
  • the plurality of conducting metal contacts 219 allow each of the wirebond pads 205 at one level (e.g., at the first packaged product 251 ) to be interconnected to another level (e.g., to the second packaged product 253 ) to be electrically connected through the use of solder (e.g., solder paste), conductive epoxy, metal bonding (e.g., through an application of ultrasonic or thermal forces), and so on.
  • solder e.g., solder paste
  • conductive epoxy e.g., conductive epoxy
  • metal bonding e.g., through an application of ultrasonic or thermal forces

Abstract

An apparatus and a method for packaging semiconductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration.

Description

    TECHNICAL FIELD
  • The invention relates to a three-dimensional stackable semiconductor package, and more particularly, to a three-dimensional stackable semiconductor package for package types having a sacrificial metal base.
    • BACKGROUND ART
  • As semiconductor integrated circuit chips become more multi-functional and highly integrated, the chips include more bonding pads (or terminal pads), and thus packages for the chips have more external terminals (or leads). When a conventional plastic package that has its leads along the perimeter of the package must accommodate a large number of leads, the footprint of the package increases. However, a goal in many electronic systems is to minimize an overall size of the systems. Thus, to accommodate a large number of pins without increasing the footprint of package, pin pitch (or lead pitch) of the package must decrease. However, a pin pitch of less than about 0.4 mm gives rise to many technical concerns. For example, trimming of a package having a pin pitch less than 0.4 mm requires expensive trimming tools, and the leads are prone to bending during handling of the package. In addition, surface-mounting of such packages demands a costly and complicated surface-mounting process due to a required critical alignment step.
  • Thus, to avoid technical problems associated with conventional fine-pitch packages, packages that have area array external terminals have been suggested. Among these packages are ball grid array packages and chip scale packages. The semiconductor industry presently uses a number of chip scale packages. A micro ball grid array package (μBGA) and a bump, chip carrier (BCC) are examples of the chip scale packages. The μBGA package includes a polyimide tape on which a conductive pattern is formed and employs a totally different manufacturing process from a conventional plastic packaging. The bump chip carrier package includes a substrate having grooves formed around a central portion of a top surface of a copper alloy plate and an electroplating layer formed in the grooves. Accordingly, chip scale packages use specialized packaging materials and processes that increase package manufacturing costs.
  • FIGS. 1A through 1C illustrate plan and cross-sectional views of a conventional apparatus for manufacturing leadless BCC packages. With reference to the plan view of FIG. 1A, a conventional metal carrier matrix array 101 has an upper surface 103, which includes an encapsulating matrix 105 with a plurality of sawing lines 107.
  • The cross-sectional view of FIG. 13 includes a plurality of bump pads 109 and a plurality of die pads 111 formed on the upper surface 103 of the metal carrier 101 by plating. Back surfaces of integrated circuit dice 113 are attached to corresponding die pads 111, and a plurality of bonding wires 115 connect a plurality of bonding pads 117 on active surfaces of the dice 113 to corresponding bump pads 109. A encapsulant 119 encapsulates the encapsulating matrix 105 including the dice 113 and the bonding wires 115.
  • With reference to the underside plan view of FIG. 10, after etching away the metal carrier 101 (not shown in FIG. 1C, the bump pads 109 and the die pads 111 are exposed from the bottom surface 121 of the encapsulant 119. Then, the encapsulant 119 is singulated by sawing along the sawing lines 107 to form a plurality of individual BCC packages.
  • Therefore, a integrated circuit package that uses conventional packaging materials and processes can only be accessed for electrical interconnection, for example, to a printed circuit board, by the bump pads on the bottom surface 121 of the package. Consequently, what is needed to provide for a higher density of integrated circuit packaging into a given printed circuit board footprint is a means of allowing the integrated circuit packages to be stacked, one atop another.
    • SUMMARY
  • The present invention is an apparatus and a method for packaging semiconductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation volume surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating. The filled tunnels extend bottom contact pads to an uppermost portion of the encapsulated area.
  • The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration. In a specific exemplary embodiment, the invention may be applied to multiple dice or combinations of circuits and dice within stackable packages. Each of the stackable packages may then be stacked three-dimensionally while not increasing an overall footprint size of a mounting area on, for example, a printed circuit board.
  • The present invention is thus, in one exemplary embodiment, a semiconductor package matrix. The semiconductor package matrix includes a plurality of three-dimensional stackable semiconductor packages arranged side-by-side in an array within the matrix and separated by kerf regions. The kerf regions are located at an outermost periphery of each of the plurality of three-dimensional stackable semiconductor packages. Each of the plurality of three-dimensional stackable semiconductor packages includes an area for mounting an integrated circuit die and/or one or more discrete electrical components and a plurality of wirebond pads substantially coplanar with a die mounting area. Each of the plurality of wirebond pads allows a bonding wire to provide electrical communication from either the integrated circuit die and/or the one or more discrete electrical components to outside of the packaged device.
  • A mold cap has a lowermost portion and an uppermost portion. The lowermost portion is at a level substantially coplanar with the die mounting area and the plurality of wirebond pads. The mold cap has a plurality of conducting contact tunnels, each of which is associated and arranged to be in electrical communication with a corresponding one of the plurality of wirebond pads once a conducting material fills the conducting contact tunnel. The plurality of conducting contact tunnels extend from an uppermost portion of the plurality of wirebond pads to the uppermost portion of the mold cap.
  • The present invention is also a method of packaging a semiconductor device (or plurality of devices within a single package). An exemplary embodiment of the method includes mounting an electrical component to a die mounting area and securing a plurality of bond wires from a plurality of bond pads on the electrical component to corresponding ones of a plurality of wirebond pads. A mold cavity is provided which has a plurality of conducting contact tunnels. The contact tunnels are arranged such that the plurality of conducting contact tunnels are disposed over the plurality of wirebond pads. The electrical component and the bond wires are encapsulated with a mold compound, substantially filling the mold cavity. The plurality of conducting contact tunnels are then filled with an electrically conductive material.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A-1C show a bumped chip carrier of the prior art.
  • FIGS. 2A-2E show exemplary cross-sections of stackable integrated circuit die and discrete component carriers in accord with the present invention.
    • DETAILED DESCRIPTION
  • In FIG. 2A, a cross-sectional view of a potentially-stackable integrated circuit die and discrete component carriers includes a sacrificial metal base strip 201, a plurality of die mounting areas 203, and a plurality of wirebond pads 205. As shown, a plurality of integrated circuit dice 207 are mounted to corresponding ones of the plurality of die mounting areas 203. Alternatively, the plurality of integrated circuit dice 207 may also be discrete components (not shown) or a combination of integrated circuit dice and discrete components mounted to a plurality of die mounting areas.
  • Also, the sacrificial metal base layer may be constructed from an electrically conducting non-metallic material such as, for example, polypropylene with embedded carbon particles or a polymer strip overplated with metal.
  • As known in the art, a thermally-conductive adhesive or adhesive tape (neither of which is shown) is commonly used for mounting the plurality of dice 207 to associated die mounting areas 203. As one skilled in the art will recognize, other types of adhesives (e.g., non-thermally conducting, electrically and non-electrically conducting, etc.) or other mounting techniques may be used as well. The plurality of dice 207 each include a plurality of bonding pads 209. Once the plurality of dice 207 are mounted, a plurality of bonding wires 211 are used to electrically connect the plurality of bonding pads 209 to selected ones of the plurality of wirebond pads 205.
  • The plurality of wirebond pads 205, dice 207, and bonding wires 211 are typically encapsulated in a molding compound. The molding compound is introduced into a molding cavity (not shown) by a mold gate located at an edge of the sacrificial metal base strip 201. The molding compound is typically a polymeric precursor comprised of an epoxy base material filled with silica and anhydrides, requiring thermal energy for curing to form a polymeric encapsulant 215. The encapsulant 215 protects the fragile plurality of bonding wires 211 and their associated electrical connections, as well as the plurality of dice 207. In this embodiment, tubes are located above each of the plurality of wirebond pads 205, thus forming tunnels 213 after the encapsulant 215 is poured and formed. The tubes may be formed by placing pins or other structures either into the mold or added afterwards (e.g., machined or welded into place into a mold cavity). Streets 217 indicate where the saw kerf is to run during a subsequent dicing operation.
  • With reference to FIG. 2E, the tunnels 213 have been filled with a conductor to produce a plurality of conducting metal contacts 219. In a specific exemplary embodiment the sacrificial metal base strip 201 provides electrical continuity required for an electrolytic plating process so the plurality of conducting metal contacts 219 (e.g., copper) can be fabricated by filling the tunnels 213 (FIG. 2A). Copper, or virtually any other metal, used for fabricating the plurality of conducting metal contacts 219 may then optionally be capped with, for example, nickel-gold alloy caps or another noble metal. Alternatively, the plurality of conducting metal contacts 219 may be fabricated by, for example, plating with materials such as tungsten or tantalum into the tunnels 213. Additionally, a conductive epoxy or polymer may be used to fill the tunnels 213. The conductive epoxy is then cured in place.
  • The sacrificial metal base strip 201 is then etch removed (FIG. 2C) by processes known in the art. Die mounting areas and wirebond pads may be plated with, for example, gold-nickel-gold or palladium-gold such that only the alloy bonding areas are left intact after etch. The dice are then singulated (FIG. 2D), for example, by a die saw or laser, producing a first 251 and a second 253 packaged product.
  • With reference to FIG. 2E, the singulated first 251 and second 253 packaged products are mechanically stacked. The plurality of conducting metal contacts 219 allow each of the wirebond pads 205 at one level (e.g., at the first packaged product 251) to be interconnected to another level (e.g., to the second packaged product 253) to be electrically connected through the use of solder (e.g., solder paste), conductive epoxy, metal bonding (e.g., through an application of ultrasonic or thermal forces), and so on. Thus, there is no limit on the number of packages than can be stacked.
  • In the foregoing specification, the present invention has been described with reference to specific embodiments thereto. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims, For example, skilled artisans will appreciate that embodiments of the present invention may be readily applied to TAPP® (thin array plastic package), ULGA® (ultra-thin land grid array), BCC® (bumped chip carrier), or other similar packages types. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (18)

1. A three-dimensional stackable semiconductor package comprising:
at least one die mounting area, the at least one die mounting area configured either to accept an integrated circuit die or one or more discrete electrical components;
a plurality of wirebond pads substantially coplanar with the at least one die mounting area, each of the plurality of wirebond pads configured to accept a bonding wire thereby providing electrical communication from either the integrated circuit die or the one or more discrete electrical components; and
a mold cap having a lowermost portion and an uppermost portion, the lowermost portion being at a level substantially coplanar with the at least one die mounting area and the plurality of wirebond pads, the mold cap also having a plurality of conducting contact tunnels, each of the plurality of conducting contact tunnels associated and arranged to be in electrical communication with a corresponding one of the plurality of wirebond pads once a conducting material fills the conducting contact tunnel, the plurality of conducting contact tunnels extending from an uppermost portion of the plurality of wirebond pads to the uppermost portion of the mold cap.
2. The three-dimensional stackable semiconductor package of claim 1 further comprising a sacrificial metal base layer, the sacrificial metal base layer serving as a mounting base and electrical contact for the at least one die mounting area and the plurality of wirebond pads.
3. The three-dimensional stackable semiconductor package of claim 2 wherein the sacrificial metal base layer is configured to be etch removed once an encapsulating mold compound is formed within the mold cap.
4. A three-dimensional stackable semiconductor package comprising:
at least one die mounting area, the at least one die mounting area configured either to accept an integrated circuit die or one or more discrete electrical components;
a plurality of wirebond pads substantially coplanar with the at least one die mounting area, each of the plurality of wirebond pads configured to accept a bonding wire thereby providing electrical communication from either the integrated circuit die or the one or more discrete electrical components;
a sacrificial base layer, the sacrificial base layer serving as a mounting base for the at least one die mounting area and the plurality of wirebond pads; and
a mold cap having a lowermost portion and an uppermost portion, the lowermost portion being at a level substantially coplanar with an uppermost surface of the sacrificial base layer, the mold cap also having a plurality of conducting contact tunnels, each of the plurality of conducting contact tunnels associated and arranged to be in electrical communication with a corresponding one of the plurality of wirebond pads once a conducting material fills the conducting contact tunnel, the plurality of conducting contact tunnels extending from an uppermost portion of the plurality of wirebond pads to the uppermost portion of the mold cap.
5. The three-dimensional stackable semiconductor package of claim 4 wherein the sacrificial base layer is comprised of a metallic material.
6. The three-dimensional stackable semiconductor package of claim 4 wherein the sacrificial base layer is comprised of a non-metallic electrically conducting material.
7. The three-dimensional stackable semiconductor package of claim 4 wherein the sacrificial base layer is configured to be etch removed once an encapsulating mold compound is formed within the mold cap.
8. A semiconductor package matrix comprising:
a plurality of three-dimensional stackable semiconductor packages arranged side-by-side in an array within the matrix and separated by kerf regions, the kerf regions being located at an outermost periphery of each of the plurality of three-dimensional stackable semiconductor packages, each of the plurality of three-dimensional stackable semiconductor packages including:
at least one die mounting area, the at least one die mounting area configured either to accept an integrated circuit die or one or more discrete electrical components;
a plurality of wirebond pads substantially coplanar with the at least one die mounting area, each of the plurality of wirebond pads configured to accept a bonding wire thereby providing electrical communication from either the integrated circuit die or the one or more discrete electrical components; and
a mold cap having a lowermost portion and an uppermost portion, the lowermost portion being at a level substantially coplanar with the at least one die mounting area and the plurality of wirebond pads, the mold cap also having a plurality of conducting contact tunnels, each of the plurality of conducting contact tunnels associated and arranged to be in electrical communication with a corresponding one of the plurality of wirebond pads once a conducting material fills the conducting contact tunnel, the plurality of conducting contact tunnels extending from an uppermost portion of the plurality of wirebond pads to the uppermost portion of the mold cap.
9. The semiconductor package matrix of claim 8 further comprising a sacrificial base layer, the sacrificial base layer serving as a mounting base for the at least one die mounting area and the plurality of wirebond pads.
10. The semiconductor package matrix of claim 9 wherein the sacrificial base layer is configured to be etch removed once an encapsulating mold compound is formed within the mold cap.
11. The semiconductor package matrix of claim 9 wherein the sacrificial base layer is comprised of metal.
12. A method of packaging a semiconductor device, the method comprising:
mounting an electrical component to a die mounting area;
securing a plurality of bond wires from a plurality of bond pads on the electrical component to corresponding ones of a plurality of wirebond pads;
providing a mold cavity having a plurality of conducting contact tunnels such that a first end of each of the plurality of conducting contact tunnels are disposed over and in contact with associated ones of the plurality of wirebond pads;
encapsulating the electrical component and the plurality of bond wires with a mold compound, the mold compound substantially filling the mold cavity; and
filling the plurality of conducting contact tunnels with an electrically conductive material.
13. The method of claim 12 further comprising selecting the electrically conductive fill material to be substantially comprised of copper.
14. The method of claim 12 further comprising providing an electrically conductive capping material to be disposed over exposed ends of the filled conducting contact tunnels.
15. The method of claim 14 wherein the capping material is selected to be a nickel-gold alloy.
16. The method of claim 12 further comprising etch-removing a sacrificial base material from the packaged semiconductor device.
17. The method of claim 12 further comprising stacking a plurality of semiconductor device packages, one atop another.
18. The method of claim 17, further comprising electrically coupling each of the plurality of filled conducting contact tunnels on a first packaged semiconductor device to each of the plurality of filled conducting contact tunnels on a second packaged semiconductor device.
US11/380,477 2006-04-27 2006-04-27 Three-dimensional packaging scheme for package types utilizing a sacrificial metal base Abandoned US20070262435A1 (en)

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US11/557,879 US7564137B2 (en) 2006-04-27 2006-11-08 Stackable integrated circuit structures and systems devices and methods related thereto
PCT/US2007/067315 WO2007127739A2 (en) 2006-04-27 2007-04-24 Three-dimensional packaging scheme for package types utilizing a sacrificail metal base
CNA200780014844XA CN101432868A (en) 2006-04-27 2007-04-24 Three-dimensional packaging scheme for package types utilizing a sacrificail metal base
TW096114978A TW200807683A (en) 2006-04-27 2007-04-27 Three-dimensional stackable semiconductor package, matrix, and method of packaging
US12/479,407 US7927918B2 (en) 2006-04-27 2009-06-05 Packaged products, including stacked package modules, and methods of forming same
US12/683,357 US7981796B2 (en) 2006-04-27 2010-01-06 Methods for forming packaged products

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070252255A1 (en) * 2006-04-27 2007-11-01 Atmel Corporation Multi-component package with both top and bottom side connection pads for three-dimensional packaging
US20090184412A1 (en) * 2007-10-25 2009-07-23 Rohm Co., Ltd. Resin-seal type semiconductor device
US20100172113A1 (en) * 2006-04-27 2010-07-08 Atmel Corporation Methods for forming packaged products
US20100314741A1 (en) * 2009-06-12 2010-12-16 Seongmin Lee Integrated circuit package stacking system with redistribution and method of manufacture thereof
US20110097855A1 (en) * 2007-07-18 2011-04-28 Infineon Technologies Ag Semiconductor device
US20110127648A1 (en) * 2008-11-14 2011-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Heat Spreader Structures in Scribe Lines
US8643147B2 (en) 2007-11-01 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with improved cracking protection and reduced problems
US9412709B2 (en) 2013-05-21 2016-08-09 Freescale Semiconductor, Inc. Semiconductor structure with sacrificial anode and passivation layer and method for forming
US20170154870A1 (en) * 2015-04-17 2017-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete Polymer in Fan-Out Packages

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021907B2 (en) * 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US8201326B2 (en) * 2008-12-23 2012-06-19 Infineon Technologies Ag Method of manufacturing a semiconductor device
CN103515249B (en) * 2013-08-06 2016-02-24 江苏长电科技股份有限公司 First be honored as a queen and lose three-dimensional systematic chip formal dress bump packaging structure and process
CN110233113A (en) * 2019-06-17 2019-09-13 青岛歌尔微电子研究院有限公司 A kind of packaging method of chip

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585675A (en) * 1994-05-11 1996-12-17 Harris Corporation Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
US5744827A (en) * 1995-11-28 1998-04-28 Samsung Electronics Co., Ltd. Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements
US6038133A (en) * 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US6320251B1 (en) * 2000-01-18 2001-11-20 Amkor Technology, Inc. Stackable package for an integrated circuit
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6489676B2 (en) * 2000-12-04 2002-12-03 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
US6674159B1 (en) * 2000-05-16 2004-01-06 Sandia National Laboratories Bi-level microelectronic device package with an integral window
US6784530B2 (en) * 2002-01-23 2004-08-31 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module with embedded semiconductor chip and method of manufacturing
US20050006768A1 (en) * 2003-02-27 2005-01-13 Mukundan Narasimhan Dielectric barrier layer films
US20050035357A1 (en) * 1997-02-18 2005-02-17 Tessera, Inc. Semiconductor package having light sensitive chips
US20050067680A1 (en) * 2003-09-30 2005-03-31 Boon Suan Jeung Castellated chip-scale packages and methods for fabricating the same
US20050218499A1 (en) * 2004-03-31 2005-10-06 Advanced Semiconductor Engineering, Inc. Method for manufacturing leadless semiconductor packages
US20060022332A1 (en) * 2004-07-30 2006-02-02 Tetsuya Koyama Semiconductor chip-embedded substrate and method of manufacturing same
US20060027908A1 (en) * 2004-08-03 2006-02-09 Shu-Ming Chang 3-D stackable semiconductor package
US20070252255A1 (en) * 2006-04-27 2007-11-01 Atmel Corporation Multi-component package with both top and bottom side connection pads for three-dimensional packaging

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002158312A (en) * 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd Semiconductor package for three-dimensional mounting, its manufacturing method and semiconductor device
US7034386B2 (en) * 2001-03-26 2006-04-25 Nec Corporation Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same
JP4204989B2 (en) * 2004-01-30 2009-01-07 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US7242081B1 (en) * 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US20070262435A1 (en) 2006-04-27 2007-11-15 Atmel Corporation Three-dimensional packaging scheme for package types utilizing a sacrificial metal base
US20080110135A1 (en) * 2006-11-15 2008-05-15 Jacob Jeffrey G Packaging machine with pivoting minor flap retainer and rotating glue gun assembly

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585675A (en) * 1994-05-11 1996-12-17 Harris Corporation Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
US5744827A (en) * 1995-11-28 1998-04-28 Samsung Electronics Co., Ltd. Three dimensional stack package device having exposed coupling lead portions and vertical interconnection elements
US20050035357A1 (en) * 1997-02-18 2005-02-17 Tessera, Inc. Semiconductor package having light sensitive chips
US6038133A (en) * 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6294407B1 (en) * 1998-05-06 2001-09-25 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein, and methods of fabricating the same
US20030038378A1 (en) * 1998-05-06 2003-02-27 Virtual Integration, Inc. Microelectronic packages including thin film decal and dielectric adhesive layer having conductive vias therein
US20020125571A1 (en) * 1998-06-30 2002-09-12 Corisis David J. Module assembly for stacked BGA packages
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6563217B2 (en) * 1998-06-30 2003-05-13 Micron Technology, Inc. Module assembly for stacked BGA packages
US20030197271A1 (en) * 1998-06-30 2003-10-23 Corisis David J. Module assembly for stacked BGA packages
US20050110135A1 (en) * 1998-06-30 2005-05-26 Corisis David J. Module assembly and method for stacked BGA packages
US6838768B2 (en) * 1998-06-30 2005-01-04 Micron Technology Inc Module assembly for stacked BGA packages
US6320251B1 (en) * 2000-01-18 2001-11-20 Amkor Technology, Inc. Stackable package for an integrated circuit
US6674159B1 (en) * 2000-05-16 2004-01-06 Sandia National Laboratories Bi-level microelectronic device package with an integral window
US6489676B2 (en) * 2000-12-04 2002-12-03 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
US6784530B2 (en) * 2002-01-23 2004-08-31 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module with embedded semiconductor chip and method of manufacturing
US20050006768A1 (en) * 2003-02-27 2005-01-13 Mukundan Narasimhan Dielectric barrier layer films
US20050067680A1 (en) * 2003-09-30 2005-03-31 Boon Suan Jeung Castellated chip-scale packages and methods for fabricating the same
US20050218499A1 (en) * 2004-03-31 2005-10-06 Advanced Semiconductor Engineering, Inc. Method for manufacturing leadless semiconductor packages
US20060022332A1 (en) * 2004-07-30 2006-02-02 Tetsuya Koyama Semiconductor chip-embedded substrate and method of manufacturing same
US20060027908A1 (en) * 2004-08-03 2006-02-09 Shu-Ming Chang 3-D stackable semiconductor package
US20070252255A1 (en) * 2006-04-27 2007-11-01 Atmel Corporation Multi-component package with both top and bottom side connection pads for three-dimensional packaging

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7927918B2 (en) 2006-04-27 2011-04-19 Atmel Corporation Packaged products, including stacked package modules, and methods of forming same
US7564137B2 (en) 2006-04-27 2009-07-21 Atmel Corporation Stackable integrated circuit structures and systems devices and methods related thereto
US20070252255A1 (en) * 2006-04-27 2007-11-01 Atmel Corporation Multi-component package with both top and bottom side connection pads for three-dimensional packaging
US20090302449A1 (en) * 2006-04-27 2009-12-10 Atmel Corporation Packaged products, including stacked package modules, and methods of forming same
US20100172113A1 (en) * 2006-04-27 2010-07-08 Atmel Corporation Methods for forming packaged products
US7981796B2 (en) 2006-04-27 2011-07-19 Atmel Corporation Methods for forming packaged products
US8343811B2 (en) * 2007-07-18 2013-01-01 Infineon Technologies Ag Semiconductor device
US8658472B2 (en) 2007-07-18 2014-02-25 Infineon Technologies Ag Semiconductor device
US20110096519A1 (en) * 2007-07-18 2011-04-28 Infineon Technologies Ag Semiconductor device
US20110097855A1 (en) * 2007-07-18 2011-04-28 Infineon Technologies Ag Semiconductor device
US8324739B2 (en) 2007-07-18 2012-12-04 Infineon Technologies Ag Semiconductor device
US9484282B2 (en) * 2007-10-25 2016-11-01 Rohm Co., Ltd. Resin-sealed semiconductor device
US20090184412A1 (en) * 2007-10-25 2009-07-23 Rohm Co., Ltd. Resin-seal type semiconductor device
US8643147B2 (en) 2007-11-01 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structure with improved cracking protection and reduced problems
US8860208B2 (en) * 2008-11-14 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreader structures in scribe lines
US20110127648A1 (en) * 2008-11-14 2011-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Heat Spreader Structures in Scribe Lines
US20100314741A1 (en) * 2009-06-12 2010-12-16 Seongmin Lee Integrated circuit package stacking system with redistribution and method of manufacture thereof
US9355962B2 (en) * 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
US9412709B2 (en) 2013-05-21 2016-08-09 Freescale Semiconductor, Inc. Semiconductor structure with sacrificial anode and passivation layer and method for forming
US10199339B2 (en) 2013-05-21 2019-02-05 Nxp Usa, Inc. Semiconductor structure with sacrificial anode and method for forming
US20170154870A1 (en) * 2015-04-17 2017-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete Polymer in Fan-Out Packages
US9837379B2 (en) * 2015-04-17 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US10269764B2 (en) 2015-04-17 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US10700040B2 (en) 2015-04-17 2020-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US11145622B2 (en) 2015-04-17 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US11676939B2 (en) 2015-04-17 2023-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages

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US7981796B2 (en) 2011-07-19
CN101432868A (en) 2009-05-13

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