US20070278729A1 - Method for forming interconnects on thin wafers - Google Patents
Method for forming interconnects on thin wafers Download PDFInfo
- Publication number
- US20070278729A1 US20070278729A1 US11/772,862 US77286207A US2007278729A1 US 20070278729 A1 US20070278729 A1 US 20070278729A1 US 77286207 A US77286207 A US 77286207A US 2007278729 A1 US2007278729 A1 US 2007278729A1
- Authority
- US
- United States
- Prior art keywords
- wafer
- shim
- ring
- fixture
- lip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
- B23K3/06—Solder feeding devices; Solder melting pans
- B23K3/0607—Solder feeding devices
- B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05006—Dual damascene structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05016—Shape in side view
- H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05171—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11472—Profile of the lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/742—Apparatus for manufacturing bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Definitions
- the present invention relates to the field of semiconductor processing; more specifically, it relates to a method of forming a solder interconnect structure on a thin wafer.
- a first aspect of the present invention is a method of forming a semiconductor interconnect comprising, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.
- a second aspect of the present invention is a method of forming a semiconductor interconnect comprising, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer to produce a reduced thickness wafer; (d) providing an evaporation fixture comprising a bottom ring, a shim, an evaporation mask and a top ring; (e) placing the shim into the bottom ring; (f) placing the reduced thickness wafer on the shim; (g) placing on and aligning the mask to the reduced thickness wafer; (h) placing said top ring over said mask and temporarily fastening said top ring to said bottom ring; (i) evaporating solder bumps on the bonding pads through the mask; (j) removing the reduced thickness wafer from the fixture; and (k) dicing the reduced thickness wafer into bumped semiconductor chips.
- a third aspect of the present invention is A fixture for holding wafer and an evaporative mask comprising: a bottom ring having a inner periphery and an outer periphery, the bottom ring having a raised inner lip formed along the inner periphery and a raised outer lip formed along the outer periphery, the height of the inner lip above a surface of the bottom ring being greater than a height of the outer lip above the surface of the bottom ring; a shim having a inner and an outer periphery, the outer periphery of the shim fitting inside and in proximity to the outer lip of the bottom ring, a bottom surface of the shim proximate to the inner periphery of the shim contacting an upper surface of the inner lip of the bottom ring; a top ring having an inner periphery and an outer periphery, the top ring having a lower raised lip formed along the inner periphery of the bottom ring and extending below a bottom surface of the top ring; and the
- FIGS. 1A through 1F are partial cross-sectional views of the fabrication of a semiconductor wafer according to the present invention.
- FIG. 2 is a cross-sectional view through an interconnect structure formed by the present invention
- FIG. 3A is a top view of a base portion of a wafer to mask alignment fixture for forming interconnects according to the present invention
- FIG. 3B is a cross-section view through line 3 B- 3 B of FIG. 3A ;
- FIG. 4 is a top view of an evaporative mask portion of the wafer to mask alignment fixture for forming interconnects according to the present invention
- FIG. 5A is a top view of a top portion of the wafer to mask alignment fixture for forming interconnects according to the present invention
- FIG. 5B is a cross-section view through line 5 B- 5 B of FIG. 5A ;
- FIG. 6A is a top view of a shim portion of a wafer to mask alignment fixture for forming interconnects according to the present invention
- FIG. 6B is a cross-section view through line 6 B- 6 B of FIG. 6A ;
- FIG. 7 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects according to the present invention.
- FIG. 8 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects illustrating dimensional relationships between the component parts of the wafer to mask alignment fixture according to the present invention.
- substrate and wafer may be used interchangeably.
- FIGS. 1A through 1F are partial cross-sectional views of the fabrication of a semiconductor wafer according to the present invention.
- a substrate 100 such as a semiconductor bulk silicon substrate or a semiconductor silicon-on-insulator (SOI) substrate has a thickness T 1 .
- Formed in/on substrate 100 is a multiplicity of active Field effect transistors (FETs) 105 .
- FETs 105 include gate electrodes 115 formed over gate dielectric formed 116 and between spacers 117 on a top surface 110 of substrate 100 and source/drains 118 formed in the substrate.
- FETs 105 are exemplary of devices and structures normally found in semiconductor circuits of semiconductor chips and many other structures and devices such as capacitors, resistors, inductors, bipolar transistors and diffused and dielectric isolation. FETs 105 are wired into circuits in a first wiring level 120 A, a second wiring level 120 B, a third wiring level 120 C and a terminal wiring level 120 D.
- First wiring level contains contacts 125 interconnecting FETs 105 to conductors 125 B in second wiring layer 120 B.
- Conductors 125 B are in turn connected to conductors 125 C in third wiring level 120 C.
- Conductors 125 C are in turn connected to terminal conductors 125 D in terminal wiring level 120 D.
- Terminal conductors 125 D include a multiplicity of bonding pads 130 . Bonding pads 130 are exposed on surface 135 of terminal wiring layer 120 D.
- First wiring level 120 A, second wiring level 120 B, third wiring level 120 C and terminal wiring level 120 D are exemplary of wiring levels found in semiconductor chips and more or less wiring levels fabricated by any number of methods well known in the art such as subetch, liftoff, damascene and dual damascene may be used.
- Substrate 100 has a backside surface 140 .
- wafer 100 A is reduced from thickness T 1 (see FIG. 1A ) to a new thickness T 2 (where T 1 >T 2 ) by any number of wafer thinning techniques well known in the art.
- backside surface 140 (see FIG. 1A ) is ground down to a new backside surface 145 by grinding the backside surface with a rotating diamond grindstone.
- backside surface 140 (see FIG. 1A ) is etched down to new backside surface 145 by etching the backside surface with a mixture of hydrofluoric and nitric acids while rotating the wafer.
- backside surface 140 see FIG.
- backside surface 140 (see FIG. 1A ) is lapped down to new backside surface 145 by introducing a slurry containing abrasive particles between the backside of the wafer and a rotating wheel.
- backside surface 140 (see FIG. 1A ) is chemical-mechanical-polished (CMP) down to new backside surface 145 by introducing a slurry containing abrasive particles mixed with a silicon etchant solution between the backside of the wafer and a rotating wheel.
- CMP chemical-mechanical-polished
- a 200 mm diameter wafer having an initial thickness T 1 of about 650 to 780 microns is thinned to a new thickness T 2 of about 150 to 450 microns.
- the present invention may be practiced using any diameter wafer including 100 mm, 125 mm and 300 mm wafer of any initial thickness T 1 , reducing the wafer to any final thickness T 2 as required by the use of the finished chip.
- an evaporative mask 150 having openings 155 is placed on top surface 135 (or very close to top surface 135 ) of terminal wiring level 120 D. Openings 155 are aligned to bonding pads 130 . Openings 155 have inner knife-edges 160 .
- Evaporative mask 150 is typical of the type of mask used to fabricate controlled collapse chip connection (C 4 ) interconnect structures. C 4 interconnect structures are also known as solder bump interconnections. In one example, mask 150 is made from molybdenum.
- a pad limiting metallurgy (PLM) 165 is evaporated through opening 155 onto bonding pads 130 .
- PLM 165 is discussed more fully infra in reference to FIG. 2 .
- PLM is also known as ball limiting metallurgy (BLM).
- solder bump 170 has the shape of a truncated cone.
- solder bumps 170 are discussed more fully infra in reference to FIG. 2 .
- FIG. 2 is a cross-sectional view through an interconnect structure formed by the present invention.
- terminal wiring level 120 D includes bonding pad 125 D embedded in a dielectric layer 175 .
- bonding pad 125 D is aluminum, copper or alloys thereof.
- Formed on top of dielectric layer 175 is an optional capping layer 180 .
- capping layer 180 is silicon nitride.
- Formed on top of capping layer 180 is an optional passivation layer 185 .
- passivation layer 185 is silicon dioxide, silicon nitride, silicon oxynitride or combinations thereof.
- Formed on top of passivation layer 185 is an optional dielectric layer 190 .
- dielectric layer 190 is polyimide.
- An optional via 195 is provided through capping layer 180 , passivation layer 185 and dielectric layer 190 exposing bonding pad 125 D in terminal wiring level 120 D.
- Via 195 may be formed by any number of well known plasma etch techniques.
- PLM 165 is formed over dielectric layer 190 , sidewalls of via 195 and exposed portions of terminal wiring level 120 D.
- PLM 165 is titanium nitride, copper, gold, titanium-tungsten, chrome, chrome-copper or combinations thereof. A typical combination is gold over copper over chrome. Another typical combination is copper over chrome copper over titanium-tungsten.
- PLM 165 is in electrical contact with bonding pad 130 .
- C 4 ball 170 A is formed on and in electrical contact with PLM 165 .
- C 4 ball 170 A compositions include but are not limited to 95% lead and 5% tin, 97% lead and 3% tin, 100% lead, other lead alloys, 100% tin and tin alloys.
- the reflow anneal mentioned supra is performed at a temperature of between about 350° C. and 380° C. in a reducing atmosphere such as hydrogen or forming gas.
- Thinned substrate 100 A may now be diced into individual thin chips.
- the evaporation process for forming PLMs 165 and solder bumps 170 is performed by placing the semiconductor substrate in wafer to mask alignment fixture that allows alignment of mask 150 to thinned substrate 100 A (see FIG. 1E ).
- the evaporation process includes loading multiple wafer to mask alignment fixtures (with wafers and masks and in the case of the present invention, shims) into spaces in a dome of a multi-source evaporator and each material of PLM and then the solder pad are evaporated onto contacts pads on the wafer through holes in a mask.
- Such a wafer to mask alignment fixture is illustrated in FIGS. 3A, 3B , 4 , 5 A, 5 B, 6 A and 6 B and described infra.
- FIG. 3A is a top view of a base portion of a wafer to mask alignment fixture for forming interconnects according to the present invention
- FIG. 3B is a cross-section view through line 3 B- 3 B of FIG. 3A
- a bottom ring 200 includes an outer lip 205 and an inner lip 210 joined by an integral plate portion 215 .
- Inner lip 210 defines the extent of an opening 220 centered in bottom ring 200 .
- Plate portion 215 includes a multiplicity of openings 225 and a multiplicity of retaining post holes 227 . Opening 220 provides access for a wafer handling fixture (not shown) and openings 225 are for thermal expansion and heat retention control.
- Bottom ring 200 has a diameter D 1 and opening 220 has a diameter D 2 .
- the inside distance between opposite points on outer lip 205 is D 3 .
- Outer lip 205 has a height H 1 measured from a top surface 230 of plate portion 215 and inner lip 210 has a height H 2 measured from the top surface of the plate portion.
- H 2 is about 0.080 inches and H 1 is about 0.073 inches, making H 3 about 0.007 inches.
- H 1 and H 2 will vary based on wafer diameters and standard un-thinned wafer thickness.
- FIG. 4 is a top view of an evaporative mask portion of the wafer to mask alignment fixture for forming interconnects according to the present invention.
- mask 250 includes a multiplicity of openings 255 arranged in groups 260 . Each group 260 corresponds to a chip on a wafer that will be placed under mask 250 as illustrated in FIG. 7 and described infra.
- Mask 250 has a diameter of D 1 , the same as the diameter of bottom ring 200 illustrated in FIG. 3A and described supra.
- Mask 250 includes a multiplicity of retaining post holes 262 .
- FIG. 5A is a top view of a top portion of the wafer to mask alignment fixture for forming interconnects according to the present invention and FIG. 5B is a cross-section view through line 5 B- 5 B of FIG. 5A .
- top ring 270 has a lower lip 275 protruding from a bottom surface 280 of the top ring. Lower ring 275 protrudes a distance H 4 . In one example, for a standard 200 mm diameter wafer having a thickness of about 650 microns, H 4 is about 0.002 inches.
- Top ring 270 includes an opening 280 centered within ring 270 .
- Top ring 270 has a diameter of D 1 , the same as the diameter of bottom ring 200 illustrated in FIG. 3A and described supra.
- Top ring 270 includes a multiplicity of retaining posts 282 .
- FIG. 6A is a top view of a shim portion of a wafer to mask alignment fixture for forming interconnects according to the present invention and FIG. 6B is a cross-section view through line 6 B- 6 B of FIG. 6A .
- a shim 290 has an opening 295 centered within the shim.
- Shim 290 has a diameter D 3 A where D 3 A is just slightly smaller than D 3 , the inside distance between opposite points on outer lip 205 (see FIG. 3A ).
- D 3 is greater than the diameter of the wafer being held in the fixture.
- Opening 295 has a diameter D 2 the same as the diameter of opening 220 of bottom ring 200 illustrated in FIG. 3A and described supra.
- Shim 290 has a thickness T 3 .
- Shim 290 includes a multiplicity of retaining post notches 297 in a perimeter 298 of the shim.
- FIG. 7 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects according to the present invention.
- shim 290 is placed in bottom ring 200 (contacting inner lip 210 )
- thinned substrate 100 A is placed on shim 290
- mask 250 is placed on thinned substrate 100 A
- top ring 270 is placed on mask 250 .
- Mask 250 is pressed between top ring 270 and outer lip 205 of bottom ring 200 and lower lip 275 of the top ring presses on mask 250 .
- the only portion of bottom ring 200 contacted by shim 290 is inner lip 210 .
- Retaining post 282 passes through retaining post hole 262 in mask 250 , retaining post notches 297 in shim 290 and retaining post hole 227 in bottom ring 200 .
- a spring clip 310 engages retaining post 305 and temporarily fastens assembled fixture 300 together.
- FIG. 8 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects illustrating dimensional relationships between the component parts of the wafer to mask alignment fixture according to the present invention.
- the dimensions H 1 , H 2 of outer and inner lips 205 and 210 of bottom ring 200 and the dimension H 4 of lower lip 275 of top ring 270 are experimentally determined for each combination of wafer diameter and standard un-thinned wafer thickness. Note it is possible that one wafer manufacturer may produce standard 200 mm diameter wafers that are 780 microns thick, while another manufacturer may produce standard 200 mm diameter wafers that are 640 microns thick.
- T 3 thickness
- T 1 un-thinned or standard wafer thickness that fixture is designed for
- T 2 thinned wafer thickness
- the second method is to experimentally determine for a given thinned wafer thickness (T 2 ) a shim thickness (T 3 ) that yields the same wafer deflection (D 4 ) (see FIG. 7 ) as the un-thinned standard wafer (of thickness T 1 ) that the fixture was designed for.
- T 2 thinned wafer thickness
- T 3 shim thickness
- D 4 wafer deflection
- FIG. 7 the un-thinned standard wafer
- T 3 will be selected from an experimentally determined table of shim thickness (T 3 ) versus thinned wafer thickness (T 2 ) versus wafer deflection (D 4 ) to give the same wafer deflection (D 4 ) with a shim in place as a 640 micron thick wafer even if the original thickness of the wafer was not equal to 640 microns.
Abstract
A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.
Description
- This Application is a division of U.S. patent application Ser. No. 11/184,695 filed on Jul. 19, 2005, which is a division of U.S. patent application Ser. No. 10/604,164 filed on Jun. 28, 2003, now U.S. Pat. No. 6,951,775.
- The present invention relates to the field of semiconductor processing; more specifically, it relates to a method of forming a solder interconnect structure on a thin wafer.
- Increasing density of semiconductor devices has allowed semiconductor chips to decrease in area. Along with the decrease in chip area, has come a need to make the semiconductor chips thinner. Current methods of thinning semiconductor wafers often lead to damage of the semiconductor chips.
- A first aspect of the present invention is a method of forming a semiconductor interconnect comprising, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.
- A second aspect of the present invention is a method of forming a semiconductor interconnect comprising, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer to produce a reduced thickness wafer; (d) providing an evaporation fixture comprising a bottom ring, a shim, an evaporation mask and a top ring; (e) placing the shim into the bottom ring; (f) placing the reduced thickness wafer on the shim; (g) placing on and aligning the mask to the reduced thickness wafer; (h) placing said top ring over said mask and temporarily fastening said top ring to said bottom ring; (i) evaporating solder bumps on the bonding pads through the mask; (j) removing the reduced thickness wafer from the fixture; and (k) dicing the reduced thickness wafer into bumped semiconductor chips.
- A third aspect of the present invention is A fixture for holding wafer and an evaporative mask comprising: a bottom ring having a inner periphery and an outer periphery, the bottom ring having a raised inner lip formed along the inner periphery and a raised outer lip formed along the outer periphery, the height of the inner lip above a surface of the bottom ring being greater than a height of the outer lip above the surface of the bottom ring; a shim having a inner and an outer periphery, the outer periphery of the shim fitting inside and in proximity to the outer lip of the bottom ring, a bottom surface of the shim proximate to the inner periphery of the shim contacting an upper surface of the inner lip of the bottom ring; a top ring having an inner periphery and an outer periphery, the top ring having a lower raised lip formed along the inner periphery of the bottom ring and extending below a bottom surface of the top ring; and the bottom ring and the top ring adapted to press a bottom surface of the wafer against an upper surface of the shim and to press a top surface of the wafer against a bottom surface of the mask and to press a top surface of the mask proximate to the periphery of the mask against a lower surface of the lower raised lip of the top ring.
- The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
-
FIGS. 1A through 1F are partial cross-sectional views of the fabrication of a semiconductor wafer according to the present invention; -
FIG. 2 is a cross-sectional view through an interconnect structure formed by the present invention; -
FIG. 3A is a top view of a base portion of a wafer to mask alignment fixture for forming interconnects according to the present invention; -
FIG. 3B is a cross-section view throughline 3B-3B ofFIG. 3A ; -
FIG. 4 is a top view of an evaporative mask portion of the wafer to mask alignment fixture for forming interconnects according to the present invention; -
FIG. 5A is a top view of a top portion of the wafer to mask alignment fixture for forming interconnects according to the present invention; -
FIG. 5B is a cross-section view throughline 5B-5B ofFIG. 5A ; -
FIG. 6A is a top view of a shim portion of a wafer to mask alignment fixture for forming interconnects according to the present invention; -
FIG. 6B is a cross-section view throughline 6B-6B ofFIG. 6A ; -
FIG. 7 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects according to the present invention; and -
FIG. 8 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects illustrating dimensional relationships between the component parts of the wafer to mask alignment fixture according to the present invention. - For the purposes of the present invention, the terms substrate and wafer may be used interchangeably.
-
FIGS. 1A through 1F are partial cross-sectional views of the fabrication of a semiconductor wafer according to the present invention. InFIG. 1A , asubstrate 100 such as a semiconductor bulk silicon substrate or a semiconductor silicon-on-insulator (SOI) substrate has a thickness T1. Formed in/onsubstrate 100 is a multiplicity of active Field effect transistors (FETs) 105. FETs 105 includegate electrodes 115 formed over gate dielectric formed 116 and betweenspacers 117 on atop surface 110 ofsubstrate 100 and source/drains 118 formed in the substrate.FETs 105 are exemplary of devices and structures normally found in semiconductor circuits of semiconductor chips and many other structures and devices such as capacitors, resistors, inductors, bipolar transistors and diffused and dielectric isolation. FETs 105 are wired into circuits in afirst wiring level 120A, asecond wiring level 120B, athird wiring level 120C and aterminal wiring level 120D. First wiring level containscontacts 125 interconnectingFETs 105 toconductors 125B insecond wiring layer 120B.Conductors 125B are in turn connected toconductors 125C inthird wiring level 120C.Conductors 125C are in turn connected toterminal conductors 125D interminal wiring level 120D.Terminal conductors 125D include a multiplicity ofbonding pads 130.Bonding pads 130 are exposed onsurface 135 ofterminal wiring layer 120D.First wiring level 120A,second wiring level 120B,third wiring level 120C andterminal wiring level 120D are exemplary of wiring levels found in semiconductor chips and more or less wiring levels fabricated by any number of methods well known in the art such as subetch, liftoff, damascene and dual damascene may be used.Substrate 100 has abackside surface 140. - In
FIG. 1B ,wafer 100A is reduced from thickness T1 (seeFIG. 1A ) to a new thickness T2 (where T1>T2) by any number of wafer thinning techniques well known in the art. In a first example, backside surface 140 (seeFIG. 1A ) is ground down to anew backside surface 145 by grinding the backside surface with a rotating diamond grindstone. In a second example, backside surface 140 (seeFIG. 1A ) is etched down tonew backside surface 145 by etching the backside surface with a mixture of hydrofluoric and nitric acids while rotating the wafer. In a third example, backside surface 140 (seeFIG. 1A ) is lapped down tonew backside surface 145 by introducing a slurry containing abrasive particles between the backside of the wafer and a rotating wheel. In a fourth example, backside surface 140 (seeFIG. 1A ) is chemical-mechanical-polished (CMP) down tonew backside surface 145 by introducing a slurry containing abrasive particles mixed with a silicon etchant solution between the backside of the wafer and a rotating wheel. - In one example of thinning, a 200 mm diameter wafer having an initial thickness T1 of about 650 to 780 microns is thinned to a new thickness T2 of about 150 to 450 microns. The present invention may be practiced using any diameter wafer including 100 mm, 125 mm and 300 mm wafer of any initial thickness T1, reducing the wafer to any final thickness T2 as required by the use of the finished chip.
- In
FIG. 1C anevaporative mask 150 havingopenings 155 is placed on top surface 135 (or very close to top surface 135) ofterminal wiring level 120D.Openings 155 are aligned tobonding pads 130.Openings 155 have inner knife-edges 160.Evaporative mask 150 is typical of the type of mask used to fabricate controlled collapse chip connection (C4) interconnect structures. C4 interconnect structures are also known as solder bump interconnections. In one example,mask 150 is made from molybdenum. - In
FIG. 1D , a pad limiting metallurgy (PLM) 165 is evaporated throughopening 155 ontobonding pads 130.PLM 165 is discussed more fully infra in reference toFIG. 2 . PLM is also known as ball limiting metallurgy (BLM). - In
FIG. 1E ,mask 150 is not moved and asolder bump 170 is evaporated throughopening 155 ontoPLM 165.Solder bump 170 has the shape of a truncated cone. - In
FIG. 1F , mask 150 (seeFIG. 1E ) is removed and a reflow anneal is performed in order to reshapesolder bumps 170 into semi-spherical solder bumps (also known as solder balls or C4 balls) 170A. Solder bumps 170A are discussed more fully infra in reference toFIG. 2 . -
FIG. 2 is a cross-sectional view through an interconnect structure formed by the present invention. InFIG. 2 ,terminal wiring level 120D includesbonding pad 125D embedded in adielectric layer 175. In one example,bonding pad 125D is aluminum, copper or alloys thereof. Formed on top ofdielectric layer 175 is anoptional capping layer 180. In one example, cappinglayer 180 is silicon nitride. Formed on top of cappinglayer 180 is anoptional passivation layer 185. In one example,passivation layer 185 is silicon dioxide, silicon nitride, silicon oxynitride or combinations thereof. Formed on top ofpassivation layer 185 is anoptional dielectric layer 190. In one example,dielectric layer 190 is polyimide. An optional via 195 is provided throughcapping layer 180,passivation layer 185 anddielectric layer 190 exposingbonding pad 125D interminal wiring level 120D. Via 195 may be formed by any number of well known plasma etch techniques.PLM 165 is formed overdielectric layer 190, sidewalls of via 195 and exposed portions ofterminal wiring level 120D. In one example,PLM 165 is titanium nitride, copper, gold, titanium-tungsten, chrome, chrome-copper or combinations thereof. A typical combination is gold over copper over chrome. Another typical combination is copper over chrome copper over titanium-tungsten.PLM 165 is in electrical contact withbonding pad 130.C4 ball 170A is formed on and in electrical contact withPLM 165. Examples ofC4 ball 170A compositions include but are not limited to 95% lead and 5% tin, 97% lead and 3% tin, 100% lead, other lead alloys, 100% tin and tin alloys. In one example, the reflow anneal mentioned supra is performed at a temperature of between about 350° C. and 380° C. in a reducing atmosphere such as hydrogen or forming gas. Thinnedsubstrate 100A (seeFIG. 1F ) may now be diced into individual thin chips. - The evaporation process for forming
PLMs 165 and solder bumps 170 (seeFIG. 1E ) is performed by placing the semiconductor substrate in wafer to mask alignment fixture that allows alignment ofmask 150 to thinnedsubstrate 100A (seeFIG. 1E ). The evaporation process includes loading multiple wafer to mask alignment fixtures (with wafers and masks and in the case of the present invention, shims) into spaces in a dome of a multi-source evaporator and each material of PLM and then the solder pad are evaporated onto contacts pads on the wafer through holes in a mask. Such a wafer to mask alignment fixture is illustrated inFIGS. 3A, 3B , 4, 5A, 5B, 6A and 6B and described infra. -
FIG. 3A is a top view of a base portion of a wafer to mask alignment fixture for forming interconnects according to the present invention andFIG. 3B is a cross-section view throughline 3B-3B ofFIG. 3A . InFIGS. 3A and 3B , abottom ring 200 includes anouter lip 205 and aninner lip 210 joined by anintegral plate portion 215.Inner lip 210 defines the extent of anopening 220 centered inbottom ring 200.Plate portion 215 includes a multiplicity ofopenings 225 and a multiplicity of retaining post holes 227.Opening 220 provides access for a wafer handling fixture (not shown) andopenings 225 are for thermal expansion and heat retention control.Bottom ring 200 has a diameter D1 andopening 220 has a diameter D2. The inside distance between opposite points onouter lip 205 is D3.Outer lip 205 has a height H1 measured from atop surface 230 ofplate portion 215 andinner lip 210 has a height H2 measured from the top surface of the plate portion. The difference in height betweenouter lip 205 andinner lip 210 is H3 where H3=H2−H1 and H2 is greater than H1. In one example, for an standard un-thinned 200 mm diameter wafer about 650 microns thick, H2 is about 0.080 inches and H1 is about 0.073 inches, making H3 about 0.007 inches. H1 and H2 will vary based on wafer diameters and standard un-thinned wafer thickness. -
FIG. 4 is a top view of an evaporative mask portion of the wafer to mask alignment fixture for forming interconnects according to the present invention. InFIG. 4 ,mask 250 includes a multiplicity ofopenings 255 arranged ingroups 260. Eachgroup 260 corresponds to a chip on a wafer that will be placed undermask 250 as illustrated inFIG. 7 and described infra.Mask 250 has a diameter of D1, the same as the diameter ofbottom ring 200 illustrated inFIG. 3A and described supra.Mask 250 includes a multiplicity of retaining post holes 262. -
FIG. 5A is a top view of a top portion of the wafer to mask alignment fixture for forming interconnects according to the present invention andFIG. 5B is a cross-section view throughline 5B-5B ofFIG. 5A . InFIGS. 5A and 5B ,top ring 270 has alower lip 275 protruding from abottom surface 280 of the top ring.Lower ring 275 protrudes a distance H4. In one example, for a standard 200 mm diameter wafer having a thickness of about 650 microns, H4 is about 0.002 inches.Top ring 270 includes anopening 280 centered withinring 270.Top ring 270 has a diameter of D1, the same as the diameter ofbottom ring 200 illustrated inFIG. 3A and described supra.Top ring 270 includes a multiplicity of retainingposts 282. -
FIG. 6A is a top view of a shim portion of a wafer to mask alignment fixture for forming interconnects according to the present invention andFIG. 6B is a cross-section view throughline 6B-6B ofFIG. 6A . InFIGS. 6A and 6B ashim 290 has anopening 295 centered within the shim.Shim 290 has a diameter D3A where D3A is just slightly smaller than D3, the inside distance between opposite points on outer lip 205 (seeFIG. 3A ). D3 is greater than the diameter of the wafer being held in the fixture.Opening 295 has a diameter D2 the same as the diameter of opening 220 ofbottom ring 200 illustrated inFIG. 3A and described supra.Shim 290 has a thickness T3.Shim 290 includes a multiplicity of retainingpost notches 297 in aperimeter 298 of the shim. -
FIG. 7 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects according to the present invention. InFIG. 7 , only half of the assembled fixture 300 (about centerline 305) is illustrated. To load/assemblefixture 300,shim 290 is placed in bottom ring 200 (contacting inner lip 210), thinnedsubstrate 100A is placed onshim 290,mask 250 is placed on thinnedsubstrate 100A andtop ring 270 is placed onmask 250.Mask 250 is pressed betweentop ring 270 andouter lip 205 ofbottom ring 200 andlower lip 275 of the top ring presses onmask 250. The only portion ofbottom ring 200 contacted byshim 290 isinner lip 210. Clips (not shown) hold assembledfixture 300 together. Also, alignment pins and alignment holes in bottom andtop rings mask 250 and shim 290 are present but not illustrated inFIG. 7 . The combination of the difference in heights between outer andinner lips bottom ring 200 and the height oflower lip 275 oftop ring 270 deflects (or bows)shim 290,substrate 100A andmask 250 into very shallow but semi-spherical shapes by pressing the peripheries ofmask 250 andsubstrate 100A towardsbottom ring 200. The degree of deflection ofsubstrate 100A is D4 measured along the top surface ofsubstrate 100A. The bow imparted tosubstrate 100A prevents or reduces such problems associated with evaporation through an knife edge opening in a mask such as sputter haze, PLM flaring and solder pad haloing. - Retaining
post 282 passes through retainingpost hole 262 inmask 250, retainingpost notches 297 inshim 290 and retainingpost hole 227 inbottom ring 200. Aspring clip 310 engages retainingpost 305 and temporarily fastens assembledfixture 300 together. -
FIG. 8 is a partial cross-section view through the assembled wafer to mask alignment fixture for forming interconnects illustrating dimensional relationships between the component parts of the wafer to mask alignment fixture according to the present invention. The dimensions H1, H2 of outer andinner lips bottom ring 200 and the dimension H4 oflower lip 275 of top ring 270 (seeFIG. 5A ) are experimentally determined for each combination of wafer diameter and standard un-thinned wafer thickness. Note it is possible that one wafer manufacturer may produce standard 200 mm diameter wafers that are 780 microns thick, while another manufacturer may produce standard 200 mm diameter wafers that are 640 microns thick. Either two sets of fixtures having different values of H1, H2 and H4 are required, or 640 micron thick wafers are treated as “thin” wafers compared to the 780 micron thick wafers and a single fixture is designed for 780 micron thick wafers. There are two methods of determining the thickness T3 forshim 290. The first method is to use the formula T3 (shim thickness) equals T1 (un-thinned or standard wafer thickness that fixture is designed for) minus T2 (thinned wafer thickness). For example, assume a fixture designed for a 200 mm diameter 640 micron thick having values of 0.073 for H1, 0.080 for H2 and 0.002 for H4. If the wafer has been thinned to 250 microns, then T3 will be 390 microns (640−250=390) even if the original thickness of the wafer was greater than 640 microns. If the fixture had been designed for a 780 micron thick wafer thanshim 290, in the present example, would be 530 microns (720−250=530) thick. - The second method is to experimentally determine for a given thinned wafer thickness (T2) a shim thickness (T3) that yields the same wafer deflection (D4) (see
FIG. 7 ) as the un-thinned standard wafer (of thickness T1) that the fixture was designed for. For example assume a fixture designed for a 200 mm diameter 640 micron thick having values of 0.073 for H1, 0.080 for H2 and 0.002 for H4. If the wafer has been thinned to 250 microns, then T3 will be selected from an experimentally determined table of shim thickness (T3) versus thinned wafer thickness (T2) versus wafer deflection (D4) to give the same wafer deflection (D4) with a shim in place as a 640 micron thick wafer even if the original thickness of the wafer was not equal to 640 microns. - The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims (14)
1. A fixture for holding a wafer and an evaporative mask comprising:
a bottom ring having a inner periphery and an outer periphery, said bottom ring having a raised inner lip formed along said inner periphery and a raised outer lip formed along said outer periphery, the height of said inner lip above a surface of said bottom ring being greater than a height of said outer lip above said surface of said bottom ring;
a shim having a inner and an outer periphery, the outer periphery of said shim fitting inside and in proximity to said outer lip of said bottom ring, a bottom surface of said shim proximate to said inner periphery of said shim contacting an upper surface of said inner lip of said bottom ring; and
a top ring having an inner periphery and an outer periphery, said top ring having a lower raised lip formed along said inner periphery of said bottom ring and extending below a bottom surface of said top ring.
2. The fixture of claim 1 , wherein said bottom ring and said top ring are adapted to press a bottom surface of said wafer against an upper surface of said shim and to press a top surface of said wafer against a bottom surface of said evaporative mask and to press a top surface of said evaporative mask proximate to said periphery of said evaporative mask against a lower surface of said lower raised lip of said top ring.
3. The fixture of claim 1 , wherein the combined thicknesses of said wafer and said shim are substantially equal to a thickness of a thicker wafer, said fixture designed to hold said thicker wafer without said shim being present.
4. The fixture of claim 1 , wherein said shim has thickness such that said wafer is bowed substantially a same amount as a thicker wafer would be bowed without said shim being present, said fixture designed to hold said thicker wafer.
5. A fixture, comprising:
a bottom ring having opposite top and bottom surfaces and inner and outer raised lips on said top surface;
a shim having a circular opening and opposite top and bottom surfaces;
a top ring having opposite top and bottom surface surfaces; and
said bottom ring and said top ring adapted to press said bottom surface of said shim adjacent to said circular opening against said inner raised lip, to press a bottom surface of a wafer against said upper surface of said shim, to press a top surface of said wafer against a bottom surface of a mask and to press a top surface of said mask proximate to a periphery of said mask against said lower surface of said top ring.
6. The fixture of claim 5 , wherein said shim, said top ring and said bottom ring are adapted to impart a bow to said wafer and said mask, a central part of said wafer and a central part of said mask bowed away from said bottom ring and peripheral portions of said wafer and said mask bowed toward said bottom ring.
7. The fixture of claim 5 , wherein the combined thicknesses of said wafer and said shim are substantially equal to a thickness of a thicker wafer said fixture is designed to hold without said shim being present.
8. The fixture of claim 5 , wherein said shim has thickness such that said wafer is bowed substantially a same amount as a thicker wafer would be bowed without said shim being present, said fixture designed to hold said thicker wafer.
9. The fixture of claim 5 , wherein said inner raised lip extends a first distance above said top surface of said bottom ring, said outer raised lip extends a second distance above said top surface of said bottom ring, said first distance is greater than said second distance.
10. A fixture, comprising:
a bottom ring having a inner periphery and an outer periphery, said bottom ring having a raised inner lip formed along said inner periphery and a raised outer lip formed along said outer periphery;
a shim having a inner and an outer periphery, the outer periphery of said shim fitting inside and in proximity to said outer lip of said bottom ring, a bottom surface of said shim proximate to said inner periphery of said shim contacting an upper surface of said inner lip of said bottom ring; and
a top ring having an inner periphery and an outer periphery, said top ring having a lower raised lip formed along said inner periphery of said bottom ring and extending below a bottom surface of said top ring.
11. The fixture of claim 10 , wherein the height of said inner lip above a surface of said bottom ring being greater than a height of said outer lip above said surface of said bottom ring.
12. The fixture of claim 11 , wherein said height of said inner lip is about 0.080 inches and said height of said outer lip is about 0.073 inches.
13. The fixture of claim 10 , wherein said bottom ring includes openings extending between said surface and an opposite surface of said bottom ring, said opening located between said inner and outer lips.
14. The fixture of claim 10 , wherein a thickness of said shim is substantially equal to a difference between a thickness of said wafer and a thickness of a thicker wafer after said thicker wafer has been thinned, said fixture designed to hold said thicker wafer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/772,862 US20070278729A1 (en) | 2003-06-28 | 2007-07-03 | Method for forming interconnects on thin wafers |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/604,164 US6951775B2 (en) | 2003-06-28 | 2003-06-28 | Method for forming interconnects on thin wafers |
US11/184,695 US7288492B2 (en) | 2003-06-28 | 2005-07-19 | Method for forming interconnects on thin wafers |
US11/772,862 US20070278729A1 (en) | 2003-06-28 | 2007-07-03 | Method for forming interconnects on thin wafers |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/184,695 Division US7288492B2 (en) | 2003-06-28 | 2005-07-19 | Method for forming interconnects on thin wafers |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070278729A1 true US20070278729A1 (en) | 2007-12-06 |
Family
ID=33539922
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/604,164 Expired - Fee Related US6951775B2 (en) | 2003-06-28 | 2003-06-28 | Method for forming interconnects on thin wafers |
US11/184,695 Expired - Fee Related US7288492B2 (en) | 2003-06-28 | 2005-07-19 | Method for forming interconnects on thin wafers |
US11/772,862 Abandoned US20070278729A1 (en) | 2003-06-28 | 2007-07-03 | Method for forming interconnects on thin wafers |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/604,164 Expired - Fee Related US6951775B2 (en) | 2003-06-28 | 2003-06-28 | Method for forming interconnects on thin wafers |
US11/184,695 Expired - Fee Related US7288492B2 (en) | 2003-06-28 | 2005-07-19 | Method for forming interconnects on thin wafers |
Country Status (1)
Country | Link |
---|---|
US (3) | US6951775B2 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10213296B9 (en) * | 2002-03-25 | 2007-04-19 | Infineon Technologies Ag | Electronic component with a semiconductor chip, method for its production and method for producing a benefit |
US6951775B2 (en) * | 2003-06-28 | 2005-10-04 | International Business Machines Corporation | Method for forming interconnects on thin wafers |
US7285477B1 (en) * | 2006-05-16 | 2007-10-23 | International Business Machines Corporation | Dual wired integrated circuit chips |
US7710128B2 (en) * | 2006-09-09 | 2010-05-04 | Honeywell International Inc. | Method and apparatus for controlling the sensitivity and value of a capacitive humidity sensor |
US8558353B2 (en) * | 2006-11-15 | 2013-10-15 | Texas Instruments Incorporated | Integrated circuit having an uppermost layer comprising landing pads that are distributed thoughout one side of the integrated circuit |
US20090121287A1 (en) * | 2007-11-14 | 2009-05-14 | Kerry Bernstein | Dual wired integrated circuit chips |
US8723325B2 (en) * | 2009-05-06 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of forming a pad structure having enhanced reliability |
US9583364B2 (en) | 2012-12-31 | 2017-02-28 | Sunedison Semiconductor Limited (Uen201334164H) | Processes and apparatus for preparing heterostructures with reduced strain by radial compression |
CN106001724B (en) * | 2016-05-18 | 2018-11-23 | 盐城工学院 | A kind of processing unit (plant) of the hard rotation Milling Machining cutter of the non-homogeneous passivation of cutting edge |
US10276426B2 (en) | 2016-05-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for performing spin dry etching |
US11646242B2 (en) | 2018-11-29 | 2023-05-09 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US11705428B2 (en) | 2019-01-23 | 2023-07-18 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
EP3915134A1 (en) | 2019-01-23 | 2021-12-01 | Qorvo US, Inc. | Rf semiconductor device and manufacturing method thereof |
US20200235040A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11646289B2 (en) | 2019-12-02 | 2023-05-09 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3458925A (en) * | 1966-01-20 | 1969-08-05 | Ibm | Method of forming solder mounds on substrates |
US4434434A (en) * | 1981-03-30 | 1984-02-28 | International Business Machines Corporation | Solder mound formation on substrates |
US5159535A (en) * | 1987-03-11 | 1992-10-27 | International Business Machines Corporation | Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate |
US5267607A (en) * | 1991-05-28 | 1993-12-07 | Tokyo Electron Limited | Substrate processing apparatus |
US5629564A (en) * | 1994-06-28 | 1997-05-13 | International Business Machines Corporation | Electroplated solder terminal |
US5820367A (en) * | 1995-09-20 | 1998-10-13 | Tokyo Electron Limited | Boat for heat treatment |
US5961375A (en) * | 1997-10-30 | 1999-10-05 | Lsi Logic Corporation | Shimming substrate holder assemblies to produce more uniformly polished substrate surfaces |
US6077764A (en) * | 1997-04-21 | 2000-06-20 | Applied Materials, Inc. | Process for depositing high deposition rate halogen-doped silicon oxide layer |
US6133136A (en) * | 1999-05-19 | 2000-10-17 | International Business Machines Corporation | Robust interconnect structure |
US6219910B1 (en) * | 1999-03-05 | 2001-04-24 | Intel Corporation | Method for cutting integrated circuit dies from a wafer which contains a plurality of solder bumps |
US6333559B1 (en) * | 1998-10-07 | 2001-12-25 | International Business Machines Corporation | Method/structure for creating aluminum wirebound pad on copper BEOL |
US6342434B1 (en) * | 1995-12-04 | 2002-01-29 | Hitachi, Ltd. | Methods of processing semiconductor wafer, and producing IC card, and carrier |
US6354917B1 (en) * | 1998-01-05 | 2002-03-12 | Micron Technology, Inc. | Method of processing a wafer utilizing a processing slurry |
US6528881B1 (en) * | 1999-08-27 | 2003-03-04 | Nec Corporation | Semiconductor device utilizing a side wall to prevent deterioration between electrode pad and barrier layer |
US6534387B1 (en) * | 1999-12-21 | 2003-03-18 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20030213382A1 (en) * | 2002-01-11 | 2003-11-20 | Massachusetts Institute Of Technology | Microcontact printing |
US7288492B2 (en) * | 2003-06-28 | 2007-10-30 | International Business Machines Corporation | Method for forming interconnects on thin wafers |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6117299A (en) * | 1997-05-09 | 2000-09-12 | Mcnc | Methods of electroplating solder bumps of uniform height on integrated circuit substrates |
JP2000124177A (en) | 1998-10-15 | 2000-04-28 | Sony Corp | Manufacture of semiconductor device |
-
2003
- 2003-06-28 US US10/604,164 patent/US6951775B2/en not_active Expired - Fee Related
-
2005
- 2005-07-19 US US11/184,695 patent/US7288492B2/en not_active Expired - Fee Related
-
2007
- 2007-07-03 US US11/772,862 patent/US20070278729A1/en not_active Abandoned
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3458925A (en) * | 1966-01-20 | 1969-08-05 | Ibm | Method of forming solder mounds on substrates |
US4434434A (en) * | 1981-03-30 | 1984-02-28 | International Business Machines Corporation | Solder mound formation on substrates |
US5159535A (en) * | 1987-03-11 | 1992-10-27 | International Business Machines Corporation | Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate |
US5267607A (en) * | 1991-05-28 | 1993-12-07 | Tokyo Electron Limited | Substrate processing apparatus |
US5629564A (en) * | 1994-06-28 | 1997-05-13 | International Business Machines Corporation | Electroplated solder terminal |
US5820367A (en) * | 1995-09-20 | 1998-10-13 | Tokyo Electron Limited | Boat for heat treatment |
US6342434B1 (en) * | 1995-12-04 | 2002-01-29 | Hitachi, Ltd. | Methods of processing semiconductor wafer, and producing IC card, and carrier |
US6077764A (en) * | 1997-04-21 | 2000-06-20 | Applied Materials, Inc. | Process for depositing high deposition rate halogen-doped silicon oxide layer |
US5961375A (en) * | 1997-10-30 | 1999-10-05 | Lsi Logic Corporation | Shimming substrate holder assemblies to produce more uniformly polished substrate surfaces |
US6354917B1 (en) * | 1998-01-05 | 2002-03-12 | Micron Technology, Inc. | Method of processing a wafer utilizing a processing slurry |
US6333559B1 (en) * | 1998-10-07 | 2001-12-25 | International Business Machines Corporation | Method/structure for creating aluminum wirebound pad on copper BEOL |
US6219910B1 (en) * | 1999-03-05 | 2001-04-24 | Intel Corporation | Method for cutting integrated circuit dies from a wafer which contains a plurality of solder bumps |
US6133136A (en) * | 1999-05-19 | 2000-10-17 | International Business Machines Corporation | Robust interconnect structure |
US6528881B1 (en) * | 1999-08-27 | 2003-03-04 | Nec Corporation | Semiconductor device utilizing a side wall to prevent deterioration between electrode pad and barrier layer |
US6534387B1 (en) * | 1999-12-21 | 2003-03-18 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US20030213382A1 (en) * | 2002-01-11 | 2003-11-20 | Massachusetts Institute Of Technology | Microcontact printing |
US7288492B2 (en) * | 2003-06-28 | 2007-10-30 | International Business Machines Corporation | Method for forming interconnects on thin wafers |
Also Published As
Publication number | Publication date |
---|---|
US7288492B2 (en) | 2007-10-30 |
US20040266159A1 (en) | 2004-12-30 |
US6951775B2 (en) | 2005-10-04 |
US20050272241A1 (en) | 2005-12-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7288492B2 (en) | Method for forming interconnects on thin wafers | |
US7375032B2 (en) | Semiconductor substrate thinning method for manufacturing thinned die | |
US6420209B1 (en) | Integrated circuits and methods for their fabrication | |
US6908565B2 (en) | Etch thinning techniques for wafer-to-wafer vertical stacks | |
US20060046436A1 (en) | Manufacturing method of stack-type semiconductor device | |
US6674162B2 (en) | Semiconductor device and manufacturing method thereof | |
US9355934B2 (en) | Method and apparatus providing integrated circuit having redistribution layer with recessed connectors | |
US6949158B2 (en) | Using backgrind wafer tape to enable wafer mounting of bumped wafers | |
US11688639B2 (en) | Semiconductor device and method | |
US11322464B2 (en) | Film structure for bond pad | |
US11532589B2 (en) | Semiconductor wafer and method of manufacturing the same | |
US20230101989A1 (en) | Techniques for wafer stack processing | |
TW201906126A (en) | Semiconductor device | |
US7722446B2 (en) | System and device for thinning wafers that have contact bumps | |
US7381636B2 (en) | Planar bond pad design and method of making the same | |
TWI677057B (en) | Methods of forming integrated circuit structure for joining wafers and resulting structure | |
US20190229081A1 (en) | Semiconductor devices | |
US10446514B2 (en) | Combing bump structure and manufacturing method thereof | |
US11908831B2 (en) | Method for manufacturing a wafer level chip scale package (WLCSP) | |
US10685831B2 (en) | Semiconductor structures and fabrication methods thereof | |
US20240030082A1 (en) | Semiconductor structure and method of manufacturing thereof | |
TWI692064B (en) | Semiconductor chip having coplanar bumps and manufacturing method thereof | |
US11894331B2 (en) | Chip package structure, chip structure and method for forming chip structure | |
US20240021515A1 (en) | Semiconductor structure and method of manufacturing thereof | |
US11804445B2 (en) | Method for forming chip package structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |