US20070296052A1 - Methods of forming silicide regions and resulting MOS devices - Google Patents

Methods of forming silicide regions and resulting MOS devices Download PDF

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US20070296052A1
US20070296052A1 US11/474,670 US47467006A US2007296052A1 US 20070296052 A1 US20070296052 A1 US 20070296052A1 US 47467006 A US47467006 A US 47467006A US 2007296052 A1 US2007296052 A1 US 2007296052A1
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Prior art keywords
gate
source
silicide region
drain
region
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US11/474,670
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Tan-Chen Lee
Bor-Wen Chan
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US11/474,670 priority Critical patent/US20070296052A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHAN, BOR-WEN, LEE, TAN-CHEN
Priority to CNA2007100058337A priority patent/CN101097953A/en
Priority to CN2011102705094A priority patent/CN102332402A/en
Publication of US20070296052A1 publication Critical patent/US20070296052A1/en
Priority to US12/904,809 priority patent/US8173540B2/en
Priority to US13/444,715 priority patent/US8841192B2/en
Priority to US14/491,786 priority patent/US9899494B2/en
Priority to US15/296,511 priority patent/US9947758B2/en
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Definitions

  • This invention relates generally to the structure and manufacturing methods of metal-oxide-semiconductor (MOS) devices, and more particularly to the formation of silicide regions of MOS devices.
  • MOS metal-oxide-semiconductor
  • CMOS complementary metal oxide silicon
  • metal silicides atop the source/drain regions and the gate electrodes prior to application of the conductive film for formation of the various conductive interconnect lines.
  • metal silicide materials are nickel silicide and cobalt silicide, typically formed by a salicide (self-aligned silicide) process.
  • a salicide process a thin layer of metal is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps, for example at a temperature of 700° C. or higher.
  • This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide.
  • the process is referred to as a self-aligned silicidation process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode.
  • the un-reacted metal is removed and an interconnect process is performed to provide conductive paths, such as by forming via holes through a deposited interlayer dielectric and filling the via holes with a conductive material, e.g., tungsten.
  • nickel silicide has a low resistivity and can be formed at a low temperature.
  • it is sensitive to the high temperatures of subsequent processes, such as the formation of highly stressed CESL and/or ILD layers.
  • Undesired effects such as stringers and encroachments may occur at the source/drain regions in the silicidation process and the effects are pronounced if nickel silicide alone is implemented.
  • the function and reliability of the integrated circuit is thus adversely affected.
  • Cobalt silicide is more stable at high temperatures and the manufacturing process is more mature, thus is less likely to be adversely affected by the subsequent processes adopting high temperatures.
  • a semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate stack including the gate dielectric and the gate electrode, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
  • a semiconductor device in accordance with another aspect of the present invention, includes a semiconductor substrate having a channel region, a gate dielectric on the substrate and over the channel region, a gate silicide region over the gate dielectric, a source/drain region adjacent the channel region, and source/drain silicide regions on the source/drain regions.
  • the source/drain silicide region has a roll-off resistivity at a higher dimension than the gate silicide region.
  • a method for forming a semiconductor device includes providing a semiconductor substrate, forming a gate dielectric overlying the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region adjacent the gate electrode and the gate dielectric, forming a source/drain silicide region on the source/drain region, and forming a gate silicide region over the gate dielectric using the gate electrode, wherein the gate silicide region comprises a different metallic composition from the source/drain silicide region.
  • a method for forming a semiconductor device includes providing a semiconductor substrate, forming a gate dielectric overlying the semiconductor substrate, forming a gate electrode overlying the gate dielectric, forming a mask on the gate electrode, forming a source/drain region adjacent the gate dielectric, blanket forming a first metallic layer, performing a first annealing to form a source/drain silicide region on the source/drain region, blanket forming a dielectric layer, exposing the mask through the dielectric layer, removing the mask, blanket forming a second metallic layer wherein the second metallic layer has a different composition from the first metallic layer, and performing a second annealing to form a gate silicide region over the gate dielectric.
  • MOS devices formed using the preferred embodiments of the present invention have improved roll-off resistivities and reliability.
  • FIGS. 1 through 7 are cross-sectional views of intermediate stages in the manufacture of a preferred embodiment, wherein a gate silicide region is formed after the formation of a contact etch stop layer;
  • FIGS. 8 through 10 illustrate intermediate stages of a variation of the preferred embodiment, wherein a gate silicide region is formed after the formation of an inter-layer dielectric
  • FIG. 11 illustrates a further variation of the preferred embodiment, wherein source/drain silicide regions are further silicided along with the formation of a gate silicide region.
  • a semiconductor device formed by a novel silicide formation process is discussed in subsequent paragraphs.
  • the intermediate stages of manufacturing preferred embodiments of the present invention are illustrated.
  • like reference numbers are used to designate like elements.
  • FIG. 1 illustrates the formation of shallow trench isolation (STI) regions 10 and a portion of a metal-oxide-semiconductor (MOS) device, which includes lightly-doped drain/source (LDD) regions 9 in substrate 2 and a gate structure on substrate 2 .
  • substrate 2 is a silicon substrate.
  • SiGe, bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), and other commonly used semiconductor substrates can be used.
  • STI regions 10 are preferably formed by etching shallow trenches in substrate 2 and filling the trenches with an insulator such as silicon oxide.
  • a gate dielectric 4 is deposited on the surface of substrate 2 .
  • Gate dielectric 4 may be an oxide.
  • the forming method can be any of the known methods, such as thermal oxidation, chemical vapor deposition (CVD), etc.
  • Silicon nitride can also be used since it is an effective barrier to impurity diffusion.
  • the silicon nitride film is preferably formed by thermal nitridation of silicon. It can also be prepared by plasma anodic nitridation using nitrogen-hydrogen or thermal nitridation of SiO 2 .
  • Gate dielectric 4 may also include high-k dielectric materials such as oxynitride, oxygen-containing dielectric, nitrogen-containing dielectric, or combinations thereof.
  • gate electrode 6 is formed on the gate dielectric 4 .
  • gate electrode 6 comprises polysilicon.
  • the preferred methods of formation include chemical vapor deposition (CVD) methods.
  • Gate electrode 6 is preferably doped to reduce sheet resistance. In other embodiments, gate electrode 6 comprises amorphous silicon.
  • a first mask layer 7 is formed over gate electrode 6 .
  • Mask layer 7 preferably comprises silicon nitride, although other materials such as oxides can also be used.
  • mask layer 7 utilizes the anti-reflective coating (ARC) layer, which is commonly used in the existing integrated circuit fabrication process for patterning. After the patterning of gate electrode 6 , the ARC layer is left without being removed and acts as mask layer 7 .
  • mask layer 7 is specifically formed.
  • mask layer 7 , gate electrode 6 and gate dielectric 4 are blanket deposited and then patterned. Lightly doped source/drain regions 9 are then formed, preferably by implanting appropriate impurities using the gate stack as a mask.
  • spacers 8 are formed along sidewalls of the gate dielectric 4 , gate electrode 6 and mask layer 7 .
  • spacers 8 are preferably formed by blanket depositing a dielectric layer over the entire region, and then anisotropically etching to remove dielectric material from horizontal surfaces.
  • Spacers 8 may be formed of a single dielectric layer, as is shown in FIG. 1 , or of a composite layer including more than one dielectric layer, for example, a silicon nitride layer on a silicon oxide liner (not shown).
  • mask layer 7 may also be formed after the formation of spacers 8 , or at any other time before the subsequently formed source/drain regions are silicided.
  • FIG. 2 illustrates the formation of source/drain regions 12 .
  • source/drain regions 12 are formed by implanting impurities into substrate 2 . Spacers 8 ′ and the gate stack are used as a mask for the subsequent source/drain implantation process.
  • source/drain regions 12 are formed by recessing the source/drain regions, and then epitaxially growing semiconductor materials, such as silicon, silicon germanium, or silicon carbide, in the recesses.
  • the desired impurities may be doped simultaneously with the epitaxial growth or may be implanted after the epitaxial growth.
  • Metal layer 14 is deposited on the source/drain regions 12 , as is shown in FIG. 3 .
  • Metal layer 14 preferably comprises cobalt (Co). However, it may also comprise other metals such as platinum, nickel, and combinations thereof. Pure nickel is generally not preferred, but a nickel-based alloy comprising nickel may be included in metal layer 14 .
  • the weight percentage of nickel in the alloy is preferably less than about 99 weight percent, more preferably less than about 97 percent, and even more preferably less than about 95 percent.
  • PVD physical vapor deposition
  • electroless plating which can selectively form a metal layer on the source and drain regions 12 , but not on the dielectrics such as gate spacers 8 and mask layer 7 , is used for forming metal layer 14 .
  • the annealing is then performed, forming source/drain silicide regions 16 , and the resulting structure is shown in FIG. 4 .
  • the annealing is preferably performed at a temperature of about 400° C. or higher, although a lower temperature is always desirable, providing the quality of the resulting silicide regions is not compromised.
  • the annealing process may be performed using thermal annealing, flash annealing, laser annealing, and the like.
  • the annealing process comprises two steps.
  • the first step includes a first annealing at a relatively low temperature. In the first step, a portion of the metal layer 14 reacts with silicon to form a silicide.
  • the silicide typically has a higher resistivity than in the final structure. Un-reacted metal is then removed.
  • the second step includes a second annealing to convert the high-resistivity silicide to a low-resistivity silicide.
  • the first annealing is performed at about 300° C. to about 400° C., while the second annealing is performed at about 700° C.
  • the resulting source/drain silicide regions 16 preferably have a relatively high thermal stability at relatively high temperatures, which may be adopted by subsequent processes, such as the formation of a highly stressed contact etch stop layer and inter-layer dielectric layer.
  • second mask layer 18 is formed to cover the source/drain silicide regions 16 .
  • second mask layer 18 is a contact etch stop layer (CESL), which is preferably blanket deposited to cover the entire device, including source/drain silicide regions 16 and the first mask layer 7 .
  • second mask layer 18 is specifically formed for, and is subsequently removed after, the formation of a gate silicide region.
  • An opening 20 is formed in the second mask layer 18 , through which the first mask layer 7 is exposed. Mask layer 7 is then removed.
  • FIG. 6 illustrates the formation of a second metal layer 22 .
  • Metal layer 22 preferably has a different composition from metal layer 14 (refer to FIG. 3 ), wherein “different composition” means either that metal layer 14 has at least one different metallic element from metal layer 22 or that the percentage of the metallic elements are substantially different even if the metallic elements in metal layers 14 and 22 are substantially the same. For example, if one metal element in metal layers 14 and 22 has a percentage of difference greater than about five percent, the compositions of metal layer 14 and 22 are different. More preferably, metal layer 22 includes metals whose silicides have a relatively low resistivity, and whose silicide resistivity suffers a roll-off resistivity at a much smaller dimension than the source/drain silicide regions 16 .
  • the term “roll-off” means that the resistivity of the respective silicide regions experiences a significant resistivity increase when the dimension of the silicide region is less than a certain value.
  • the preferred metals include nickel, nickel-platinum, and the like. Cobalt is generally undesired since the respective cobalt silicide has a roll-off resistivity at a relatively high dimension compared with other metals, such as nickel. However, a small amount of cobalt, for example, less than about five percent, may be included in metal layer 22 . Due to the different compositions of metal layer 14 (refer to FIG. 3 ) and metal layer 22 , the resulting silicide regions formed from metal layer 14 and metal layer 22 have different compositions.
  • a second silicidation process is then performed.
  • the second silicidation process is preferably performed at substantially lower temperatures than the first silicidation process.
  • the second silicidation process is performed at a temperature of lower than about 300° C.
  • a first annealing of the second silicidation process is performed at about 300° C.
  • a second annealing is performed at about 400° C.
  • the second silicidation process results in a silicide region 24 on top of gate electrode 6 , as is shown in FIG. 7 .
  • ILD 23 is deposited over the surface of CESL 18 .
  • ILD 23 is preferably a low-k dielectric layer having a dielectric constant of less than about 3.5.
  • Contact plugs (not shown), which connect source/drain silicide regions 16 and gate silicide region 24 to metal lines in the overlying metallization layers, are then formed. The formation processes for ILD 23 and contact plugs are well known in the art, and thus are not repeated.
  • FIGS. 8 through 10 A variation of the preferred embodiment is shown in FIGS. 8 through 10 .
  • the initial steps are essentially the same as illustrated in FIGS. 1 through 4 .
  • a CMP is performed to level ILD 23 , CESL 18 and gate spacers 8 to the top surface of gate electrode 6 .
  • Mask layer 7 is preferably polished so that gate electrode 6 is exposed.
  • FIG. 9 A resulting structure is shown in FIG. 9 .
  • the CMP process polishes to the top surface of mask layer 7 , and a selective etching is performed to remove mask layer 7 .
  • a metal layer (not shown) preferably comprising essentially the same metals as in metal layer 22 (refer to FIG. 6 ), is then formed.
  • An annealing process which is essentially similar to the silicidation process of metal layer 22 (refer to FIG. 6 ), is then performed, and un-reacted metal is removed.
  • the resulting structure with gate silicide region 24 is illustrated in FIG. 10 .
  • ILD 23 may then be re-deposited to the desired thickness if necessary.
  • the gate silicide region 24 can be formed at any time after the source/drain silicide regions 16 are formed. More preferably, the formation of the gate silicide region 24 is performed after high temperature processes are performed, so that gate silicide region 24 is less affected by the high temperatures.
  • mask layer 7 is removed before the formation of CESL 18 .
  • a metal layer 34 which is essentially similar to metal layer 22 , is blanket formed.
  • An annealing process is performed to form gate silicide region 24 on top of gate electrode 6 .
  • the second annealing process causes the introduction of additional metal elements into source/drain silicide regions 16 .
  • source/drain silicide regions 16 and gate silicide region 24 are likely to have substantially different thicknesses. Silicide processes can be further controlled to increase the difference in silicide region thicknesses.
  • gate electrode 6 is fully silicided. This may be achieved, for example, by depositing a thicker metal film and/or annealing the gate electrode 6 for a longer duration. As is known in the art, a fully-silicided gate is free from charge depletion effects, and thus is a desirable feature. With the gate silicide region 24 formed separately from the source/drain silicide regions 16 , gate electrode 6 can be fully silicided without causing the over silicidation of source/drain regions 12 .
  • NMOS devices and PMOS devices may have different metal compositions in their source/drain regions as well as in their gates. More customized silicidation processes can thus be performed for NMOS devices and PMOS devices to suit different design requirements.
  • Source/drain regions 12 typically have a greater dimension than the gate electrode 6 . Therefore, cobalt can be used for the formation of silicide regions 16 . Due to the greater dimension, the roll-off problem is less likely to occur even when the MOS device is formed using 65 nm technology or below.
  • the subsequent high-temperature processes for example, the processes for forming highly stressed CESL 18 and/or ILD 23 , may be adopted without affecting the already formed source/drain silicide regions.
  • the gate silicide region 24 may be formed with less concern of being affected by high temperature processes, thus there are more choices in adopting metals with better resistivity roll-off performance.

Abstract

A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

Description

    TECHNICAL FIELD
  • This invention relates generally to the structure and manufacturing methods of metal-oxide-semiconductor (MOS) devices, and more particularly to the formation of silicide regions of MOS devices.
    • BACKGROUND
  • Deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, contact resistance becomes more significant and needs to be reduced.
  • The principle way of reducing contact resistances between polysilicon gates and source/drain regions and interconnect lines is by forming metal silicides atop the source/drain regions and the gate electrodes prior to application of the conductive film for formation of the various conductive interconnect lines. Among the most common metal silicide materials are nickel silicide and cobalt silicide, typically formed by a salicide (self-aligned silicide) process. In the salicide process, a thin layer of metal is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps, for example at a temperature of 700° C. or higher. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide. The process is referred to as a self-aligned silicidation process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode. Following the formation of the silicide layer, the un-reacted metal is removed and an interconnect process is performed to provide conductive paths, such as by forming via holes through a deposited interlayer dielectric and filling the via holes with a conductive material, e.g., tungsten.
  • The conventional silicidation process, however, suffers drawbacks. For example, commonly used nickel silicide has a low resistivity and can be formed at a low temperature. However, it is sensitive to the high temperatures of subsequent processes, such as the formation of highly stressed CESL and/or ILD layers. Undesired effects such as stringers and encroachments may occur at the source/drain regions in the silicidation process and the effects are pronounced if nickel silicide alone is implemented. The function and reliability of the integrated circuit is thus adversely affected. Cobalt silicide, on the other hand, is more stable at high temperatures and the manufacturing process is more mature, thus is less likely to be adversely affected by the subsequent processes adopting high temperatures. However, it has a significant resistivity roll-off at dimensions of about 35 nm or below, meaning that its resistivity significantly increases when the dimension of the cobalt silicide features reach about 35 nm or lower. Since the gate of a MOS device typically has a smaller dimension than the respective source/drain regions, the resistivity roll-off will be observed on the gate silicide region first. This limits the usage of cobalt silicide in advanced technologies with small scales.
  • Accordingly, what is needed in the art is a new method and structure that may incorporate silicides to take advantage of the benefits associated with reduced resistivity while at the same time overcoming the deficiencies of the prior art.
    • SUMMARY OF THE INVENTION
  • In accordance with one aspect of the present invention, a semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate stack including the gate dielectric and the gate electrode, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
  • In accordance with another aspect of the present invention, a semiconductor device includes a semiconductor substrate having a channel region, a gate dielectric on the substrate and over the channel region, a gate silicide region over the gate dielectric, a source/drain region adjacent the channel region, and source/drain silicide regions on the source/drain regions. The source/drain silicide region has a roll-off resistivity at a higher dimension than the gate silicide region.
  • In accordance with yet another aspect of the present invention, a method for forming a semiconductor device includes providing a semiconductor substrate, forming a gate dielectric overlying the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region adjacent the gate electrode and the gate dielectric, forming a source/drain silicide region on the source/drain region, and forming a gate silicide region over the gate dielectric using the gate electrode, wherein the gate silicide region comprises a different metallic composition from the source/drain silicide region.
  • In accordance with yet another aspect of the present invention, a method for forming a semiconductor device includes providing a semiconductor substrate, forming a gate dielectric overlying the semiconductor substrate, forming a gate electrode overlying the gate dielectric, forming a mask on the gate electrode, forming a source/drain region adjacent the gate dielectric, blanket forming a first metallic layer, performing a first annealing to form a source/drain silicide region on the source/drain region, blanket forming a dielectric layer, exposing the mask through the dielectric layer, removing the mask, blanket forming a second metallic layer wherein the second metallic layer has a different composition from the first metallic layer, and performing a second annealing to form a gate silicide region over the gate dielectric.
  • The MOS devices formed using the preferred embodiments of the present invention have improved roll-off resistivities and reliability.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
  • FIGS. 1 through 7 are cross-sectional views of intermediate stages in the manufacture of a preferred embodiment, wherein a gate silicide region is formed after the formation of a contact etch stop layer;
  • FIGS. 8 through 10 illustrate intermediate stages of a variation of the preferred embodiment, wherein a gate silicide region is formed after the formation of an inter-layer dielectric; and
  • FIG. 11 illustrates a further variation of the preferred embodiment, wherein source/drain silicide regions are further silicided along with the formation of a gate silicide region.
    •  DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
  • A semiconductor device formed by a novel silicide formation process is discussed in subsequent paragraphs. The intermediate stages of manufacturing preferred embodiments of the present invention are illustrated. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.
  • FIG. 1 illustrates the formation of shallow trench isolation (STI) regions 10 and a portion of a metal-oxide-semiconductor (MOS) device, which includes lightly-doped drain/source (LDD) regions 9 in substrate 2 and a gate structure on substrate 2. In the preferred embodiment, substrate 2 is a silicon substrate. In other embodiments, SiGe, bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), and other commonly used semiconductor substrates can be used. STI regions 10 are preferably formed by etching shallow trenches in substrate 2 and filling the trenches with an insulator such as silicon oxide.
  • A gate dielectric 4 is deposited on the surface of substrate 2. Gate dielectric 4 may be an oxide. The forming method can be any of the known methods, such as thermal oxidation, chemical vapor deposition (CVD), etc. Silicon nitride can also be used since it is an effective barrier to impurity diffusion. The silicon nitride film is preferably formed by thermal nitridation of silicon. It can also be prepared by plasma anodic nitridation using nitrogen-hydrogen or thermal nitridation of SiO2. Gate dielectric 4 may also include high-k dielectric materials such as oxynitride, oxygen-containing dielectric, nitrogen-containing dielectric, or combinations thereof.
  • A gate electrode 6 is formed on the gate dielectric 4. In the preferred embodiment, gate electrode 6 comprises polysilicon. The preferred methods of formation include chemical vapor deposition (CVD) methods. Gate electrode 6 is preferably doped to reduce sheet resistance. In other embodiments, gate electrode 6 comprises amorphous silicon.
  • As shown in FIG. 1, a first mask layer 7 is formed over gate electrode 6. Mask layer 7 preferably comprises silicon nitride, although other materials such as oxides can also be used. In the preferred embodiment, mask layer 7 utilizes the anti-reflective coating (ARC) layer, which is commonly used in the existing integrated circuit fabrication process for patterning. After the patterning of gate electrode 6, the ARC layer is left without being removed and acts as mask layer 7. In other embodiments, mask layer 7 is specifically formed. Preferably, mask layer 7, gate electrode 6 and gate dielectric 4 are blanket deposited and then patterned. Lightly doped source/drain regions 9 are then formed, preferably by implanting appropriate impurities using the gate stack as a mask.
  • Also shown in FIG. 1, a pair of spacers 8 is formed along sidewalls of the gate dielectric 4, gate electrode 6 and mask layer 7. As is known in the art, spacers 8 are preferably formed by blanket depositing a dielectric layer over the entire region, and then anisotropically etching to remove dielectric material from horizontal surfaces. Spacers 8 may be formed of a single dielectric layer, as is shown in FIG. 1, or of a composite layer including more than one dielectric layer, for example, a silicon nitride layer on a silicon oxide liner (not shown). It is to be noted that mask layer 7 may also be formed after the formation of spacers 8, or at any other time before the subsequently formed source/drain regions are silicided.
  • FIG. 2 illustrates the formation of source/drain regions 12. In the preferred embodiment, source/drain regions 12 are formed by implanting impurities into substrate 2. Spacers 8′ and the gate stack are used as a mask for the subsequent source/drain implantation process. In other embodiments, source/drain regions 12 are formed by recessing the source/drain regions, and then epitaxially growing semiconductor materials, such as silicon, silicon germanium, or silicon carbide, in the recesses. The desired impurities may be doped simultaneously with the epitaxial growth or may be implanted after the epitaxial growth.
  • A thin metal layer 14 is deposited on the source/drain regions 12, as is shown in FIG. 3. Metal layer 14 preferably comprises cobalt (Co). However, it may also comprise other metals such as platinum, nickel, and combinations thereof. Pure nickel is generally not preferred, but a nickel-based alloy comprising nickel may be included in metal layer 14. For example, the weight percentage of nickel in the alloy is preferably less than about 99 weight percent, more preferably less than about 97 percent, and even more preferably less than about 95 percent. In the preferred embodiment, physical vapor deposition (PVD) is used for forming metal layer 14, although other commonly used methods, such as sputtering, low pressure CVD (LPCVD), and atomic layer chemical vapor deposition (ALD), can also be used. In alternative embodiments, electroless plating, which can selectively form a metal layer on the source and drain regions 12, but not on the dielectrics such as gate spacers 8 and mask layer 7, is used for forming metal layer 14.
  • An annealing is then performed, forming source/drain silicide regions 16, and the resulting structure is shown in FIG. 4. The annealing is preferably performed at a temperature of about 400° C. or higher, although a lower temperature is always desirable, providing the quality of the resulting silicide regions is not compromised. As is known in the art, the annealing process may be performed using thermal annealing, flash annealing, laser annealing, and the like. In an exemplary embodiment, the annealing process comprises two steps. The first step includes a first annealing at a relatively low temperature. In the first step, a portion of the metal layer 14 reacts with silicon to form a silicide. This silicide typically has a higher resistivity than in the final structure. Un-reacted metal is then removed. The second step includes a second annealing to convert the high-resistivity silicide to a low-resistivity silicide. In an exemplary embodiment for forming cobalt silicide, the first annealing is performed at about 300° C. to about 400° C., while the second annealing is performed at about 700° C. The resulting source/drain silicide regions 16 preferably have a relatively high thermal stability at relatively high temperatures, which may be adopted by subsequent processes, such as the formation of a highly stressed contact etch stop layer and inter-layer dielectric layer.
  • Referring to FIG. 5, a second mask layer 18 is formed to cover the source/drain silicide regions 16. In the preferred embodiment, second mask layer 18 is a contact etch stop layer (CESL), which is preferably blanket deposited to cover the entire device, including source/drain silicide regions 16 and the first mask layer 7. In other embodiments, second mask layer 18 is specifically formed for, and is subsequently removed after, the formation of a gate silicide region. An opening 20 is formed in the second mask layer 18, through which the first mask layer 7 is exposed. Mask layer 7 is then removed.
  • FIG. 6 illustrates the formation of a second metal layer 22. Metal layer 22 preferably has a different composition from metal layer 14 (refer to FIG. 3), wherein “different composition” means either that metal layer 14 has at least one different metallic element from metal layer 22 or that the percentage of the metallic elements are substantially different even if the metallic elements in metal layers 14 and 22 are substantially the same. For example, if one metal element in metal layers 14 and 22 has a percentage of difference greater than about five percent, the compositions of metal layer 14 and 22 are different. More preferably, metal layer 22 includes metals whose silicides have a relatively low resistivity, and whose silicide resistivity suffers a roll-off resistivity at a much smaller dimension than the source/drain silicide regions 16. The term “roll-off” means that the resistivity of the respective silicide regions experiences a significant resistivity increase when the dimension of the silicide region is less than a certain value. As is known in the art, the dimension of gates of MOS devices are typically smaller than other lateral dimensions, and thus a resistivity problem tends to occur at the gate first. The preferred metals include nickel, nickel-platinum, and the like. Cobalt is generally undesired since the respective cobalt silicide has a roll-off resistivity at a relatively high dimension compared with other metals, such as nickel. However, a small amount of cobalt, for example, less than about five percent, may be included in metal layer 22. Due to the different compositions of metal layer 14 (refer to FIG. 3) and metal layer 22, the resulting silicide regions formed from metal layer 14 and metal layer 22 have different compositions.
  • A second silicidation process is then performed. The second silicidation process is preferably performed at substantially lower temperatures than the first silicidation process. Preferably, the second silicidation process is performed at a temperature of lower than about 300° C. In an exemplary embodiment wherein nickel silicide is formed, a first annealing of the second silicidation process is performed at about 300° C., and a second annealing is performed at about 400° C. The second silicidation process results in a silicide region 24 on top of gate electrode 6, as is shown in FIG. 7.
  • Next, an inter-layer dielectric (ILD) 23 is deposited over the surface of CESL 18. ILD 23 is preferably a low-k dielectric layer having a dielectric constant of less than about 3.5. Contact plugs (not shown), which connect source/drain silicide regions 16 and gate silicide region 24 to metal lines in the overlying metallization layers, are then formed. The formation processes for ILD 23 and contact plugs are well known in the art, and thus are not repeated.
  • A variation of the preferred embodiment is shown in FIGS. 8 through 10. In this embodiment, the initial steps are essentially the same as illustrated in FIGS. 1 through 4. After the formation of source/drain silicide regions 16, CESL 18 and ILD 23 are formed, as is illustrated, and a CMP is performed to level ILD 23, CESL 18 and gate spacers 8 to the top surface of gate electrode 6. Mask layer 7 is preferably polished so that gate electrode 6 is exposed. A resulting structure is shown in FIG. 9. Alternatively, the CMP process polishes to the top surface of mask layer 7, and a selective etching is performed to remove mask layer 7. A metal layer (not shown) preferably comprising essentially the same metals as in metal layer 22 (refer to FIG. 6), is then formed. An annealing process, which is essentially similar to the silicidation process of metal layer 22 (refer to FIG. 6), is then performed, and un-reacted metal is removed. The resulting structure with gate silicide region 24 is illustrated in FIG. 10. ILD 23 may then be re-deposited to the desired thickness if necessary.
  • It should be appreciated that the gate silicide region 24 can be formed at any time after the source/drain silicide regions 16 are formed. More preferably, the formation of the gate silicide region 24 is performed after high temperature processes are performed, so that gate silicide region 24 is less affected by the high temperatures.
  • In a further variation of the preferred embodiment, as shown in FIG. 11, before the formation of CESL 18, mask layer 7 is removed. A metal layer 34, which is essentially similar to metal layer 22, is blanket formed. An annealing process is performed to form gate silicide region 24 on top of gate electrode 6. The second annealing process causes the introduction of additional metal elements into source/drain silicide regions 16.
  • Due to the separate gate and source/drain silicide formation processes, source/drain silicide regions 16 and gate silicide region 24 are likely to have substantially different thicknesses. Silicide processes can be further controlled to increase the difference in silicide region thicknesses. In an exemplary embodiment, gate electrode 6 is fully silicided. This may be achieved, for example, by depositing a thicker metal film and/or annealing the gate electrode 6 for a longer duration. As is known in the art, a fully-silicided gate is free from charge depletion effects, and thus is a desirable feature. With the gate silicide region 24 formed separately from the source/drain silicide regions 16, gate electrode 6 can be fully silicided without causing the over silicidation of source/drain regions 12.
  • It should be appreciated that the preferred embodiment of the present invention may be applied to the silicidation of SiGe, for example, SiGe stressors formed for PMOS devices. In addition, NMOS devices and PMOS devices may have different metal compositions in their source/drain regions as well as in their gates. More customized silicidation processes can thus be performed for NMOS devices and PMOS devices to suit different design requirements.
  • The preferred embodiments of the present invention have several advantageous features. Source/drain regions 12 typically have a greater dimension than the gate electrode 6. Therefore, cobalt can be used for the formation of silicide regions 16. Due to the greater dimension, the roll-off problem is less likely to occur even when the MOS device is formed using 65 nm technology or below. By forming highly thermal-stable source/drain silicide regions 16, the subsequent high-temperature processes, for example, the processes for forming highly stressed CESL 18 and/or ILD 23, may be adopted without affecting the already formed source/drain silicide regions. The gate silicide region 24, on the other hand, may be formed with less concern of being affected by high temperature processes, thus there are more choices in adopting metals with better resistivity roll-off performance.
  • Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (16)

1. A semiconductor device comprising:
a semiconductor substrate;
a gate stack comprising:
a gate dielectric overlying the semiconductor substrate; and
a gate electrode overlying the gate dielectric;
a gate silicide region on the gate electrode;
a source/drain region adjacent the gate stack; and
a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
2. The semiconductor device of claim 1, wherein at least one metal is included in only one of the source/drain silicide region and the gate silicide region.
3. The semiconductor device of claim 1, wherein the source/drain silicide region has a higher thermal stability than the gate silicide region has.
4. The semiconductor device of claim 1, wherein the source/drain silicide region and the gate silicide region have substantially different thicknesses.
5. The semiconductor device of claim 1, wherein the source/drain silicide region is substantially free from nickel, and the gate silicide region is substantially free from cobalt.
6. The semiconductor device of claim 5, wherein the source/drain silicide region comprises cobalt as an only metallic element, and the gate silicide region comprises nickel as an only metallic element.
7. The semiconductor device of claim 1, wherein the source/drain silicide region has a substantially greater concentration of cobalt than does the gate silicide region.
8. The semiconductor device of claim 1, wherein the source/drain silicide region has a substantially smaller concentration of nickel than does the gate silicide region.
9. The semiconductor device of claim 1, wherein the source/drain silicide region comprises a metal selected from the group consisting essentially of cobalt, platinum, nickel, and combinations thereof, and the gate silicide region comprises a metallic material selected from the group consisting essentially of nickel, nickel-platinum, cobalt, and combinations thereof.
10. A semiconductor device comprising:
a semiconductor substrate having a channel region;
a gate dielectric on the substrate and over the channel region;
a gate silicide region over the gate dielectric;
a source/drain region adjacent the gate dielectric with the channel region therebetween; and
a source/drain silicide region on the source/drain region, wherein the source/drain silicide region has a roll-off resistivity at a higher dimension than does the gate silicide region.
11. The semiconductor device of claim 10, wherein the source/drain silicide region comprises silicides having a higher thermal stability than does the gate silicide region.
12. The semiconductor device of claim 10, wherein the source/drain silicide region comprises a metal selected from the group consisting essentially of cobalt, platinum, nickel, and combinations thereof, and wherein the gate silicide region comprises a metal selected from the group consisting essentially of nickel, nickel-platinum, cobalt, and combinations thereof.
13. The semiconductor device of claim 12, wherein the source/drain silicide region comprises cobalt, and wherein the gate silicide region comprises nickel.
14. The semiconductor device of claim 10, wherein the source/drain silicide region further comprises germanium.
15. The semiconductor device of claim 10, wherein the gate silicide region is directly on the gate dielectric.
16. The semiconductor device of claim 10 further comprising a polysilicon region between the gate silicide region and the gate dielectric.
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US20120196420A1 (en) 2012-08-02

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