US20080014409A1 - Method of making a circuitized substrate - Google Patents
Method of making a circuitized substrate Download PDFInfo
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- US20080014409A1 US20080014409A1 US11/863,820 US86382007A US2008014409A1 US 20080014409 A1 US20080014409 A1 US 20080014409A1 US 86382007 A US86382007 A US 86382007A US 2008014409 A1 US2008014409 A1 US 2008014409A1
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- conductive layer
- substrate
- side wall
- layer
- substantially planar
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
- B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B15/00—Layered products comprising a layer of metal
- B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/04—Layered products comprising a layer of synthetic resin as impregnant, bonding, or embedding substance
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/06—Layered products comprising a layer of synthetic resin as the main or only constituent of a layer, which is next to another layer of the same or of a different material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/30—Layered products comprising a layer of synthetic resin comprising vinyl (co)polymers; comprising acrylic (co)polymers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/38—Layered products comprising a layer of synthetic resin comprising epoxy resins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
A circuitized substrate and a method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.
Description
- This application is a continuation of Ser. No. 11/619,789, filed Jan. 4, 2007; which is a divisional of U.S. Pat. No. 7,185,428, issued Mar. 6, 2007; which is divisional of U.S. Pat. No. 6,822,332, issued on Nov. 23, 2004.
- The invention relates generally to a circuitized substrate, and more particularly to a substrate having tightly spaced fine line circuitization positioned thereon, and method of forming same.
- Circuitized substrates, such as chip scale packages, ball grid array substrates, test carriers, multi chip modules, and printed wiring boards, often include patterns of conductors. In addition, conductive vias can be formed to electrically connect the conductors to contacts, or other patterns of conductors, located on different surfaces or internal conductive planes of the circuitized substrate.
- The two approaches in the art used in mass production for forming conductors and associated connections to contacts or vias are additive circuitization using pattern plating, and subtractive circuitization following full panel plating. Typically both approaches start with a multilayer composite board or substrate that has been laminated with an external metal foil commoning layer, and which has been drilled with blind vias or through holes to make subsequent connections to internal wiring. The external metal foil, usually copper, may be thinned by chemical or mechanical means to facilitate further processing. In the typical additive circuitization process the conductor pattern is then defined by patterning a photoresist, and formed by electroplating metal into the defined pattern and drilled vias not covered by the resist. After plating, the photoresist is stripped and the original thin metal commoning layer is etched away leaving a pattern of conductors and plated vias/through holes. In the typical subtractive process, the first step after the multilayer composite board has been laminated with an external metal foil commoning layer and drilled is to blanket plate all surfaces, including drilled vias, to a final conductor thickness. The conductor pattern is then formed by patterning a photoresist on metal features to remain. All unwanted metal is removed by a chemical etching leaving a pattern of conductors and plated vias/through holes.
- The additive approach to circuitization is generally capable of producing well shaped conductors with fine spacing, since the conductors are built up into channels predefined by resist. The shape and density of the conductors is limited by the ability to define channels in photoresist. However, additive methods have many challenges including uniformity of plating across the panel and inside the plated through holes, adhesion of the resist through processing steps, and problems associated with removing the thin metal commoning layer after the resist is stripped. These challenges only increase as boards become thicker and more complex. Furthermore, additive circuitization processes that use electroless plating to avoid the need for a commoning layer are very expensive, and the electroless plating baths tend to have unstable characteristics requiring close monitoring. The subtractive circuitization approach is inherently more simple, with less process steps, and is less costly. Since there is no commoning layer to remove after the conductors are formed as with additive circuitization, all problems associated with the commoning layer etch process step are avoided. In addition, very uniform plating thickness is obtained across the panel and inside plated through holes independent of board thickness. A main disadvantage of the typical subtractive process is that it is more difficult to produce substantially rectangularly shaped surface conductors of dense spacing since the process is limited by the ability to etch away surface metal, which will not normally result in the same sharp edge definition that is possible by a photopattern in resist. This disadvantage becomes more pronounced as boards become thicker and features become more dense because the process parameters required to plate inside the high aspect ratio drilled vias of thick boards will result in thicker surface plating, which in turn further limits the ability to produce dense and rectangular shaped conductors.
- As circuitized substrates become denser, thicker and more complex, it is increasingly more difficult, and in many cases impossible, to use conventional processes to form the conductors. In particular, the required size, spacing and shape of the conductors most often cannot be achieved by using conventional processes, especially solely with a subtractive circuitization process.
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FIG. 1 shows a much-enlarged sectional view, in elevation of a known circuitizedsubstrate 10. Thecircuitized substrate 10 includes asubstrate 12 having a substantially planarupper surface 14 and a plurality ofconductors 16 positioned on the substantially planar upper surface of the substrate. A photoimageable photopatterneddielectric material 18 is positioned on anupper surface 20 of plurality ofconductors 16. - Plurality of
conductors 16 are formed using solely the conventional subtractive circuitization process described above. A conductive layer is blanket deposited onsubstrate 12, photopatterned with photoimageable dielectric material to expose portions of the conductive layer and then chemically etched to form plurality ofconductors 16. The conductive layer includes aside wall 24 therein defining anopening 26. Chemical etching action, being substantially uniform on the exposed portions of the conductive layer,shapes side wall 24 in a curved concave manner and can formundercut regions 28, especially when the thickness of the conductive layer is greater than about 8 microns. The resultant shape in cross-section ofconductors 16 is that of a half hourglass. In general, this half hourglass shape has poorer electrical performance characteristics and lower current carrying capability than substantially rectangular cross-sectional shaped conductors of the same height, width, and spacing. Furthermore, the half hourglass shape clearly limits the conductor density (number of conductors per unit area) because conductors of such shape cannot be placed as closely together as rectangular shaped conductors without creating yield (potential shorting), reliability, and electrical concerns.Conductors 16 can be acceptable when electrical performance is not important, that is, when tight spacing between the center to center dimension of the conductors is not a requirement, and when there is no need for features, such as vias, to be located between conductors. When one or all of these factors is desired, half hourglass shaped conductors are undesirable. Tight spacing between the center to center dimension of plurality ofconductors 16 is difficult to achieve by chemical etching without thebases 30 of the plurality of conductors touching one another or being substantially close to touching one another creating a potential short or cross-talk between adjacent conductors. - In the industry today, these problems can be addressed by specifying the conductive layer and the resultant conductors to have a thickness of less than about 8 microns. The undercutting action of chemical etching on a conductor layer having a thickness of less than about 8 microns is of short duration with less pronounced undercutting. However, conductors having a thickness of less than about 8 microns still can have poor electrical characteristics and do have lower current carrying capability. Moreover, about 8 microns of surface copper is not a realistic limit with thick boards that include high aspect through holes that need complete plating throughout, as discussed above. When the thickness of conductors greater than about 8 microns is required in combination with tightly spaced fine lines, sufficiently more etching is required to increase the spacing between the base of the conductors. More etching increases undercutting of the conductors, makes the half hourglass shape more pronounced, and thins the distance between sidewalls of an individual conductor even further resulting in conductors having even poorer electrical performance.
FIG. 2 illustratescircuitized substrate 10′ after further chemical etching of circuitizedsubstrate 10 ofFIG. 1 to increase spacing betweenbases 30′ andconductors 16′. Circuitizedsubstrate 10′ has increased spacing betweenbases 30′ ofconductors 16′, however further undesirable undercutting 28′ and an even more pronounced half hourglass shaped conductors exist. - The processes illustrated in
FIGS. 1 and 2 are performed uniformly across an entire substrate or panel, and therefore affect every conductor and conductor sidewall in the same way. However, in circuit design for a circuit board or circuit substrate, the total length of conductor involved in areas of tight spacing is normally a small fraction of the total conductor length. For example, tight spacing may be required only on some conductor sidewalls within a fine pitch ball grid array (BGA) site of a printed wiring board, or on the inside sidewalls of two adjacent coupled-pair conductors, but not required on the majority of surface conductors. The process resulting in the structure illustrated inFIG. 1 would be adequate for the vast majority of conductor sidewalls, even though not acceptable in the limited areas of tight spacing. Similarly, the additional etch process, necessary to product tight spacing on only a portion of a circuitized substrate, resulting in the structure illustrated inFIG. 2 would also adversely affect all conductor sidewalls, even where tight spacing was not required. The ideal solution is a process that can differentiate areas of tight spacings from those which can be processed with conventional subtractive circuitization methods. - Accordingly, there is a need in the art for improved processes for fabricating tightly spaced finer patterns of conductors to make a circuitized substrate by utilizing a partial subtractive etching process in the area of the circuitized substrate, where these finer patterns of conductors are desired, which overcomes the disadvantages of the known method and structure.
- Accordingly, it is the object of this invention to enhance the art of electronic packaging.
- Another object of the present invention is to provide a circuitized substrate including a conductive layer having an opening therein, the conductive layer positioned on a substantially planar upper surface of the circuitized substrate, at least one side wall of the opening being substantially perpendicular to the substantially planar upper surface of the substrate, and the conductive layer including an end portion spaced from the opening forming an acute angle with the substantially planar upper surface of the substrate.
- Yet another object of the present invention is to provide a method of making a circuitized substrate having a substrate with an upper surface and a conductive layer on the upper surface of the substrate, the conductive layer including a side wall and a bottom wall, the bottom wall defined by the upper surface of the substrate, the side wall being substantially perpendicular with the bottom wall.
- Another object of the present invention is to provide a circuitized substrate and method of making the circuitized substrate that includes at least one tightly spaced fine pattern of conductors thereon and assures electrical performance.
- According to one aspect of the invention, there is provided a circuitized substrate comprising a substrate having a substantially planar upper surface, a conductive layer positioned on the substantially planar upper surface including at least one side wall therein defining an opening in the conductive layer, the conductive layer including an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate, the at least one side wall being substantially perpendicular to the substantially planar upper surface of the substrate.
- According to another aspect of the invention, there is provided a method of making a circuitized substrate comprising the steps of providing a substrate having an upper surface, positioning a conductive layer having a substantially planar upper surface on the upper surface of the substrate, positioning a layer of patternable material on the substantially planar upper surface of the conductive layer, removing a portion of the layer of patternable material to form a side wall in the patternable layer and to expose a predetermined pattern on the substantially planar upper surface of the conductive layer, the side wall in the layer of patternable material being substantially perpendicular to the substantially planar upper surface of the conductive layer, removing a portion of the conductive layer under the predetermined pattern to form an interim side wall in the conductive layer, and removing portions of the interim side wall in the conductive layer to form a second side wall and a bottom wall, the bottom wall defined by the upper surface of the substrate, the second side wall being substantially perpendicular with the bottom wall.
- According to yet another aspect of the invention, there is provided a method of making a circuitized substrate comprising the steps of providing a substrate having an upper surface, positioning a conductive layer having a substantially planar upper surface on the upper surface of the substrate, removing a portion of the conductive layer to form a interim side wall in the conductive layer, positioning a layer of patternable material on the substantially planar upper surface of the conductive layer and on the interim side wall in the conductive layer, removing a portion of the layer of patternable material on the conductive layer to expose the interim side wall in the conductive layer and a portion of the substantially planar upper surface of the conductive layer relative to the interim side wall to form a side wall in the layer of patternable material, the side wall in the layer of patternable material being substantially perpendicular to the substantially planar upper surface of the conductive layer, and removing portions of the interim side wall in the conductive layer to form a second side wall and a bottom wall, the bottom wall defined by the upper surface of the substrate, the second side wall being substantially perpendicular with the bottom wall.
- The above objects, advantages, and features of the present invention will become more readily apparent from the following detailed description of the preferred embodiments as illustrated in the accompanying drawings.
-
FIG. 1 represents a much-enlarged sectional view in elevation of a known circuitized substrate having conductors formed from a chemically etched conductive layer. -
FIG. 2 represents the known circuitized substrate ofFIG. 1 , with the conductive layer shown as being further chemically etched. -
FIG. 3 represents a much-enlarged sectional view in elevation of one embodiment of the circuitized substrate of the present invention. -
FIGS. 4-7 represent the various steps of making a circuitized substrate in accordance with one embodiment of the invention. -
FIGS. 8-11 represent the various steps of making a circuitized substrate in accordance with another embodiment of the invention. - A
circuitized substrate 10 illustrating one embodiment of the present invention is shown inFIG. 3 . The circuitized substrate includes asubstrate 12 having a substantially planarupper surface 14. Aconductive layer 16 is positioned on substantially planarupper surface 14.Conductive layer 16 includes anupper surface 17 and at least oneside wall 18 therein, defining anopening 20 in the conductive layer. Theconductive layer 16 includes anend portion 22 spaced from opening 20, the end portion forming an acute angle θ with substantially planarupper surface 14 ofsubstrate 12. Acute angle θ is defined as the angle between substantially planarupper surface 14 ofsubstrate 12 and the intersection of a line drawn between points p1 and p2 ofend portion 22. The acute angle θ can vary, depending on processing conditions and conductor layer thickness, from about 60 degrees to about 80 degrees. The at least oneside wall 18 is substantially perpendicular to substantially planarupper surface 14 ofsubstrate 12. Substantially perpendicular is defined as an angle of greater than about 80 degrees to about 90 degrees. -
Substrate 12 can comprise a chip carrier, printed wiring board, or any suitable substrate on which a conductor layer is to be positioned for electrical interconnect purposes. Examples of suitable substrates that can be used in this invention may be comprised of epoxy resins filled with glass, ceramics, silicon, polyimide, and polytetrafluoroethylene.Conductive layer 16 can be electrically connected to conductive through apertures (not shown) withinsubstrate 12 to make electrical connections to other electronic devices.Conductive layer 16 comprises a metal selected from the group of metals consisting of copper, aluminum, tin, gold, nickel, titanium, tungsten, and hafnium and alloys thereof.Conductor layer 16 can also comprise a semiconductor such as silicon, polysilicon, germanium, or gallium arsenide. -
End portion 22 ofconductive layer 16 can, at least in part, include a curvilinear surface. The curvilinear surface can be substantially concave and can be formed by chemical etching ofconductive layer 16.End portion 22 ofconductive layer 16 defines asecond opening 24 in the conductive layer.Second opening 24separates conductors conductors conductive layer 16 must be etched so that the width betweenconductors upper surface 17 ofconductive layer 16, is dimension b.Second opening 24 betweenconductors conductive layer 16 and the conductive layer has a thickness of more than about 8 microns,sidewall 18 is formed by laser etching followed by chemically etching, as described in detail below. A chemically etched opening having a substantially rectangular shape with dimension c is not possible when the conductor is greater than about 8 microns, because a chemically etched opening would have a bowl shape similar tosecond opening 24. For example, if minimum width a betweenconductors FIG. 3 illustrates that, if chemical etching is used alone to form opening 20, it would be necessary to chemically etch the opening to dimension b to achieve spacing c.Conductors - The advantage of this structure is that it enables a circuitized substrate designer and the manufacturer of the circuitized substrate the flexibility of designing and manufacturing a circuitized substrate having both tightly spaced conductors, spaced less than about 125 microns apart and, conventionally spaced conductors on the same circuitized substrate when the conductors are about 8 microns thick or more. Importantly, when tightly spaced fine line conductors are necessary for electrical performance of a circuitized substrate or it is necessary to place features, such as vias or pads, between tightly spaced conductor portions on a circuitized substrate, the laser etching (or scribing, drilling or machining) and chemical etching methods, described in detail below, can be utilized to yield substantially rectangular conductor portions with substantially vertical side walls. Where improved electrical performance characteristics or higher conductor density, resulting from tight spacing with substantially rectangular shaped conductors, are not as important on certain other areas of the circuitized substrate, a conventional chemical etching process to make conductors on that area of the same circuitized substrate can be used.
- In
FIG. 4 , there is shown asubstrate 32 which may be used in one embodiment of the present invention to produce a circuitized substrate (shown inFIG. 7 and described herein below).Substrate 32 includes anupper surface 34 and has been previously described in detail above. Positioned onupper surface 34 ofsubstrate 32 is aconductive layer 36.Conductive layer 36 can be positioned onupper surface 34 ofsubstrate 32 to a thickness of from about 8 microns to about 150 microns by a process of laminating, plating, evaporating, sputtering or combinations thereof. The conductive layer has been previously described in detail above. Positioned on a substantially planarupper surface 38 ofconductive layer 36 is a layer ofpatternable material 40. The layer ofpatternable material 40 can be an acrylic or an epoxy acrylic photosensitive or photopolymerizable material such as a photoresist or a soldermask and can be a positive or a negative acting. Positive acting photoresists, when applied and exposed through a suitable photomask, undergo a physical and chemical change in the exposed areas that renders these exposed areas soluble to subsequent developer solution which is to be applied thereto. Negative acting photoresists, when applied and exposed through a suitable photomask, undergo a physical and chemical change in the exposed areas that renders these exposed areas insoluble to subsequent developer solution which is to be applied thereto. An electrodeposited positive acting resist can also be used with this invention. The patternable material can be applied by a process of spraying, laminating, spin-coating, screening, curtain coating, and dipping or in the case of an electrodeposited resist, by electroplating. - The thickness of
patternable material 40 can range from about 6 microns to about 75 microns. Some examples of suitable commercially available patternable materials are Riston available from E. I. du Pont de Nemours and Company, Wilmington, Del., Dynavia Series and PEPR Series, both available from Shipley Ronal, 2675 Antler Drive, Carson City, Nev. 89701, and PSR Series, available from Taiyo America, 455 Forest St., Marborough, Mass. 01752. - In
FIG. 5 , portions of layer ofpatternable material 40 ofsubstrate 32 are shown as being removed to form asidewall 42 in the layer of patternable material and to expose apredetermined pattern 44 on substantially planarupper surface 38 ofconductive layer 36 to which further processing is to eventually occur.Predetermined pattern 44 can be formed by a process of exposing a pattern in a negative acting photoresist to UV light and removing the unexposed portions of the patterned photoresist with a developing solution (e.g., sodium carbonate or propylene carbonate).Predetermined pattern 44 can also be formed by the action of a laser, such as a CO2 or YAG laser on the portions of the layer of patternable material to be removed.Side wall 42 in layer ofpatternable material 40 is shown as being substantially perpendicular to substantially planarupper surface 38 ofconductive layer 36. In the present invention,side wall 42 is not limited to being formed perpendicular to substantially planarupper surface 38 and can be formed having an acute angle with the planar upper surface ofconductive layer 36. - In
FIG. 6 , a portion of substantially planarupper surface 38 ofconductive layer 36 within predeterminedpattern 44 ofsubstrate 32 is shown after being subjected to a laser etching process to remove the portion of the conductive layer under the predetermined pattern forming aninterim sidewall 46 in the conductive layer.Interim side wall 46 is formed inconductive layer 36 to a depth of from about 50% to about 95% of the thickness of the conductive layer. Theinterim side wall 46 is formed having a minimum thickness (remaining conductor material) of from about 5% to about 50% of the thickness ofconductive layer 36. In one example, laser etching was performed with an ESI 5200 Laser Microvia System. A frequency-tripled Nd:YAG laser, operating at a wavelength of from about 150 nanometers (nm) to about 600 nm with a pulse width of from about 20 nanoseconds (ns) to about 150 ns, was used. Pulse width of a YAG laser is defined as the length of time for which the energy of a given laser pulse is greater than or equal to 1/e2 the maximum energy for that pulse. The laser etching process includes the steps of focusing the YAG laser beam to a diameter of from about 6 microns to about 300 microns at a power of from about 0.5 watts to about 15 watts on the portion ofconductive layer 36 under predeterminedpattern 44. The spatial distribution of energy in the laser spot can be gaussian, greatest at the center of the spot, diminishing toward the perimeter. Laser etching at these parameters removes portions ofconductive layer 36 under predeterminedpattern 44 in about 6 micron to about 150 micron bites at a repetition rate of from about 10 hertz to about 50 kilohertz. Bite size is defined as center to center distance between laser pulses and the repetition rate is defined as the number of laser pulses delivered to portions ofconductive layer 36 per unit time. Although a YAG laser is described to forminterim side wall 46, it is understood that the invention is not limited thereto. Other lasers for example, Nd:YLF, Argon Ion, and Xenon can be used to forminterim side wall 46. Other techniques, for example, focused ion beam, can also be used to forminterim side wall 46. - In
FIG. 7 ,circuitized substrate 45 is shown after portions of theinterim side wall 46 inconductive layer 36 of substrate 32 (seeFIG. 6 ) have been subjected to wet chemical etching. In a preferred embodiment of the invention, portions ofinterim side wall 46 have been removed by a wet chemical etching process to form asecond side wall 48 and abottom wall 50, the bottom wall defined byupper surface 34 ofsubstrate 32, the second side wall being substantially perpendicular withbottom wall 50. The wet etching process can be accomplished with a solution consisting essentially of cupric chloride, sulfuric acid, ferric chloride, sodium persulfate, or potassium persulfate at a temperature of from about 120° F. to about 140° F. for about 2 minutes to about 20 minutes (depending on the concentration of the etching solution).Second side wall 48 andbottom wall 50 define anopening 52 having a width of less than about 125 microns, as described above, which is a space in cross-section that separates portions ofconductive layer 36 intoconductors patternable material 40. It is understood that opening 52 is shown for illustration purposes only and does not limit the invention to those as shown. - In
FIG. 8 , there is shown asubstrate 58 which may be used in another embodiment of the present invention to produce a circuitized substrate (shown inFIG. 11 and described herein below).Substrate 58 includes anupper surface 60 and has been described in detail above. Positioned onupper surface 60 is aconductive layer 62 having a substantiallyplanar surface 64. Theconductive layer 62 and the process for positioning the conductive layer onupper surface 60 have been previously described above. A portion of substantially planarupper surface 64 ofconductive layer 62 is shown as being removed forming aninterim side wall 66 in the conductive layer.Interim side wall 66 can be formed with, but is not limited to, the laser and laser etching process used to forminterim side wall 46 inconductive layer 36, as previously described in detail above, and can have a minimum thickness (remaining conductor material) of from about 5% to about 50% of the thickness ofconductive layer 62. Substantially planarupper surface 64 may need cleaning to remove remnants ofconductive layer 62 after laser etching, which may have been redeposited on substantially planar upper surface during the laser etching process. The cleaning process can consist of immersion ofsubstrate 58, or spraying substantially planarupper surface 64, with a mild etching solution that slowly removes a small amount ofconductive layer 62 undercutting any debris that may be present, and thereby lifting it from the surface. - In
FIG. 9 , a layer ofpatternable material 68 is shown as being positioned on substantially planarupper surface 64 ofconductive layer 62 and oninterim side wall 66 in the conductive layer. The layer ofpatternable material 68 and the process to position the layer of patternable material on substantially planarupper surface 64 and oninterim side wall 66 can comprise the same material and process as described in detail above regarding layer ofpatternable material 40. - In
FIG. 10 , a portion of layer ofpatternable material 68 onconductive layer 62 is shown as being removed to exposeinterim side wall 66 in the conductive layer and to expose aportion 70 of substantially planarupper surface 64 of the conductive layer relative to the interim side wall. Aside wall 72 is formed in layer ofpatternable material 68, the side wall being shown as being substantially perpendicular to planarupper surface 64 ofconductive layer 62. In the present invention,side wall 72 is not limited to being formed perpendicular to planarupper surface 64 and can be formed having an acute angle with the planar upper surface ofconductive layer 62. - In
FIG. 11 ,circuitized substrate 73 is shown with asecond side wall 74 and abottom wall 76 defined byupper surface 64 of the substrate. Thesecond side wall 74 is formed by removing portions ofinterim side wall 66, andportion 70 of substantially planarupper surface 64 of conductive layer 62 (shown inFIG. 10 ). The step of removing portions ofinterim side wall 66 andportion 70 of substantially planarupper surface 64 comprises chemical etching, as previously described above.Second side wall 74 is shown as being substantially perpendicular withbottom wall 76.Sidewall 74 andbottom wall 76 define anopening 78 having a width less than about 125 microns which is a space in cross-section which separatesconductors patternable material 68. - Thus there have been shown and described three facile methods for producing a circuitized substrate which are capable of being readily performed using many established processes in the art. The invention thus represents a relatively inexpensive yet effective process for producing high electrical performance circuitized substrates on a mass scale having tightly spaced fine lines. As stated above, it is also readily possible to utilize alternative procedures which are also known in the art, to accomplish this invention.
- While there have been shown and described what are at present considered the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (17)
1. A method of making a circuitized substrate, comprising the steps of:
Providing a substrate having an upper surface;
forming a conductive layer having a substantially planar upper surface on and in direct mechanical contact with the upper surface of the substrate by laminating, plating, or sputtering a metal on the upper surface of the substrate;
removing a portion of the conductive layer to form an interim side wall in the conductive layer;
forming a layer of patternable material on the substantially planar upper surface of the conductive layer and on the interim side wall in the conductive layer;
removing a portion of the layer of patternable material on the conductive layer to expose the interim side wall in the conductive layer and a portion of the substantially planar upper surface of the conductive layer relative to the interim side wall to form a side wall in the layer of patternable material;
removing portions of the interim side wall in the conductive layer to form a second side wall and a bottom wall, said bottom wall defined by the upper surface of the substrate, said second side wall being substantially perpendicular to the bottom wall; and
after said removing portions of the interim side wall, removing a remaining portion of the layer of patternable material.
2. The method of claim 1 , wherein the side wall in the layer of patternable material makes an acute angle with the substantially planar upper surface of the conductive layer.
3. The method of claim 1 , wherein the interim side wall, resulting from the step of removing a portion of the conductive layer under the predetermined pattern, is formed to a depth in the conductive layer from about 50% to about 95% of the total thickness of the conductive layer.
4. The method of claim 1 , wherein the method further comprises electrically connecting the conductive layer to an electronic device through an aperture within the substrate.
5. A method of making a circuitized substrate comprising the steps of:
providing a substrate having an upper surface;
forming a conductive layer having a substantially planar upper surface on and in direct mechanical contact with said upper surface of said substrate by laminating, plating, or sputtering a metal on the upper surface of the substrate to form the conductive layer;
forming a layer of patternable material on and in direct mechanical contact with said substantially planar upper surface of said conductive layer, wherein the layer of patternable material has a total thickness in a direction perpendicular to the substantially planar upper surface of said conductive layer;
removing a portion of said layer of patternable material to form a side wall in said patternable layer and to expose a predetermined pattern on said substantially planar upper surface of said conductive layer;
removing a portion of said conductive layer under said predetermined pattern to form an interim side wall in said conductive layer;
removing portions of said interim side wall in said conductive layer to form a second side wall and a bottom wall, said bottom wall defined by said upper surface of said substrate, said second side wall being substantially perpendicular with said bottom wall, wherein after the step of removing portions of said interim side wall is performed a remaining portion of said layer of patternable material is in direct mechanical contact with the substantially planar upper surface of the conductive layer and has said total thickness in said direction perpendicular to the substantially planar upper surface of said conductive layer; and
after said removing portions of said interim side wall, removing a remaining portion of the layer of patternable material.
6. The method of claim 5 , wherein said interim side wall is formed having a thickness of from about 5% to about 50% of said thickness of said conductive layer.
7. The method of claim 5 ,
wherein said step of removing said portion of said conductive layer under said predetermined pattern comprises laser etching,
wherein said laser etching is accomplished with a YAG laser beam operating at a wavelength of about 150 nanometers to about 600 nanometers with a pulse width of about 20 nanoseconds to about 150 nanoseconds, and
wherein said laser etching includes the steps of focusing said YAG laser beam to a diameter of about 6 microns to about 150 microns at a power of about 0.5 watts to about 15 watts on said portion of said conductive layer under said predetermined pattern, and removing about 6 micron to about 150 micron bites of said conductive layer at a repetition rate of about 10 hertz to about 50 kilohertz.
8. The method of claim 5 , wherein the side wall in the patternable layer, resulting from the step of removing a portion of said layer of patternable material, makes an acute angle with the substantially planar upper surface of the conductive layer.
9. The method of claim 5 , wherein the interim side wall, resulting from the step of removing a portion of the conductive layer under the predetermined pattern, is formed to a depth in the conductive layer from about 50% to about 95% of the total thickness of the conductive layer.
10. The method of claim 5 , wherein the method further comprises electrically connecting the conductive layer to an electronic device through an aperture within the substrate.
11. A circuitized substrate comprising:
a substrate having a substantially planar upper surface;
a conductive layer positioned on the upper surface of the substrate, said conductive layer including a bottom surface that is in direct mechanical contact with the upper surface of the substrate, said conductive layer including a top surface above and separated from the upper surface of said substrate, said conductive layer including a first opening extending from the top surface of the conductive layer to the bottom surface of the conductive layer, said conductive layer including a first conductive segment, said first conductive segment having a first end surface and a second end surface, said first end surface coinciding with a side wall of the first opening, said side wall being substantially perpendicular to the upper surface of the substrate, said second end surface comprising a first point on the bottom surface of the conductive layer and a second point on the top surface of the conductive layer, said first point being in direct mechanical contact with the upper surface of the substrate, wherein a straight line through the first point and the second point forms an acute angle from about 60 degrees to about 80 degrees with the upper surface of the substrate.
12. The circuitized substrate of claim 11 , wherein the second end surface is curvilinear.
13. The circuitized substrate of claim 12 , wherein said curvilinear second end surface is substantially concave such that a void region exists between the second end surface and the straight line.
14. The circuitized substrate of claim 11 , wherein the conductive layer further includes a second conductive segment separated from the first conductive segment by a first width of separation at the bottom surface of the conductive layer and by a second width of separation at the top surface of the conductive layer.
15. The circuitized substrate of claim 14 , wherein the second width of separation exceeds the first width of separation.
16. The circuitized substrate of claim 14 , wherein the conductive layer has a second opening between the first and second conductive segments, and wherein the second opening is bowl shaped.
17. The circuitized substrate of claim 14 , wherein the conductive layer is electrically connected to an electronic device through an aperture within the substrate.
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JP5052464B2 (en) * | 2008-09-11 | 2012-10-17 | 富士フイルム株式会社 | Method for manufacturing organic electroluminescent display device |
TW201110839A (en) * | 2009-09-04 | 2011-03-16 | Advanced Semiconductor Eng | Substrate structure and method for manufacturing the same |
JP5561761B2 (en) * | 2009-11-26 | 2014-07-30 | 株式会社Uacj製箔 | Manufacturing method of flexible printed wiring board |
KR101859126B1 (en) | 2011-04-25 | 2018-05-17 | 해성디에스 주식회사 | Method of forming a fine pattern by using ultraviolet irradiation |
CN103488323B (en) * | 2012-06-13 | 2016-06-08 | 东元奈米应材股份有限公司 | Contact panel and manufacture method thereof |
KR101909832B1 (en) * | 2017-09-14 | 2018-10-18 | 김애경 | Manufacturing method of film type data communication cable and its products |
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Also Published As
Publication number | Publication date |
---|---|
US7596862B2 (en) | 2009-10-06 |
US6822332B2 (en) | 2004-11-23 |
JP3899058B2 (en) | 2007-03-28 |
US7325299B2 (en) | 2008-02-05 |
US20070102396A1 (en) | 2007-05-10 |
US7185428B2 (en) | 2007-03-06 |
JP2004119968A (en) | 2004-04-15 |
US20040130003A1 (en) | 2004-07-08 |
US20040056330A1 (en) | 2004-03-25 |
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