US20080029400A1

US20080029400A1 - Selective electroplating onto recessed surfaces

Info

Publication number: US20080029400A1
Application number: US11/432,929
Authority: US
Inventors: Stephen Mazur
Original assignee: Individual
Current assignee: EIDP Inc
Priority date: 2005-05-13
Filing date: 2006-05-12
Publication date: 2008-02-07

Abstract

Processes for electroplating recessed features on a substrate are provided. The processes are useful in applications such as creating Cu interconnects on integrated circuits.

Description

FIELD OF THE INVENTION

This invention is directed to processes for electrochemically depositing metal into recessed features on an otherwise flat substrate without the necessity of concurrently depositing metal on intervening plateau areas. The processes of the invention are useful for creating Cu interconnects on integrated circuits without the need to planarize and remove large amounts of excess Cu.

BACKGROUND

Cu interconnects on integrated circuits (IC's) are presently fabricated by a multi-step damascene process. Four stages in this process are illustrated in FIG. 1 and can be summarized briefly as follows. For each layer of interconnects on top of a silicon wafer 1, the circuit pattern is lithographically etched as a series of lines and holes in a dielectric layer 2, for example a layer of SiO₂approximately 500 nm thick. Then, by means of vapor phase deposition, the entire surface is coated with a thin barrier layer 3, for example TaN and Ta approximately 25 nm thick, followed by a “seed” layer 4 of Cu approximately 100 nm thick. The seed layer 4 prevents the formation of oxides on the Ta barrier layer 3 and provides a surface for subsequent deposition of a much thicker layer of Cu 5 by means of electroplating (also called electrochemical deposition, ECD). ECD is used to completely fill the recessed circuit features with Cu up to the level of the surrounding dielectric areas. But to achieve this requires the deposition of a considerable excess of Cu over the entire surface. Specialized ECD plating solutions and processing conditions have been developed so as to completely fill the smallest circuit features, to limit the amount of excess Cu deposited on plateau areas which separate the circuit features, and to minimize the topographic structure on the final plated surface. See for example, J. Reid et al., MRS Conference Proceedings Series, Vol. V-15, p 53, (1999). Nevertheless, excess Cu deposited in the ECD step generally exceeds the amount of Cu required to fill the circuits. To fill circuits 500 nm deep typically requires ECD deposition of more than 1000 nm of Cu overall (FIG. 1B). It is then necessary to planarize and remove the excess Cu from the plateau areas down to the level of the barrier layer 3. This is presently accomplished by chemical mechanical polishing (CMP) which employs a combination of chemical oxidation and mechanical abrasion. Electrochemical mechanical polishing (ECMP) is a related method that employs electrochemical oxidation in combination with mechanical abrasion. (L. Economikos, et al., IEEE International Interconnect Technology Symposium, Session 13, Burlingame, Calif., 2004). The first Cu CMP or ECMP step is required to planarize the excess Cu as represented in FIG. 1C, and a second CMP step is used to clear excess Cu from the plateau areas as represented as in FIG. 1D. Finally, the barrier layer is removed from the plateau areas by yet another CMP operation (not shown).
This standard Cu damascene fabrication process suffers from a number of disadvantages. The need to deposit and then remove a substantial amount of excess Cu is wasteful of time and materials, requires several expensive pieces of equipment, and generates a waste stream contaminated by toxic chemicals. The consumption of the specialized CMP polishing slurries and pads represents a substantial operating cost. In addition, the CMP process can be a source of defects and yield loss. Among the defects associated with Cu CMP are abrasive erosion of the barrier layer and dielectric material on narrow dielectric features. This problem has become more important with the introduction of low-K dielectric materials, which are mechanically more fragile than SiO₂. Another defect associated with Cu CMP is “dishing”, where over-polishing causes partial loss of Cu in the circuit features such that the surface of these features recedes below the plane of the surrounding dielectric.
Numerous methods have been explored to overcome limitations and/or improve the efficiency of the standard Cu damascene process, and especially to limit the accumulation and removal of excess Cu. For example, H. Talieh, U.S. Pat. No. 6,176,992 (2001) and T. Wang et al., Thin Solid Films, 478, 3345 (2005) describe an electrochemical mechanical deposition (ECMD) technique whereby electroplating is carried out simultaneously with mechanical abrasion in order to minimize accumulation of excess Cu and to planarize the excess.
Another method is described in WO 01/20647 A2 and illustrated schematically in FIG. 2. In this method, prior to ECD, the Cu seed layer 4 is selectively removed from the surface of the plateau areas by mechanical polishing or by CMP so as to expose the barrier layer 3 on the plateau surfaces while retaining the seed layer in the recessed areas. The exposed barrier metal, for example Ta, is readily oxidized on exposure to air to form a thin, dense, insoluble electrically insulating oxide layer 6. The oxide functions as a passivating layer preventing oxidation of the remaining Ta and/or TaN 7. When the wafer is then subjected to ECD, the oxide layer also insulates the plateau areas so that plating occurs exclusively in the recessed areas. Consequently, when the recessed areas have been completely filled with Cu 8, no excess Cu is left on the plateaus. By avoiding the need to deposit and then remove large amounts of excess Cu, this process can greatly reduce the consumption of time and materials and the generation of waste.
However, ECD requires that all of the recessed areas be electrically connected to the negative terminal of the power supply. When the seed layer 4 has been removed from the surrounding plateau areas, electrical continuity must be provided by the remaining barrier layer 7. If regions of the barrier layer 7 are excessively oxidized or abrasively removed during selective removal of the seed layer, then neighboring recessed areas may become electrically isolated and fail to be plated. Thus, the practicality of this strategy hinges on how selectively the seed layer can be removed from plateau areas without interrupting or compromising the electrical continuity of the barrier layer.
Therefore, there remains a need for a process that overcomes the limitations of the current damascene process and other known processes.

SUMMARY OF THE INVENTION

One aspect of the present invention is a process comprising:

- a. providing a substrate, wherein a first surface of the substrate comprises substantially flat areas and recessed features;
- b. coating the first surface of the substrate with a continuous, conformal first metallic layer;
- c. coating the continuous conformal first metallic layer with a conformal layer of a second metal;
- d. selectively removing substantially all of the second metal from the substantially flat areas using membrane-mediated electropolishing to expose the first metallic layer in the substantially flat areas, while leaving the recessed areas substantially covered by the second metal;
- e. creating a layer of a substantially insoluble, electrically insulating compound on the exposed surfaces of the conformal layer of the first metallic layer, while leaving intact a sufficient portion of the first metallic layer to carry electrical current to all recessed areas on the substrate surface;
- f. electroplating a conformal layer of a third metal onto the second metal layer in the recessed areas.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a schematic showing idealized cross-sections of a wafer at four stages in the Cu damascene fabrication process of the prior art.

FIG. 2 is a schematic showing idealized cross-sections of a wafer during a process in which Cu is selectively electroplated into recessed areas

FIG. 3 is a schematic showing idealized cross-sections of a wafer illustrating the selective electroplating of Cu into dished areas following overpolishing by MMEP.

FIGS. 4A and 4B are optical micrographs of circuit features on a damascene wafer after severe over-polishing by means of MMEP (4A), and the same area after selective electroplating into the dished areas (4B), according to an embodiment of this invention. FIGS. 5A and 5B are profilometry scans of 100 μm circuit lines and intervening spaces on a damascene wafer after severe over-polishing by means of MMEP (5A), and the same area after selective electroplating into the dished areas (5B), according to an embodiment of this invention.

FIG. 6 is a schematic of an electroplating apparatus for depositing Cu selectively onto dished areas on an over-polished wafer, according to an embodiment of this invention.

DETAILED DESCRIPTION

In order to use the barrier layer to carry electrical current to selectively deposit Cu in the recessed areas of a substrate by ECD, a non-abrasive, topographically selective process to remove the Cu seed layer from substantially flat areas (also referred to as “plateau areas”), without disrupting the electrical continuity of the barrier layer is desired. In co-pending applications (U.S. Patent applications Ser. No. 60/546,192; U.S. Ser. No. 60/546,198; U.S. Ser. No. 60/611,699; U.S. Ser. No. 60/570,967; and Ser. No. 60/676338), a membrane-mediated electropolishing (MMEP) process is described. MMEP can provide high removal rates for Cu and topographic selectivity similar to those of CMP. But in contrast with CMP, under suitable operating conditions MMEP neither erodes nor completely oxidizes the Ta barrier layer. For example, even after severe over-polishing by MMEP, it was discovered that the exposed barrier layer had only a modest sheet resistance and was capable of carrying significant current density across the surface of the wafer. It was also discovered that this electrical continuity could be used to selectively deposit Cu into recessed areas surrounded by the exposed barrier layer with no deposition on the exposed barrier surfaces.
In one embodiment, the present invention provides a process to selectively remove the seed layer from plateau areas on a wafer by MMEP (membrane-mediated electropolishing), exposing the barrier layer without substantially reducing or disrupting its electrical continuity, and allowing the recessed areas to be selectively filled with Cu by electrochemical deposition (or electroplating) using the barrier layer to carry the current.
FIG. 2 represents one embodiment of this invention suitable for use in the manufacture of wafers for the electronics industry. FIG. 2A is a schematic of a cross-section of a wafer 1 at an intermediate stage in the fabrication of electrical interconnects by the Cu damascene process. The circuit features have been etched into a dielectric layer 2 and the entire surface has been coated with a thin continuous conformal layer of barrier metal (“first metallic layer”) 3 (e.g., Ta), or a combination of barrier metals (e.g., Ta/TaN), followed by a thin conformal “seed” layer of Cu 4, such that the total thickness of layers 3 and 4 is less than the depth of the recessed circuit features. Technology for fabricating a wafer as shown in 2A is well-known in the art and can be used to provide a substrate. A first surface of the substrate comprises substantially flat areas and recessed features.
FIG. 2B shows schematically the wafer after treatment by MMEP, where the barrier 3 has been exposed and then partially oxidized, and 6 represents the oxidized barrier surface and 7 represents the remaining un-oxidized barrier layer. A sufficient thickness of barrier layers 3 and 7 are left intact to carry electrical current to all areas of the wafer in the subsequent electroplating step, and the Cu seed layer is left substantially intact within the recessed areas to serve as a seed layer for the electroplating step.
Standard ECD processes can be used to electroplate Cu into the recessed areas, while leaving the exposed, oxidized surface of the surrounding barrier layer free of Cu, as illustrated in FIG. 2C where 8 represents Cu that has been selectively plated onto a recessed area.
Suitable substrate materials for use in the present process include a Si wafer or Si wafer covered by partially fabricated semiconductor devices and interconnects and by a dielectric material such as SiO₂, porous SiO₂, silicon oxycarbide or other hybrid materials with low dielectric constant. Silicon is commonly used in the electronics industry to make wafers for electronic components. Other substrate materials can include ceramic, plastic, or composite materials such as those used for fabrication of printed wiring boards or for the packaging of semiconductor devices.
The recessed features in the first surface of the substrate are typically 100 nm to 200 μm wide and 500 nm to 1000 nm deep. The recessed features are typically lines and vias, but the shape is not critical for this invention. The first metallic layer can be deposited onto the first surface of the substrate by any method known in the art that is capable of producing a continuous, conformal layer. Such methods include sputtering, chemical vapor deposition, physical vapor deposition and atomic layer deposition. Suitable materials for the first metallic layer include metals such as Ta, Ru, W, Mo, Ti, V, Cr, Ni, Al, and Co as well as the corresponding nitrides, carbides and carbonitrides. A commonly used metallic compound is TaN.
The first metallic layer can also be formed using mixtures of metals or mixtures of metals and metallic compounds. For example, in one embodiment of this invention, the first metallic layer comprises Ta and TaN. The depth of the first metallic layer is typically from 10 nm to about 30 nm.
The conformal layer of a second metal, which is coated onto the first metallic layer, it typically used as a seed layer in the manufacture of electronic wafers. Suitable deposition techniques include sputtering, chemical vapor deposition, physical vapor deposition and atomic layer deposition. Suitable second metals include Cu, Ag, Al, and W, provided that the second metal is different from the composition of the first metallic layer. In one embodiment of this invention, the second metal is Cu.
The thickness of the conformal layer of the second metal is typically from about 2 nm to about 400 nm. In one embodiment of this invention, the layer of the second metal is quite thin, about 2 nm to about 100 nm, and is often termed a “seed” layer. In another embodiment of this invention, the second metal layer is thicker, typically 100 nm to about 1000 nm, and is usually created by electrodeposition of additional metal onto the seed layer.
In the present invention, the second metal layer is selectively removed from the raised plateau areas by means of membrane-mediated electropolishing (MMEP) so as to expose the first metallic layer. Detailed descriptions of the MMEP process are given in co-pending applications U.S. Ser. No. 60/546,192; U.S. Ser. No. 60/546,198; U.S. Ser. No. 60/611,699; U.S. Ser. No. 60/570,967; and U.S. Ser. No. 60/676338. MMEP is an electrochemical process in which metal is removed by anodic oxidation and dissolution of the resulting ions. No abrasive action is involved in MMEP, and the conditions can be chosen so that only the second metal is anodically oxidized and dissolved. In this way, the exposed first metallic layer remains continuous over the entire surface of the wafer and retains sufficiently low electrical sheet resistance to supply current to all areas of the wafer during subsequent electroplating. The present MMEP process can be used to remove either a seed layer of the second metal or an electroplated layer of second metal from the flat areas of the substrate to expose the underlying first metallic layer.
In one embodiment, the present MMEP process comprises:

- a. providing a cathode half-cell comprising:
  - 1. a fully or partially enclosed volume, cavity or vessel;
  - 2. an electrolyte solution or gel which partially or essentially fills the enclosed volume, cavity or vessel;
  - 3. an electrode in contact with the electrolyte solution or gel;
  - 4. a means for electrically connecting the electrode to a DC power source; and
  - 5. a charge-selective ion-conducting membrane which seals one surface of the enclosed volume, cavity or vessel in such a way that the internal surface of said membrane contacts the electrolyte solution or gel and the external surface is accessible to contact the conformal layer of the second metal and a low-conductivity solvent or solution;
- b. substantially covering the conformal layer of the second metal with the low-conductivity solvent or solution;
- c. providing a source of DC electrical power whose positive terminal is connected to the conformal layer of the second metal and whose negative terminal is connected to the electrode in the half-cell; and
- d. contacting the conformal layer of the second metal with at least a portion of the external surface of the membrane.

In the MMEP process, a cathode half-cell is provided, which can be a fully or partially enclosed volume, cavity or vessel. The half-cell contains an electrode (the cathode) in contact with an electrolyte solution or gel, and is sealed on at least one surface with a charge-selective ion-conducting membrane. Preferably, the electrolyte in the half-cell is maintained at a hydrostatic pressure greater than ambient atmospheric pressure, and the membrane is sufficiently flexible to expand under the influence of this pressure to establish a convex external surface (a “bulge” or “blister”) extending beyond adjacent surfaces of the half-cell to contact work piece. A source of DC electrical power is connected between the work piece (which functions as the anode) and the electrode in the cell (which functions as the cathode). Polishing is accomplished when a portion of the external surface of the ion-conducting membrane is pressed against a portion of the work piece otherwise covered by the low-conductivity solvent, and this interfacial area is moved across the surface of the work piece. In many applications of this process, the work-piece can be held stationary and the membrane moved across its surface, or the half-cell can be held stationary and the work-piece moved, or both the work piece and the half-cell can be in motion, provided that the area of contact is not static. When a suitable voltage is applied between the anode and cathode under these conditions, some of the metal becomes oxidized to form solvated metal ions that migrate across the membrane into the half-cell.
The external surface of the membrane used in the cathode half-cell can be smooth or can be topographically patterned to create a plurality of “lands”, locally projecting substantially flat areas, surrounded by locally recessed channels, which extend to the edges of the contour area. A convenient means to prepare a topographically patterned membrane for use in the invention is to permanently emboss the desired pattern into the surface of a pre-existing smooth membrane. The embossing tool can consist of a screen, grid, mesh, pierced, porous, or woven sheet or expanded lattice composed of metal, glass, polymeric or natural fibers or any other material sufficiently hard to permanently deform the surface of the membrane when the two surfaces are pressed together under a suitable combination of temperature and pressure. The topographic pattern embossed into the membrane surface in this way corresponds to a cast of the embossing tool. In this, or any other operation it is important that no holes or tears occur which would compromise the ability of the membrane to serve as a barrier between the electrolyte solution and low-conductivity fluid.
Suitable membranes are substantially impermeable to the electrolyte in order to maintain the desirably low conductivity of the solvent or solution covering the anode. On the other hand, in order to maintain Faradaic current required for the polishing process, it is desirable that the membrane be permeable by the solvated or complexed metal ions produced in anodic oxidation of the work piece. If the metal ions are positively charged, then the membrane is a cation-conducting membrane. Similarly, under conditions where anodic oxidation produces a complex metal anion, an anion-conducting membrane is used.
Charge-selective ion-conducting membranes are generally solid organic polymers that bear covalently bound ionic functional groups. The bound ions constitute fixed charges that are balanced by unbound, mobile counter-ions of the opposite charge. The latter may diffuse within the membrane or migrate under the influence of an electric field to carry electric current. Small ions in adjacent solutions with the same sign as the mobile counter-ions exchange readily with those in the membrane. By contrast, ions in adjacent solution with the same charge as the fixed ions in the membrane tend to be excluded from such membranes due to electrostatic repulsion. Thus, all charge-selective ion-conducting membranes are more or less impermeable to electrolyte solutions due to exclusion of ions that share the same sign as the fixed charges.
Suitable charge-selective ion-conducting membranes include film-forming ionic polymers that are stable under the conditions of the electropolishing process. Ionic polymers useful as fuel-cell membranes may also be useful in this membrane-mediated electropolishing process. A preferred class of membranes is cation-conducting membranes, especially those formed from polymeric ionomers functionalized with strong acid groups, i.e., acid groups with a pKa of less than 3. Sulfonic acid groups are preferred strong acid groups. Preferred polymeric ionomers are copolymers of fluorinated and/or perfluorinated olefins and monomers containing strong acid groups.
Nafion® perfluorosulfonate ionomer membranes (E.I. du Pont de Nemours, Inc., Wilmington, Del.) are composed of fluorocarbon chains bearing highly acidic sulfonic acid groups. On exposure to water, the acid groups ionize, leaving fixed sulfonate anions and mobile hydrated protons. The protons may be readily exchanged with various metal cations. Such perfluorosulfonate ionomer membranes are particularly well-suited for use in MMEP due to its strong common-ion exclusion, high conductivity, strong acidity, chemical stability and robust mechanical properties. Also, such perfluorosulfonate ionomer membranes can be patterned by common thermoforming techniques.
MMEP polishing of Cu in water in the processes herein is desirably carried out in an acidic environment at the surface of the anode because at pH>4 Cu⁺²precipitates from water as CuO. The membrane material preferably provides the necessary acidic environment to solubilize Cu⁺².
The low-conductivity solvent or solution used in MMEP contacts both the anode and the external surface of the membrane. The solvent (or solution) serves to solvate the metal ions and facilitate their transport through the membrane, and also to limit the anodic dissolution reaction to areas of the work piece in contact with, or in close proximity to the membrane. To so limit the anodic dissolution reaction, the electrical conductivity of the solvent or solution must be low, preferably less than 500 μS/cm, preferably less than 5 μS/cm.
For many typical anode compositions suitable for use in MMEP, corresponding suitable choices for cathode and electrolyte compositions can be found in “Electroplating Engineering Handbook”, 4^thEdition, pp. 100-120, by D. E. Ward, L. J. Durney, Ed., Van Nostrand Co., New York, 1984. The electrolyte is chosen to provide high solubility for the metal ions or coordinated metal ions produced by oxidation of the anode, and must have sufficiently high conductivity to carry current densities up to several hundred mA/cm²without introducing significant voltage drop or heating. A conductivity of at least 100 mS/cm is preferred. The most common electroplating (EP) electrolytes are concentrated aqueous solutions of strong acids.
The cathode can be made from any electrically conductive material that is chemically stable in the electrolyte. During polishing one or more reduction reactions may occur at the cathode. For example, in aqueous acids these may include electrolysis of water to liberate hydrogen and the reduction or plating of metal ions derived from the anode. In order to minimize hydrogen evolution relative to plating, metal salts, e.g., CuSO₄, can be included in the electrolyte. An example of an electrolyte solution useful for MMEP of Cu is 0.5 M CuSO₄in 1.0 M aqueous H₂SO₄.
MMEP can be used to polish various different metals using strong acid electrolytes in a MMEP cell. Differences in the coordination chemistry and solubility of different metal ions may require the use of different electrolytes for different metals. Chloride ion has been found to be effective in maintaining the solubility of Sn⁺²and Al⁺³.
If a source of strong base or cyanide ion is used in the electrolyte or in the low-conductivity solution in an anodic generation of complex metal anions such as Al(OH)₆ ⁻³or Fe(CN)₆ ⁻³, one would need to use an anion-conducting membrane instead of a cation-conducting membrane in the MMEP step.
MMEP can be used with a wide variety of metals and metal alloys. Suitable metals include silver, nickel, cobalt, tin, aluminum, copper, lead, tantalum, titanium, iron, chromium, vanadium, manganese, zinc, zirconium, niobium, molybdenum, ruthenium, rhodium, hafnium, tungsten, rhenium, osmium, iridium, and alloys of these metals, including brass, lead/tin alloys and steel. Preferred metals and alloys include silver, nickel, cobalt, tin, aluminum, copper, lead, brass, steel and alloys of lead/tin.
Once the second metal is removed from the substantially flat areas of the substrate, the exposed portions of the first metallic layer are treated to create a thin dense layer of substantially insoluble, electrically insulating compound on the surface of the conformal layer. The thickness of the thin dense layer is preferably no greater than 20 nm, more preferably less than 5 nm. It is desirable that the thin dense layer be sufficiently thick, dense and defect free to prevent electroplating on the substantially flat areas. Typically, the insulating compound is an oxide of the material of the first metallic layer. For example, when the first metallic layer comprises Ta and/or TaN, an electrically insulating layer of tantalum oxide forms spontaneously when the overlying second metal layer is removed by MMEP and the Ta and/or TaN layer is exposed to oxygen or air. Ta and certain other heavy metals with low oxidation potentials spontaneously form passivating oxide layers when exposed to air and moisture. The oxide layers are effective at preventing further oxidation of the metal and can also prevent or retard electroplating of other metals.
Electroplating can be carried out by any of several processes known in the art. For example, as illustrated in FIG. 6, the barrier layer is the cathode and is connected to the negative terminal of a power supply. The surface of the substrate is in contact with an electroplating solution, and the anode is connected to the positive terminal of the power supply and is in contact with the electroplating solution. The electroplating solution contains a reducible form of the third metal. In one embodiment of this invention, the second metal and the third metal are the same, for example, copper. In such an embodiment, the electroplating solution comprises a soluble form of copper, for example, an aqueous solution of copper sulfate.
When a sufficient voltage is supplied to establish a Faradaic current between the cathode and the anode, a portion of the third metal will be electrodeposited (electroplated) in the recessed features of the substrate. The electrically insulating layer on the first metallic layer prevents the deposition of metal on the flat areas of the substrate.
The present process simplifies the fabrication of electrical interconnects on integrated circuits by eliminating the need to deposit and then subsequently remove large amounts of excess Cu metal. The invention also eliminates the need for Cu CMP steps in fabricating Cu damascene interconnects.

EXAMPLES

Nafion® perfluorosulfonic acid (PFSA) membranes (N112, N115, N117, and NE1135, E. I. DuPont de Nemours and Company, Inc., Wilmington, Del.) were embossed with topographic patterns by pressing against a wire mesh screen at approximately 80° C. and 1000 psi. 200 mm Cu damascene test wafers 854AZ were obtained from Sematech International (2706 Montopolis Drive, Austin, Tex.).
All MMEP processes were performed using an apparatus as follows. The wafer was held facing up on a circular turntable by means of a vacuum chuck. The cathode half-cell with membrane blister facing down was mounted to a low-friction bearing allowing free vertical motion but no horizontal motion. The bearing was mounted on a motorized rail allowing the half-cell to be moved to any radial distance from the center of the work-piece. 80 ml of electrolyte solution (0.5M CuSO₄in 1.0 M H₂SO₄) was continuously re-circulated from a remote reservoir through the half-cell by means of a peristaltic pump (Masterflex #7523-00) connected with PTFE tubing. Hydrostatic pressure Ph was measured by means of a transducer also connected to the half-cell with PTFE tubing. Hydrostatic pressure was adjusted by varying the pumping rate. The contour area was established by lowering the cathode half-cell onto work-piece to the limit of its own weight partially counter-balanced by an adjustable coil spring. Contour area was systematically varied by adjusting the tension on the coil spring. De-ionized water (initial conductivity 0.56 μS/cm) was supplied directly to the surface of the work from the de-ionizing unit (Barnstead Nanopure Infinity) at rate of approximately 2 liters/min. Interface velocity v was determined by the combination of the radial position of the contour area and the angular velocity of the turntable. The voltage was supplied between the cathode and the work piece from a programmable DC power supply (Kepco BOP 20-5D). Electrical contact to the work-piece was provided by a metal ring contact at its outer edge and a set of slip ring contacts on the shaft of the turntable.
MMEP was performed by programming both the angular velocity of the turntable and radial velocity of the half-cell in such a way that the net interface velocity and integrated residence time of the contour area remained nearly constant at all positions on the surface of the work-piece. The step height of topographic features on the work-piece was measured using a mechanical profilometery (KLA-Tencor Alpha-Step 500).

Example 1

Over-Polishing of a Cu Damascene Wafer by MMEP

A Cu damascene test wafer (Sematech 854AZ) was over-polished using MMEP to a point where all excess Cu was removed from plateau areas and the circuit features were dished to the extent than no more than about 200 nm of Cu remained in the recessed areas. (“Over-polishing” is a term of art indicating that the wafer was polished beyond the point where the first area of barrier is exposed.) The electrolyte solution in the cathode half-cell comprised 0.5M CuSO₄in 1.0M aqueous H₂SO₄. The final stage of polishing employed a Nafion®) N117 membrane embossed with a topographic pattern comprising isolated lands 2.4×10⁴cm²separated by continuous channels approximately 50 μm deep. The surface of the wafer was flushed with de-ionized water (˜10 MOhm cm). The interface velocity was held at 10 cm/sec under a hydrostatic pressure of 1.5 psi, while applying 0.1 msec pulses of 6V separated by 0.2 msec intervals producing an interfacial current density of approximately 2 amp/cm².
FIG. 4A shows an optical micrograph of the polished wafer in a region of the test pattern labeled “GC 100 100”, and FIG. 5A shows a profilometry scan across 100 μm circuit lines and spaces located just above the upper edge of the micrograph. From contrasting colors not reproduced in FIG. 4, it is apparent that Cu has been retained in the circuit elements but is completely absent from the surrounding plateau areas. Profilometry (FIG. 5A) shows that the over-polished circuit lines corresponding to region “R” in the scan are recessed by approximately 300 nm below the level of the exposed barrier layer on the plateaus corresponding to region “P” in the scan.

Example 2

Selective Electroplating onto Dished Areas of an Over-Polished Damascene Wafer

The over-polished test wafer from Example 1 was fitted with a simple electroplating apparatus as illustrated schematically in FIG. 6. A cylindrical Pyrex flange joint 9 with 4 cm rubber O-ring 10 was clamped onto the surface of the wafer at a location approximately 5 cm from the center, creating a cell for exposing a 12.5 cm²circular area to electroplating solution. Approximately 50 ml of electrolyte solution 11 comprising 18.6 g CuSO₄.5H₂O, 2.4 g H₂SO₄and 0.5 mg of thiourea in 100 ml of water was poured into the cell. A wire 13 extending from the negative terminal of a galvanostat (Model 173, Princeton Applied Research) was clamped onto the surface of the barrier layer 7 at one edge of the wafer located approximately 4 cm from the outer edge of the flange joint. A Cu anode 12 was suspended in the electrolyte solution above the surface of the wafer and connected to the positive terminal of the power supply. Electroplating was carried out by applying 0.10 amp pulses of current for intervals of 0.5 sec while manually stirring the electrolyte with a pipette until a total of 1 coulomb of charge had been passed.
The wafer was thoroughly rinsed with de-ionized water and dried. A weight increase of 0.6 mg confirmed that plating had occurred.
FIG. 4B shows an optical micrograph of the same test pattern as in FIG. 4A after electroplating. The dashed ellipse in FIGS. 4A and 4B indicates identical areas of the test pattern respectively before and after plating.
As before, color contrast (not shown here) confirms that no Cu has plated onto the exposed barrier surfaces surrounding the circuit features. On the other hand addition of electrodeposited Cu to the circuit features is revealed by a decrease in reflectivity of these surfaces which appear dark grey in FIG. 4B. FIG. 5B shows the profilometry scans for the same series of 100 μm lines and spaces represented in FIG. 5A following electroplating. By reference to the dashed lines, which identify the features R and P before and after plating, it is apparent that circuit lines which were initially dished by 200 nm were increased in thickness by the plating to the extent so that they now extend above the level of the barrier layer by about 250 nm.

Example 3

Effect of MMEP Over-Polishing on Electrical Resistance of Exposed Barrier Layer

Using the MMEP process under conditions similar to Example 2, a Cu damascene test wafer was over-polished to remove all Cu from both plateaus and recessed circuit features so that the entire barrier layer was exposed. The surface of the exposed barrier layer exhibited a bronze colored metallic reflectivity. The sheet resistance was measured to be 20 ohms/square. For comparison, all the Cu was removed from another test wafer of the same initial composition by soaking in a 10% aqueous solution of potassium monopersulfate (Oxone®)). In this case the remaining exposed barrier layer exhibited a silver colored metallic reflectivity and a sheet resistivity of 17 ohms/square.
These examples show that on direct exposure to MMEP, the Ta barrier layer remains continuous and retains sufficiently low electrical resistance to carry the current densities required for electroplating, for example 0.1 amp/cm². They further demonstrate that the loss of Ta due to surface oxidation and/or mechanical caused by MMEP is no more than 15% greater than that which occurs on exposure to purely chemical oxidation.

Claims

1. A process comprising:

a. providing a substrate, wherein a first surface of the substrate comprises substantially flat areas and recessed features;

b. coating the first surface of the substrate with a continuous, conformal first metallic layer;

c. coating the continuous conformal first metallic layer with a conformal layer of a second metal;

d. selectively removing substantially all of the second metal from the substantially flat areas using membrane-mediated electropolishing to expose the first metallic layer in the substantially flat areas, while leaving the recessed areas substantially covered by the second metal;

e. creating a layer of a substantially insoluble, electrically insulating compound on the exposed surfaces of the conformal layer of the first metallic layer, while leaving intact a sufficient portion of the first metallic layer to carry electrical current to all recessed features on the substrate surface; and

f. electroplating a conformal layer of a third metal onto the second metal layer in the recessed features.

2. The process of claim 1, wherein the first metallic layer comprises at least one material selected from Ta and TaN.

3. The process of claim 1, wherein the second metal comprises Cu.

4. The process of claim 1, wherein the third metal comprises Cu.

5. The process of claim 1, wherein the first metallic layer comprises Ta and the substantially insoluble, electrically insulating layer comprises an oxide of Ta.

6. The process of claim 1, wherein the substrate is a silicon wafer.

7. The process of claim 1, wherein coating the first metallic layer on the substrate is conducted by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

8. The process of claim 1, wherein coating the second metal on the first metallic layer is conducted by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

9. The process of claim 1, wherein the membrane-mediated electropolishing comprises:

a. providing a cathode half-cell comprising:

1. a fully or partially enclosed volume, cavity or vessel;

2. an electrolyte solution or gel which partially or essentially fills the enclosed volume, cavity or vessel;

3. an electrode in contact with the electrolyte solution or gel;

4. a means for electrically connecting the electrode to a DC power source; and

5. a charge-selective ion-conducting membrane which seals one surface of the enclosed volume, cavity or vessel in such a way that the internal surface of said membrane contacts the electrolyte solution or gel and the external surface is accessible to contact the conformal layer of the second metal and a low-conductivity solvent or solution;

b. substantially covering the conformal layer of the second metal with the low-conductivity solvent or solution;

c. providing a source of DC electrical power whose positive terminal is connected to the conformal layer of the second metal and whose negative terminal is connected to the electrode in the half-cell; and

d. contacting the conformal layer of the second metal with at least a portion of the external surface of the membrane.

10. The process of claim 9, wherein the membrane is a perfluorosulfonate ionomer membrane.