US20080042265A1 - Chip scale module package in bga semiconductor package - Google Patents

Chip scale module package in bga semiconductor package Download PDF

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Publication number
US20080042265A1
US20080042265A1 US11/464,699 US46469906A US2008042265A1 US 20080042265 A1 US20080042265 A1 US 20080042265A1 US 46469906 A US46469906 A US 46469906A US 2008042265 A1 US2008042265 A1 US 2008042265A1
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Prior art keywords
semiconductor package
csmp
package
substrate
ipd
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Abandoned
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US11/464,699
Inventor
Leo A. Merilo
Emmanuel A. Espiritu
Dario S. Filoteo
Rachel L. Abinan
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Priority to US11/464,699 priority Critical patent/US20080042265A1/en
Assigned to STATS CHIPPAC, LTD. reassignment STATS CHIPPAC, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ABINAN, RACHEL L., ESPIRITU, EMMANUEL A., FILOTEO, JR., DARIO S., MERILO, LEO A.
Publication of US20080042265A1 publication Critical patent/US20080042265A1/en
Priority to US12/882,728 priority patent/US9281300B2/en
Abandoned legal-status Critical Current

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    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present invention relates in general to semiconductor devices and, more particularly, to multi-chip semiconductor packages that have stacked dies.
  • Chips are used not only in very sophisticated industrial and commercial electronic equipment, but also in many household and consumer items such as televisions, clothes washers and dryers, radios, and telephones. As products become smaller but more functional, there is a need to include more chips in the smaller products to perform the functionality.
  • the reduction in size of cellular telephones is one example of how more and more capabilities are incorporated into smaller and smaller electronic products.
  • MCM structures have been developed to meet the demand.
  • MCM structures have a number of dies and other semiconductor components mounted within a single semiconductor package.
  • the number of dies and other components can be mounted in a vertical manner, a lateral manner, or combinations thereof.
  • stacked-die packages offer a number of advantages that relate to the manufacturing of the package, such as ease of handling and assembly.
  • the dies are wire-bonded sequentially, typically with automated wire-bonding equipment employing well-known thermal compression or ultrasonic wire-bonding techniques.
  • the head of a wire-bonding apparatus applies a downward pressure on a conductive wire held in contact with a wire-bonding pad on the die to weld, or bond, the wire to the bonding pad on the die.
  • stacked-die semiconductors can be fabricated faster and more cheaply than several semiconductors, each having a single die, which perform the same functions.
  • a stacked-die approach is advantageous because of the increase in circuit density achieved.
  • the present invention is a semiconductor package, comprising a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array substrate, and an application die attached to the integrated passive device.
  • BGA ball grid array
  • CSMP flip chip chip scale module package
  • IPD integrated passive device
  • the present invention is a method of manufacturing a semiconductor package, comprising providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array substrate, and attaching an application die to the integrated passive device.
  • BGA ball grid array
  • CSMP flip chip chip scale module package
  • IPD integrated passive device
  • the present invention is a semiconductor package, comprising a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the cavity of the thermally-enhanced substrate, and an application die attached to the integrated passive device.
  • CSMP flip chip chip scale module package
  • IPD integrated passive device
  • the present invention is a method of manufacturing a semiconductor package, comprising providing a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the cavity of the thermally-enhanced substrate, and attaching an application die to the integrated passive device.
  • CSMP flip chip chip scale module package
  • IPD integrated passive device
  • the present invention is a semiconductor package, comprising a ball grid array (BGA) substrate having integrated metal circuitry, a wafer level chip scale package (WLCSP) attached to the ball grid array (BGA) substrate, the wafer level chip scale package having a first integrated passive device (IPD), and an application die attached to the integrated passive device (IPD).
  • BGA ball grid array
  • WLCSP wafer level chip scale package
  • IPD first integrated passive device
  • IPD integrated passive device
  • FIG. 1 a illustrates an example prior art “Known Good Unit” flip chip chip scale module package (CSMP);
  • FIG. 1 b illustrates an example prior art ball grid array (BGA) package
  • FIG. 2 illustrates an example embodiment of a semiconductor package having an incorporated ball grid array (BGA) package together with a “Known Good Unit” (KGU) flip chip chip scale module package (CSMP);
  • BGA ball grid array
  • KGU known Good Unit flip chip chip scale module package
  • FIG. 3 a illustrates an example embodiment of a semiconductor package having an incorporated BGA package together with a KGU flip chip CSMP in a land grid array (LGA) configuration;
  • FIG. 3 b illustrates an example embodiment of a semiconductor package having an incorporated BGA package together with a KGU flip chip CSMP in a ball grid array (BGA) configuration;
  • FIG. 3 c illustrates an example embodiment of a semiconductor package having an incorporated BGA package together with a KGU flip chip CSMP having an additional external pad and bond finger configuration;
  • FIG. 4 a illustrates a first step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c;
  • FIG. 4 b illustrates a first option of a second step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c;
  • FIG. 4 c illustrates a second option of a second step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c;
  • FIG. 4 d illustrates a third step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c;
  • FIG. 4 e illustrates a fourth step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c;
  • FIG. 4 f illustrates a fifth step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c;
  • FIG. 4 g illustrates a sixth step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c;
  • FIG. 5 a illustrates an example prior art “Known Good Unit” flip chip chip scale module package (CSMP);
  • FIG. 5 b illustrates an example prior art thermally-enhanced package
  • FIG. 6 illustrates an example embodiment of a semiconductor package having an incorporated KGU flip chip CSMP together with a thermally-enhanced package
  • FIG. 7 a illustrates a first step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 7 b illustrates a second step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 7 c illustrates a third step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 7 d illustrates a fourth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 7 e illustrates a fifth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 7 f illustrates a sixth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 7 g illustrates a seventh step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 7 h illustrates a eighth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 ;
  • FIG. 8 a illustrates an example prior art “Known Good” wafer level chip scale package/chip scale module package (WLCSP-CSMP);
  • FIG. 8 b illustrates an example prior art ball grid array (BGA) package
  • FIG. 9 illustrates an example embodiment of a semiconductor package having an incorporated ball grid array (BGA) package together with a “Known Good Unit” (KGU) WLCSP-CSMP package.
  • BGA ball grid array
  • KGU known Good Unit
  • the chip scale module package (CSMP) has been implemented.
  • the present invention utilizes the CSMP to incorporate the CSMP into a standard ball grid array (BGA) semiconductor package to provide increased functionality and a smaller package footprint.
  • BGA ball grid array
  • FIG. 1 a an example prior art “Known Good Unit” (KGU) flip chip CSMP package 10 is depicted.
  • Package 10 includes a substrate which is connected to an integrated passive device (IPD).
  • IPD integrated passive device
  • the IPD uses a solder interconnect to connect with an integrated semiconductor die.
  • Chip scale module packaging is an advanced system-in-package (SiP) which features a modular architecture that integrates mixed integrated circuit (IC) technologies and a wide variety of integrated passive devices such as resistors, capacitors, inductors, filters, BALUNs and interconnects directly onto the silicon substrate.
  • SiP system-in-package
  • FIG. 1 b depicts an example prior art ball grid array (BGA) package 12 .
  • Package 12 includes a substrate with integrated metal circuitry connected to an array of solder balls.
  • a die is wirebonded to the substrate, and enclosed with an encapsulant for protection.
  • FIG. 2 illustrates an example embodiment of a semiconductor package 14 according to the present invention.
  • Package 14 incorporates a modified BGA package 12 with a modified KGU flip chip CSMP package 16 .
  • Package 16 can include either a land grid array (LGA) or a ball grid array (BGA) type configuration.
  • Package 16 includes a flip chip die 18 which is incorporated into package 16 as shown.
  • a first application die 20 such as an integrated circuit (IC) or an integrated passive device (IPD) as previously described is also incorporated into the package 16 .
  • An adhesive material 21 bonds a second application die 22 to the top surface of die 20 as depicted.
  • Dies 20 , 22 can be a combination IC/IC, IPD/IPD, or a combination of both IC/IPD.
  • additional application dies can be mounted to die 22 in any desired IC/IPD configuration to fulfill a specific need.
  • An underfill material 24 is disposed between die 18 and die 20 to provide structural support.
  • Package 16 is attached on the BGA substrate 28 by a solder paste, flux, or adhesive material at bump pad 26 .
  • the application die 22 can use wirebond 30 to connect the wire bond pad 32 of die 22 with the BGA metal layer circuitry and/or bond fingers 34 .
  • application die 22 can utilize wirebond 36 to connect the wire bond pad 38 to external bond pads and/or bond fingers 40 located on package 16 .
  • An encapsulant 42 is formed over package 16 to provide structural support to package 16 within overall package 14 .
  • Package 14 can be constructed utilizing standard molding or TOP mold gate techniques. By combining CSMP package 16 and BGA package 12 into package 14 , package 14 can take advantage of the positive aspects of each package to provide enhanced device functionality for applications such as wireless local area networks (WLAN), Bluetooth or similar application specific integrated circuits (ASIC), digital signal processing (DSP), memory applications, gate arrays, PC chipsets, and the like. In addition, package 14 can achieve passive function integration through the use of integrated passive devices (IPDs) which are incorporated on the CSMP module 16 without the use of a standard external passive component.
  • IPDs integrated passive devices
  • FIG. 3 a an example embodiment of a semiconductor package 14 having an incorporated modified BGA package together with a modified KGU flip chip CSMP utilizing an additional external pad and bond finger configuration is illustrated.
  • Package 14 includes components as illustrated in FIG. 2 , such as flip chip die 18 , first application die 20 , second application die 22 , underfill material 24 , BGA substrate 28 with incorporated metal circuitry, wire bonding 30 , 36 and bond pads 32 , 34 , 38 , and 40 .
  • An encapsulant 42 is again disposed over the application dies 20 , 22 to provide structural support.
  • interconnectivity from the flip chip CSMP external pads to pads located on the BGA substrate 28 is provided at junction 44 using solder paste or a conductive epoxy.
  • FIG. 3 b illustrates an example embodiment of a semiconductor package 14 having an incorporated modified BGA package together with a modified KGU flip chip CSMP in a ball grid array (BGA) configuration.
  • package 14 includes many of the same subcomponents as illustrated. Interconnectivity from the flip CSMP solder balls to the BGA bump pads are provided along junction 44 using solder paste, flux, or a conductive epoxy.
  • package 14 makes use of a grounded flip chip die 48 in place of flip chip die 18 for enhanced thermal performance.
  • FIG. 3 c illustrates an example embodiment of a semiconductor package 14 having an incorporated modified BGA package together with a KGU flip chip CSMP having an additional external pad 50 and bond finger configuration. Interconnectivity from the flip chip CSMP to the BGA substrate is provided using conventional wire bonding. As such, an additional wire bonding 46 is shown connecting external bond pad 50 to bond pad 34 .
  • FIG. 4 a depicts a first step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c .
  • a BGA substrate 28 having incorporated metal circuitry is provided.
  • solder flux, solder paste, or conductive epoxy is disposed over the substrate 28 at junction 44 , to provide interconnectivity between BGA bump pads and the CSMP package.
  • a thermal/conductive adhesive material 52 is also disposed over substrate 28 as depicted to promote adhesion. If a grounded flip chip die 48 is utilized, the use of material 52 is optional.
  • FIG. 4 b illustrates a first option of a second step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c .
  • the option depicted in the present embodiment reflects the use of a land grid array-configured flip chip CSMP 10 which is attached to BGA substrate 28 at junction 44 .
  • FIG. 4 c illustrates the second option of the second step in the example method, reflecting the use of a ball grid array-configured flip chip CSMP 10 which is attached to the BGA substrate 28 .
  • FIG. 4 d illustrates a third step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2 , 3 a , 3 b , or 3 c .
  • a film or adhesive mount 21 is disposed on the backside surface of IPD 20 as shown.
  • FIG. 4 e illustrating a fourth step in the method, depicts the attachment of a second application die 22 to the film 21 as shown.
  • FIG. 4 f depicts the various wire bonding which provides interconnectivity between bond pads 32 , 38 located as part of application die 22 and external bond pads/fingers 34 , 40 on the CSMP package and BGA substrate as depicted.
  • the dies and wirebonding are overmolded with the encapsulant 42 as shown in FIG. 4 g.
  • a modified KGU flip chip CSMP can be incorporated in a modified thermally-enhanced package for a particular application.
  • FIG. 5 a again illustrates an example prior art “Known Good Unit” (KGU) flip chip chip scale module package (CSMP) 10 which is used in applications such as WLAN, Bluetooth, GPS, switches, and the like.
  • FIG. 5 b refers to an example prior art thermally-enhanced semiconductor package 54 used in applications featuring application specific integrated circuits (ASICs), digital signal processing (DSP), microprocessors and controllers, chipsets, or other various applications requiring enhanced thermal performance.
  • ASICs application specific integrated circuits
  • DSP digital signal processing
  • microprocessors and controllers chipsets, or other various applications requiring enhanced thermal performance.
  • FIG. 6 refers to a semiconductor package 56 having a thermally-enhanced substrate 57 which has been adapted for a modified KGU flip chip CSMP package 58 .
  • An IPD 60 , or IC 60 is integrated into the CSMP package 58 .
  • the flip chip CSMP package 58 is attached to substrate 57 .
  • Substrate 57 includes a heat sink structure 70 and an integrated cavity 59 , as well as metal circuitry incorporated into the substrate 57 to conduct electricity.
  • Package 58 is attached in the cavity by an adhesive material or film 62 which can be thermal or conductive.
  • a high thermal flip chip 64 is incorporated into package 56 as depicted and bonded to the cavity 59 using adhesive 62 .
  • An additional die 66 which can include an IC or additional IPD is mounted with adhesive 62 to die 60 .
  • dies 60 , 66 can include any combination of IC/IC, IPD/IPD, IC/IPD, or IPD/IC.
  • Additional dies (IC or IPD) can be mounted to the top surface of die 66 using a similar approach with adhesive 62 .
  • An underfill/encapsulant material 63 is utilized between dies 60 , 64 to provide structural support.
  • an encapsulant or mold compound 68 is disposed over package 58 to provide structural support to dies 60 , 66 within package 58 and the overall package 56 .
  • Wire bonding can be incorporated into package 56 as follows.
  • Wire bonds 72 provide electrical interconnectivity between bond pads 74 located on die 66 and bond pads 76 located as part of the modified thermally-enhanced package.
  • Wire bonds 76 provide electrical connectivity between pads 80 , also on die 66 , and pads 82 , located externally on CSMP package 58 .
  • wire bonds 84 provide connectivity between pads 86 located as part of the modified thermally-enhanced substrate 57 and pads 88 located externally on modified CSMP package 58 .
  • solder balls 90 provide electrical connectivity to external electrical circuitry as depicted.
  • FIG. 7 a illustrates a first step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6 .
  • a modified thermally-enhanced substrate 57 is provided, the substrate 57 having a heat sink 70 with an integrated cavity 59 again as shown to accommodate package 58 .
  • Film or adhesive material 62 is disposed on the thermally-enhanced substrate 57 as shown.
  • a KGU flip chip CSMP 58 is attached to the material 62 .
  • FIG. 7 c depicts underfill material 63 disposed between dies 60 , 64 .
  • FIG. 7 d depicts the following step of applying a film/adhesive material 62 on the top surface of die 60 , where FIG. 7 e shows die 66 attached to die 60 as a next step.
  • FIG. 7 f the various wirebonding as previously described takes place as shown in FIG. 7 f .
  • Package 58 with dies 60 , 64 is then encapsulated/overmolded with encapsulant 68 as depicted in FIG. 7 g .
  • FIG. 7 h depicts solder balls 90 attached to the modified thermally-enhanced substrate 57 to provide connectivity to external circuitry.
  • a “Known Good” wafer level chip scale package/chip scale module package can be modified to be incorporated into a modified ball grid array (BGA) package to perform specific functionality for a particular application.
  • FIG. 8 a illustrates an example prior art “Known Good” wafer level chip scale package/chip scale module package 92 (WLCSP-CSMP).
  • FIG. 8 b illustrates an example prior art ball grid array (BGA) package 12 .
  • FIG. 9 illustrates an example embodiment of a semiconductor package 94 having an incorporated modified ball grid array (BGA) package 12 together with a modified KGU WLCSP-CSMP package.
  • the WLCSP-CSMP is attached on the BGA substrate 28 by an adhesive material, solder paste, or flux-reflow material.
  • An additional application die 98 is disposed at the backside of the IPD die 92 by using adhesive material 100 .
  • Additional dies 92 can be stacked on die 92 depending upon the application.
  • dies 92 can include ICs, IPDs, or any combination thereof.
  • Connectivity of the modified WLCSP-CSMP to the BGA substrate 28 can be performed by wirebonds 102 connecting bond pads 104 located as part of die 98 to pads 106 connected to metal circuitry incorporated into BGA substrate 28 . Additionally, junction 96 provides electrical connectivity between solder balls of the modified WLCSP-CSMP and additional pads 106 also connected to metal circuitry of the BGA substrate 28 .
  • Package 94 can be constructed using standard molding or TOP mold gate techniques.
  • the package 94 provides enhanced device functionality due to combining favorable aspects of the WLCSP-CSMP and BGA package designs for applications such as WLAN, Bluetooth, DSP, chipsets, and a host of related applications.
  • Package 94 adds passive function integration through the use of IPDs 98 as application dies 98 which are incorporated on the modified CSMP module as previously depicted without the requirement of using a standard external passive component.
  • packages such as package 94 , package 56 , and package 14 provides enhanced functionality and serves to take advantage of positive aspects of older designs which are modified to create the packages 94 , 56 , and 14 .

Abstract

A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate, and an application die attached to the integrated passive device (IPD). A method of manufacturing a semiconductor package includes providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate, and attaching an application die to the integrated passive device (IPD).

Description

    FIELD OF THE INVENTION
  • The present invention relates in general to semiconductor devices and, more particularly, to multi-chip semiconductor packages that have stacked dies.
    • BACKGROUND OF THE INVENTION
  • Semiconductors, or computer chips, are found in virtually every electrical product manufactured today. Chips are used not only in very sophisticated industrial and commercial electronic equipment, but also in many household and consumer items such as televisions, clothes washers and dryers, radios, and telephones. As products become smaller but more functional, there is a need to include more chips in the smaller products to perform the functionality. The reduction in size of cellular telephones is one example of how more and more capabilities are incorporated into smaller and smaller electronic products.
  • As the demand for semiconductor devices with low-cost, high performance, increased miniaturization, and greater packaging densities has increased, Multi-Chip Module (MCM) structures have been developed to meet the demand. MCM structures have a number of dies and other semiconductor components mounted within a single semiconductor package. The number of dies and other components can be mounted in a vertical manner, a lateral manner, or combinations thereof.
  • One such approach is to stack one die on top of another and then enclose the stack of dies in one package. The final package for a semiconductor with stacked dies is much smaller than would result if the dies were each packaged separately. In addition to providing a smaller size, stacked-die packages offer a number of advantages that relate to the manufacturing of the package, such as ease of handling and assembly.
  • In a stacked-die arrangement, the dies are wire-bonded sequentially, typically with automated wire-bonding equipment employing well-known thermal compression or ultrasonic wire-bonding techniques. During the wire-bonding process, the head of a wire-bonding apparatus applies a downward pressure on a conductive wire held in contact with a wire-bonding pad on the die to weld, or bond, the wire to the bonding pad on the die.
  • In many cases, stacked-die semiconductors can be fabricated faster and more cheaply than several semiconductors, each having a single die, which perform the same functions. A stacked-die approach is advantageous because of the increase in circuit density achieved.
  • A variety of semiconductor package configurations having stacked die arrangements are found in the art. However, the configurations currently known could stand to benefit from additional flexibility of implementing subcomponents such as integrated circuits (ICs) and integrated passive devices (IPDs) which can include resistors, capacitors, inductors, filters, and BALUNs. Accordingly, a need exists for a semiconductor package with such increased functionality. Additionally, a need exists for a semiconductor package which promotes higher performance while providing lower cost and a smaller footprint.
    • SUMMARY OF THE INVENTION
  • In one embodiment, the present invention is a semiconductor package, comprising a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array substrate, and an application die attached to the integrated passive device.
  • In another embodiment, the present invention is a method of manufacturing a semiconductor package, comprising providing a ball grid array (BGA) substrate having integrated metal layer circuitry, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array substrate, and attaching an application die to the integrated passive device.
  • In another embodiment, the present invention is a semiconductor package, comprising a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the cavity of the thermally-enhanced substrate, and an application die attached to the integrated passive device.
  • In still another embodiment, the present invention is a method of manufacturing a semiconductor package, comprising providing a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity, attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the cavity of the thermally-enhanced substrate, and attaching an application die to the integrated passive device.
  • In still another embodiment, the present invention is a semiconductor package, comprising a ball grid array (BGA) substrate having integrated metal circuitry, a wafer level chip scale package (WLCSP) attached to the ball grid array (BGA) substrate, the wafer level chip scale package having a first integrated passive device (IPD), and an application die attached to the integrated passive device (IPD).
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 a illustrates an example prior art “Known Good Unit” flip chip chip scale module package (CSMP);
  • FIG. 1 b illustrates an example prior art ball grid array (BGA) package;
  • FIG. 2 illustrates an example embodiment of a semiconductor package having an incorporated ball grid array (BGA) package together with a “Known Good Unit” (KGU) flip chip chip scale module package (CSMP);
  • FIG. 3 a illustrates an example embodiment of a semiconductor package having an incorporated BGA package together with a KGU flip chip CSMP in a land grid array (LGA) configuration;
  • FIG. 3 b illustrates an example embodiment of a semiconductor package having an incorporated BGA package together with a KGU flip chip CSMP in a ball grid array (BGA) configuration;
  • FIG. 3 c illustrates an example embodiment of a semiconductor package having an incorporated BGA package together with a KGU flip chip CSMP having an additional external pad and bond finger configuration;
  • FIG. 4 a illustrates a first step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c;
  • FIG. 4 b illustrates a first option of a second step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c;
  • FIG. 4 c illustrates a second option of a second step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c;
  • FIG. 4 d illustrates a third step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c;
  • FIG. 4 e illustrates a fourth step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c;
  • FIG. 4 f illustrates a fifth step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c;
  • FIG. 4 g illustrates a sixth step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c;
  • FIG. 5 a illustrates an example prior art “Known Good Unit” flip chip chip scale module package (CSMP);
  • FIG. 5 b illustrates an example prior art thermally-enhanced package;
  • FIG. 6 illustrates an example embodiment of a semiconductor package having an incorporated KGU flip chip CSMP together with a thermally-enhanced package;
  • FIG. 7 a illustrates a first step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 7 b illustrates a second step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 7 c illustrates a third step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 7 d illustrates a fourth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 7 e illustrates a fifth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 7 f illustrates a sixth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 7 g illustrates a seventh step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 7 h illustrates a eighth step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6;
  • FIG. 8 a illustrates an example prior art “Known Good” wafer level chip scale package/chip scale module package (WLCSP-CSMP);
  • FIG. 8 b illustrates an example prior art ball grid array (BGA) package; and
  • FIG. 9 illustrates an example embodiment of a semiconductor package having an incorporated ball grid array (BGA) package together with a “Known Good Unit” (KGU) WLCSP-CSMP package.
    •  DETAILED DESCRIPTION OF THE DRAWINGS
  • The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
  • Current semiconductor packaging trends toward delivering towards low cost, smaller size, and higher performance. To help achieve lower cost and smaller size packages with higher performance, the chip scale module package (CSMP) has been implemented. The present invention utilizes the CSMP to incorporate the CSMP into a standard ball grid array (BGA) semiconductor package to provide increased functionality and a smaller package footprint.
  • Turning to FIG. 1 a, an example prior art “Known Good Unit” (KGU) flip chip CSMP package 10 is depicted. Package 10 includes a substrate which is connected to an integrated passive device (IPD). The IPD uses a solder interconnect to connect with an integrated semiconductor die.
  • Chip scale module packaging is an advanced system-in-package (SiP) which features a modular architecture that integrates mixed integrated circuit (IC) technologies and a wide variety of integrated passive devices such as resistors, capacitors, inductors, filters, BALUNs and interconnects directly onto the silicon substrate.
  • FIG. 1 b depicts an example prior art ball grid array (BGA) package 12. Package 12 includes a substrate with integrated metal circuitry connected to an array of solder balls. A die is wirebonded to the substrate, and enclosed with an encapsulant for protection.
  • FIG. 2 illustrates an example embodiment of a semiconductor package 14 according to the present invention. Package 14 incorporates a modified BGA package 12 with a modified KGU flip chip CSMP package 16. Package 16 can include either a land grid array (LGA) or a ball grid array (BGA) type configuration. Package 16 includes a flip chip die 18 which is incorporated into package 16 as shown. A first application die 20 such as an integrated circuit (IC) or an integrated passive device (IPD) as previously described is also incorporated into the package 16. An adhesive material 21 bonds a second application die 22 to the top surface of die 20 as depicted. Dies 20, 22 can be a combination IC/IC, IPD/IPD, or a combination of both IC/IPD. Moreover, additional application dies can be mounted to die 22 in any desired IC/IPD configuration to fulfill a specific need. An underfill material 24 is disposed between die 18 and die 20 to provide structural support.
  • Package 16 is attached on the BGA substrate 28 by a solder paste, flux, or adhesive material at bump pad 26. To provide connectivity, the application die 22 can use wirebond 30 to connect the wire bond pad 32 of die 22 with the BGA metal layer circuitry and/or bond fingers 34. Similarly, application die 22 can utilize wirebond 36 to connect the wire bond pad 38 to external bond pads and/or bond fingers 40 located on package 16. An encapsulant 42 is formed over package 16 to provide structural support to package 16 within overall package 14.
  • Package 14 can be constructed utilizing standard molding or TOP mold gate techniques. By combining CSMP package 16 and BGA package 12 into package 14, package 14 can take advantage of the positive aspects of each package to provide enhanced device functionality for applications such as wireless local area networks (WLAN), Bluetooth or similar application specific integrated circuits (ASIC), digital signal processing (DSP), memory applications, gate arrays, PC chipsets, and the like. In addition, package 14 can achieve passive function integration through the use of integrated passive devices (IPDs) which are incorporated on the CSMP module 16 without the use of a standard external passive component.
  • Turning to FIG. 3 a, an example embodiment of a semiconductor package 14 having an incorporated modified BGA package together with a modified KGU flip chip CSMP utilizing an additional external pad and bond finger configuration is illustrated. Package 14 includes components as illustrated in FIG. 2, such as flip chip die 18, first application die 20, second application die 22, underfill material 24, BGA substrate 28 with incorporated metal circuitry, wire bonding 30, 36 and bond pads 32, 34, 38, and 40. An encapsulant 42 is again disposed over the application dies 20, 22 to provide structural support.
  • In the depicted embodiment, interconnectivity from the flip chip CSMP external pads to pads located on the BGA substrate 28 is provided at junction 44 using solder paste or a conductive epoxy.
  • FIG. 3 b illustrates an example embodiment of a semiconductor package 14 having an incorporated modified BGA package together with a modified KGU flip chip CSMP in a ball grid array (BGA) configuration. Here again, package 14 includes many of the same subcomponents as illustrated. Interconnectivity from the flip CSMP solder balls to the BGA bump pads are provided along junction 44 using solder paste, flux, or a conductive epoxy. In the depicted embodiment, package 14 makes use of a grounded flip chip die 48 in place of flip chip die 18 for enhanced thermal performance.
  • FIG. 3 c illustrates an example embodiment of a semiconductor package 14 having an incorporated modified BGA package together with a KGU flip chip CSMP having an additional external pad 50 and bond finger configuration. Interconnectivity from the flip chip CSMP to the BGA substrate is provided using conventional wire bonding. As such, an additional wire bonding 46 is shown connecting external bond pad 50 to bond pad 34.
  • FIG. 4 a depicts a first step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c. A BGA substrate 28 having incorporated metal circuitry is provided. Depending on the configuration, as previously described, solder flux, solder paste, or conductive epoxy is disposed over the substrate 28 at junction 44, to provide interconnectivity between BGA bump pads and the CSMP package. A thermal/conductive adhesive material 52 is also disposed over substrate 28 as depicted to promote adhesion. If a grounded flip chip die 48 is utilized, the use of material 52 is optional.
  • FIG. 4 b illustrates a first option of a second step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c. The option depicted in the present embodiment reflects the use of a land grid array-configured flip chip CSMP 10 which is attached to BGA substrate 28 at junction 44. Similarly, FIG. 4 c illustrates the second option of the second step in the example method, reflecting the use of a ball grid array-configured flip chip CSMP 10 which is attached to the BGA substrate 28.
  • FIG. 4 d illustrates a third step in an example method of manufacturing a semiconductor package as illustrated in FIGS. 2, 3 a, 3 b, or 3 c. A film or adhesive mount 21 is disposed on the backside surface of IPD 20 as shown. FIG. 4 e, illustrating a fourth step in the method, depicts the attachment of a second application die 22 to the film 21 as shown.
  • In the fifth step of the method, FIG. 4 f depicts the various wire bonding which provides interconnectivity between bond pads 32, 38 located as part of application die 22 and external bond pads/ fingers 34, 40 on the CSMP package and BGA substrate as depicted. As a sixth step, the dies and wirebonding are overmolded with the encapsulant 42 as shown in FIG. 4 g.
  • In an additional embodiment, a modified KGU flip chip CSMP can be incorporated in a modified thermally-enhanced package for a particular application. For purposes of conception, FIG. 5 a again illustrates an example prior art “Known Good Unit” (KGU) flip chip chip scale module package (CSMP) 10 which is used in applications such as WLAN, Bluetooth, GPS, switches, and the like. FIG. 5 b refers to an example prior art thermally-enhanced semiconductor package 54 used in applications featuring application specific integrated circuits (ASICs), digital signal processing (DSP), microprocessors and controllers, chipsets, or other various applications requiring enhanced thermal performance.
  • FIG. 6 refers to a semiconductor package 56 having a thermally-enhanced substrate 57 which has been adapted for a modified KGU flip chip CSMP package 58. An IPD 60, or IC 60 is integrated into the CSMP package 58. The flip chip CSMP package 58 is attached to substrate 57. Substrate 57 includes a heat sink structure 70 and an integrated cavity 59, as well as metal circuitry incorporated into the substrate 57 to conduct electricity. Package 58 is attached in the cavity by an adhesive material or film 62 which can be thermal or conductive. A high thermal flip chip 64 is incorporated into package 56 as depicted and bonded to the cavity 59 using adhesive 62. An additional die 66, which can include an IC or additional IPD is mounted with adhesive 62 to die 60. Again, as before, dies 60, 66 can include any combination of IC/IC, IPD/IPD, IC/IPD, or IPD/IC. Additional dies (IC or IPD) can be mounted to the top surface of die 66 using a similar approach with adhesive 62. An underfill/encapsulant material 63 is utilized between dies 60, 64 to provide structural support. Similarly, an encapsulant or mold compound 68 is disposed over package 58 to provide structural support to dies 60, 66 within package 58 and the overall package 56.
  • Wire bonding can be incorporated into package 56 as follows. Wire bonds 72 provide electrical interconnectivity between bond pads 74 located on die 66 and bond pads 76 located as part of the modified thermally-enhanced package. Wire bonds 76 provide electrical connectivity between pads 80, also on die 66, and pads 82, located externally on CSMP package 58. Similarly, wire bonds 84 provide connectivity between pads 86 located as part of the modified thermally-enhanced substrate 57 and pads 88 located externally on modified CSMP package 58. Finally, solder balls 90 provide electrical connectivity to external electrical circuitry as depicted.
  • FIG. 7 a illustrates a first step in an example method of manufacturing a semiconductor package as illustrated in FIG. 6. A modified thermally-enhanced substrate 57 is provided, the substrate 57 having a heat sink 70 with an integrated cavity 59 again as shown to accommodate package 58. Film or adhesive material 62 is disposed on the thermally-enhanced substrate 57 as shown. In FIG. 7 b, a KGU flip chip CSMP 58 is attached to the material 62. As a next step, FIG. 7 c depicts underfill material 63 disposed between dies 60, 64. FIG. 7 d depicts the following step of applying a film/adhesive material 62 on the top surface of die 60, where FIG. 7 e shows die 66 attached to die 60 as a next step.
  • As a next step, the various wirebonding as previously described takes place as shown in FIG. 7 f. Package 58 with dies 60, 64 is then encapsulated/overmolded with encapsulant 68 as depicted in FIG. 7 g. As a next step, FIG. 7 h depicts solder balls 90 attached to the modified thermally-enhanced substrate 57 to provide connectivity to external circuitry.
  • In an additional embodiment, a “Known Good” wafer level chip scale package/chip scale module package (WLCSP-CSMP) can be modified to be incorporated into a modified ball grid array (BGA) package to perform specific functionality for a particular application. Again, for purposes of conceptual illustration, FIG. 8 a illustrates an example prior art “Known Good” wafer level chip scale package/chip scale module package 92 (WLCSP-CSMP). FIG. 8 b illustrates an example prior art ball grid array (BGA) package 12.
  • FIG. 9 illustrates an example embodiment of a semiconductor package 94 having an incorporated modified ball grid array (BGA) package 12 together with a modified KGU WLCSP-CSMP package. The WLCSP-CSMP is attached on the BGA substrate 28 by an adhesive material, solder paste, or flux-reflow material. An additional application die 98 is disposed at the backside of the IPD die 92 by using adhesive material 100. Additional dies 92 can be stacked on die 92 depending upon the application. Here, as before, dies 92 can include ICs, IPDs, or any combination thereof.
  • Connectivity of the modified WLCSP-CSMP to the BGA substrate 28 can be performed by wirebonds 102 connecting bond pads 104 located as part of die 98 to pads 106 connected to metal circuitry incorporated into BGA substrate 28. Additionally, junction 96 provides electrical connectivity between solder balls of the modified WLCSP-CSMP and additional pads 106 also connected to metal circuitry of the BGA substrate 28.
  • Package 94 can be constructed using standard molding or TOP mold gate techniques. The package 94 provides enhanced device functionality due to combining favorable aspects of the WLCSP-CSMP and BGA package designs for applications such as WLAN, Bluetooth, DSP, chipsets, and a host of related applications.
  • Package 94 adds passive function integration through the use of IPDs 98 as application dies 98 which are incorporated on the modified CSMP module as previously depicted without the requirement of using a standard external passive component.
  • In summary, the use of packages such as package 94, package 56, and package 14 provides enhanced functionality and serves to take advantage of positive aspects of older designs which are modified to create the packages 94, 56, and 14.
  • While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (43)

1. A semiconductor package comprising:
a ball grid array (BGA) substrate having integrated metal layer circuitry;
a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the ball grid array (BGA) substrate; and
an application die attached to the integrated passive device (IPD).
2. The semiconductor package of claim 1, wherein the flip chip CSMP is attached to the BGA substrate using an adhesive material.
3. The semiconductor package of claim 2, wherein the adhesive material further includes a solder paste or flux material.
4. The semiconductor package of claim 1, wherein the application die is wirebonded to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
5. The semiconductor package of claim 1, wherein the application die is wirebonded to the CSMP to provide electrical connectivity.
6. The semiconductor package of claim 1, wherein the CSMP is wirebonded to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
7. The semiconductor package of claim 1, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
8. The semiconductor package of claim 1, further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package.
9. The semiconductor package of claim 1, wherein the CSMP includes a grounded flip chip die for enhanced thermal performance.
10. A method of manufacturing a semiconductor package, comprising:
providing a ball grid array (BGA) substrate having integrated metal layer circuitry;
attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the ball grid array (BGA) substrate; and
attaching an application die to the integrated passive device (IPD).
11. The method of manufacturing a semiconductor package of claim 10, wherein the flip chip CSMP is attached to the BGA substrate using an adhesive material.
12. The method of manufacturing a semiconductor package of claim 11, wherein the adhesive material further includes a solder paste or flux material.
13. The method of manufacturing a semiconductor package of claim 10, further including wirebonding the application die to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
14. The method of manufacturing a semiconductor package of claim 10, further including wirebonding the application die to the CSMP to provide electrical connectivity.
15. The method of manufacturing a semiconductor package of claim 10, further including wirebonding the CSMP to the metal layer circuitry of the BGA substrate to provide electrical connectivity.
16. The method of manufacturing a semiconductor package of claim 10, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
17. The method of manufacturing a semiconductor package of claim 1, further including forming an encapsulant over the CSMP for providing structural support to the CSMP within the semiconductor package.
18. The method of manufacturing a semiconductor package of claim 10, wherein the CSMP includes a grounded flip chip die for enhanced thermal performance.
19. A semiconductor package comprising:
a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity;
a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the cavity of the thermally-enhanced substrate; and
an application die attached to the integrated passive device (IPD).
20. The semiconductor package of claim 19, wherein the flip chip CSMP is attached to the thermally-enhanced substrate using an adhesive material.
21. The semiconductor package of claim 19, wherein the application die is attached to the integrated passive device using an adhesive material.
22. The semiconductor package of claim 19, wherein the application die is wirebonded to a bond finger of the thermally-enhanced substrate to provide electrical connectivity.
23. The semiconductor package of claim 19, wherein the application die is bonded to the flip chip CSMP package to provide electrical connectivity.
24. The semiconductor package of claim 19, wherein the flip chip CSMP package is wirebonded to a bond finger of the thermally-enhanced package to provide electrical connectivity.
25. The semiconductor package of claim 19, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
26. The semiconductor package of claim 19, wherein the CSMP includes a thermally-enhanced flip chip die.
27. The semiconductor package of claim 19, further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package.
28. A method of manufacturing a semiconductor package comprising:
providing a thermally-enhanced substrate, the thermally-enhanced substrate having a heat sink portion with an integrated cavity;
attaching a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD) to the cavity of the thermally-enhanced substrate; and
attaching an application die to the integrated passive device (IPD).
29. The method of manufacturing a semiconductor package of claim 28, wherein the flip chip CSMP is attached to the cavity of the thermally-enhanced substrate using an adhesive material.
30. The method of manufacturing a semiconductor package of claim 28, wherein the application die is attached to the integrated passive device using an adhesive material.
31. The method of manufacturing a semiconductor package of claim 28, wherein the application die is wirebonded to a bond finger of the thermally-enhanced substrate to provide electrical connectivity.
32. The method of manufacturing a semiconductor package of claim 28, wherein the application die is bonded to the flip chip CSMP package to provide electrical connectivity.
33. The method of manufacturing a semiconductor package of claim 28, wherein the flip chip CSMP package is wirebonded to a bond finger of the thermally-enhanced package to provide electrical connectivity.
34. The method of manufacturing a semiconductor package of claim 28, wherein the application die further comprises a second IPD or an integrated circuit (IC) device.
35. The method of manufacturing a semiconductor package of claim 28, wherein the CSMP includes a thermally-enhanced flip chip die.
36. The method of manufacturing a semiconductor package of claim 28, further including an encapsulant formed over the CSMP for providing structural support to the CSMP within the semiconductor package.
37. A semiconductor package, comprising:
a ball grid array (BGA) substrate having integrated metal circuitry;
a wafer level chip scale package (WLCSP) attached to the ball grid array substrate, the wafer level chip scale package having a first integrated passive device (IPD); and
an application die attached to the integrated passive device (IPD).
38. The semiconductor package of claim 37, wherein the WLCSP is attached to the BGA substrate, or the application die is attached to the IPD using an adhesive material.
39. The semiconductor package of claim 38, wherein the adhesive material further includes solder paste or flux-reflow material.
40. The semiconductor package of claim 37, wherein the application die further includes a second IPD or an integrated circuit (IC) device.
41. The semiconductor device of claim 37, wherein the WLCSP is wirebonded to the integrated metal circuitry of the BGA substrate to provide electrical connectivity.
42. The semiconductor device of claim 37, wherein a solder ball of the WLCSP is bonded to a ball pad located on the BGA substrate to provide electrical connectivity.
43. The semiconductor device of claim 37, further including an encapsulant formed over the WLCSP to provide structural support to the WLCSP within the semiconductor package.
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Cited By (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080088011A1 (en) * 2006-10-12 2008-04-17 Siliconware Precision Industries Co., Ltd. Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof
US20080206519A1 (en) * 2007-02-15 2008-08-28 Frieder Haag Component assembly
US20080237825A1 (en) * 2007-03-30 2008-10-02 Lionel Chien Hui Tay Stacked integrated circuit package system with conductive spacer
US20090020885A1 (en) * 2006-12-28 2009-01-22 Masanori Onodera Semiconductor device and method of manufacturing the same
US20090057867A1 (en) * 2007-08-30 2009-03-05 Vincent Hool Integrated Circuit Package with Passive Component
US20090152704A1 (en) * 2007-02-06 2009-06-18 Philip Lyndon Cablao Integrated circuit packaging system with interposer
US20090230553A1 (en) * 2008-03-14 2009-09-17 Infineon Technologies Ag Semiconductor device including adhesive covered element
US20100320591A1 (en) * 2009-06-19 2010-12-23 Zigmund Ramirez Camacho Integrated circuit packaging system with contact pads and method of manufacture thereof
CN102237331A (en) * 2011-05-25 2011-11-09 北京索爱普天移动通信有限公司 Stack package and manufacturing method thereof
US20130181359A1 (en) * 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
US20140291842A1 (en) * 2013-03-29 2014-10-02 Stmicroelectronics, Inc. Enhanced flip-chip die architecture
CN105990299A (en) * 2015-02-06 2016-10-05 展讯通信（上海）有限公司 BGA (Ball Grid Array) packaging structure and preparation method thereof
US20160293582A1 (en) * 2015-03-30 2016-10-06 Kabushiki Kaisha Toshiba Semiconductor device
US9515052B1 (en) * 2015-06-26 2016-12-06 SK Hynix Inc. Semiconductor package including a step type substrate
US20170103968A1 (en) * 2015-10-12 2017-04-13 Invensas Corporation Embedded wire bond wires
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
CN110634856A (en) * 2019-09-23 2019-12-31 华天科技（西安）有限公司 Flip-chip and wire bonding hybrid packaging structure and packaging method thereof
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US10930573B2 (en) * 2016-08-31 2021-02-23 Murata Manufacturing Co., Ltd. Circuit module and manufacturing method therefor
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200522293A (en) * 2003-10-01 2005-07-01 Koninkl Philips Electronics Nv Electrical shielding in stacked dies by using conductive die attach adhesive
US8716065B2 (en) 2011-09-23 2014-05-06 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and method of manufacture thereof
US8698297B2 (en) 2011-09-23 2014-04-15 Stats Chippac Ltd. Integrated circuit packaging system with stack device
US8867231B2 (en) 2012-01-13 2014-10-21 Tyco Electronics Corporation Electronic module packages and assemblies for electrical systems
JP6125209B2 (en) * 2012-11-19 2017-05-10 株式会社ジェイデバイス Semiconductor device and manufacturing method thereof
US9016552B2 (en) * 2013-03-15 2015-04-28 Sanmina Corporation Method for forming interposers and stacked memory devices
US9318451B2 (en) * 2013-10-31 2016-04-19 Freescale Semiconductor, Inc. Wirebond recess for stacked die
US11291146B2 (en) 2014-03-07 2022-03-29 Bridge Semiconductor Corp. Leadframe substrate having modulator and crack inhibiting structure and flip chip assembly using the same
US10121768B2 (en) 2015-05-27 2018-11-06 Bridge Semiconductor Corporation Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same
US10354984B2 (en) 2015-05-27 2019-07-16 Bridge Semiconductor Corporation Semiconductor assembly with electromagnetic shielding and thermally enhanced characteristics and method of making the same
US9209144B1 (en) * 2014-09-29 2015-12-08 Freescale Semiconductor, Inc. Substrate with electrically isolated bond pads
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
TWI582916B (en) * 2015-04-27 2017-05-11 南茂科技股份有限公司 Multi chip package structure, wafer level chip package structure and manufacturing method thereof
US10050024B2 (en) * 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10910233B2 (en) * 2018-04-11 2021-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11948871B2 (en) 2021-01-08 2024-04-02 Texas Instruments Incorporated Process for thin film capacitor integration

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US20020027295A1 (en) * 2000-09-04 2002-03-07 Fujitsu Limited Stacked semiconductor device and method of producing the same
US20030141583A1 (en) * 2002-01-31 2003-07-31 Yang Chaur-Chin Stacked package
US20040183181A1 (en) * 2002-09-11 2004-09-23 International Business Machines Corporation Stacked package for integrated circuits
US20040212067A1 (en) * 2003-04-25 2004-10-28 Advanced Semiconductor Engineering, Inc. Multi-chips stacked package
US6921968B2 (en) * 2003-05-02 2005-07-26 Advance Semiconductor Engineering, Inc. Stacked flip chip package
US20050242422A1 (en) * 2003-01-27 2005-11-03 Klein Dean A Semiconductor component having multiple stacked dice
US20050248019A1 (en) * 2004-05-10 2005-11-10 Te-Tsung Chao Overhang support for a stacked semiconductor device, and method of forming thereof
US6989586B2 (en) * 2003-03-31 2006-01-24 Intel Corporation Integrated circuit packages with reduced stress on die and associated substrates, assemblies, and systems
US7078788B2 (en) * 2000-08-16 2006-07-18 Intel Corporation Microelectronic substrates with integrated devices
US20060220206A1 (en) * 2005-03-29 2006-10-05 Texas Instruments Incorporated Vertically integrated system-in-a-package
US7129583B2 (en) * 2003-12-31 2006-10-31 Advanced Semiconductor Engineering, Inc. Multi-chip package structure

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5994166A (en) * 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
JP2001077301A (en) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc Semiconductor package and its manufacturing method
US6368894B1 (en) * 1999-09-08 2002-04-09 Ming-Tung Shen Multi-chip semiconductor module and manufacturing process thereof
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
TW533561B (en) * 2002-02-26 2003-05-21 Orient Semiconductor Elect Ltd Opening-type multi-chip stacking package
US20040183179A1 (en) * 2003-03-20 2004-09-23 Wen-Lo Shieh Package structure for a multi-chip integrated circuit
TWI233682B (en) * 2003-08-22 2005-06-01 Advanced Semiconductor Eng Flip-chip package, semiconductor chip with bumps, and method for manufacturing semiconductor chip with bumps
US20050285254A1 (en) * 2004-06-23 2005-12-29 Buot Joan R V Semiconducting device having stacked dice

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US7078788B2 (en) * 2000-08-16 2006-07-18 Intel Corporation Microelectronic substrates with integrated devices
US20020027295A1 (en) * 2000-09-04 2002-03-07 Fujitsu Limited Stacked semiconductor device and method of producing the same
US20030141583A1 (en) * 2002-01-31 2003-07-31 Yang Chaur-Chin Stacked package
US20040183181A1 (en) * 2002-09-11 2004-09-23 International Business Machines Corporation Stacked package for integrated circuits
US20050242422A1 (en) * 2003-01-27 2005-11-03 Klein Dean A Semiconductor component having multiple stacked dice
US6989586B2 (en) * 2003-03-31 2006-01-24 Intel Corporation Integrated circuit packages with reduced stress on die and associated substrates, assemblies, and systems
US20040212067A1 (en) * 2003-04-25 2004-10-28 Advanced Semiconductor Engineering, Inc. Multi-chips stacked package
US6921968B2 (en) * 2003-05-02 2005-07-26 Advance Semiconductor Engineering, Inc. Stacked flip chip package
US7129583B2 (en) * 2003-12-31 2006-10-31 Advanced Semiconductor Engineering, Inc. Multi-chip package structure
US20050248019A1 (en) * 2004-05-10 2005-11-10 Te-Tsung Chao Overhang support for a stacked semiconductor device, and method of forming thereof
US20060220206A1 (en) * 2005-03-29 2006-10-05 Texas Instruments Incorporated Vertically integrated system-in-a-package

Cited By (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080088011A1 (en) * 2006-10-12 2008-04-17 Siliconware Precision Industries Co., Ltd. Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof
US7679178B2 (en) * 2006-10-12 2010-03-16 Siliconware Precision Industries Co., Ltd. Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof
US20090020885A1 (en) * 2006-12-28 2009-01-22 Masanori Onodera Semiconductor device and method of manufacturing the same
US7911046B2 (en) 2007-02-06 2011-03-22 Stats Chippac Ltd. Integrated circuit packaging system with interposer
US20090152704A1 (en) * 2007-02-06 2009-06-18 Philip Lyndon Cablao Integrated circuit packaging system with interposer
US20080206519A1 (en) * 2007-02-15 2008-08-28 Frieder Haag Component assembly
US7838981B2 (en) * 2007-02-15 2010-11-23 Robert Bosch Gmbh Component assembly
US20080237825A1 (en) * 2007-03-30 2008-10-02 Lionel Chien Hui Tay Stacked integrated circuit package system with conductive spacer
US8134227B2 (en) * 2007-03-30 2012-03-13 Stats Chippac Ltd. Stacked integrated circuit package system with conductive spacer
US20090057867A1 (en) * 2007-08-30 2009-03-05 Vincent Hool Integrated Circuit Package with Passive Component
US8659154B2 (en) 2008-03-14 2014-02-25 Infineon Technologies Ag Semiconductor device including adhesive covered element
US20090230553A1 (en) * 2008-03-14 2009-09-17 Infineon Technologies Ag Semiconductor device including adhesive covered element
US9984900B2 (en) 2008-03-14 2018-05-29 Infineon Technologies Ag Semiconductor device including at least one element
DE102009011975B4 (en) * 2008-03-14 2018-04-19 Infineon Technologies Ag Semiconductor arrangement with a position-stable covered element
US20100320591A1 (en) * 2009-06-19 2010-12-23 Zigmund Ramirez Camacho Integrated circuit packaging system with contact pads and method of manufacture thereof
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US10593643B2 (en) 2011-05-03 2020-03-17 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US11424211B2 (en) 2011-05-03 2022-08-23 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
CN102237331A (en) * 2011-05-25 2011-11-09 北京索爱普天移动通信有限公司 Stack package and manufacturing method thereof
US11735563B2 (en) 2011-10-17 2023-08-22 Invensas Llc Package-on-package assembly with wire bond vias
US10756049B2 (en) 2011-10-17 2020-08-25 Invensas Corporation Package-on-package assembly with wire bond vias
US11189595B2 (en) 2011-10-17 2021-11-30 Invensas Corporation Package-on-package assembly with wire bond vias
US9646922B2 (en) 2012-01-13 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for thinner package on package structures
US20130181359A1 (en) * 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10510659B2 (en) 2012-05-22 2019-12-17 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10297582B2 (en) 2012-08-03 2019-05-21 Invensas Corporation BVA interposer
US9177903B2 (en) * 2013-03-29 2015-11-03 Stmicroelectronics, Inc. Enhanced flip-chip die architecture
US20140291842A1 (en) * 2013-03-29 2014-10-02 Stmicroelectronics, Inc. Enhanced flip-chip die architecture
US10460958B2 (en) 2013-08-07 2019-10-29 Invensas Corporation Method of manufacturing embedded packaging with preformed vias
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10290613B2 (en) 2013-11-22 2019-05-14 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US10629567B2 (en) 2013-11-22 2020-04-21 Invensas Corporation Multiple plated via arrays of different wire heights on same substrate
US11404338B2 (en) 2014-01-17 2022-08-02 Invensas Corporation Fine pitch bva using reconstituted wafer with area array accessible for testing
US10529636B2 (en) 2014-01-17 2020-01-07 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
CN105990299A (en) * 2015-02-06 2016-10-05 展讯通信（上海）有限公司 BGA (Ball Grid Array) packaging structure and preparation method thereof
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10806036B2 (en) 2015-03-05 2020-10-13 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10115704B2 (en) * 2015-03-30 2018-10-30 Toshiba Memory Corporation Semiconductor device
US20160293582A1 (en) * 2015-03-30 2016-10-06 Kabushiki Kaisha Toshiba Semiconductor device
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9515052B1 (en) * 2015-06-26 2016-12-06 SK Hynix Inc. Semiconductor package including a step type substrate
US20170103968A1 (en) * 2015-10-12 2017-04-13 Invensas Corporation Embedded wire bond wires
US10490528B2 (en) * 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US11462483B2 (en) 2015-10-12 2022-10-04 Invensas Llc Wire bond wires for interference shielding
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US10559537B2 (en) 2015-10-12 2020-02-11 Invensas Corporation Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10325877B2 (en) 2015-12-30 2019-06-18 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10658302B2 (en) 2016-07-29 2020-05-19 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10930573B2 (en) * 2016-08-31 2021-02-23 Murata Manufacturing Co., Ltd. Circuit module and manufacturing method therefor
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
CN110634856A (en) * 2019-09-23 2019-12-31 华天科技（西安）有限公司 Flip-chip and wire bonding hybrid packaging structure and packaging method thereof

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