US20080044968A1 - Method for improving transistor performance through reducing the salicide interface resistance - Google Patents
Method for improving transistor performance through reducing the salicide interface resistance Download PDFInfo
- Publication number
- US20080044968A1 US20080044968A1 US11/899,881 US89988107A US2008044968A1 US 20080044968 A1 US20080044968 A1 US 20080044968A1 US 89988107 A US89988107 A US 89988107A US 2008044968 A1 US2008044968 A1 US 2008044968A1
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- silicon germanium
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- silicon
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- 238000000034 method Methods 0.000 title claims description 46
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 150
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 117
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 59
- 239000010703 silicon Substances 0.000 claims abstract description 58
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 51
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 38
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 34
- 239000000956 alloy Substances 0.000 claims abstract description 34
- FCFLBEDHHQQLCN-UHFFFAOYSA-N [Ge].[Si].[Ni] Chemical compound [Ge].[Si].[Ni] FCFLBEDHHQQLCN-UHFFFAOYSA-N 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 57
- 239000000758 substrate Substances 0.000 claims description 47
- 229910052732 germanium Inorganic materials 0.000 claims description 39
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 39
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 32
- 238000000151 deposition Methods 0.000 claims description 27
- 239000012212 insulator Substances 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 18
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 16
- 239000000203 mixture Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 230000006835 compression Effects 0.000 claims description 7
- 238000007906 compression Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 2
- 229910000990 Ni alloy Inorganic materials 0.000 claims 2
- 238000000137 annealing Methods 0.000 claims 2
- 235000011149 sulphuric acid Nutrition 0.000 claims 1
- 230000009467 reduction Effects 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 239000003870 refractory metal Substances 0.000 description 14
- 238000012545 processing Methods 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 11
- 230000037230 mobility Effects 0.000 description 10
- 230000008901 benefit Effects 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 229910000927 Ge alloy Inorganic materials 0.000 description 2
- 229910006990 Si1-xGex Inorganic materials 0.000 description 2
- 229910007020 Si1−xGex Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910007264 Si2H6 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 bulk silicon Chemical compound 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000000135 prohibitive effect Effects 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
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- H01L29/66234—Bipolar junction transistors [BJT]
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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Abstract
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
Description
- This application is a divisional application of application Ser. No. 11/171,097 filed on Jun. 29, 2005, which is a divisional application of application Ser. No. 10/731,269 filed Dec. 8, 2003, now U.S. Pat. No. 6,949,482.
- Embodiments of the invention relate to high speed semiconductor transistors, and more specifically to increasing transistor performance by utilizing silicon germanium and improved methods of application thereof.
- Silicon complementary metal oxide semiconductor (“CMOS”) technology is a dominant microelectronic technology. CMOS offers high reliability, high levels of integration, low power dissipation, and is very cost-effective. For lower frequency applications CMOS will most likely remain the dominant technology. However, electron and hole mobility in silicon limits the extent to which CMOS devices can be utilized for higher speed applications such as radars and mobile communication devices that require high transistor switching rates.
- One historical solution has been to use semiconductor compounds instead of elemental semiconductors such as Group IV silicon and germanium. These compounds can be binary, tertiary, and quaternary combinations of Group II (Zn and Cd), Group III (B, Al, Ga, and In), Group IV (C, Si, and Ge), Group V (P, As, and Sb) and Group VI (S, Se, and Te) elements. Common III-V semiconductors include Gallium Arsenide (GaAs), Gallium Phosphide (GaP), and Indium Phosphide (InP). Gallium Arsenide, in particular, has widespread use as a source of and sensor to near infrared light given its 1.43 electron volt (“eV”) band gap and as the primary semiconductor for high speed electronic devices. Despite the speed improvements over silicon CMOS devices, GaAs is for most applications cost prohibitive. One estimate indicates that per square millimeter in 1995 dollars, silicon CMOS has a $0.01 cost while GaAs epitaxy has a $2.00 cost.
- A newer approach, and one that offers the speed benefits of GaAs and improved cost-effectiveness of silicon CMOS, employs silicon germanium (strained or unstrained, usually denoted more precisely by Si1-xGex or simply as SiGe) and/or strained silicon. Germanium has a 4.2% larger lattice constant (e.g., atomic spacing) than silicon. Silicon germanium also has a larger lattice constant, the extent of which depends on the percentage composition of germanium. When silicon is grown on silicon germanium, under proper conditions the silicon lattice stretches to match that of the silicon germanium at the silicon/silicon germanium interface. When silicon germanium is grown on silicon, under proper conditions the silicon germanium lattice gets compressed. For each method, there is critical thickness of the grown layer (be it silicon or silicon germanium) past which the grown layer relaxes as lattice defects propagate.
- There are two reasons why strained silicon and silicon germanium offer improved speed characteristics for transistors comprised thereof. Compared to elemental silicon, germanium has a lower electron effective mass and lower hole effective mass (leading to higher electron mobility and higher hole mobility). Silicon germanium compounds benefit from the increased mobilities of the constituent germanium. Further, the induced strain in silicon or silicon germanium (tension and compression respectively) creates an anisotropic structure that alters the conduction and valence bands of the materials. When combined with other semiconductor layers (e.g., heterolayers) with different band gaps, conduction band and valence band discontinuities can be designed to create quantum wells or built-in electric fields to accelerate carriers across the heterolayers.
- Silicon germanium deposition can be incorporated into CMOS process flows relatively easily. For example, the only major increase in cost is the addition of a silicon germanium epitaxy step. Given the ease of integration and the band gap engineering possible with silicon germanium (e.g., bulk silicon, bulk silicon germanium, and strained variants of each) the possibility of manufacturing an entire system on one silicon or silicon on insulator (“SOI”) substrate is real. Integrated systems could include fiber optic connections, waveguides, optical detectors, CMOS, heterojunction bipolar transistors, and quantum devices all on the same chip.
- Simply using strained silicon and/or silicon germanium does not render immediately superior devices. As with all paradigm shifts, incorporating strained silicon and silicon germanium into current semiconductor processing flows creates a new set of problems to solve.
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FIG. 1 a: illustration of a substrate cross section following the formation of the gate and nitride spacers -
FIG. 1 b: illustration of a substrate cross section following the deposition of a dielectric film over the entire substrate surface -
FIG. 1 c: illustration of a substrate cross section following the patterning and etching of the dielectric film to expose the source and drain regions -
FIG. 2 : illustration of a substrate cross section following the source and drain region undercut etch -
FIG. 3 : illustration of a substrate cross section following the deposition of silicon germanium in the undercut etched source and drain regions -
FIG. 4 a: illustration of a substrate cross section following the deposition of a refractory metal -
FIG. 4 b: illustration of a substrate cross section following a formation anneal to form a silicide contact layer on the surface of the silicon germanium source drain regions and gate region -
FIG. 4 c: illustration of a substrate cross section following the removal of unreacted refractory metal -
FIG. 5 : illustration of the band structure of p-type silicon versus silicon germanium -
FIG. 6 : illustration of the band structure of p-type silicon in contact with a metal -
FIG. 7 : illustration of the band structure of silicon germanium in contact with a metal -
FIG. 8 : illustration of a substrate cross section indicating the external resistance (Rext) of the metal oxide semiconductor transistor - Embodiments of a method for improving transistor performance will be described. Reference will now be made in detail to a description of these embodiments as illustrated in the drawings. While the embodiments will be described in connection with these drawings, there is no intent to limit them to drawings disclosed therein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents within the spirit and scope of the described embodiments as defined by the accompanying claims.
- An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and an increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
- The first transistor created in 1947 was germanium. However, given its narrow band gap of 0.67 electron volts (versus 1.11 electron volts for silicon), reverse-biased germanium p-n junctions exhibit large leakage currents. This limited the operating temperature of germanium to below 100° C. In addition, it is difficult to manufacture a passivation layer as required by semiconductor processing techniques. Germanium oxide, for example, is water soluble and dissociates at 80° C. These qualities, coupled with electronics-grade germanium demanding an order of magnitude higher cost versus silicon, have virtually eliminated elemental germanium from modern semiconductor technology.
- There are, however, benefits to using germanium versus silicon. For example, at room temperature, germanium has a electron mobility of 3600 cm2/V-s compared to 1350 cm2/V-s for silicon. Even more striking is germanium's hole mobility of 1800 cm2 V-s versus 480 cm2/V-s for silicon. As germanium has an intrinsic carrier concentration of 2.5*1013 cm-3 and silicon has 1.5*1010 cm-3 at 300K, given that conductivity is proportional to the product of the sum of the mobilities and the intrinsic carrier concentration, germanium has a significantly higher conductivity. As will be more further described below, the performance of a transistor is related to the external resistance. Given that resistivity is the inverse of conductivity, utilizing a more highly conductive material increases the performance of a transistor. Alloying silicon and germanium provides the ability to tune the material to utilize the benefits of each constituent semiconductor. As will be described with reference to an embodiment of the invention, a semiconductor alloy of silicon and germanium offers promising improvements in certain semiconductor applications.
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FIG. 1 a illustrates a substrate cross section following various processing steps to begin creation of a metal oxide semiconductor (“MOS”) transistor. One skilled in the art will recognize what processing steps have occurred, the explanation of which will be omitted. In an embodiment of the invention, the transistor is a p-type MOS or PMOS.Substrate 100 is silicon. Anisolation barrier 101 serves as a channel stop to prevent parasitic effects between closely arrayed transistors in an integrated circuit application. Theisolation barrier 101 may be, for example, a shallow trench isolation (“STI”) region formed by etching a trench in thesubstrate 100 and filling the trench with a deposited oxide isolation material. Agate 102 has been formed and patterned atop aninsulator 104, the composition of thegate 102 being, for example, polycrystalline silicon. The polycrystalline silicon ofgate 102 may be further pre-doped. On each side of thegate 102 there is asidewall spacer 103 usually formed of silicon nitride. Eachsidewall spacer 103 serves as a hard mask for subsequent self-aligned processing steps. One skilled in the art will understand that, for example, thesidewall spacer 103 is a hard mask for high dose implants in a lightly doped drain transistor design or other designs that would benefit from the sidewall spacing as is well known in the art. - Through the processing steps illustrated by
FIG. 1 a, the process as described is a standard CMOS process flow as is well known in the art. The next processing step afterFIG. 1 a for a CMOS flow would be to create the source and drain regions of the MOS transistor by doping the source and drain regions by ion implant. However, at this point the process of an embodiment of the invention departs from a standard CMOS process flow. In an embodiment of the invention the silicon germanium is used for the PMOS devices only. Instead of a source and drain region implant (i.e., the next step in a standard CMOS process flow), the exposed surface of the wafer is covered with a dielectric layer of, for example, SiO2 or Si3N4 as illustrated bydielectric layer 104 inFIG. 1 b. The dielectric layer is patterned using any known photolithographic or related patterning technique to expose the source and drain regions of the intended PMOS devices as illustrated byFIG. 1 c, leaving the intended NMOS devices completely covered. An SF6-based plasma etch then selectively removes the exposedsilicon substrate 100 material in the source and drain regions of the PMOS device. The etch is selective in that it removes thebulk silicon substrate 100 material at a much higher rate than the SiO2 or Si3N4dielectric layer 105 andsidewall spacer 103 material serving as an etch mask. The etched source and drain regions are then selectively filled with silicon germanium (in an embodiment, in situ doped silicon germanium). Thedielectric layer 105 serving as a mask for the source and drain region etch and silicon germanium deposition is then removed using, for example, an HF-based wet etch. A silicide layer is formed to provide contact to the source, drain, and gate regions of the PMOS and NMOS. The wafer can then undergo the remaining CMOS process steps to create devices that benefit from an embodiment of the invention. More specific processing techniques of an embodiment of the invention will be described in turn. -
FIG. 2 illustrates the substrate cross section ofFIG. 1 c following an undercutetch 201 to removesubstrate 100 silicon from the source and drain regions of the PMOS devices as introduced above. The profile of the etch is such thatsubstrate 100 material has been removed from beneathsidewall spacers 103. In an embodiment, the undercutetch 201 extends beneath thegate 102. The undercut aspect of the undercutetch 201 has a substantial impact on the performance benefit created by an embodiment of the invention. - Specifically, as shown in
FIG. 2 , the undercutetch 201 is formed insubstrate 100 along laterally opposite sidewalls ofgate 102. In an embodiment an isotropic etch process is used to form the undercutetch 201. An isotropic etch not only etches vertically into the substrate but also etches horizontally (laterally) beneath eachsidewall spacer 103 and in an embodiment beneathgate 102. Such a lateral undercut etch can be produced by using an isotropic dry etch process in, for example, a parallel plate RF plasma etching system using a gas mix chemistry comprising SF6 and helium and process conditions that favor isotropy. Such conditions include high pressure and low RF power density. In an embodiment, a process parameters include a pressure of approximately 900 mT, a gap of 1.1 cm, an RF power of 100 W, a helium flow of 150 sccm, and a SF6 flow of 100 sccm is used. RF power may be varied in a range, for example, of 50 W to 200 W, and the process pressure may be varied but should be greater than approximately 500 mT. In an embodiment the undercutetch 201 has a maximum vertical depth of between 100 and 1500 angstroms below the surface ofsubstrate 100 and extends between 25 to 200 angstrom horizontally or laterally beneath thegate 102 edge at thesubstrate 100/insulator 104 interface. It is to be appreciated that alternative process conditions and etch chemistries (e.g., a wet etch) can be utilized to generate otherundercut etch 201 geometry profiles is desired. - Not only does such an etching process produce lateral undercuts beneath each
sidewall spacer 103 and in an embodiment beneath thegate 102 but the etch chemistry is also highly selective to theinsulator 104 oxide and to thesidewall spacer 103 nitride material. In this way the undercut etch does not attack the insulator andsidewall spacer 103 material and the geometry of each is preserved. - The etch chemistry used to form the undercut
etch 201 is further slightly oxidizing. Utilizing an oxidizing etchant causes a portion of theinsulator 104 layer exposed during the undercut etch process to become thicker than the unexposed portion of theinsulator 104 layer. By increasing the thickness of theinsulator 104 layer at the edge of thegate 102, the gate edge leakage at the tip overlap region of the device is reduced. Athicker insulator 104 layer at thegate 102 edge helps to increase the breakdown voltage of the device. - A further advantage of the undercut
etch 201 process is that the etch rate reduced to between 5 to 30 angstroms per second, causing the etch of the silicon substrate to concave inwards. With this geometry, a large LMET (metallurgical channel length or physical channel length) is achieved during the off state of the MOS transistor (low Ioff) while a smaller LMET is realized during the on state of the MOS transistor when the channel is formed. A smaller LMET during the on state directly translates to a smaller channel resistance and accordingly higher Ion. -
FIG. 3 illustrates the substrate cross section ofFIG. 2 following the deposition ofsilicon germanium 301 in the undercutetch 201 source and drain regions. The silicon germanium, as noted, can be represented by Si1-xGex. The domain of x is [0,1] ranging from pure silicon to pure germanium, and can be adjusted to tune the conductivity and band gap to the requirements of a particular device. In an embodiment, x is approximately between 0.05 and 0.5 (e.g., approximately between 5% and 50% atomically germanium in the silicon germanium alloy). In another embodiment, x is approximately between 0.1 and 0.4 (e.g., approximately between 10% and 40% atomically germanium in the silicon germanium alloy). In yet another embodiment x is approximately between 0.15 and 0.3 (e.g., approximately between 15% and 30% atomically germanium in the silicon germanium alloy). The band gap energy associated with thesilicon germanium 301 alloy can be approximated by the following equations:
E g(x)=(1.155−0.43x+0.0206x) eV for 0<x<0.85 (1)
E g(x)=(2.010−1.27x) eV for 0.85<x<1 (2)
In an embodiment, therefore, according to equation (1) the band gap energy of thesilicon germanium 301 is approximately between 1.13 eV and 095 eV for 5% atomically germanium and 50% atomically germanium respectively. In another embodiment, the band gap energy of thesilicon germanium 301 is approximately between 1.11 eV and 0.99 eV for 10% atomically germanium and 40% atomically germanium respectively. In yet another embodiment the band gap energy of thesilicon germanium 301 is approximately between 1.09 eV and 1.03 eV for 15% atomically germanium and 30% atomically germanium respectively. - The
silicon germanium 301 is deposited by selective epitaxial deposition in that the silicon germanium is deposited only on the bulk silicon substrate surface exposed by the undercutetch 201 and uncovered by thedielectric layer 105. Thesilicon germanium 301 crystal does not grow on the SiO2 or Si3N4 dielectric layer. In an embodiment, the deposition technique is reduced pressure chemical vapor deposition (“CVD”) epitaxial deposition. In other embodiments, the deposition technique includes atmospheric CVD epitaxy and ultra high vacuum CVD epitaxy. Each deposition technique is a specific form of vapor phase epitaxy as the depositedsilicon germanium 301 is single crystal. - As noted, in an embodiment, the silicon germanium deposition method is CVD epitaxy. Environmentally, the epitaxy occurs between 600° C. and 800° C. at a pressure between 10 and 760 torr. Either H2 or He can be used as a carrier gas. The silicon source precursor gas can be SiH2Cl, SiH4, or Si2H6. In an embodiment, GeH4 is the germanium source precursor gas. HCl or Cl2 may be added as an etching agent to increase the material selectivity of the deposition. In an embodiment, the resulting
silicon germanium 301 deposited in the undercutetch 201 source and drain regions has a thickness between 500 and 2000 angstroms. In an embodiment, thesilicon germanium 301 deposition extends above the surface ofsubstrate 100. In this way thesilicon germanium 301 is formed both above and below the surface ofsubstrate 100. By formingsilicon germanium 301 above the surface ofsubstrate 100, a raised tip is formed, increasing the conductivity of the tip. The increased conductivity in turn improves device performance. - The
silicon germanium 301 can further be doped to adjust its electrical and chemical properties. The doping can occur using a variety of dopants and with a variety of doping techniques. For example, thesilicon germanium 301 can be in situ doped with p-type impurities to a dopant concentration level between 1*1018/cm3 and 3*1021/cm3 with a concentration of approximately 1*1020 cm3 being preferred. In an embodiment, and creating a PMOS device, thesilicon germanium 301 is doped with boron in situ during epitaxy by utilizing the precursors noted above and an additional B2H6 precursor gas as the source of the boron dopant during thesilicon germanium 301 epitaxial deposition. The benefit ofdoping silicon germanium 301 in situ is that the undercut nature of undercutetch 201 makes it very difficult to dope thesilicon germanium 301 after it has been deposited in area shadowed by the sidewall spacer. An angled implant, as one possible solution to doping the silicon germanium shadowed by the sidewall spacer, reduces the short channel performance of the resulting PMOS device. - In an embodiment, a fraction of the boron dopant added during the
silicon germanium 301 deposition is not activated at this time. That is, after deposition boron atoms are in thesilicon germanium 301 layer but have not yet substituted into silicon sites in the lattice where they can provide a hole (i.e., a lack of an electron). In an embodiment, the thermal activation of the dopant is deferred until subsequent processing steps, reducing the thermal budget and resulting dopant diffusion to enable a very abrupt source/drain junction to be formed, improving device performance. - As introduced, the deposited
silicon germanium 301 has a larger lattice constant, the magnitude of which depends on the atomic percent germanium in thesilicon germanium 301 alloy. When deposited on thesubstrate 100 silicon, the lattice of thesilicon germanium 301 is compresses to accommodate crystalline growth. The compression in thesilicon germanium 301 source and drain regions further creates compression in thesubstrate 100 region located between thesilicon germanium 301 source and drain regions and beneath theinsulator 104 region (i.e., the channel of the MOS device). The compression creates an anisotropic atomic structure in the channel region, altering the conduction and valence bands of the channel material. The compressive stress further reduces the hole effective mass in the channel area ofsubstrate 100, in turn increasing hole mobility. The increased hole mobility increases the saturation channel current of the resulting MOS transistor, thereby improving the device performance. -
FIGS. 4 a, 4 b, and 4 c illustrate the substrate cross section ofFIG. 3 during the creation of a silicide layer. More specifically, the layer is a self-aligned silicide or salicide layer. One skilled in the art will recognize thatsilicide layer 402 is formed by depositing a thin layer of refractory metal, in an embodiment with standard sputtering techniques (i.e., physical vapor deposition or “PVD”), on thesilicon germanium 301 followed by subsequent processing steps to create the metal, silicon, and germanium silicide alloy.Silicide 403 differs in that the semiconductor element of the silicide alloy depends on the material composition ofgate 102. - Refractory metals include, among others, cobalt, titanium and nickel. In an embodiment, the refractory metal is nickel. The selection of a refractory metal requires consideration of not only electrical compatibility, but also mechanical and chemical compatibility with the
underlying silicon germanium 301 material occupying the undercutetch 201 source and drain regions and the exposed source, drain, and gate regions of the corresponding NMOS devices on the same substrate. For example, thesilicide layer 402 must be continuous and uniform to aid reducing interface resistance between thesilicide layer 402 and theunderlying silicon germanium 301. Nickel tends to react uniformly with both silicon and germanium, forming a stable ternary Ni(SiGe) phase whereas cobalt and titanium react preferentially with silicon and segregate the germanium component of thesilicon germanium 301 alloy. Further, the titanium and cobalt based silicon germanium silicides have reduced thermal stability compared to nickel silicon germanium silicide. Improper refractory metal selection creates a non-ideal interface between the silicide and semiconductor that increases the interface resistance independent of otherwise electrically compatible materials. -
FIG. 4 a illustrates the substrate ofFIG. 3 following the blanket deposition ofrefractory metal 401. As noted, in an embodiment the refractory metal is PVD nickel. Environmentally, the PVD nickel deposition occurs between 20° C. and 200° C. and at a pressure less than 50 millitorr. The thickness of the nickel is between 50 and 200 angstroms. The nickel deposition is followed by a rapid formation anneal at between 325° C. and 450° C. for less than or equal to 60 seconds using, for example, rapid thermal anneal (“RTA”) equipment. During the formation anneal therefractory metal 401 atop thesilicon germanium 301 andgate 102 reacts to formsilicide 402 andsilicide 403 respectively as illustrated byFIG. 4 b. As the nickel is deposited over the entire exposed surface of thesubstrate 100, the unreacted nickel (i.e., the nickel that has not reacted with silicon or silicon germanium to form a silicide with its underlying layer as it is deposited atop thesidewall spacer 103 nitride or theisolation 101 regions) is removed using a wet etch chemistry of, for example, a mixture of hot H2O2 and hot H2SO4. The remaining reacted nickel atop thesilicon germanium 301 source and drain regions and thegate 102 regions then undergoes a final anneal between 400° C. and 550° C. to complete the nickelsilicon germanium silicide 402 andsilicide 403 formation as illustrated byFIG. 4 c. The silicide layer(s) may be further capped with, for example, a titanium nitride cap to prevent the nickel silicongermanium silicide layer 402 andsilicide layer 403 from oxidizing during subsequent processing steps as is well known in the art. -
FIGS. 5 through 7 illustrate the physics of how the proper material selection for both the refractory metal and the source-drain region material reduce the corresponding contact resistivity.FIG. 5 illustrates energy band diagrams for the bulk metal, p-type silicon, and silicon germanium. The Fermi energy of the metal is denoted EFm. The Fermi energies of the p-type silicon and silicon germanium are EFSi and EFSiGe respectively. As shown, though not necessarily to scale, the conduction band edge of the silicon germanium ECSiGe is slightly lower than the conduction band edge of silicon ECSi. Further, the valence band edge of the silicon germanium EVSiGe is higher than the valence band edge of the silicon EVSi, and is proportionately higher based on the percentage composition of germanium in the silicon germanium alloy. Accordingly, the energy band gap of the silicon germanium alloy is smaller than the energy band gap of silicon, the extent to which is, as introduced with reference to equations (1) and (2), dependant upon the percentage composition of germanium in the germanium alloy. -
FIG. 6 illustrates the band bending associated with contact between the refractory metal and the p-type silicon. Of note is the magnitude of the energy barrier. With the p-type semiconductor, aligning the Fermi levels at equilibrium mandates a positive charge on the metal side and a negative charge on the semiconductor side. The semiconductor accommodates the negative charge by generating a depletion region in which ionized acceptors are left uncompensated by holes. -
FIG. 7 illustrates the energy band bending associated with contact between the refractory metal and thesilicon germanium 301 alloy. Again of note is the magnitude of the energy barrier, in this case the relative difference in energy barrier height of the silicon germanium alloy when compared to p-type silicon. In other words, the metal-semiconductor work function is smaller for the metal-silicon germanium 301 contact versus the metal-p-type silicon contact. Current conduction for the contact is dominated by tunneling. The specific contact resistivity relationship is as follows: - The salient variables in equation (3) are the metal-semiconductor work function ΦB, the semiconductor doping Nsurf, and the effective carrier mass in the semiconductor m*. As noted, the effective mass for holes in a silicon germanium film is 0.34 m0 versus 0.37 m0 for silicon, where m0 represents the rest mass of the electron.
- The specific contact resistivity equation (3) illustrates that the specific contact resistivity for a metal-semiconductor interface depends primarily on the metal-semiconductor work function, the doping density in the semiconductor, and the effective mass of the carrier. Altering any one of the variables, or combinations thereof, impacts the specific contact resistivity. Utilizing
silicon germanium 301, as noted, decreases the metal semiconductor work function and decreases the carrier effective mass. In an embodiment, the silicon germanium is further doped as noted with reference toFIG. 3 . - The interface between the
silicon germanium 301 and thesilicide 402 can be further discussed as a metal-semiconductor ohmic contact. To begin, the effect of the energy barrier at the contact between the silicide and the semiconductor must be viewed from a quantum mechanical view. As is well know in the art, the wave-particle duality dictates that an electron be treated as both a particle and a wave to determine how it behaves. The energy barrier created by the silicide-semiconductor interface can be viewed potential barrier of finite thickness and height. For a given barrier height greater than the energy of an incident electron and a given barrier width, there is a certain probability that the electron will penetrate the barrier and appear on the other side. Such a tunneling phenomena is an important mechanism in the conduction of electrons in solids. - More specifically, contact resistivity is a measure of how easily current can flow across a metal-semiconductor interface. If a contact is ohmic, by definition there is an unimpeded transfer of majority carriers from one material to another—in this case between the
silicide 402 and thesilicon germanium 301. This can also be represented as a linear current-voltage characteristic. In the case of a metal-semiconductor interface, the conduction mechanism is dictated in part by the width of the semiconductor depletion region adjacent to the contact interface. If the semiconductor is lightly doped (e.g., the Fermi energy is neither close to the conduction band edge energy or the valence band edge energy), the depletion region becomes wide enough that the only way for an electron to transfer between the two contact materials is by jumping the potential barrier by thermionic emission over the barrier maximum. Alternatively, if the semiconductor is heavily doped (the Fermi energy approaching the conduction band edge energy for n-type and approaching the valence band edge energy for p-type) the depletion region becomes sufficiently narrow that the field emission, or carrier tunneling, is the dominant conduction mechanism. Both field emission and thermionic emission contribute to conduction across the interface and can be engineered by, for example, material selection and doping. -
FIG. 8 illustrates an embodiment of the invention utilizingsilicon germanium 301 source and drain regions with, for example, a nickel silicongermanium silicide layer 402. Anexternal resistance R ext 801 is the total series resistance between the source (or drain) contact and the channel of the intrinsic transistor. The interface resistance between thesilicon germanium 301 andsilicide 402 is a significant component of the total series resistance.R ext 801 has been reduced by using silicon germanium versus using p-type silicon for the source and drain regions. Further, proper selection of thesilicide layer 402 refractory metal, in an embodiment nickel, has ensured a chemically and mechanically compatible metal-semiconductor interface that does not adversely contribute toR ext 801 as noted with reference toFIG. 4 . - One skilled in the art will recognize the elegance of the disclosed embodiment in that it decreases the specific contact resistivity between the silicon germanium source and drain regions and their respective silicide contacts by utilizing novel material selection and processing techniques. As the contact resistivity contributes to the overall external resistivity of the transistor, a reduction in the contact resistivity contributes to an overall performance increase in the transistor.
Claims (28)
1. A method comprising:
forming an insulator region on a substrate having a first lattice constant;
etching a source region and a drain region in the substrate, thereby defining a channel region located between the source region and the drain region, and beneath the insulator region;
depositing a semiconductor material in the source region and in the drain region, the semiconductor material having a second lattice constant larger than the first lattice constant;
wherein the semiconductor material in the source region and in the drain region creates compression in the channel region; and
forming contacts on the top surface of the semiconductor material in the source region and in the drain region;
wherein the contacts comprise an alloy of nickel and the semiconductor material.
2. The method of claim 1 wherein the semiconductor material is a silicon germanium alloy.
3. The method of claim 2 wherein the contacts comprise nickel silicon germanium silicide.
4. The method of claim 2 wherein the silicon germanium alloy has a germanium composition between 5% and 50%.
5. The method of claim 4 wherein the silicon germanium alloy has a germanium composition between 10% and 40%.
6. The method of claim 5 wherein the silicon germanium alloy has a germanium composition between 15% and 30%.
7. The method of claim 2 further comprising doping the silicon germanium alloy with a boron concentration between 1*1018/cm3 and 3*1021/cm3.
8. The method of claim 2 wherein the silicon germanium alloy is doped in situ during the deposition of the silicon germanium alloy.
9. The method of claim 3 further comprising etching the source region and the drain region laterally beneath the insulator region.
10. A method comprising:
providing a substrate;
forming an insulator on the substrate;
forming and patterning a gate region atop the insulator;
etching a source region and a drain region in the substrate;
depositing a silicon germanium alloy in the source region and in the drain region;
wherein the silicon germanium alloy in the source region and in the drain region further creates compression in a substrate region located between the source region and drain region, and beneath the insulator; and
forming a nickel silicon germanium silicide layer on the top surface of the silicon germanium alloy in the source region and in the drain region.
11. The method of claim 10 further comprising depositing nickel on the surface of silicon germanium alloy in the source region and in the drain region prior to forming the nickel silicon germanium silicide layer.
12. The method of claim 11 wherein the nickel has a thickness between 50 and 200 angstroms.
13. The method of claim 10 wherein forming the nickel silicon germanium silicide layer further comprises:
depositing nickel on the surface of the silicon germanium alloy in the source region and in the drain region;
annealing the substrate at a temperature between 325° C. and 450° C. for less than or equal to 60 seconds;
removing excess nickel with a wet etch chemistry of hot H2O2 and H2SO4; and
annealing the substrate at a temperature between 400° C. and 550° C.
14. The method of claim 10 wherein forming the nickel silicon germanium silicide layer is a self aligned process.
15. The method of claim 10 further comprising etching the source region and the drain region laterally beneath the insulator.
16. The claim 15 further comprising etching the source region and the drain region laterally beneath the gate region.
17. The method of claim 16 further comprising etching the source region and the drain region between 25 angstroms and 200 angstroms laterally beneath the gate region.
18. The method of claim 10 further comprising etching the source region and the drain region a vertical depth between 100 angstroms and 1500 angstroms beneath the surface of the silicon substrate.
19. The method of claim 10 further comprising doping the silicon germanium alloy.
20. The method of claim 19 wherein the silicon germanium alloy is doped in situ during the deposition of the silicon germanium alloy.
21. A transistor comprising:
an insulator region on a substrate having a first lattice constant;
a source region and a drain region in the substrate, thereby defining a channel region located between the source region and the drain region and beneath the insulator region, the source region and the drain region comprising a semiconductor material having a second lattice constant larger than the first lattice constant, wherein the semiconductor material creates compression in the channel region; and
contacts on the top surface of the semiconductor material in the source region and in the drain region, wherein the contacts comprise an alloy of nickel and the semiconductor material.
22. The transistor of claim 21 , wherein the semiconductor material is a silicon germanium alloy.
23. The transistor of claim 22 , wherein the contacts comprise nickel, silicon, germanium silicide.
24. The transistor of claim 22 , wherein the silicon germanium alloy has a germanium composition of between 5% and 50%.
25. The transistor of claim 24 , wherein the silicon germanium alloy has a germanium composition between 10% and 40%.
26. The transistor of claim 25 , wherein the silicon germanium alloy has a germanium composition between 15% and 30%.
27. The transistor of claim 22 , wherein the silicon germanium alloy is doped with boron to a concentration between 1×1018/cm3 and 3×1021/cm3.
28. The transistor of claim 23 , wherein the semiconductor material in a source region and in the drain region extend laterally beneath the insulator region.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/899,881 US20080044968A1 (en) | 2003-12-08 | 2007-09-07 | Method for improving transistor performance through reducing the salicide interface resistance |
US12/655,323 US20110006344A1 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US12/655,341 US8482043B2 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US13/931,678 US9202889B2 (en) | 2003-12-08 | 2013-06-28 | Method for improving transistor performance through reducing the salicide interface resistance |
US14/583,042 US9437710B2 (en) | 2003-12-08 | 2014-12-24 | Method for improving transistor performance through reducing the salicide interface resistance |
US15/220,355 US9680016B2 (en) | 2003-12-08 | 2016-07-26 | Method for improving transistor performance through reducing the salicide interface resistance |
US15/220,304 US9876113B2 (en) | 2003-12-08 | 2016-07-26 | Method for improving transistor performance through reducing the salicide interface resistance |
Applications Claiming Priority (3)
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---|---|---|---|
US10/731,269 US6949482B2 (en) | 2003-12-08 | 2003-12-08 | Method for improving transistor performance through reducing the salicide interface resistance |
US11/171,097 US7274055B2 (en) | 2003-12-08 | 2005-06-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US11/899,881 US20080044968A1 (en) | 2003-12-08 | 2007-09-07 | Method for improving transistor performance through reducing the salicide interface resistance |
Related Parent Applications (1)
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US11/171,097 Division US7274055B2 (en) | 2003-12-08 | 2005-06-29 | Method for improving transistor performance through reducing the salicide interface resistance |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US12/655,323 Continuation US20110006344A1 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US12/655,341 Continuation US8482043B2 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
Publications (1)
Publication Number | Publication Date |
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US20080044968A1 true US20080044968A1 (en) | 2008-02-21 |
Family
ID=34652745
Family Applications (9)
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---|---|---|---|
US10/731,269 Expired - Lifetime US6949482B2 (en) | 2003-12-08 | 2003-12-08 | Method for improving transistor performance through reducing the salicide interface resistance |
US11/171,097 Expired - Lifetime US7274055B2 (en) | 2003-12-08 | 2005-06-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US11/899,881 Abandoned US20080044968A1 (en) | 2003-12-08 | 2007-09-07 | Method for improving transistor performance through reducing the salicide interface resistance |
US12/655,323 Abandoned US20110006344A1 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US12/655,341 Active 2024-07-12 US8482043B2 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US13/931,678 Expired - Lifetime US9202889B2 (en) | 2003-12-08 | 2013-06-28 | Method for improving transistor performance through reducing the salicide interface resistance |
US14/583,042 Expired - Lifetime US9437710B2 (en) | 2003-12-08 | 2014-12-24 | Method for improving transistor performance through reducing the salicide interface resistance |
US15/220,355 Expired - Lifetime US9680016B2 (en) | 2003-12-08 | 2016-07-26 | Method for improving transistor performance through reducing the salicide interface resistance |
US15/220,304 Expired - Lifetime US9876113B2 (en) | 2003-12-08 | 2016-07-26 | Method for improving transistor performance through reducing the salicide interface resistance |
Family Applications Before (2)
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US10/731,269 Expired - Lifetime US6949482B2 (en) | 2003-12-08 | 2003-12-08 | Method for improving transistor performance through reducing the salicide interface resistance |
US11/171,097 Expired - Lifetime US7274055B2 (en) | 2003-12-08 | 2005-06-29 | Method for improving transistor performance through reducing the salicide interface resistance |
Family Applications After (6)
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US12/655,323 Abandoned US20110006344A1 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US12/655,341 Active 2024-07-12 US8482043B2 (en) | 2003-12-08 | 2009-12-29 | Method for improving transistor performance through reducing the salicide interface resistance |
US13/931,678 Expired - Lifetime US9202889B2 (en) | 2003-12-08 | 2013-06-28 | Method for improving transistor performance through reducing the salicide interface resistance |
US14/583,042 Expired - Lifetime US9437710B2 (en) | 2003-12-08 | 2014-12-24 | Method for improving transistor performance through reducing the salicide interface resistance |
US15/220,355 Expired - Lifetime US9680016B2 (en) | 2003-12-08 | 2016-07-26 | Method for improving transistor performance through reducing the salicide interface resistance |
US15/220,304 Expired - Lifetime US9876113B2 (en) | 2003-12-08 | 2016-07-26 | Method for improving transistor performance through reducing the salicide interface resistance |
Country Status (6)
Country | Link |
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US (9) | US6949482B2 (en) |
KR (1) | KR100810776B1 (en) |
CN (2) | CN101677110B (en) |
DE (1) | DE112004002409B4 (en) |
TW (1) | TWI257689B (en) |
WO (1) | WO2005062366A1 (en) |
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Also Published As
Publication number | Publication date |
---|---|
KR100810776B1 (en) | 2008-03-07 |
WO2005062366A1 (en) | 2005-07-07 |
US20050130454A1 (en) | 2005-06-16 |
US9437710B2 (en) | 2016-09-06 |
US9202889B2 (en) | 2015-12-01 |
US20160336447A1 (en) | 2016-11-17 |
US20110101418A1 (en) | 2011-05-05 |
DE112004002409T5 (en) | 2006-10-05 |
DE112004002409B4 (en) | 2010-05-20 |
US20050253200A1 (en) | 2005-11-17 |
US8482043B2 (en) | 2013-07-09 |
CN101677110A (en) | 2010-03-24 |
US9680016B2 (en) | 2017-06-13 |
US20110006344A1 (en) | 2011-01-13 |
US20150108546A1 (en) | 2015-04-23 |
KR20060123271A (en) | 2006-12-01 |
CN101677110B (en) | 2012-09-05 |
US9876113B2 (en) | 2018-01-23 |
CN100565823C (en) | 2009-12-02 |
TW200524090A (en) | 2005-07-16 |
US6949482B2 (en) | 2005-09-27 |
TWI257689B (en) | 2006-07-01 |
US20160336446A1 (en) | 2016-11-17 |
US20130302961A1 (en) | 2013-11-14 |
US7274055B2 (en) | 2007-09-25 |
CN1883040A (en) | 2006-12-20 |
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