US20080062286A1 - Method and apparatus for suppressing noise in image sensor devices - Google Patents
Method and apparatus for suppressing noise in image sensor devices Download PDFInfo
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- US20080062286A1 US20080062286A1 US11/470,657 US47065706A US2008062286A1 US 20080062286 A1 US20080062286 A1 US 20080062286A1 US 47065706 A US47065706 A US 47065706A US 2008062286 A1 US2008062286 A1 US 2008062286A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Definitions
- the present invention relates to image sensor devices formed in integrated circuits (ICs). More particularly, the invention relates to suppressing noise in the video and reset sample values obtained when sampling an IC image sensor device.
- FIG. 1 illustrates a schematic diagram of a known pixel 2 that has four transistors 3 - 6 , reset (RST), Transfer (TX) and Row control lines 7 , 8 and 9 , and a photodiode 11 .
- This pixel 2 is a four-transistor (4-T) buried gated photodiode device commonly referred to as a 4-T pinned photodiode pixel.
- an analog readout column line 12 External to the pixel 2 is an analog readout column line 12 , a current source 13 , a reset sampling switch 14 controlled by reset sampling signal S 1 , a capacitor C 15 , a video sampling switch 16 controlled by video sampling signal S 2 , and a capacitor C 17 .
- the reset sampling switch 14 connects and disconnects capacitor C 15 to and from the readout column line 12 .
- the video sampling switch 16 connects and disconnects capacitor C 17 to and from the readout column line 12 .
- FIG. 2 illustrates a timing diagram that demonstrates the operations of the pixel 2 during sampling of the reset and video sample values.
- the Row control signal 9 is asserted high.
- switch 14 is closed connecting the capacitor C 15 to the analog readout column line 12 .
- the RST control signal 7 then goes high.
- the TX control signal 8 and the video sampling signal S 2 are both low at this time.
- the RST control signal 7 is high, the RST transistor 3 is on and the floating diffusion (FD) node 18 is connected to the power supply, V DD , which turns on the source follower (SF) transistor 4 and causes a buffered voltage corresponding to the voltage on the FD node 18 to be driven onto the analog readout column line 12 .
- switch S 1 14 opens and stores the value of the analog readout column line 12 on the reset storage capacitor C 15 . This value is the reset sampling value of the pixel 2 .
- the video sampling signal S 2 goes high.
- switch 16 is closed connecting the capacitor C 17 to the analog readout column line 12 .
- the TX control signal 8 then goes high.
- the RST control signal 7 and the reset sampling signal S 1 are both low at this time.
- the TX control signal 8 goes high, the TX transistor 5 is turned on, connecting the photodiode 11 to the FD node 18 . Charge that had been previously integrated on the photodiode 11 due to light is transferred to the FD node 18 at this time.
- the SF transistor 4 is turned on. This causes the video sampling value, which corresponds to the value of the voltage on the FD node 18 at this time, to be driven onto the analog readout column line 12 .
- switch S 2 16 opens and stores the value of the analog readout column line 12 on the video storage capacitor C 17 . This value is the video sampling value of the pixel 2 .
- the reset sampling value stored on capacitor C 15 is sampled by sampling circuitry (not shown) and converted from an analog reset sampling value to a digital reset sampling value.
- the video sampling value stored on capacitor C 17 is sampled by sampling circuitry (not shown) and converted from an analog video sampling value to a digital video sampling value. The difference between the digital reset and video sampling values is then obtained, and this difference value corresponds to the pixel sample value.
- the only practical solution for reducing random telegraph noise is to increase the size of the SF transistor.
- Increasing the size of the SF transistor increases the overall size of the pixel, which is undesirable.
- increasing the size of the SF transistor also decreases the fill factor (i.e., the amount of area that is available for implementing the photodiode), which also is undesirable.
- a need exists for a way to eliminate or reduce random telegraph noise in image sensor devices.
- a need also exists for a way to eliminate or reduce random telegraph noise in image sensor devices without having to increase the size of the SF transistor and without having to reduce the pixel fill factor.
- the invention provides a method and an apparatus for reducing or eliminating noise in an image sensor device formed in an IC.
- the apparatus comprises an analog sampling circuit electrically connected to an output of a pixel.
- the analog sampling circuit obtains an average reset sampling value and an average video sampling value.
- the analog sampling circuit obtains the average reset sampling value by sampling a reset sampling level on the pixel output at different instants in time during a reset sampling phase to obtain a plurality of respective reset sampling values, and averaging the plurality of reset sampling values to produce the average reset sampling value.
- the analog sampling circuit obtains the average video sampling value by sampling a video sampling level on the pixel output at different instants in time during a video sampling phase to obtain a plurality of respective video sampling values, and averaging the plurality of video sampling values to produce the average video sampling value.
- the method comprises sampling a reset sampling level on an output of a pixel at different instants in time during a reset sampling phase to obtain a plurality of respective reset sampling values, averaging the plurality of reset sampling values to produce an average reset sampling value, sampling a video sampling level on the output of the pixel at different instants in time during a video sampling phase to obtain a plurality of respective video sampling values, and averaging the plurality of video sampling values to produce an average video sampling value.
- FIG. 1 illustrates a schematic diagram of a known four-transistor (4-T) buried gated photodiode device commonly referred to as a 4-T pinned photodiode pixel.
- FIG. 2 illustrates a timing diagram that demonstrates the timing of events during operations of the pixel shown in FIG. 1 .
- FIG. 3 illustrates a schematic diagram of a pixel that uses the analog sampling circuit of the invention to reduce or eliminate random telegraph noise.
- FIG. 4 illustrates a timing diagram that demonstrates the timing of events during operations of the pixel shown in FIG. 3 .
- FIG. 5 illustrates a flowchart that represents the method of the invention in accordance with an exemplary embodiment.
- an analog sampling circuit comprising a plurality of capacitors is used to sample the reset and video sampling levels at different instants in time to obtain average reset and video sampling values.
- FIG. 3 illustrates a schematic diagram of a pixel 22 having an output that is connected to an analog sampling circuit 50 of the invention.
- the analog sampling circuit 50 comprises a reset sampling circuit 60 and a video sampling circuit 70 .
- eight capacitors 62 - 69 are used in the reset sampling circuit 60 to sample the reset sampling level of the pixel 22 over respective timing intervals during the reset sampling period. These reset sampling values are then averaged to produce a reduced-noise reset sampling value, i.e., a reset sampling value from which random telegraph noise has been removed.
- eight capacitors 82 - 89 are used in the video sampling circuit 70 to sample the video sampling level of the pixel 22 over respective timing intervals during the video sampling period. These video sampling values are then averaged to produce a reduced-noise video sampling value.
- the reset sampling circuit 60 employs a switching configuration comprising switches S 1 Global and switches S 1 ( 1 )-S 1 ( 8 ).
- the video sampling circuit 70 employs a switching configuration comprising switches S 2 Global and switches S 2 ( 1 )-S 2 ( 8 ).
- the components 23 , 24 , 25 , 26 , 27 , 28 , 29 and 31 of the pixel 22 may be identical to the components 3 , 4 , 5 , 6 , 7 , 8 , 9 and 11 of the pixel 2 shown in FIG. 1 .
- the analog readout column line 33 and the current source 34 shown in FIG. 3 may be identical to the analog readout column line 12 and the current source 13 shown in FIG. 1 .
- the pixel 2 shown in FIG. 1 is a 4-T buried gated photodiode device. While the invention is suitable for use with this type of photodiode device, the invention is not limited with respect to the type of photodiode device with which the invention is implemented. The invention is being described with reference to a 4-T buried gated photodiode device for exemplary purposes and to demonstrate the principles and concepts of the invention.
- the Row control signal 29 is asserted high.
- S 1 Global goes high
- S 1 Global switch is closed.
- S 1 Global goes high
- all of the individual S 1 sampling signals S 1 ( 1 )-S 1 ( 8 ) also go high, causing all of the switches S 1 ( 1 )-S 1 ( 8 ) to close.
- the RST control signal 27 goes high just after the signals S 1 Global and S 1 ( 1 )-S 1 ( 8 ) go high.
- the TX control signal 28 and the video sampling signals S 2 Global and S 2 ( 1 )-S 2 ( 8 ) are all low at this time.
- the RST control signal 27 is high, the RST transistor 23 is on and the FD node 32 is connected to the power supply, V DD , which turns on the source follower (SF) transistor 24 and causes a buffered voltage corresponding to the voltage on the FD node 32 to be driven onto the analog readout column line 33 .
- the capacitors 62 - 69 are then disconnected by opening the S 1 ( 1 )-S 1 ( 8 ) switches one at a time, as indicated in the timing diagram by the S 1 ( 1 )-S 1 ( 8 ) signals going low one at a time.
- each of the capacitors 62 - 69 samples the reset sampling value from the analog readout column line 33 over a respective timing interval during the reset sampling period.
- the global switch S 1 GLOBAL is opened and all of the S 1 ( 1 )-S 1 ( 8 ) switches are closed simultaneously (not shown), thereby causing the values stored on the capacitors 62 - 69 to be redistributed such that each capacitor has an average reset sampling value stored on it.
- This average reset sampling value contains a reduced level of random telegraph noise and is subsequently used by circuitry downstream (not shown) to obtain the difference between the average reset and average video sampling values.
- the SF transistor 24 is turned on, causing the video sampling value, which corresponds to the value of the voltage on the FD node 32 at this time, to be driven onto the analog readout column line 33 .
- the capacitors 82 - 89 are then disconnected one at a time by opening the S 2 ( 1 )-S 2 ( 8 ) switches one at a time, as indicated in the timing diagram by the S 2 ( 1 )-S 2 ( 8 ) signals going low one after the other.
- each of the capacitors 82 - 89 samples the video sampling value over a respective timing interval during the video sampling period.
- the global switch S 2 Global is opened and all of the S 2 ( 1 )-S 2 ( 8 ) switches are closed simultaneously (not shown), thereby causing the values stored on the capacitors 82 - 89 to be redistributed such that each capacitor has an average video sampling value stored on it.
- This average video sampling value has a reduced level of random telegraph noise and is subsequently used by circuitry downstream (not shown) to obtain the difference between the average reset and average video sampling values.
- the analog sampling circuit 50 is shown as having eight reset sampling capacitors 62 - 69 and eight video sampling capacitors 82 - 89 .
- the invention is not limited to the configuration shown. Any configuration that is capable of sampling the reset and video levels over time and averaging the sampling values to obtain average reset and video sampling values is suitable for achieving the goals of the invention.
- One of the advantages of the configuration of the analog sampling circuit 50 shown in FIG. 3 is that it generally requires the same amount of area on the IC as that required by the components 14 - 17 shown in FIG. 1 .
- each of the capacitors 62 - 69 consumes only one eighth of the amount of space consumed by the capacitor 15 , i.e., all of the capacitors 62 - 69 combined consume the same amount of area as that consumed by the single capacitor 15 .
- each of the capacitors 82 - 89 consumes only one eighth of the amount of space consumed by the capacitor 17 , i.e., all of the capacitors 82 - 89 combined consume the same amount of area as that consumed by the single capacitor 17 . Consequently, the invention provides a solution for eliminating or at least substantially reducing random telegraph noise that does not increase the overall size of the image sensor device and does not reduce the fill factor of the image sensor device.
- FIG. 5 illustrates a flowchart that demonstrates the method of the invention in accordance with an exemplary embodiment.
- a reset sampling level on an output of a pixel is sampled at different instants in time during a reset sampling phase to obtain a plurality of respective reset sampling values, as indicated by block 101 .
- the reset sampling values are averaged to produce an average reset sampling value, as indicated by block 102 .
- a video sampling level on the output of the pixel is sampled at different instants in time during a video sampling phase to obtain a plurality of respective video sampling values, as indicated by block 103 .
- the video sampling values are averaged to produce an average video sampling value, as indicated by block 104 .
- the invention is not limited with respect to the order in which the steps represented by blocks 101 - 104 are performed. For example, the steps represented by blocks 103 and 104 may be performed before the steps represented by blocks 101 and 102 are performed.
Abstract
Description
- The present invention relates to image sensor devices formed in integrated circuits (ICs). More particularly, the invention relates to suppressing noise in the video and reset sample values obtained when sampling an IC image sensor device.
- Image sensor devices contained in ICs are made up of arrays of pixels. Each pixel comprises a plurality of transistors that function as gates, signal control lines that control the operations of the pixel through switching of the gates, and a photodiode that receives light and produces electrical signals in response to the received light.
FIG. 1 illustrates a schematic diagram of a knownpixel 2 that has four transistors 3-6, reset (RST), Transfer (TX) andRow control lines pixel 2 is a four-transistor (4-T) buried gated photodiode device commonly referred to as a 4-T pinned photodiode pixel. External to thepixel 2 is an analogreadout column line 12, acurrent source 13, areset sampling switch 14 controlled by reset sampling signal S1, acapacitor C 15, avideo sampling switch 16 controlled by video sampling signal S2, and acapacitor C 17. Thereset sampling switch 14 connects and disconnectscapacitor C 15 to and from thereadout column line 12. Likewise, thevideo sampling switch 16 connects and disconnectscapacitor C 17 to and from thereadout column line 12. -
FIG. 2 illustrates a timing diagram that demonstrates the operations of thepixel 2 during sampling of the reset and video sample values. To sample thepixel 2, theRow control signal 9 is asserted high. When the reset sampling signal S1 goes high,switch 14 is closed connecting thecapacitor C 15 to the analogreadout column line 12. TheRST control signal 7 then goes high. The TXcontrol signal 8 and the video sampling signal S2 are both low at this time. When theRST control signal 7 is high, theRST transistor 3 is on and the floating diffusion (FD)node 18 is connected to the power supply, VDD, which turns on the source follower (SF)transistor 4 and causes a buffered voltage corresponding to the voltage on theFD node 18 to be driven onto the analogreadout column line 12. When the reset sampling signal S1 goes low,switch S1 14 opens and stores the value of the analogreadout column line 12 on the resetstorage capacitor C 15. This value is the reset sampling value of thepixel 2. - After reset sampling signal S1 goes low, the video sampling signal S2 goes high. When the video sampling signal S2 goes high,
switch 16 is closed connecting thecapacitor C 17 to the analogreadout column line 12. The TXcontrol signal 8 then goes high. TheRST control signal 7 and the reset sampling signal S1 are both low at this time. When theTX control signal 8 goes high, theTX transistor 5 is turned on, connecting the photodiode 11 to theFD node 18. Charge that had been previously integrated on the photodiode 11 due to light is transferred to theFD node 18 at this time. TheSF transistor 4 is turned on. This causes the video sampling value, which corresponds to the value of the voltage on theFD node 18 at this time, to be driven onto the analogreadout column line 12. When video sampling signal S2 goes low,switch S2 16 opens and stores the value of the analogreadout column line 12 on the video storage capacitor C17. This value is the video sampling value of thepixel 2. - On the falling edge of the reset sampling signal S1 (indicated by dashed line 19), the reset sampling value stored on
capacitor C 15 is sampled by sampling circuitry (not shown) and converted from an analog reset sampling value to a digital reset sampling value. Likewise, on the falling edge of the video sampling signal S2 (indicated by dashed line 21), the video sampling value stored oncapacitor C 17 is sampled by sampling circuitry (not shown) and converted from an analog video sampling value to a digital video sampling value. The difference between the digital reset and video sampling values is then obtained, and this difference value corresponds to the pixel sample value. - In the image sensor industry, efforts are continuously being made to reduce the amount of area consumed by the transistors, signal control lines and readout circuitry of the pixels. At the same time, efforts are also being made to increase the photodiode area. As the area of the SF transistor in the pixel decreases, temporal fluctuations in the threshold voltage of the SF transistor increase. Because of the temporal variation in the threshold voltage of the SF transistor, the threshold voltage may not be the same when the reset sampling value and the video sampling value are taken. The temporal variation in threshold voltage of each pixel results in random noise in the reset and video sampling values, which, of course, is undesirable. This type of noise is sometimes referred to in the image sensor industry as random telegraph noise. In addition, as the transistors are made increasingly smaller, the differences between the threshold voltages that can exist when the reset sampling value and the video sampling value are taken also increase, which increases the amount of telegraph noise contained in the reset and video sampling values.
- Currently, the only practical solution for reducing random telegraph noise is to increase the size of the SF transistor. Increasing the size of the SF transistor, however, increases the overall size of the pixel, which is undesirable. In addition, increasing the size of the SF transistor also decreases the fill factor (i.e., the amount of area that is available for implementing the photodiode), which also is undesirable.
- Accordingly, a need exists for a way to eliminate or reduce random telegraph noise in image sensor devices. A need also exists for a way to eliminate or reduce random telegraph noise in image sensor devices without having to increase the size of the SF transistor and without having to reduce the pixel fill factor.
- The invention provides a method and an apparatus for reducing or eliminating noise in an image sensor device formed in an IC. The apparatus comprises an analog sampling circuit electrically connected to an output of a pixel. The analog sampling circuit obtains an average reset sampling value and an average video sampling value. The analog sampling circuit obtains the average reset sampling value by sampling a reset sampling level on the pixel output at different instants in time during a reset sampling phase to obtain a plurality of respective reset sampling values, and averaging the plurality of reset sampling values to produce the average reset sampling value. The analog sampling circuit obtains the average video sampling value by sampling a video sampling level on the pixel output at different instants in time during a video sampling phase to obtain a plurality of respective video sampling values, and averaging the plurality of video sampling values to produce the average video sampling value.
- The method comprises sampling a reset sampling level on an output of a pixel at different instants in time during a reset sampling phase to obtain a plurality of respective reset sampling values, averaging the plurality of reset sampling values to produce an average reset sampling value, sampling a video sampling level on the output of the pixel at different instants in time during a video sampling phase to obtain a plurality of respective video sampling values, and averaging the plurality of video sampling values to produce an average video sampling value.
- These and other features and advantages of the invention will become apparent from the following description, drawings and claims.
-
FIG. 1 illustrates a schematic diagram of a known four-transistor (4-T) buried gated photodiode device commonly referred to as a 4-T pinned photodiode pixel. -
FIG. 2 illustrates a timing diagram that demonstrates the timing of events during operations of the pixel shown inFIG. 1 . -
FIG. 3 illustrates a schematic diagram of a pixel that uses the analog sampling circuit of the invention to reduce or eliminate random telegraph noise. -
FIG. 4 illustrates a timing diagram that demonstrates the timing of events during operations of the pixel shown inFIG. 3 . -
FIG. 5 illustrates a flowchart that represents the method of the invention in accordance with an exemplary embodiment. - In accordance with the invention, an analog sampling circuit comprising a plurality of capacitors is used to sample the reset and video sampling levels at different instants in time to obtain average reset and video sampling values. By averaging the reset and video sampling levels over time, random telegraph noise in the reset and video sampling values is eliminated or at least substantially reduced.
-
FIG. 3 illustrates a schematic diagram of apixel 22 having an output that is connected to ananalog sampling circuit 50 of the invention. Theanalog sampling circuit 50 comprises areset sampling circuit 60 and avideo sampling circuit 70. In accordance with this exemplary embodiment, eight capacitors 62-69 are used in thereset sampling circuit 60 to sample the reset sampling level of thepixel 22 over respective timing intervals during the reset sampling period. These reset sampling values are then averaged to produce a reduced-noise reset sampling value, i.e., a reset sampling value from which random telegraph noise has been removed. Likewise, eight capacitors 82-89 are used in thevideo sampling circuit 70 to sample the video sampling level of thepixel 22 over respective timing intervals during the video sampling period. These video sampling values are then averaged to produce a reduced-noise video sampling value. - The
reset sampling circuit 60 employs a switching configuration comprising switches S1 Global and switches S1(1)-S1(8). Thevideo sampling circuit 70 employs a switching configuration comprising switches S2 Global and switches S2(1)-S2(8). Thecomponents pixel 22 may be identical to thecomponents pixel 2 shown inFIG. 1 . The analogreadout column line 33 and thecurrent source 34 shown inFIG. 3 may be identical to the analogreadout column line 12 and thecurrent source 13 shown inFIG. 1 . - As stated above, the
pixel 2 shown inFIG. 1 is a 4-T buried gated photodiode device. While the invention is suitable for use with this type of photodiode device, the invention is not limited with respect to the type of photodiode device with which the invention is implemented. The invention is being described with reference to a 4-T buried gated photodiode device for exemplary purposes and to demonstrate the principles and concepts of the invention. - The manner in which the
pixel 22 andanalog sampling circuit 50 operate will now be described with reference toFIG. 3 and with reference to the timing diagram shown inFIG. 4 . To sample thepixel 22, theRow control signal 29 is asserted high. When the reset sampling signal S1 Global goes high, S1 Global switch is closed. When S1 Global goes high, all of the individual S1 sampling signals S1(1)-S1(8) also go high, causing all of the switches S1(1)-S1(8) to close. TheRST control signal 27 goes high just after the signals S1 Global and S1(1)-S1(8) go high. TheTX control signal 28 and the video sampling signals S2 Global and S2(1)-S2(8) are all low at this time. When theRST control signal 27 is high, theRST transistor 23 is on and theFD node 32 is connected to the power supply, VDD, which turns on the source follower (SF)transistor 24 and causes a buffered voltage corresponding to the voltage on theFD node 32 to be driven onto the analogreadout column line 33. The capacitors 62-69 are then disconnected by opening the S1(1)-S1(8) switches one at a time, as indicated in the timing diagram by the S1(1)-S1(8) signals going low one at a time. Thus, each of the capacitors 62-69 samples the reset sampling value from the analogreadout column line 33 over a respective timing interval during the reset sampling period. Subsequent to this sampling sequence, the global switch S1 GLOBAL is opened and all of the S1(1)-S1(8) switches are closed simultaneously (not shown), thereby causing the values stored on the capacitors 62-69 to be redistributed such that each capacitor has an average reset sampling value stored on it. This average reset sampling value contains a reduced level of random telegraph noise and is subsequently used by circuitry downstream (not shown) to obtain the difference between the average reset and average video sampling values. - After reset sampling signals S1 Global and S1(1)-S1(8) go low, the video sampling signals S2 Global and S2(1)-S2(8) go high, causing the S2 Global switch and the S2(1)-S2(8) switches to close. The
TX control signal 28 then goes high. TheRST control signal 27 and the reset sampling signals S1 Global and S1(1)-S1(8) are all low at this time. When theTX control signal 28 goes high, theTX transistor 25 is turned on, connecting thephotodiode 31 to theFD node 32. Charge that had been previously integrated on thephotodiode 31 due to light is transferred to theFD node 32 at this time. TheSF transistor 24 is turned on, causing the video sampling value, which corresponds to the value of the voltage on theFD node 32 at this time, to be driven onto the analogreadout column line 33. The capacitors 82-89 are then disconnected one at a time by opening the S2(1)-S2(8) switches one at a time, as indicated in the timing diagram by the S2(1)-S2(8) signals going low one after the other. Thus, each of the capacitors 82-89 samples the video sampling value over a respective timing interval during the video sampling period. Subsequent to this sampling process, the global switch S2 Global is opened and all of the S2(1)-S2(8) switches are closed simultaneously (not shown), thereby causing the values stored on the capacitors 82-89 to be redistributed such that each capacitor has an average video sampling value stored on it. This average video sampling value has a reduced level of random telegraph noise and is subsequently used by circuitry downstream (not shown) to obtain the difference between the average reset and average video sampling values. - In
FIG. 3 , theanalog sampling circuit 50 is shown as having eight reset sampling capacitors 62-69 and eight video sampling capacitors 82-89. The invention is not limited to the configuration shown. Any configuration that is capable of sampling the reset and video levels over time and averaging the sampling values to obtain average reset and video sampling values is suitable for achieving the goals of the invention. One of the advantages of the configuration of theanalog sampling circuit 50 shown inFIG. 3 is that it generally requires the same amount of area on the IC as that required by the components 14-17 shown inFIG. 1 . This is because each of the capacitors 62-69 consumes only one eighth of the amount of space consumed by thecapacitor 15, i.e., all of the capacitors 62-69 combined consume the same amount of area as that consumed by thesingle capacitor 15. Likewise, each of the capacitors 82-89 consumes only one eighth of the amount of space consumed by thecapacitor 17, i.e., all of the capacitors 82-89 combined consume the same amount of area as that consumed by thesingle capacitor 17. Consequently, the invention provides a solution for eliminating or at least substantially reducing random telegraph noise that does not increase the overall size of the image sensor device and does not reduce the fill factor of the image sensor device. -
FIG. 5 illustrates a flowchart that demonstrates the method of the invention in accordance with an exemplary embodiment. A reset sampling level on an output of a pixel is sampled at different instants in time during a reset sampling phase to obtain a plurality of respective reset sampling values, as indicated byblock 101. The reset sampling values are averaged to produce an average reset sampling value, as indicated byblock 102. A video sampling level on the output of the pixel is sampled at different instants in time during a video sampling phase to obtain a plurality of respective video sampling values, as indicated byblock 103. The video sampling values are averaged to produce an average video sampling value, as indicated byblock 104. It should be noted that the invention is not limited with respect to the order in which the steps represented by blocks 101-104 are performed. For example, the steps represented byblocks blocks - It should be noted that the invention has been described with reference to a few example embodiments and that the present invention is not limited to these embodiments. The embodiments described herein are meant to convey the principles and concepts of the present invention and are not intended to demonstrate exclusive embodiments for carrying out the invention. For example, the invention is not limited to the particular configuration shown in
FIG. 3 or to the timing of events represented by the timing diagram shown inFIG. 4 . Other modifications may be made to the embodiments described herein and all such modifications are within the scope of the present invention.
Claims (9)
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Also Published As
Publication number | Publication date |
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US7688366B2 (en) | 2010-03-30 |
EP2062431B1 (en) | 2016-03-16 |
WO2008030327A2 (en) | 2008-03-13 |
TW200818483A (en) | 2008-04-16 |
EP2062431A2 (en) | 2009-05-27 |
WO2008030327A3 (en) | 2008-06-05 |
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