US20080087980A1 - Semiconductor device and method for fabricating a semiconductor device - Google Patents

Semiconductor device and method for fabricating a semiconductor device Download PDF

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US20080087980A1
US20080087980A1 US11/999,466 US99946607A US2008087980A1 US 20080087980 A1 US20080087980 A1 US 20080087980A1 US 99946607 A US99946607 A US 99946607A US 2008087980 A1 US2008087980 A1 US 2008087980A1
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semiconductor
semiconductor device
insulation layers
semiconductor layer
patterned
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Jun-hee Cho
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Definitions

  • An embodiment of the invention relates to semiconductor device fabrication technologies. Other embodiments are also described and claimed.
  • semiconductor devices typically include a number of unit devices or cells. As the semiconductor devices become highly integrated, the unit devices should be formed with high density on a fixed cell area. Accordingly, the sizes of the unit devices, e.g., transistors and capacitors, have decreased. In semiconductor devices such as dynamic random access memory (DRAM) devices, as the design rule has been decreased, the sizes of the unit devices formed inside of the cell have also decreased. Recently, the unit device has reached a minimum line width that is smaller than 0.1 ⁇ m, e.g. smaller than 70 nm. Accordingly, a length of a transistor channel has been shortened due to the decreased design rule, thereby inducing a decrease in refresh time.
  • DRAM dynamic random access memory
  • FIG. 1 is a cross-sectional view illustrating a process for fabricating a conventional semiconductor device.
  • multiple device isolation layers 102 in a substrate 101 on either side of an active region are formed.
  • a shallow trench isolation (STI) process is performed in the substrate 101 , thereby forming a trench. Then, a buffer oxide layer, a nitride layer for insulation, and a liner oxide layer are sequentially deposited into the trench and afterwards, a high density plasma (HDP) oxide layer is buried into the trench through a chemical vapor deposition (CVD) method.
  • STI shallow trench isolation
  • the HDP oxide layer is planarized by performing a chemical mechanical polishing (CMP) process and afterwards, the buffer oxide layer, the nitride layer for the insulation, and the liner oxide layer existing on the substrate 101 except for the trench are removed, thereby forming the device isolation layers 102 .
  • CMP chemical mechanical polishing
  • a gate insulation layer 103 and a gate conductive layer 104 are sequentially deposited on the substrate 101 provided with the device isolation layers 102 and then, a selective etching process is performed, thereby forming a gate pattern 105 on the active region of the substrate 101 .
  • a plurality of source/drain regions 106 are formed.
  • a plurality of spacers 107 are formed on sidewalls of the gate pattern 105 .
  • the conventional semiconductor unit device induces limitations including a junction leakage and a short channel effect as a DRAM device has been highly integrated.
  • an increase in a parasitic capacitance and degradation in a punch through property may occur, thereby degrading a refresh property of the DRAM device.
  • An embodiment of the invention is a semiconductor device that may be capable of improving a refresh property through a decrease in a parasitic capacitance and an improvement of a punch through property. A method for fabricating such a device is also described.
  • a semiconductor device including: a semiconductor structure providing an active region by being formed on a substrate, and including recessed portions formed at lower edges of lateral portions of the semiconductor structure; a number of patterned first insulation layers for device isolation buried into the recessed portions; and a number of second insulation layers for device isolation formed on sidewalls of the first insulation layers and the semiconductor structure.
  • a semiconductor device including: a semiconductor structure providing an active region by being formed on a substrate and including recessed portions formed at lower edges of lateral portions of the semiconductor structure; and a number of insulation layers for device isolation formed to be aligned with upper edges of the semiconductor structure.
  • a method for fabricating a semiconductor device including: forming a number of patterned first insulation layers opening a predetermined portion on a substrate; forming a first semiconductor layer on the predetermined portion between the patterned first insulation layers; forming a second semiconductor layer on the first semiconductor layer and the patterned first insulation layers; selectively etching the second semiconductor layer and the patterned first insulation layers, thereby obtaining a stacked structure; and forming a plurality of second insulation layers on sidewalls of the stacked structure.
  • a method for fabricating a semiconductor device including: forming a number of patterned first insulation layers opening a predetermined portion on a substrate; forming a first semiconductor layer on the predetermined portion between the patterned first insulation layers; forming a second semiconductor layer on the first semiconductor layer and the patterned first insulation layers; selectively etching the second semiconductor layer and the patterned first insulation layers; removing the patterned first insulation layers; and forming a plurality of second insulation layers to be aligned with sidewalls of the selectively etched second semiconductor layer.
  • FIG. 1 is a cross-sectional view illustrating a fabrication process of a conventional semiconductor device
  • FIGS. 2A to 2 E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a first embodiment of the present invention
  • FIGS. 3A to 3 E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a second embodiment of the present invention.
  • FIG. 4 is a graph exhibiting comparison results of a parasitic capacitance of a word line of the conventional semiconductor device and a semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 5 is a graph exhibiting a punch through property of the conventional semiconductor device and a semiconductor device in accordance with an embodiment of the present invention.
  • FIGS. 2A to 2 E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a first embodiment of the present invention.
  • a number of patterned first insulation layers 202 are deposited on a substrate 201 .
  • the formation of the patterned first insulation layers 202 is explained as follows. First, although not shown, a first insulation layer is formed on the substrate 201 and then, the first insulation layer is selectively etched to open regions in which first semiconductor layers will be formed.
  • the patterned first insulation layers 202 are dielectric layers including an oxide layer and a nitride layer.
  • a plurality of first semiconductor layers 203 are formed in the opened regions between the patterned first insulation layers 202 .
  • the first semiconductor layers 203 are single crystal silicon formed by performing one of a solid phase epitaxy (SPE) process and a silicon epitaxy growth (SEG) process.
  • SPE solid phase epitaxy
  • SEG silicon epitaxy growth
  • a second semiconductor layer 204 is formed on the first semiconductor layers 203 and the patterned first insulation layers 202 .
  • the second semiconductor layer 204 is silicon formed by performing an epitaxial lateral overgrowth (ELO) process.
  • ELO epitaxial lateral overgrowth
  • a number of photoresist patterns 205 are formed to etch the second semiconductor layer 204 and the patterned first insulation layers 202 .
  • the second semiconductor layer 204 and the patterned first insulation layers 202 are etched by using the photoresist patterns 205 as an etch barrier.
  • reference numerals 204 A and 202 A denote the patterned second semiconductor layers and the further patterned first insulation layers, respectively.
  • a number of second insulation layers 206 in contact with side walls of the patterned second semiconductor layers 204 A and the further patterned first insulation layers 202 A are formed on the substrate 201 which is exposed due to the aforementioned etching process.
  • the second insulation layers 206 are HDP layers formed through a CVD method.
  • a number of gate insulation layers 207 and a plurality of gate conductive layers 208 are sequentially formed on the substrate 201 provided with the second insulation layers 206 . Then, the gate insulation layers 207 and the gate conductive layers 208 are selectively etched, thereby forming a number of gate patterns 209 .
  • a plurality of source/drain regions are formed in the patterned second semiconductor layers 204 A exposed on both sides of the gate patterns 209 .
  • FIGS. 3A to 3 E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a second embodiment of the present invention.
  • a number of patterned first insulation layers 302 are deposited on a substrate 301 .
  • the formation of the patterned first insulation layers 302 is explained as follows. First, although not shown, a first insulation layer is deposited on the substrate 301 and then, the first insulation layer is selectively etched to open regions in which first semiconductor layers will be formed.
  • the patterned first insulation layer 302 is a dielectric layer including an oxide layer and a nitride layer.
  • a number of first semiconductor layers 303 are formed in the opened regions between the patterned first insulation layers 302 .
  • the first semiconductor layers 303 are single crystal silicon formed by performing one of a SPE process and a SEG process.
  • a second semiconductor layer 304 is formed on the first semiconductor layers 303 and the patterned first insulation layers 302 .
  • the second semiconductor layer 304 is silicon formed by performing an ELO process.
  • a number of photoresist patterns 305 are formed to etch the second semiconductor layer 304 and the patterned first insulation layers 302 .
  • the second semiconductor layer 304 and the patterned first insulation layers 302 are etched by using the photoresist patterns 305 as an etch barrier.
  • reference numeral 304 A denotes the patterned second semiconductor layers.
  • the photoresist patterns 305 are removed and then, the patterned first insulation layers 302 are removed.
  • a number of second insulation layers 306 are formed on the substrate 301 (which is exposed due to the aforementioned etching process) to be aligned with both edges of the patterned second semiconductor layers 304 A.
  • the second insulation layers 306 are HDP layers formed through a CVD method.
  • regions in which the further patterned first insulation layers 302 A are removed become a number of void regions 307 .
  • a number of gate insulation layers 308 and a number of gate conductive layers 309 are sequentially deposited on the substrate 301 provided with the second insulation layers 306 .
  • a number of source/drain regions (not shown) are formed in the patterned second semiconductor layers 304 A and afterwards, a number of spacers 311 are formed on sidewalls of the gate patterns 310 .
  • FIG. 4 is a graph exhibiting comparison results of parasitic capacitance of word lines of a conventional semiconductor device and a semiconductor device in accordance with the present invention.
  • the parasitic capacitance of the word line of the conventional semiconductor device group A is larger than that of the semiconductor device group B in accordance with an embodiment of the present invention.
  • the conventional semiconductor device group may operate slower than the semiconductor device group in accordance with an embodiment of the present invention.
  • FIG. 5 is a graph exhibiting comparison results of punch through properties of a conventional semiconductor device and a semiconductor device in accordance with the present invention.
  • FIG. 5 it is shown that the punch through property of the conventional semiconductor group C is worse than that of the semiconductor device group D which is in accordance with an embodiment of the present invention.
  • the punch through property is not shown in a predetermined portion of the semiconductor device group B (which is in accordance with an embodiment of the present invention), even at a threshold voltage of approximately 0.75V.
  • a device isolation region of a substrate is largely formed to improve parasitic capacitance and a punch through property.
  • a refresh time property can be improved due to improvements in the low parasitic capacitance and the punch through property according to a threshold voltage.
  • a region in which a device isolation region and an active region of a substrate are two-dimensionally overlapped with each other is formed.
  • a refresh time property can be improved due to improvements in the low parasitic capacitance and the punch through property according to a threshold voltage.

Abstract

A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.

Description

    FIELD OF THE INVENTION
  • An embodiment of the invention relates to semiconductor device fabrication technologies. Other embodiments are also described and claimed.
    • DESCRIPTION OF RELATED ARTS
  • Typically, semiconductor devices include a number of unit devices or cells. As the semiconductor devices become highly integrated, the unit devices should be formed with high density on a fixed cell area. Accordingly, the sizes of the unit devices, e.g., transistors and capacitors, have decreased. In semiconductor devices such as dynamic random access memory (DRAM) devices, as the design rule has been decreased, the sizes of the unit devices formed inside of the cell have also decreased. Recently, the unit device has reached a minimum line width that is smaller than 0.1 μm, e.g. smaller than 70 nm. Accordingly, a length of a transistor channel has been shortened due to the decreased design rule, thereby inducing a decrease in refresh time.
  • FIG. 1 is a cross-sectional view illustrating a process for fabricating a conventional semiconductor device.
  • As shown in FIG. 1, multiple device isolation layers 102 in a substrate 101 on either side of an active region are formed.
  • Regarding the formation of the device isolation layers 102, a shallow trench isolation (STI) process is performed in the substrate 101, thereby forming a trench. Then, a buffer oxide layer, a nitride layer for insulation, and a liner oxide layer are sequentially deposited into the trench and afterwards, a high density plasma (HDP) oxide layer is buried into the trench through a chemical vapor deposition (CVD) method.
  • Next, the HDP oxide layer is planarized by performing a chemical mechanical polishing (CMP) process and afterwards, the buffer oxide layer, the nitride layer for the insulation, and the liner oxide layer existing on the substrate 101 except for the trench are removed, thereby forming the device isolation layers 102.
  • Next, a gate insulation layer 103 and a gate conductive layer 104 are sequentially deposited on the substrate 101 provided with the device isolation layers 102 and then, a selective etching process is performed, thereby forming a gate pattern 105 on the active region of the substrate 101.
  • Next, impurities are implanted into the substrate 101 exposed on both sides of the gate pattern 105 and thus, a plurality of source/drain regions 106 are formed. Afterwards, a plurality of spacers 107 are formed on sidewalls of the gate pattern 105.
  • The conventional semiconductor unit device induces limitations including a junction leakage and a short channel effect as a DRAM device has been highly integrated.
  • Furthermore, due to the aforementioned limitations, an increase in a parasitic capacitance and degradation in a punch through property may occur, thereby degrading a refresh property of the DRAM device.
    • SUMMARY OF THE INVENTION
  • An embodiment of the invention is a semiconductor device that may be capable of improving a refresh property through a decrease in a parasitic capacitance and an improvement of a punch through property. A method for fabricating such a device is also described.
  • In accordance with one aspect of the present invention, there is provided a semiconductor device, including: a semiconductor structure providing an active region by being formed on a substrate, and including recessed portions formed at lower edges of lateral portions of the semiconductor structure; a number of patterned first insulation layers for device isolation buried into the recessed portions; and a number of second insulation layers for device isolation formed on sidewalls of the first insulation layers and the semiconductor structure.
  • In accordance with another aspect of the present invention, there is provided a semiconductor device, including: a semiconductor structure providing an active region by being formed on a substrate and including recessed portions formed at lower edges of lateral portions of the semiconductor structure; and a number of insulation layers for device isolation formed to be aligned with upper edges of the semiconductor structure.
  • In accordance with further aspect of the present invention, there is provided a method for fabricating a semiconductor device, including: forming a number of patterned first insulation layers opening a predetermined portion on a substrate; forming a first semiconductor layer on the predetermined portion between the patterned first insulation layers; forming a second semiconductor layer on the first semiconductor layer and the patterned first insulation layers; selectively etching the second semiconductor layer and the patterned first insulation layers, thereby obtaining a stacked structure; and forming a plurality of second insulation layers on sidewalls of the stacked structure.
  • In accordance with still further aspect of the present invention, there is provided a method for fabricating a semiconductor device, including: forming a number of patterned first insulation layers opening a predetermined portion on a substrate; forming a first semiconductor layer on the predetermined portion between the patterned first insulation layers; forming a second semiconductor layer on the first semiconductor layer and the patterned first insulation layers; selectively etching the second semiconductor layer and the patterned first insulation layers; removing the patterned first insulation layers; and forming a plurality of second insulation layers to be aligned with sidewalls of the selectively etched second semiconductor layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a cross-sectional view illustrating a fabrication process of a conventional semiconductor device;
  • FIGS. 2A to 2E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a first embodiment of the present invention;
  • FIGS. 3A to 3E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a second embodiment of the present invention;
  • FIG. 4 is a graph exhibiting comparison results of a parasitic capacitance of a word line of the conventional semiconductor device and a semiconductor device in accordance with an embodiment of the present invention; and
  • FIG. 5 is a graph exhibiting a punch through property of the conventional semiconductor device and a semiconductor device in accordance with an embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Hereinafter, detailed descriptions on certain embodiments of the present invention will be provided with reference to the accompanying drawings.
  • FIGS. 2A to 2E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a first embodiment of the present invention.
  • In accordance with the first embodiment of the present invention, as shown in FIG. 2A, a number of patterned first insulation layers 202 are deposited on a substrate 201. The formation of the patterned first insulation layers 202 is explained as follows. First, although not shown, a first insulation layer is formed on the substrate 201 and then, the first insulation layer is selectively etched to open regions in which first semiconductor layers will be formed.
  • At this time, it is preferable that the patterned first insulation layers 202 are dielectric layers including an oxide layer and a nitride layer.
  • Next, as shown in FIG. 2B, a plurality of first semiconductor layers 203 are formed in the opened regions between the patterned first insulation layers 202.
  • At this time, it is preferable that the first semiconductor layers 203 are single crystal silicon formed by performing one of a solid phase epitaxy (SPE) process and a silicon epitaxy growth (SEG) process.
  • Next, as shown in FIG. 2C, a second semiconductor layer 204 is formed on the first semiconductor layers 203 and the patterned first insulation layers 202.
  • It is preferable that the second semiconductor layer 204 is silicon formed by performing an epitaxial lateral overgrowth (ELO) process.
  • Next, a number of photoresist patterns 205 are formed to etch the second semiconductor layer 204 and the patterned first insulation layers 202.
  • Next, as shown in FIG. 2D, the second semiconductor layer 204 and the patterned first insulation layers 202 are etched by using the photoresist patterns 205 as an etch barrier. Herein, reference numerals 204A and 202A denote the patterned second semiconductor layers and the further patterned first insulation layers, respectively.
  • Next, the photoresist patterns 205 are removed.
  • Next, as shown in FIG. 2E, a number of second insulation layers 206 in contact with side walls of the patterned second semiconductor layers 204A and the further patterned first insulation layers 202A are formed on the substrate 201 which is exposed due to the aforementioned etching process.
  • At this time, it is preferable that the second insulation layers 206 are HDP layers formed through a CVD method.
  • Next, a number of gate insulation layers 207 and a plurality of gate conductive layers 208 are sequentially formed on the substrate 201 provided with the second insulation layers 206. Then, the gate insulation layers 207 and the gate conductive layers 208 are selectively etched, thereby forming a number of gate patterns 209.
  • Next, a plurality of source/drain regions (not shown) are formed in the patterned second semiconductor layers 204A exposed on both sides of the gate patterns 209.
  • FIGS. 3A to 3E are cross-sectional views illustrating a fabrication process of a semiconductor device in accordance with a second embodiment of the present invention.
  • In accordance with the second embodiment of the present invention, as shown in FIG. 3A, a number of patterned first insulation layers 302 are deposited on a substrate 301. The formation of the patterned first insulation layers 302 is explained as follows. First, although not shown, a first insulation layer is deposited on the substrate 301 and then, the first insulation layer is selectively etched to open regions in which first semiconductor layers will be formed.
  • At this time, it is preferable that the patterned first insulation layer 302 is a dielectric layer including an oxide layer and a nitride layer.
  • Next, as shown in FIG. 3B, a number of first semiconductor layers 303 are formed in the opened regions between the patterned first insulation layers 302.
  • At this time, it is preferable that the first semiconductor layers 303 are single crystal silicon formed by performing one of a SPE process and a SEG process.
  • Next, as shown in FIG. 3C, a second semiconductor layer 304 is formed on the first semiconductor layers 303 and the patterned first insulation layers 302.
  • It is preferable that the second semiconductor layer 304 is silicon formed by performing an ELO process.
  • Next, a number of photoresist patterns 305 are formed to etch the second semiconductor layer 304 and the patterned first insulation layers 302.
  • Next, as shown in FIG. 3D, the second semiconductor layer 304 and the patterned first insulation layers 302 are etched by using the photoresist patterns 305 as an etch barrier. Herein, reference numeral 304A denotes the patterned second semiconductor layers.
  • Next, the photoresist patterns 305 are removed and then, the patterned first insulation layers 302 are removed.
  • Next, as shown in FIG. 3E, a number of second insulation layers 306 are formed on the substrate 301 (which is exposed due to the aforementioned etching process) to be aligned with both edges of the patterned second semiconductor layers 304A.
  • At this time, it is preferable that the second insulation layers 306 are HDP layers formed through a CVD method.
  • Furthermore, regions in which the further patterned first insulation layers 302A are removed become a number of void regions 307.
  • Next, a number of gate insulation layers 308 and a number of gate conductive layers 309 are sequentially deposited on the substrate 301 provided with the second insulation layers 306.
  • Next, a number of source/drain regions (not shown) are formed in the patterned second semiconductor layers 304A and afterwards, a number of spacers 311 are formed on sidewalls of the gate patterns 310.
  • FIG. 4 is a graph exhibiting comparison results of parasitic capacitance of word lines of a conventional semiconductor device and a semiconductor device in accordance with the present invention.
  • Referring to FIG. 4, it is shown that the parasitic capacitance of the word line of the conventional semiconductor device group A is larger than that of the semiconductor device group B in accordance with an embodiment of the present invention.
  • Accordingly, the conventional semiconductor device group may operate slower than the semiconductor device group in accordance with an embodiment of the present invention.
  • FIG. 5 is a graph exhibiting comparison results of punch through properties of a conventional semiconductor device and a semiconductor device in accordance with the present invention.
  • Referring to FIG. 5, it is shown that the punch through property of the conventional semiconductor group C is worse than that of the semiconductor device group D which is in accordance with an embodiment of the present invention.
  • Furthermore, it is also shown that the punch through property is not shown in a predetermined portion of the semiconductor device group B (which is in accordance with an embodiment of the present invention), even at a threshold voltage of approximately 0.75V.
  • As described above, in accordance with an embodiment of the present invention, a device isolation region of a substrate is largely formed to improve parasitic capacitance and a punch through property.
  • Accordingly, a refresh time property can be improved due to improvements in the low parasitic capacitance and the punch through property according to a threshold voltage.
  • As described above, to improve parasitic capacitance and a punch through property, a region in which a device isolation region and an active region of a substrate are two-dimensionally overlapped with each other is formed.
  • Accordingly, a refresh time property can be improved due to improvements in the low parasitic capacitance and the punch through property according to a threshold voltage.
  • Due to the improvement in the refresh time, an operation speed and stability of the semiconductor device can be secured.
  • The present application contains subject matter related to the Korean patent application No. KR 2005-0055863, filed in the Korean Patent Office on Jun. 27, 2005, the entire contents of which being incorporated herein by reference.
  • While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (11)

1. A semiconductor device, comprising:
a semiconductor structure having an active region on a substrate, and recessed portions formed at lower edges of lateral portions of the semiconductor structure;
a plurality of patterned first insulation layers for device isolation buried into the recessed portions; and
a plurality of second insulation layers for device isolation formed on sidewalls of the first insulation layers.
2. The semiconductor device of claim 1, wherein the semiconductor structure comprises a first semiconductor layer formed between the recessed portions, and a second semiconductor layer formed on the first semiconductor layer and having a width wider than that of the first semiconductor layer.
3. The semiconductor device of claim 2, wherein the first semiconductor layer comprises single crystal silicon grown by one of a solid phase epitaxy (SPE) process and a silicon epitaxy growth (SEG) process.
4. The semiconductor device of claim 2, wherein the second semiconductor layer comprises silicon grown by an epitaxial lateral overgrowth (ELO) process.
5. The semiconductor device of claim 1, wherein each of the plurality of patterned first insulation layers comprises one of an oxide layer and a nitride layer.
6. The semiconductor device of claim 1, wherein each of the plurality of second insulation layers comprises a high density plasma (HDP) layer formed through a chemical vapor deposition (CVD) method.
7. A semiconductor device, comprising:
a semiconductor structure having an active region on a substrate and including recessed portions formed at lower edges of lateral portions of the semiconductor structure; and
a plurality of insulation layers for device isolation formed to be aligned with upper edges of the semiconductor structure.
8. The semiconductor device of claim 7, wherein the semiconductor structure comprises a first semiconductor layer formed between the recessed portions, and a second semiconductor layer formed on the first semiconductor layer and having a width wider that that of the first semiconductor layer.
9. The semiconductor device of claim 8, wherein the first semiconductor layer comprises single crystal silicon grown by one of a solid phase epitaxy (SPE) process and a silicon epitaxy growth (SEG) process.
10. The semiconductor device of claim 8, wherein the second semiconductor layer comprises silicon grown by an epitaxial lateral overgrowth (ELO) process.
11. The semiconductor device of claim 10, wherein each of the plurality of insulation layers comprises a high density plasma (HDP) layer formed through a chemical vapor deposition (CVD) method.
US11/999,466 2005-06-27 2007-12-04 Semiconductor device and method for fabricating a semiconductor device Abandoned US20080087980A1 (en)

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JP2007005759A (en) 2007-01-11
US7348255B2 (en) 2008-03-25

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