US20080150079A1

US20080150079A1 - Capacitor in semiconductor device and manufacturing method

Info

Publication number: US20080150079A1
Application number: US12/044,394
Authority: US
Inventors: Jae Suk Lee
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-12-29
Filing date: 2008-03-07
Publication date: 2008-06-26
Also published as: CN1992353A; US7364968B2; CN100508217C; KR100823034B1; KR20070071150A; US20070152296A1

Abstract

The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.

Description

The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0134350 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety.

BACKGROUND

With the increasingly large scale of integration of semiconductor devices, the space for forming capacitors is decreasing. Therefore, intense research efforts have been directed toward assuring sufficient capacitance in the space available.
The capacitance of a capacitor is determined by the area of the electrodes, the dielectric constant of a dielectric layer, and the distance between electrodes. Accordingly, in order to increase the capacitance, methods of increasing the effective area of a capacitor, of decreasing the thickness of a dielectric layer between two electrodes, and of replacing the dielectric layer with a material having a high dielectric constant have been intensively and extensively studied.
The method of increasing the effective area takes chip real estate away from other devices, due to the high degree of integration and miniaturization. A better solution is to increase the capacitance through optimizing the layering process. However, it becomes difficult to deposit the upper film and the structure becomes complicated, thereby resulting in a difficult manufacturing process. Further, when the dielectric constant is increased or the thickness of the dielectric layer is decreased, leakage current may be increased and faulty devices may result from electrical breakdown or the like.

SUMMARY

Embodiments relate to a capacitor in a semiconductor device and a manufacturing method thereof, and more particularly, to a capacitor having a structure of metal/insulator/metal (MIM) and a manufacturing method thereof.
Embodiments relate to a capacitor with greater capacitance and which avoids the production of faulty devices.
Embodiments relate to a capacitor in a semiconductor device, comprising a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed along the surface of the agglomerates to thus form an uneven surface, and an upper electrode formed over the dielectric layer.
The agglomerates may comprise a low-melting-point metal, and the low-melting-point metal may be Sn or Zn.
The dielectric layer may comprise at least one selected from among Si₃N₄, SiO₂, Ta₂O₅, TiO₂, PZT, PLZT, and BaTiO₃.
The diffusion barrier may comprise Ru or RuO₂.
The agglomerates may have a spherical shape, and the projected area of all of the agglomerates may constitute 50˜60% of the area of the diffusion barrier.
Embodiments relate to a method of manufacturing a capacitor in a semiconductor device, comprising forming a first metal film over a substrate, forming a second metal film over the first metal film, forming a low-melting-point metal film over the second metal film, thermally treating the low-melting-point metal film to form spherical agglomerates, forming a dielectric film over the agglomerates, forming a third metal film over the dielectric film, and etching the third metal film, the dielectric film, the agglomerates, an oxide film, and the first metal film.
The second metal film may be formed of Ru.
After forming the second metal film, the method may further comprise oxidizing the second metal film, and such oxidizing may be performed by thermally treating the second metal film at 300˜400° C. in an atmosphere of N₂O or O₂gas.
The low-melting-point metal film may be formed of Zn or Sn.
The low-melting-point metal film may be formed through atomic layer deposition or the like.
The thermal treating may be performed at a temperature equal to or less than 200° C. in an inert gas atmosphere.
As such, the inert gas may comprise at least one selected from among Ar, He, Ne, Kr, Xe, and Rn.
The dielectric film may be formed in a thickness of about 100 Å.

BRIEF DESCRIPTION OF THE DRAWINGS

Example FIG. 1 illustrates a cross sectional view of a capacitor in a semiconductor device, according to embodiments; and

Example FIGS. 2 to 4 sequentially illustrate cross sectional views of the process of manufacturing a semiconductor device, according to embodiments.

DETAILED DESCRIPTION

In the drawings, thicknesses are exaggerated in order to clearly depict the plurality of layers and regions, wherein like parts appearing in the drawings are represented by like reference numerals.
FIG. 1 illustrates a cross sectional view of the structure of a capacitor in a semiconductor device, according to embodiments.
As illustrated in FIG. 1, a capacitor 114 is composed of a lower electrode 102, a diffusion barrier 104, agglomerates 106, a dielectric layer 108, and an upper electrode 110.
Specifically, as illustrated in the drawing, the lower electrode 102 is formed over the substrate 100.
The substrate includes semiconductor elements (not shown) and/or metal wires, or the like, which may be electrically connected to the semiconductor elements. The lower electrode 102 is also electrically connected to the semiconductor elements and/or metal elements on the substrate. The lower electrode 102 may be formed of a single layer consisting of W, Al or Ti, or of multiple layers or sublayers consisting of TiN or TaN.
The diffusion barrier 104 is formed over the lower electrode 102, and a plurality of agglomerates 106 are formed over the diffusion barrier 104.
The diffusion barrier 104 functions to prevent the diffusion of metal atoms located above the diffusion barrier 104 to the lower film, or of metal atoms located under the diffusion barrier 104 to the upper film. Such a diffusion barrier 104 is formed of Ru or RuO₂in a thickness of 10˜1,000.
The agglomerates 106 may be formed in a spherical shape to increase the surface area of the film over the agglomerates 106. A low-melting-point metal, such as Zn or Ru is aggregated to form agglomerates 106. Further, the agglomerates 106 may or may not be uniformly distributed over the diffusion barrier 104. The projected area of all of the agglomerates 106 constitutes 40˜60% of the area of the diffusion barrier 104.
The dielectric layer 108 and the upper electrode 110 are layered on the agglomerates 106. Since the agglomerates are spherical, the surface area of dielectric layer 108 formed over the surface of the agglomerates is increased. Moreover, the dielectric layer 108 has an uneven surface due to the agglomerates 106, and the average thickness thereof may be, for example, about 100 Å.
The dielectric layer 108 may be formed of a single layer or a double layer consisting of at least one of Si₃N₄, SiO₂, Ta₂O₅, TiO₂, PZT, PLZT, and BaTiO₃.
As in the lower electrode, the upper electrode 110 may be formed of a single layer consisting of W, Al, Ti, or the like, or of multiple layers or sublayers consisting of TiN, TaN, or the like.
A barrier metal layer (not shown) may be further formed between the upper electrode 110 and the dielectric layer 108 in order to increase contact properties and prevent the migration of metal atoms of the upper electrode 110. The barrier metal layer may be formed of one or more layers consisting of Ti or TiN.
In embodiments, it is easy to increase the surface area of the dielectric layer 108 using the agglomerates. Thereby, the capacitance of the capacitor may be readily increased without changing the design of the semiconductor device or the interlayer structure thereof.
An insulating layer, for example TEOS (tetra ethyl ortho silicate), is formed on the upper electrode 110 to cover the capacitor 114.
The method of manufacturing the capacitor in the semiconductor device is described below, with reference to the appended drawings.
Example FIGS. 2 to 4 sequentially illustrate cross sectional views of an example of a process of manufacturing the capacitor, according to embodiments.
As illustrated in FIG. 2, a first metal film and a second metal film are layered over a substrate 100 through sputtering or the like. The first metal film 102 a may be formed of W, and the second metal film 104 a may be formed of Ru.
Thereafter, the second metal film 104 a may be oxidized through thermal treatment at 300˜400° C. in a plasma atmosphere of O₂or N₂O, thus forming an oxide film 104 b composed of, for example, RuO₂.
As illustrated in example FIG. 3, a low-melting-point metal, for example Sn, is deposited over the oxide film 104 b, thus forming a low-melting-point metal film. In this example, a layer of Sn 200 Å thick is formed through atomic layer deposition or the like.
Subsequently, the low-melting-point metal film is agglomerated to form spherical agglomerates 106. The low-melting-point metal film may be agglomerated, for example, through thermal treatment at a temperature equal to or less than 200° C. in an inert gas atmosphere. The reason the film agglomerates is to decrease the surface energy of the thin film. If the temperature is higher than 200° C., the thin film does not agglomerate, but evaporates.
As such, the inert gas includes at least one gas selected from among Ar, He, Ne, Kr, Ze, and Rn.
Further, a dielectric material is deposited over the agglomerates 106, thus forming a dielectric film 108 a. The dielectric film 108 a is formed with a thickness of about 100 Å along the surface of the agglomerates 106. Furthermore, since the dielectric film 108 a is unevenly formed, the surface area thereof is enlarged.
As illustrated in FIG. 4, a metal is deposited over the dielectric film 108 a through sputtering or the like, thus forming a third metal film 110 a. The third metal film 110 a may be composed of W.
Then, as illustrated in FIG. 1, the third conductive film 110 a, the dielectric film 108 a, the agglomerates 106, the oxide film 104 b, and the first conductive film 102 a are etched through a selective etching process, thereby completing a capacitor composed of the upper electrode 110, the dielectric layer 108, the agglomerates 106, the diffusion barrier 104 and the lower electrode 102.
Depending on the design of the capacitor, the lower electrode 102 may be wider than the upper electrode 110, or it may be the same width.
Thereafter, an oxide material, or the like, is deposited to cover the capacitor 114, thus forming an interlayer insulating film 112. The interlayer insulating film may be formed with a thickness of 5000˜6000 Å, for example. Moreover, processes of forming metal wires, metal lines, metal connections and/or an interlayer insulating film may be further conducted, if necessary.
As described hereinbefore, embodiments relate to a capacitor in a semiconductor device and a manufacturing method thereof. According to embodiments, spherical agglomerates are formed to increase the surface area of a dielectric layer, such that the capacitance of the capacitor can be easily increased without changing the design of the semiconductor device or the structure thereof, thereby providing a semiconductor device having high quality.
It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.

Claims

1. A capacitor comprising:

a substrate;

a lower electrode formed over the substrate;

a diffusion barrier formed over the lower electrode;

a plurality of agglomerates formed over the diffusion barrier;

a dielectric layer covering the agglomerates and having an uneven surface due to the agglomerates; and

an upper electrode formed over the dielectric layer.

2. The capacitor of claim 1, wherein the agglomerates comprise a low-melting-point metal.

3. The capacitor of claim 2, wherein the low-melting-point metal comprises at least one of Sn or Zn.

4. The capacitor of claim 1, wherein the dielectric layer comprises at least one of Si₃N₄, SiO₂, Ta₂O₅, TiO₂, PZT, PLZT, and BaTiO₃.

5. The capacitor of claim 1, wherein the diffusion barrier comprises Ru.

6. The capacitor of claim 1, wherein the agglomerates have a spherical shape.

7. The capacitor of claim 1, wherein a projected area of all of the agglomerates constitutes about 50˜60% of an area of the diffusion barrier.

8. The capacitor of claim 1, wherein the diffusion barrier comprises RuO₂.

9. (canceled)

10. (canceled)

11. (canceled)

12. (canceled)

13. (canceled)

14. (canceled)

15. (canceled)

16. (canceled)

17. (canceled)