US20080155307A1 - Responding to a storage processor failure with continued write caching - Google Patents
Responding to a storage processor failure with continued write caching Download PDFInfo
- Publication number
- US20080155307A1 US20080155307A1 US11/529,124 US52912406A US2008155307A1 US 20080155307 A1 US20080155307 A1 US 20080155307A1 US 52912406 A US52912406 A US 52912406A US 2008155307 A1 US2008155307 A1 US 2008155307A1
- Authority
- US
- United States
- Prior art keywords
- storage processor
- cache
- write
- failure
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
- G06F11/2089—Redundant storage control functionality
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Definitions
- One conventional data storage system includes two storage processors and an array of disk drives.
- Each storage processor includes, among other things, a local write cache.
- the local write caches mirror each other.
- the storage processors perform read and write operations on behalf of one or more external host computers (or simply external hosts). Since the contents of the local write caches are mirrored, the storage processors initially attend to write operations in a write-back manner. That is, the write policy employed by the storage processors involves acknowledging host write operations once the write data is stored in both write caches. By the time the external hosts receive such acknowledgement, the storage processors may not have yet evicted the write data from the write caches to the array of disk drives.
- the remaining storage processor vaults the contents of the its local write cache to one or more magnetic disk drives, and then disables its local write cache.
- the remaining storage processor then flushes the vaulted write cache contents (which are now stored on the magnetic disk drive) to the array of disk drives, i.e., the remaining storage processor empties the vaulted write cache contents by storing the vaulted write data to the array of disk drives.
- the remaining storage processor is capable of performing host read and write operations while the remaining storage processor flushes the vaulted write data contents and after such flushing is complete. For example, the remaining storage processor now carries out write operations in a write-through manner where the remaining storage processor stores new write data from an external host to the array of disk drives before acknowledging that the write operation is complete.
- the remaining storage processor vaults the contents of its write cache to the magnetic disk drive and disables its write cache so that a second failure will not result in loss of the cached write data. For example, suppose that the remaining storage processor subsequently encounters a software failure after vaulting the write cache to the magnetic disk drive. When the remaining storage processor recovers from the software failure (i.e., performs a soft reset), the remaining storage processor overwrites its local write cache. In particular, Basic Input/Output System (BIOS) firmware directs the remaining storage processor to clear and test its local write cache. Additionally, the remaining storage processor uses at least a portion of its local write cache for temporarily holding Power-On Self Test (POST) code for running a Power-On Self Test. Although the contents of the local write cache have been overwritten, no write data is lost since the previously-cached write data was immediately vaulted to the magnetic disk drive and since all subsequently received write data is processed in a write-through manner.
- BIOS Basic Input/Output System
- the process of flushing the vaulted write cache contents from the magnetic disk drive to the array of disk drives may take a considerable amount of time (e.g., several hours). During this time, there is a significant time latency associated with processing a new write operation.
- the remaining storage processor receives new write data from an external host computer, the remaining storage processor first accesses the vaulted write cache contents from the magnetic disk drive to see if the new write operation pertains to any vaulted write data from an earlier write operation in order to maintain data integrity.
- the remaining storage processor completes the earlier write operation, i.e., writes the vaulted write data to the array of disk drives. Then, the remaining storage processor processes the new write operation in a write-through manner.
- the remaining storage processor After the remaining storage processor has finished flushing the vaulted write cache contents from the magnetic disk drive (or alternatively from a mini array of drives holding the vault) to the array of disk drives, the remaining storage processor continues to operate in write-though mode thus passing on a relatively large performance hit onto the external hosts. That is, the remaining storage processor stores write data onto the array of disk drives prior to acknowledging completion of write operations. Such operation results in significant latency compared to response times for processing write data in write-back mode.
- the failed storage processor encounters only a minor failure (e.g., a software anomaly resulting in a soft reset). In such a situation, the failed storage processor is able to quickly recover from the failure, e.g., a couple of minutes to reboot and perform self-tests. Nevertheless, to prevent the recovered storage processor from interfering with the vault flushing process, the recovered storage processor cannot rejoin the data storage system until the remaining storage processor has completed flushing the vaulted write cache contents to the array of disk drives. Accordingly, the recovered storage processor must remain sidelined during the vault flushing process which may take several hours to complete.
- a minor failure e.g., a software anomaly resulting in a soft reset
- an enhanced technique for responding to a storage processor failure involves continuing to perform write-back caching operations while the failed storage processor remains unavailable.
- Such a technique alleviates the need for the remaining storage processor to vault cached write data to a magnetic disk and then flush the vaulted write data in response to the failed storage processor.
- Such a technique provides better response time on new host write operations than write-through caching which is performed following the failure in the above-described conventional vaulting scheme.
- One embodiment is directed to a method for responding to a storage processor failure.
- the method includes performing write-back caching operations using a cache of a first storage processor, and mirroring data from the cache of the first storage processor to a cache of a second storage processor.
- the method further includes, after of a failure of the second storage processor in which the second storage processor becomes unavailable, continuing to perform write-back caching operations using the cache of the first storage processor while the second storage processor remains unavailable.
- a cache controller is capable of being modified so that any write data in the cache of the first storage processor persists if the first storage processor encounters most failures thus preventing loss of the cached write data.
- FIG. 1 is a block diagram of a data storage system which is configured to continue write caching after a storage processor failure.
- FIG. 2 is a block diagram of a storage processor of the data storage system of FIG. 1 .
- FIG. 3 is a flowchart of a procedure which is performed by a first storage processor in response to a failure of a second storage processor.
- FIG. 4 is a flowchart of a procedure which is performed by the first storage processor in response to a failure of the first storage processor.
- An enhanced technique for responding to a storage processor failure involves continuing to perform write-back caching operations while the failed storage processor remains unavailable.
- Such a technique alleviates the need for the remaining storage processor to vault cached write data to one or more magnetic disks and then flush the vaulted write data in response to the failed storage processor as in conventional vaulting schemes which require that the data storage system remain unavailable during the vaulting process and which prevent the failed storage processor from returning during the vault flushing process.
- such a technique provides better response time on new host write operations than write-through caching which is performed following a failure in the conventional vaulting schemes.
- FIG. 1 is a block diagram of a data storage system 20 which is configured to continue write caching on behalf of a set of external host computers 22 ( 1 ), 22 ( 2 ), . . . (collectively, external hosts 22 ) after a storage processor failure.
- the external hosts 22 connect to the data storage system 20 via a respective communications medium 24 ( 1 ), 24 ( 2 ), . . . (collectively, communications media 24 ).
- the data storage system 20 includes multiple storage processors 26 (A), 26 (B) (collectively, storage processors 26 ), a cache mirror bus 28 and a set of disk drives 30 ( 1 ), . . . 30 (N) (collectively, disk drives 30 ).
- the storage processors 26 are configured to perform data storage operations (e.g., read operations, write operations, etc.) on behalf of the external hosts 22 .
- the cache mirror bus 28 is configured to convey data between caches of the storage processors 26 thus enabling cache mirroring between the storage processors 26 .
- the set of disk drives 30 enables the data storage system 20 to store and retrieve data on behalf of the external hosts 22 in a fault tolerant, non-volatile manner (e.g., using a RAID scheme).
- Each storage processor 26 is configured to perform write-back caching in response to write operations 32 from the external hosts 22 while both storage processors 26 are in operation. That is, each storage processor 26 acknowledges completion of a write operation 32 once the write data reaches its local write cache and, if possible, once the write data is mirrored in the local write cache of the other storage processor 26 . Additionally, each storage processor 26 is configured to continue to perform such write-back caching after a failure of the other storage processor 26 . Such operation enables the data storage system 20 to provide improved response times and quicker recovery in the event a storage processor failure.
- the storage processor 26 (A) fails for a short period of time (e.g., due to an unanticipated soft reset).
- the storage processor 26 (B) continues to operating under a write-back write policy.
- Such continued write-back operation alleviates the need to vault the write cache of the storage processor 26 (B) which would otherwise make the data storage system 20 unavailable for a period of time. Additionally, such continued write-back operation avoids the performance hit associated with subsequently flushing the vaulted write cache contents to magnetic disk as well as running the data storage system in a write-through mode.
- the storage processor 26 (B) continues in write-back mode, the storage processor 26 (A) is capable of easily becoming active again (i.e., rejoining in performance of host-based read and write operations) rather than having to wait until vault flushing is complete which could take several hours. Further details will now be provided with reference to FIG. 2 .
- FIG. 2 is a block diagram of each storage processor 26 of the data storage system 20 .
- Each storage processor 26 includes a communications interface 40 , a controller 42 and a memory subsystem 44 .
- the communications interface 40 includes a host interface 46 , a cache mirroring interface 48 , and a disk interface 50 .
- the memory subsystem 44 includes a control circuit 52 , a local write cache 54 and additional memory 58 .
- the additional memory 58 includes operating system storage, firmware for storing BIOS and POST code, optional flash memory, etc.
- the communications interface 40 is configured to provide connectivity from the storage processor 26 to various other components.
- the host interface 46 is configured to connect the storage processor 26 to one or more external hosts 22 through the connection media 24 (also see FIG. 1 ).
- the cache mirroring interface 48 is configured to connect the storage processor 26 (e.g., the storage processor 26 (A)) to another storage processor 26 (e.g., the storage processor 26 (B)) to enable cache mirroring through the cache mirroring bus 28 .
- the disk interface 50 is configured to connect the storage processor 26 to the set of disk drives 30 .
- the controller 42 is configured to carryout data storage operations on behalf of one or more of the external hosts 22 through the communications interface 40 (e.g., see the write operations 32 in FIG. 1 ).
- the controller 42 is implemented as a set of processors running an operating system which is capable of being stored in a designated area on one or more of the disk drives 30 .
- the controller 42 is implemented as logic circuitry (e.g., Application Specific Integrated Circuitry, Field Programmable Gate Arrays, etc.), microprocessors or processor chip sets, analog circuitry, various combinations thereof, and so on.
- the memory subsystem 44 is configured to provide memory services to the controller 42 .
- the control circuitry 54 of the memory subsystem 54 is configured to provide persistent write caching using the write cache 56 , i.e., enable the storage processor 26 to continue write caching even after a storage processor failure.
- the control circuit 54 is further capable of performing other tasks using the additional memory 58 (e.g., operating a read cache, operating as an instruction cache, optionally vaulting contents of the write cache 56 into non-volatile flash memory or disk drive memory in response to a failure of the controller 42 , etc.). Further details will now be provided with reference to FIG. 3 .
- FIG. 3 is a flowchart of a procedure 70 illustrating how a first storage processor 26 (e.g., the storage processor 26 (A)) responds to a failure of a second storage processor 26 (e.g., the storage processor 26 (B)).
- the storage processors 26 attend to data storage operations on behalf of external hosts 22 (also see FIG. 1 ).
- the controller 42 of each storage processor 26 of the data storage system 20 performs write-back caching operations using its local cache 56 .
- step 74 the controller 42 of each storage processor 26 mirrors write data from its local cache 56 to the cache 56 of the other storage processor 26 .
- the controller 42 does not notify the external hosts 22 that the write operations are completed until the write data is stored in both caches 56 for fault tolerance.
- one of the storage processors 26 (e.g., the storage processor 26 (B)) encounters a failure (e.g., a hardware failure that causes the failed storage processor 26 to become unavailable for an extended period of time, a software error that causes the failed storage processor 26 to briefly become unavailable while performing a soft reset, etc.).
- a failure e.g., a hardware failure that causes the failed storage processor 26 to become unavailable for an extended period of time, a software error that causes the failed storage processor 26 to briefly become unavailable while performing a soft reset, etc.
- the remaining storage processor 26 e.g., the storage processor 26 (A)
- the control circuitry 54 FIG. 2
- maintains write data within the local cache of the remaining storage processor 26 thus enabling the remaining storage processor 26 to continue performing write-back caching operations.
- FIG. 4 is a flowchart of a procedure 90 illustrating how the remaining storage processor 26 (e.g., the storage processor 26 (A)) responds to a failure of that storage processor 26 .
- the controller 42 of the remaining storage processor 26 encounters a software failure.
- the remaining storage processor 26 may soft reset due to a crash of the operating system.
- step 94 the controller 42 maintains the current write cache data within the local write cache 56 while attempting to recover from the software failure.
- the controller 42 does not allow the local write cache 56 to be overwritten by either the BIOS or POST as the remaining storage processor 26 recovers from the failure. That is, the BIOS and POST, which traditionally write to local write cache, are prevented from corrupting the contents of the local write cache 56 . As a result, the write data within the local write cache 56 is preserved.
- step 96 the controller 42 performing subsequent write-back caching operations after recovering from the software failure and while the other storage processor (e.g., the storage processor 26 (B)) remains unavailable. Accordingly, the remaining storage processor 26 can continue to service data storage operations of the external hosts 22 .
- the other storage processor e.g., the storage processor 26 (B)
- control circuitry 54 of the memory subsystem 44 is configured to dump the contents of the local write cache 56 of the remaining storage processor 26 to a magnetic disk drive (e.g., see the set of disk drives 30 in FIG. 1 ). In other arrangements, the control circuitry 54 of the memory subsystem 44 is configured to dump the contents of the local write cache 56 of the remaining storage processor 26 to non-volatile flash memory (e.g., see the additional memory 58 in FIG. 2 ).
- the data storage system 20 was able to continue operation through one storage processor failure (e.g., the storage processor 26 (B)), and then temporarily persist the contents of the local write cache 56 until the contents are dumped to non-volatile memory in response to a second storage processor failure (e.g., the storage processor 26 (A)).
- one storage processor failure e.g., the storage processor 26 (B)
- temporarily persist the contents of the local write cache 56 until the contents are dumped to non-volatile memory in response to a second storage processor failure e.g., the storage processor 26 (A)
- an enhanced technique for responding to a storage processor failure involves continuing to perform write-back caching operations while a failed storage processor 26 (e.g., the storage processor 26 (B)) remains unavailable.
- a failed storage processor 26 e.g., the storage processor 26 (B)
- Such a technique alleviates the need for the remaining storage processor 26 (e.g., the storage processor 26 (A)) to vault cached write data to a magnetic disk and then flush the vaulted write data in response to the failed storage processor 26 as in conventional vaulting schemes which require that the data storage system remain unavailable during the vaulting process and which prevent the failed storage processor from returning during the vault flushing process.
- such a technique provides better response time on new host write operations than write-through caching which is performed following a failure in the conventional vaulting schemes.
Abstract
Description
- One conventional data storage system includes two storage processors and an array of disk drives. Each storage processor includes, among other things, a local write cache. The local write caches mirror each other.
- During operation, the storage processors perform read and write operations on behalf of one or more external host computers (or simply external hosts). Since the contents of the local write caches are mirrored, the storage processors initially attend to write operations in a write-back manner. That is, the write policy employed by the storage processors involves acknowledging host write operations once the write data is stored in both write caches. By the time the external hosts receive such acknowledgement, the storage processors may not have yet evicted the write data from the write caches to the array of disk drives.
- If one of the storage processors fails during operation of the data storage system (e.g., a hardware failure, a software failure, a loss of power to one of the storage processors, etc.), the remaining storage processor vaults the contents of the its local write cache to one or more magnetic disk drives, and then disables its local write cache. The remaining storage processor then flushes the vaulted write cache contents (which are now stored on the magnetic disk drive) to the array of disk drives, i.e., the remaining storage processor empties the vaulted write cache contents by storing the vaulted write data to the array of disk drives.
- It should be understood that the remaining storage processor is capable of performing host read and write operations while the remaining storage processor flushes the vaulted write data contents and after such flushing is complete. For example, the remaining storage processor now carries out write operations in a write-through manner where the remaining storage processor stores new write data from an external host to the array of disk drives before acknowledging that the write operation is complete.
- It should be further understood that the remaining storage processor vaults the contents of its write cache to the magnetic disk drive and disables its write cache so that a second failure will not result in loss of the cached write data. For example, suppose that the remaining storage processor subsequently encounters a software failure after vaulting the write cache to the magnetic disk drive. When the remaining storage processor recovers from the software failure (i.e., performs a soft reset), the remaining storage processor overwrites its local write cache. In particular, Basic Input/Output System (BIOS) firmware directs the remaining storage processor to clear and test its local write cache. Additionally, the remaining storage processor uses at least a portion of its local write cache for temporarily holding Power-On Self Test (POST) code for running a Power-On Self Test. Although the contents of the local write cache have been overwritten, no write data is lost since the previously-cached write data was immediately vaulted to the magnetic disk drive and since all subsequently received write data is processed in a write-through manner.
- Unfortunately, there are deficiencies in the above-described conventional vaulting scheme which involves transitioning from a write-caching mode when two storage processors are available to a write-through mode when one of the storage processors fails but the other storage processor remains. For example, the remaining storage processor requires time to vault contents of its local write cache to a magnetic disk drive. During this time, the remaining storage processor and thus the data storage system as a whole is unavailable to attend to further write or read operations from external hosts. Accordingly, a write or read operation submitted by an external host during this write cache vaulting event will unfortunately time out.
- Additionally, the process of flushing the vaulted write cache contents from the magnetic disk drive to the array of disk drives may take a considerable amount of time (e.g., several hours). During this time, there is a significant time latency associated with processing a new write operation. In particular, if the remaining storage processor receives new write data from an external host computer, the remaining storage processor first accesses the vaulted write cache contents from the magnetic disk drive to see if the new write operation pertains to any vaulted write data from an earlier write operation in order to maintain data integrity. If such vaulted write data exists and if the vaulted write data must be preserved in the event that the new write is aborted, the remaining storage processor completes the earlier write operation, i.e., writes the vaulted write data to the array of disk drives. Then, the remaining storage processor processes the new write operation in a write-through manner.
- Furthermore, after the remaining storage processor has finished flushing the vaulted write cache contents from the magnetic disk drive (or alternatively from a mini array of drives holding the vault) to the array of disk drives, the remaining storage processor continues to operate in write-though mode thus passing on a relatively large performance hit onto the external hosts. That is, the remaining storage processor stores write data onto the array of disk drives prior to acknowledging completion of write operations. Such operation results in significant latency compared to response times for processing write data in write-back mode.
- Moreover, there may be instances where the failed storage processor encounters only a minor failure (e.g., a software anomaly resulting in a soft reset). In such a situation, the failed storage processor is able to quickly recover from the failure, e.g., a couple of minutes to reboot and perform self-tests. Nevertheless, to prevent the recovered storage processor from interfering with the vault flushing process, the recovered storage processor cannot rejoin the data storage system until the remaining storage processor has completed flushing the vaulted write cache contents to the array of disk drives. Accordingly, the recovered storage processor must remain sidelined during the vault flushing process which may take several hours to complete.
- In contrast to the above-described conventional vaulting scheme which involves transitioning from a write-caching mode when two storage processors are available to a write-through mode when one of the storage processors fails but the other storage processor remains, an enhanced technique for responding to a storage processor failure involves continuing to perform write-back caching operations while the failed storage processor remains unavailable. Such a technique alleviates the need for the remaining storage processor to vault cached write data to a magnetic disk and then flush the vaulted write data in response to the failed storage processor. Furthermore, such a technique provides better response time on new host write operations than write-through caching which is performed following the failure in the above-described conventional vaulting scheme.
- One embodiment is directed to a method for responding to a storage processor failure. The method includes performing write-back caching operations using a cache of a first storage processor, and mirroring data from the cache of the first storage processor to a cache of a second storage processor. The method further includes, after of a failure of the second storage processor in which the second storage processor becomes unavailable, continuing to perform write-back caching operations using the cache of the first storage processor while the second storage processor remains unavailable. A cache controller is capable of being modified so that any write data in the cache of the first storage processor persists if the first storage processor encounters most failures thus preventing loss of the cached write data.
- The foregoing and other objects, features and advantages of the invention will be apparent from the following description of particular embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
-
FIG. 1 is a block diagram of a data storage system which is configured to continue write caching after a storage processor failure. -
FIG. 2 is a block diagram of a storage processor of the data storage system ofFIG. 1 . -
FIG. 3 is a flowchart of a procedure which is performed by a first storage processor in response to a failure of a second storage processor. -
FIG. 4 is a flowchart of a procedure which is performed by the first storage processor in response to a failure of the first storage processor. - An enhanced technique for responding to a storage processor failure involves continuing to perform write-back caching operations while the failed storage processor remains unavailable. Such a technique alleviates the need for the remaining storage processor to vault cached write data to one or more magnetic disks and then flush the vaulted write data in response to the failed storage processor as in conventional vaulting schemes which require that the data storage system remain unavailable during the vaulting process and which prevent the failed storage processor from returning during the vault flushing process. Furthermore, such a technique provides better response time on new host write operations than write-through caching which is performed following a failure in the conventional vaulting schemes.
-
FIG. 1 is a block diagram of adata storage system 20 which is configured to continue write caching on behalf of a set of external host computers 22(1), 22(2), . . . (collectively, external hosts 22) after a storage processor failure. Theexternal hosts 22 connect to thedata storage system 20 via a respective communications medium 24(1), 24(2), . . . (collectively, communications media 24). - The
data storage system 20 includes multiple storage processors 26(A), 26(B) (collectively, storage processors 26), acache mirror bus 28 and a set of disk drives 30(1), . . . 30(N) (collectively, disk drives 30). Thestorage processors 26 are configured to perform data storage operations (e.g., read operations, write operations, etc.) on behalf of theexternal hosts 22. Thecache mirror bus 28 is configured to convey data between caches of thestorage processors 26 thus enabling cache mirroring between thestorage processors 26. The set ofdisk drives 30 enables thedata storage system 20 to store and retrieve data on behalf of theexternal hosts 22 in a fault tolerant, non-volatile manner (e.g., using a RAID scheme). - Each
storage processor 26 is configured to perform write-back caching in response to writeoperations 32 from theexternal hosts 22 while bothstorage processors 26 are in operation. That is, eachstorage processor 26 acknowledges completion of awrite operation 32 once the write data reaches its local write cache and, if possible, once the write data is mirrored in the local write cache of theother storage processor 26. Additionally, eachstorage processor 26 is configured to continue to perform such write-back caching after a failure of theother storage processor 26. Such operation enables thedata storage system 20 to provide improved response times and quicker recovery in the event a storage processor failure. - For example, suppose that the storage processor 26(A) fails for a short period of time (e.g., due to an unanticipated soft reset). The storage processor 26(B) continues to operating under a write-back write policy. Such continued write-back operation alleviates the need to vault the write cache of the storage processor 26(B) which would otherwise make the
data storage system 20 unavailable for a period of time. Additionally, such continued write-back operation avoids the performance hit associated with subsequently flushing the vaulted write cache contents to magnetic disk as well as running the data storage system in a write-through mode. Moreover, since the storage processor 26(B) continues in write-back mode, the storage processor 26(A) is capable of easily becoming active again (i.e., rejoining in performance of host-based read and write operations) rather than having to wait until vault flushing is complete which could take several hours. Further details will now be provided with reference toFIG. 2 . -
FIG. 2 is a block diagram of eachstorage processor 26 of thedata storage system 20. Eachstorage processor 26 includes acommunications interface 40, acontroller 42 and amemory subsystem 44. Thecommunications interface 40 includes ahost interface 46, acache mirroring interface 48, and adisk interface 50. Thememory subsystem 44 includes a control circuit 52, alocal write cache 54 andadditional memory 58. Theadditional memory 58 includes operating system storage, firmware for storing BIOS and POST code, optional flash memory, etc. - The
communications interface 40 is configured to provide connectivity from thestorage processor 26 to various other components. In particular, thehost interface 46 is configured to connect thestorage processor 26 to one or moreexternal hosts 22 through the connection media 24 (also seeFIG. 1 ). Thecache mirroring interface 48 is configured to connect the storage processor 26 (e.g., the storage processor 26(A)) to another storage processor 26 (e.g., the storage processor 26(B)) to enable cache mirroring through thecache mirroring bus 28. Thedisk interface 50 is configured to connect thestorage processor 26 to the set of disk drives 30. - The
controller 42 is configured to carryout data storage operations on behalf of one or more of theexternal hosts 22 through the communications interface 40 (e.g., see thewrite operations 32 inFIG. 1 ). In some arrangements, thecontroller 42 is implemented as a set of processors running an operating system which is capable of being stored in a designated area on one or more of the disk drives 30. In other arrangements, thecontroller 42 is implemented as logic circuitry (e.g., Application Specific Integrated Circuitry, Field Programmable Gate Arrays, etc.), microprocessors or processor chip sets, analog circuitry, various combinations thereof, and so on. - The
memory subsystem 44 is configured to provide memory services to thecontroller 42. In particular, thecontrol circuitry 54 of thememory subsystem 54 is configured to provide persistent write caching using thewrite cache 56, i.e., enable thestorage processor 26 to continue write caching even after a storage processor failure. Thecontrol circuit 54 is further capable of performing other tasks using the additional memory 58 (e.g., operating a read cache, operating as an instruction cache, optionally vaulting contents of thewrite cache 56 into non-volatile flash memory or disk drive memory in response to a failure of thecontroller 42, etc.). Further details will now be provided with reference toFIG. 3 . -
FIG. 3 is a flowchart of aprocedure 70 illustrating how a first storage processor 26 (e.g., the storage processor 26(A)) responds to a failure of a second storage processor 26 (e.g., the storage processor 26(B)). Initially, thestorage processors 26 attend to data storage operations on behalf of external hosts 22 (also seeFIG. 1 ). Along these lines, instep 72, thecontroller 42 of eachstorage processor 26 of the data storage system 20 (FIG. 1 ) performs write-back caching operations using itslocal cache 56. - In
step 74, thecontroller 42 of eachstorage processor 26 mirrors write data from itslocal cache 56 to thecache 56 of theother storage processor 26. In some arrangements, thecontroller 42 does not notify theexternal hosts 22 that the write operations are completed until the write data is stored in bothcaches 56 for fault tolerance. - In
step 76, one of the storage processors 26 (e.g., the storage processor 26(B)) encounters a failure (e.g., a hardware failure that causes the failedstorage processor 26 to become unavailable for an extended period of time, a software error that causes the failedstorage processor 26 to briefly become unavailable while performing a soft reset, etc.). After thestorage processor 26 fails, the remaining storage processor 26 (e.g., the storage processor 26(A)) continues to perform write-back caching operations using itslocal cache 56 while the other storage processor remains unavailable. In particular, the control circuitry 54 (FIG. 2 ) maintains write data within the local cache of the remainingstorage processor 26 thus enabling the remainingstorage processor 26 to continue performing write-back caching operations. - It should be understood that such continued write-back operation alleviates the need to vault the write cache of the remaining
storage processor 26 to magnetic disk memory. Furthermore, theexternal hosts 22 can continue to enjoy relatively fast response times associated with a write-back write policy from thedata storage system 20. Further details will now be provided with reference toFIG. 4 . -
FIG. 4 is a flowchart of aprocedure 90 illustrating how the remaining storage processor 26 (e.g., the storage processor 26(A)) responds to a failure of thatstorage processor 26. Instep 92, after the remainingstorage processor 26 has performed further write-back caching operations and while current write cache data resides in thelocal cache 56 of the remainingstorage processor 26, thecontroller 42 of the remainingstorage processor 26 encounters a software failure. For example, the remainingstorage processor 26 may soft reset due to a crash of the operating system. - In
step 94, thecontroller 42 maintains the current write cache data within thelocal write cache 56 while attempting to recover from the software failure. In particular, thecontroller 42 does not allow thelocal write cache 56 to be overwritten by either the BIOS or POST as the remainingstorage processor 26 recovers from the failure. That is, the BIOS and POST, which traditionally write to local write cache, are prevented from corrupting the contents of thelocal write cache 56. As a result, the write data within thelocal write cache 56 is preserved. - In
step 96, thecontroller 42 performing subsequent write-back caching operations after recovering from the software failure and while the other storage processor (e.g., the storage processor 26(B)) remains unavailable. Accordingly, the remainingstorage processor 26 can continue to service data storage operations of theexternal hosts 22. - Optionally, if the
controller 42 of the remainingstorage processor 26 is incapable of returning to operation, other alternatives are available. In some arrangements, thecontrol circuitry 54 of thememory subsystem 44 is configured to dump the contents of thelocal write cache 56 of the remainingstorage processor 26 to a magnetic disk drive (e.g., see the set ofdisk drives 30 inFIG. 1 ). In other arrangements, thecontrol circuitry 54 of thememory subsystem 44 is configured to dump the contents of thelocal write cache 56 of the remainingstorage processor 26 to non-volatile flash memory (e.g., see theadditional memory 58 inFIG. 2 ). In these situations, thedata storage system 20 was able to continue operation through one storage processor failure (e.g., the storage processor 26(B)), and then temporarily persist the contents of thelocal write cache 56 until the contents are dumped to non-volatile memory in response to a second storage processor failure (e.g., the storage processor 26(A)). - As mentioned above, an enhanced technique for responding to a storage processor failure involves continuing to perform write-back caching operations while a failed storage processor 26 (e.g., the storage processor 26(B)) remains unavailable. Such a technique alleviates the need for the remaining storage processor 26 (e.g., the storage processor 26(A)) to vault cached write data to a magnetic disk and then flush the vaulted write data in response to the failed
storage processor 26 as in conventional vaulting schemes which require that the data storage system remain unavailable during the vaulting process and which prevent the failed storage processor from returning during the vault flushing process. Furthermore, such a technique provides better response time on new host write operations than write-through caching which is performed following a failure in the conventional vaulting schemes. - While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (20)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/529,124 US7849350B2 (en) | 2006-09-28 | 2006-09-28 | Responding to a storage processor failure with continued write caching |
PCT/US2007/007528 WO2008039236A1 (en) | 2006-09-28 | 2007-03-27 | Responding to a storage processor failure with continued write caching |
US11/729,728 US7809975B2 (en) | 2006-09-28 | 2007-03-29 | Recovering from a storage processor failure using write cache preservation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/529,124 US7849350B2 (en) | 2006-09-28 | 2006-09-28 | Responding to a storage processor failure with continued write caching |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/729,728 Continuation-In-Part US7809975B2 (en) | 2006-09-28 | 2007-03-29 | Recovering from a storage processor failure using write cache preservation |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080155307A1 true US20080155307A1 (en) | 2008-06-26 |
US7849350B2 US7849350B2 (en) | 2010-12-07 |
Family
ID=38325642
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/529,124 Active 2029-10-05 US7849350B2 (en) | 2006-09-28 | 2006-09-28 | Responding to a storage processor failure with continued write caching |
US11/729,728 Active 2029-01-21 US7809975B2 (en) | 2006-09-28 | 2007-03-29 | Recovering from a storage processor failure using write cache preservation |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/729,728 Active 2029-01-21 US7809975B2 (en) | 2006-09-28 | 2007-03-29 | Recovering from a storage processor failure using write cache preservation |
Country Status (2)
Country | Link |
---|---|
US (2) | US7849350B2 (en) |
WO (1) | WO2008039236A1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060198386A1 (en) * | 2005-03-01 | 2006-09-07 | Tong Liu | System and method for distributed information handling system cluster active-active master node |
US8954808B1 (en) * | 2010-11-30 | 2015-02-10 | Symantec Corporation | Systems and methods for performing input/output path failovers |
US9298636B1 (en) * | 2011-09-29 | 2016-03-29 | Emc Corporation | Managing data storage |
US20170003894A1 (en) * | 2015-06-30 | 2017-01-05 | HGST Netherlands B.V. | Non-blocking caching for data storage drives |
US20180173435A1 (en) * | 2016-12-21 | 2018-06-21 | EMC IP Holding Company LLC | Method and apparatus for caching data |
US10592364B2 (en) * | 2015-06-19 | 2020-03-17 | Hewlett Packard Enterprise Development Lp | Handling errors during run time backups |
US20230350786A1 (en) * | 2022-04-27 | 2023-11-02 | SK Hynix Inc. | Core dump in multiprocessor device |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009062280A1 (en) * | 2007-11-15 | 2009-05-22 | Mosaid Technologies Incorporated | Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices |
CN101232397B (en) * | 2008-02-22 | 2010-10-27 | 成都市华为赛门铁克科技有限公司 | Apparatus and method for renovating multi controller systems |
US8615678B1 (en) * | 2008-06-30 | 2013-12-24 | Emc Corporation | Auto-adapting multi-tier cache |
US8234554B2 (en) * | 2008-07-10 | 2012-07-31 | International Business Machines Corporation | Soft error correction in sleeping processors |
US8176363B2 (en) * | 2008-12-08 | 2012-05-08 | International Business Machines Corporation | Efficient method and apparatus for keeping track of in flight data in a dual node storage controller |
US8402226B1 (en) | 2010-06-18 | 2013-03-19 | Emc Corporation | Rate proportional cache write-back in a storage server |
US10225335B2 (en) | 2011-02-09 | 2019-03-05 | Cisco Technology, Inc. | Apparatus, systems and methods for container based service deployment |
US10678602B2 (en) | 2011-02-09 | 2020-06-09 | Cisco Technology, Inc. | Apparatus, systems and methods for dynamic adaptive metrics based application deployment on distributed infrastructures |
US10003672B2 (en) | 2011-02-09 | 2018-06-19 | Cisco Technology, Inc. | Apparatus, systems and methods for deployment of interactive desktop applications on distributed infrastructures |
US8862933B2 (en) | 2011-02-09 | 2014-10-14 | Cliqr Technologies, Inc. | Apparatus, systems and methods for deployment and management of distributed computing systems and applications |
US8572294B2 (en) * | 2011-05-17 | 2013-10-29 | Ncr Corporation | Device start up system and method |
US9053027B1 (en) | 2011-12-21 | 2015-06-09 | Emc Corporation | Techniques for maintaining and restoring dirty caches across CPU resets |
US10025711B2 (en) * | 2012-01-16 | 2018-07-17 | Qualcomm Incorporated | Hybrid write-through/write-back cache policy managers, and related systems and methods |
US9003129B1 (en) | 2012-03-30 | 2015-04-07 | Emc Corporation | Techniques for inter-storage-processor cache communication using tokens |
US8904229B1 (en) | 2012-06-29 | 2014-12-02 | Emc Corporation | Online recovery of a file system experiencing failure of redundant logical storage storing a single point of failure |
US9135119B1 (en) * | 2012-09-28 | 2015-09-15 | Emc Corporation | System and method for data management |
WO2014076736A1 (en) * | 2012-11-15 | 2014-05-22 | Hitachi, Ltd. | Storage system and control method for storage system |
US20150286544A1 (en) * | 2012-11-29 | 2015-10-08 | Hewlett-Packard Development Company, L.P. | Fault tolerance in a multi-core circuit |
KR20150111937A (en) | 2013-01-30 | 2015-10-06 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | Non-volatile memory write mechanism |
US9367405B1 (en) * | 2013-03-14 | 2016-06-14 | Emc Corporation | Managing software errors in storage systems |
US9239797B2 (en) * | 2013-08-15 | 2016-01-19 | Globalfoundries Inc. | Implementing enhanced data caching and takeover of non-owned storage devices in dual storage device controller configuration with data in write cache |
US9507671B2 (en) * | 2013-09-16 | 2016-11-29 | Globalfoundries Inc. | Write cache protection in a purpose built backup appliance |
US9946655B2 (en) * | 2013-10-09 | 2018-04-17 | Hitachi, Ltd. | Storage system and storage control method |
US9485099B2 (en) | 2013-10-25 | 2016-11-01 | Cliqr Technologies, Inc. | Apparatus, systems and methods for agile enablement of secure communications for cloud based applications |
US9430213B2 (en) | 2014-03-11 | 2016-08-30 | Cliqr Technologies, Inc. | Apparatus, systems and methods for cross-cloud software migration and deployment |
GB201407665D0 (en) | 2014-05-01 | 2014-06-18 | Imagination Tech Ltd | Cadence analysis for a video signal having an interlaced format |
US9753793B2 (en) | 2014-06-30 | 2017-09-05 | Intel Corporation | Techniques for handling errors in persistent memory |
WO2016115737A1 (en) | 2015-01-23 | 2016-07-28 | Hewlett-Packard Development Company, L.P. | Aligned variable reclamation |
WO2016139787A1 (en) * | 2015-03-04 | 2016-09-09 | 株式会社日立製作所 | Storage system and data writing control method |
US10997030B2 (en) * | 2015-03-31 | 2021-05-04 | EMC IP Holding Company LLC | Disaster recovery as a service |
US10120887B1 (en) * | 2015-09-28 | 2018-11-06 | EMC IP Holding Company LLC | Demand-driven initialization of data storage structures |
CN107850984A (en) * | 2016-04-29 | 2018-03-27 | 慧与发展有限责任合伙企业 | Recovered using the write-in data stored by power loss Data Protection Technologies |
US9952974B2 (en) | 2016-06-07 | 2018-04-24 | International Business Machines Corporation | Preservation of modified cache data in local non-volatile storage following a failover |
CN107506314B (en) | 2016-06-14 | 2021-05-28 | 伊姆西Ip控股有限责任公司 | Method and apparatus for managing storage system |
US10496307B1 (en) | 2016-12-30 | 2019-12-03 | EMC IP Holding Company LLC | Reaching a normal operating mode via a fastboot procedure |
CN107222340A (en) * | 2017-05-27 | 2017-09-29 | 郑州云海信息技术有限公司 | A kind of fault handling method and device based on cloud platform |
US10572359B2 (en) * | 2017-09-05 | 2020-02-25 | International Business Machines Corporation | Validation of data written via two different bus interfaces to a dual server based storage controller |
US10528475B2 (en) * | 2017-09-21 | 2020-01-07 | International Business Machines Corporation | Dynamic premigration throttling for tiered storage |
CN111124255B (en) | 2018-10-31 | 2023-09-08 | 伊姆西Ip控股有限责任公司 | Data storage method, electronic device and computer program product |
US11354208B2 (en) * | 2019-09-11 | 2022-06-07 | International Business Machines Corporation | Adjustment of safe data commit scan based on operational verification of non-volatile memory |
CN112765111A (en) | 2019-10-21 | 2021-05-07 | 伊姆西Ip控股有限责任公司 | Method, apparatus and computer program product for processing data |
US11409446B2 (en) * | 2020-11-11 | 2022-08-09 | Micro Technology, Inc. | Media management on power-up |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6490659B1 (en) * | 2000-03-31 | 2002-12-03 | International Business Machines Corporation | Warm start cache recovery in a dual active controller with cache coherency using stripe locks for implied storage volume reservations |
US20030065841A1 (en) * | 2001-09-28 | 2003-04-03 | Pecone Victor Key | Bus zoning in a channel independent storage controller architecture |
US6574709B1 (en) * | 1999-09-30 | 2003-06-03 | International Business Machine Corporation | System, apparatus, and method providing cache data mirroring to a data storage system |
US6601181B1 (en) * | 1999-12-14 | 2003-07-29 | Gateway, Inc. | Uninterruptible power supply apparatus and method |
US20030212864A1 (en) * | 2002-05-08 | 2003-11-13 | Hicken Michael S. | Method, apparatus, and system for preserving cache data of redundant storage controllers |
US6859890B2 (en) * | 2002-04-30 | 2005-02-22 | Lsi Logic Corporation | Method for reducing data/parity inconsistencies due to a storage controller failure |
US7003620B2 (en) * | 2002-11-26 | 2006-02-21 | M-Systems Flash Disk Pioneers Ltd. | Appliance, including a flash memory, that is robust under power failure |
US7120559B1 (en) * | 2004-06-29 | 2006-10-10 | Sun Microsystems, Inc. | System and method for performing automated system management |
US7159022B2 (en) * | 2001-01-26 | 2007-01-02 | American Power Conversion Corporation | Method and system for a set of network appliances which can be connected to provide enhanced collaboration, scalability, and reliability |
US20070088975A1 (en) * | 2005-10-18 | 2007-04-19 | Dot Hill Systems Corp. | Method and apparatus for mirroring customer data and metadata in paired controllers |
US7328324B2 (en) * | 2005-04-27 | 2008-02-05 | Dot Hill Systems Corp. | Multiple mode controller method and apparatus |
US7441081B2 (en) * | 2004-12-29 | 2008-10-21 | Lsi Corporation | Write-back caching for disk drives |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5802561A (en) | 1996-06-28 | 1998-09-01 | Digital Equipment Corporation | Simultaneous, mirror write cache |
US6571324B1 (en) | 1997-06-26 | 2003-05-27 | Hewlett-Packard Development Company, L.P. | Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache system |
US6671705B1 (en) * | 1999-08-17 | 2003-12-30 | Emc Corporation | Remote mirroring system, device, and method |
US6574753B1 (en) * | 2000-01-10 | 2003-06-03 | Emc Corporation | Peer link fault isolation |
US6629211B2 (en) * | 2001-04-20 | 2003-09-30 | International Business Machines Corporation | Method and system for improving raid controller performance through adaptive write back/write through caching |
US6842829B1 (en) * | 2001-12-06 | 2005-01-11 | Lsi Logic Corporation | Method and apparatus to manage independent memory systems as a shared volume |
US7062675B1 (en) * | 2002-06-25 | 2006-06-13 | Emc Corporation | Data storage cache system shutdown scheme |
US7028147B2 (en) * | 2002-12-13 | 2006-04-11 | Sun Microsystems, Inc. | System and method for efficiently and reliably performing write cache mirroring |
US6917967B2 (en) * | 2002-12-13 | 2005-07-12 | Sun Microsystems, Inc. | System and method for implementing shared memory regions in distributed shared memory systems |
US7231497B2 (en) * | 2004-06-15 | 2007-06-12 | Intel Corporation | Merging write-back and write-through cache policies |
US8677086B2 (en) * | 2004-06-30 | 2014-03-18 | Emc Corporation | System for caching data |
US7702864B2 (en) * | 2004-11-18 | 2010-04-20 | International Business Machines Corporation | Apparatus, system, and method for writing stripes in parallel to unique persistent storage devices |
-
2006
- 2006-09-28 US US11/529,124 patent/US7849350B2/en active Active
-
2007
- 2007-03-27 WO PCT/US2007/007528 patent/WO2008039236A1/en active Application Filing
- 2007-03-29 US US11/729,728 patent/US7809975B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6574709B1 (en) * | 1999-09-30 | 2003-06-03 | International Business Machine Corporation | System, apparatus, and method providing cache data mirroring to a data storage system |
US6601181B1 (en) * | 1999-12-14 | 2003-07-29 | Gateway, Inc. | Uninterruptible power supply apparatus and method |
US6490659B1 (en) * | 2000-03-31 | 2002-12-03 | International Business Machines Corporation | Warm start cache recovery in a dual active controller with cache coherency using stripe locks for implied storage volume reservations |
US7159022B2 (en) * | 2001-01-26 | 2007-01-02 | American Power Conversion Corporation | Method and system for a set of network appliances which can be connected to provide enhanced collaboration, scalability, and reliability |
US20030065841A1 (en) * | 2001-09-28 | 2003-04-03 | Pecone Victor Key | Bus zoning in a channel independent storage controller architecture |
US6859890B2 (en) * | 2002-04-30 | 2005-02-22 | Lsi Logic Corporation | Method for reducing data/parity inconsistencies due to a storage controller failure |
US20030212864A1 (en) * | 2002-05-08 | 2003-11-13 | Hicken Michael S. | Method, apparatus, and system for preserving cache data of redundant storage controllers |
US7293196B2 (en) * | 2002-05-08 | 2007-11-06 | Xiotech Corporation | Method, apparatus, and system for preserving cache data of redundant storage controllers |
US7003620B2 (en) * | 2002-11-26 | 2006-02-21 | M-Systems Flash Disk Pioneers Ltd. | Appliance, including a flash memory, that is robust under power failure |
US7120559B1 (en) * | 2004-06-29 | 2006-10-10 | Sun Microsystems, Inc. | System and method for performing automated system management |
US7441081B2 (en) * | 2004-12-29 | 2008-10-21 | Lsi Corporation | Write-back caching for disk drives |
US7328324B2 (en) * | 2005-04-27 | 2008-02-05 | Dot Hill Systems Corp. | Multiple mode controller method and apparatus |
US20070088975A1 (en) * | 2005-10-18 | 2007-04-19 | Dot Hill Systems Corp. | Method and apparatus for mirroring customer data and metadata in paired controllers |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060198386A1 (en) * | 2005-03-01 | 2006-09-07 | Tong Liu | System and method for distributed information handling system cluster active-active master node |
US8954808B1 (en) * | 2010-11-30 | 2015-02-10 | Symantec Corporation | Systems and methods for performing input/output path failovers |
US9298636B1 (en) * | 2011-09-29 | 2016-03-29 | Emc Corporation | Managing data storage |
US10592364B2 (en) * | 2015-06-19 | 2020-03-17 | Hewlett Packard Enterprise Development Lp | Handling errors during run time backups |
US20170003894A1 (en) * | 2015-06-30 | 2017-01-05 | HGST Netherlands B.V. | Non-blocking caching for data storage drives |
US10698815B2 (en) * | 2015-06-30 | 2020-06-30 | Western Digital Technologies, Inc. | Non-blocking caching for data storage drives |
US20180173435A1 (en) * | 2016-12-21 | 2018-06-21 | EMC IP Holding Company LLC | Method and apparatus for caching data |
US10496287B2 (en) * | 2016-12-21 | 2019-12-03 | EMC IP Holding Company LLC | Method and apparatus for caching data |
US20230350786A1 (en) * | 2022-04-27 | 2023-11-02 | SK Hynix Inc. | Core dump in multiprocessor device |
Also Published As
Publication number | Publication date |
---|---|
US7809975B2 (en) | 2010-10-05 |
US7849350B2 (en) | 2010-12-07 |
WO2008039236A1 (en) | 2008-04-03 |
US20080082856A1 (en) | 2008-04-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7849350B2 (en) | Responding to a storage processor failure with continued write caching | |
US10776267B2 (en) | Mirrored byte addressable storage | |
US20200034304A1 (en) | Techniques to perform power fail-safe caching without atomic metadata | |
US7421535B2 (en) | Method for demoting tracks from cache | |
US7523350B2 (en) | Timer-based apparatus and method for fault-tolerant booting of a storage controller | |
US8296534B1 (en) | Techniques for using flash-based memory in recovery processing | |
US6571324B1 (en) | Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache system | |
US7805632B1 (en) | Storage system and method for rapidly recovering from a system failure | |
US7975169B2 (en) | Memory preserved cache to prevent data loss | |
US7085886B2 (en) | Autonomic power loss recovery for a multi-cluster storage sub-system | |
US9507671B2 (en) | Write cache protection in a purpose built backup appliance | |
JP4939180B2 (en) | Run initialization code to configure connected devices | |
US7895465B2 (en) | Memory preserved cache failsafe reboot mechanism | |
US9037799B2 (en) | Rebuild of redundant secondary storage cache | |
US11221927B2 (en) | Method for the implementation of a high performance, high resiliency and high availability dual controller storage system | |
US11436086B2 (en) | Raid storage-device-assisted deferred parity data update system | |
US9921913B2 (en) | Flushing host cache data before rebuilding degraded redundant virtual disk | |
WO2008121573A1 (en) | Managing write caching | |
JP5163061B2 (en) | Multiprocessor system, microprocessor, and microprocessor fault processing method | |
JP3450132B2 (en) | Cache control circuit | |
JPH10240630A (en) | Computer system and memory control method applied to the system | |
JPH07271624A (en) | Cache flashing method for duplex memory of fault tolerant computer system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: EMC CORPORATION, MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FRENCH, DAVID;SULLIVAN, DOUGLAS;SPANG, H. AUSTIN, IV;AND OTHERS;REEL/FRAME:018359/0768 Effective date: 20060926 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT, TEXAS Free format text: SECURITY AGREEMENT;ASSIGNORS:ASAP SOFTWARE EXPRESS, INC.;AVENTAIL LLC;CREDANT TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040136/0001 Effective date: 20160907 Owner name: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT, NORTH CAROLINA Free format text: SECURITY AGREEMENT;ASSIGNORS:ASAP SOFTWARE EXPRESS, INC.;AVENTAIL LLC;CREDANT TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040134/0001 Effective date: 20160907 Owner name: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLAT Free format text: SECURITY AGREEMENT;ASSIGNORS:ASAP SOFTWARE EXPRESS, INC.;AVENTAIL LLC;CREDANT TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040134/0001 Effective date: 20160907 Owner name: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., A Free format text: SECURITY AGREEMENT;ASSIGNORS:ASAP SOFTWARE EXPRESS, INC.;AVENTAIL LLC;CREDANT TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040136/0001 Effective date: 20160907 |
|
AS | Assignment |
Owner name: EMC IP HOLDING COMPANY LLC, MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:EMC CORPORATION;REEL/FRAME:040203/0001 Effective date: 20160906 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
AS | Assignment |
Owner name: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., T Free format text: SECURITY AGREEMENT;ASSIGNORS:CREDANT TECHNOLOGIES, INC.;DELL INTERNATIONAL L.L.C.;DELL MARKETING L.P.;AND OTHERS;REEL/FRAME:049452/0223 Effective date: 20190320 Owner name: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., TEXAS Free format text: SECURITY AGREEMENT;ASSIGNORS:CREDANT TECHNOLOGIES, INC.;DELL INTERNATIONAL L.L.C.;DELL MARKETING L.P.;AND OTHERS;REEL/FRAME:049452/0223 Effective date: 20190320 |
|
AS | Assignment |
Owner name: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., TEXAS Free format text: SECURITY AGREEMENT;ASSIGNORS:CREDANT TECHNOLOGIES INC.;DELL INTERNATIONAL L.L.C.;DELL MARKETING L.P.;AND OTHERS;REEL/FRAME:053546/0001 Effective date: 20200409 |
|
AS | Assignment |
Owner name: WYSE TECHNOLOGY L.L.C., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: SCALEIO LLC, MASSACHUSETTS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: MOZY, INC., WASHINGTON Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: MAGINATICS LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: FORCE10 NETWORKS, INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: EMC IP HOLDING COMPANY LLC, TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: EMC CORPORATION, MASSACHUSETTS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: DELL SYSTEMS CORPORATION, TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: DELL SOFTWARE INC., CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: DELL PRODUCTS L.P., TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: DELL MARKETING L.P., TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: DELL INTERNATIONAL, L.L.C., TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: DELL USA L.P., TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: CREDANT TECHNOLOGIES, INC., TEXAS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: AVENTAIL LLC, CALIFORNIA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 Owner name: ASAP SOFTWARE EXPRESS, INC., ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH;REEL/FRAME:058216/0001 Effective date: 20211101 |
|
AS | Assignment |
Owner name: SCALEIO LLC, MASSACHUSETTS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC), MASSACHUSETTS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: DELL PRODUCTS L.P., TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: DELL INTERNATIONAL L.L.C., TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: DELL USA L.P., TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 Owner name: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061324/0001 Effective date: 20220329 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: SCALEIO LLC, MASSACHUSETTS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC), MASSACHUSETTS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: DELL PRODUCTS L.P., TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: DELL INTERNATIONAL L.L.C., TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: DELL USA L.P., TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 Owner name: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.), TEXAS Free format text: RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001);ASSIGNOR:THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT;REEL/FRAME:061753/0001 Effective date: 20220329 |