US20080185734A1 - Power control structure for managing a plurality of voltage islands - Google Patents
Power control structure for managing a plurality of voltage islands Download PDFInfo
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- US20080185734A1 US20080185734A1 US12/101,826 US10182608A US2008185734A1 US 20080185734 A1 US20080185734 A1 US 20080185734A1 US 10182608 A US10182608 A US 10182608A US 2008185734 A1 US2008185734 A1 US 2008185734A1
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
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- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0262—Arrangements for regulating voltages or for using plural voltages
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10053—Switch
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Definitions
- the present invention relates generally to the data processing field, and more particularly, relates to a method and power control structures for managing a plurality of voltage islands of a functional chip.
- Power dissipation today and as projected into the future is clearly one of the key limitations for electronic components and systems.
- Power dissipation issues with current and future silicon technologies include a significant leakage current component resulting from thinner oxides associated with smaller feature sizes of the ever-shrinking transistor sizes.
- BGA ball grid array
- BGA connections are not limited to BGA solder connections and should be understood to include multiple various other chip carrier technologies including, for example, Land Grid Array (LGA), pin grid array, copper-copper thermal compression connections and similar devices.
- LGA Land Grid Array
- pin grid array pin grid array
- copper-copper thermal compression connections and similar devices.
- substrate carrier should be understood to include a chip carrier, a module carrier, and a printed circuit board or PCB.
- printed circuit board or PCB means a substrate or multiple layers (multi-layer) of substrates used to electrically attach electrical components and should be understood to generally include circuit cards, printed circuit cards, printed wiring cards, and printed wiring boards.
- a power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip.
- the power control structure includes a supply control and partition chip positioned between a substrate carrier and the functional chip including the plurality of voltage islands.
- the supply control and partition chip is supported by the substrate carrier and carries the functional chip.
- the supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands.
- the supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied by predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.
- the supply control and partition chip selectively adjusts a local voltage coupled by a set of predetermined ones of the first electrical connections to the functional chip. More of the first electrical connections or interconnects at a tighter pitch are provided between the supply control and partition chip and the functional chip than the second electrical connections between the supply control and partition chip and the substrate carrier.
- FIG. 1 is a side view not to scale illustrating an exemplary power control structure for managing a plurality of voltage islands in accordance with the preferred embodiment
- FIG. 2 is a top view illustrating exemplary control functions of a supply control and partition chip in accordance with the preferred embodiment
- FIG. 3 is a side view not to scale illustrating an exemplary power control structure for managing a plurality of voltage islands in accordance with another preferred embodiment
- FIG. 4 is a side view not to scale illustrating an exemplary power control structure for managing a plurality of voltage islands in accordance with yet another preferred embodiment.
- a power control method and structures are provided for managing power to a plurality of voltage islands on a chip.
- the power control method and structures of the invention enables removing voltage from unused functions and macros on the chip and thus eliminate the leakage current component.
- the power control structures of the invention avoid the conventional challenge of increased complexity for routing and controlling the voltage islands on a PCB and through a chip carrier.
- a power control method and structures are provided for optimizing chip performance where certain functions may be the cycle limiting path.
- Power control structures of the invention are provided for selectively raising or lowering the voltage to selected functions, such as the floating point unit, or the processor, or arrays only when needed for maximizing performance of particular functions.
- Power control structures of the invention are provided for selectively lowering the voltage on selected segments of the chip in order to keep the total power dissipation of the given chip to an acceptable level and to better optimize performance of a system.
- a semiconductor device or sub-carrier chip with embedded power control circuits is placed between a conventional carrier and a functional chip or chips including a plurality of voltage islands.
- the voltage islands are selectively controlled either in an on-off fashion to reduce power dissipation or in an analog fashion to better optimize the use of the limited power dissipation and or cooling capabilities.
- FIG. 1 there is shown an exemplary power control structure for managing a plurality of voltage islands generally designated by the reference character 100 in accordance with the preferred embodiment.
- Power control structure 100 includes a supply control and partition chip generally designated by the reference character 102 in accordance with the preferred embodiment.
- Supply control and partition chip 102 of the present invention containing power capable switch and control devices for managing a plurality of voltage islands of a chip advantageously is used for coupling between a chip to chip carrier, a chip to PCB, and a multi-chip module to PCB.
- power control structure 100 includes the supply control and partition chip 102 positioned between a functional chip 104 and a substrate carrier 106 .
- Supply control and partition chip 102 is electrically connected to the functional chip 104 , by a plurality of electrical connections generally designated by the reference character 108 on an upper surface 110 of the supply control and partition chip.
- Supply control and partition chip 102 is electrically connected to the substrate carrier 106 by a plurality of electrical connections generally designated by the reference character 112 on a lower surface 114 of the supply control and partition chip.
- the plurality of electrical connections 108 and 112 include, for example, solder bumps, such as solder bumps formed by controlled collapse chip connection (C4), and arranged, for example, as a ball grid array (BGA).
- Supply control and partition chip 102 contains switching elements, such as silicon controlled rectifiers (SCRs), or Darlington transistor pairs, or small regulator devices, Micro-Electronic-Mechanical Systems (MEMS) devices, or other switch capable device architectures.
- Supply control and partition chip 102 advantageously contains also some amount of embedded capacitance to support the local supply transients caused by ramping up or down the voltage either in small increments or in a controlled turn-on/turn-off fashion.
- Supply control and partition chip 102 typically contains also some amount of control logic which is managed by a controller with knowledge of what functions or portions of functions may be required versus what can be turned off, or have a supply voltage selectively adjusted or modified up or down.
- Supply control and partition chip 102 is managed by either hardware or software which determines when, for example, a floating point engine would be used or could be shut down due to projected inactivity.
- supply control and partition chip 102 includes a predefined pattern generally designated by the reference character 200 of electrical connections 108 .
- Each power electrical connection or solder bump 108 can be switched on and off by switch and control circuitry within chip 102 , or can be coupled to a linear control set of circuitry within chip 102 to adjust a local voltage coupled by a particular electrical connection or solder bump 108 to a particular functional island on the functional chip 104 .
- a plurality of selected ones 202 of the electrical connections 108 indicated by dotted lines represent, for example, selected connections that are selectively turned on and turned off.
- a plurality of selected ones 204 of the electrical connections 108 indicated by shading represent, for example, a linear control set of for modifying a local supply voltage applied to a particular functional island on the functional chip 104 .
- the supply control and partition chip 102 can be used to switch the solder bumps or connections 108 between one voltage and another voltage. This could be a very important technique to allow for the migration of functions between different technologies. This approach could be used in its simplest form to connect an appropriate I/O supply, for example, from substrate carrier 106 to a driver/receiver cell of functional chip 104 to simplify the design of circuitry, which must be able to interoperate between the different supply voltages of different silicon technologies.
- the supply control and partition chip 102 can include a regular grid arrangement for signal and power pass through electrical connections 108 and 112 .
- the supply control and partition chip 102 includes a register accessible/controllable switch device to open and close the interconnect 108 of power between the power structure of the functional chip 104 containing a given number of voltage islands and the substrate carrier 106 .
- a particular supply control and partition chip 102 can be used for different types of functional chips 104 , that is for more than one functional chip part number.
- the additional features over traditional packages include control signals which identify and switch certain solder bumps 108 on and off between the functional chip 104 and the substrate carrier 106 . These control signals could originate either in the functional chip 104 or in the system path between another card or board (not shown) and the substrate carrier 106 .
- signals from substrate carrier 106 typically are routed directly through the supply control and partition chip 102 to the functional chip 104 , for example, essentially going in a straight-through path.
- signals from substrate carrier 106 typically are routed directly through the supply control and partition chip 102 to the functional chip 104 , for example, essentially going in a straight-through path.
- a coaxial like structure generally designated by reference character 210 is provided around a signal path or connection 108 labeled S and include a grid of electrical connections 108 labeled G surrounding the particular signal connection S.
- Capacitance and additional power and ground wiring included in the supply control and partition chip 102 is provided to compensate for and depending on the design could improve the power structure by having more decoupling. This added decoupling is used to offset any increase in inductance to on-module or on-card decoupling.
- utilizing the ability to have more interconnects at a tighter pitch in the connection between a supply control and partition chip and a functional chip enables finer control and partition on the functional chip than would otherwise be possible with conventional packaging approaches.
- such an interconnection arrangement is illustrated and described with respect to power control structures of FIGS. 3 and 4 .
- Power control structure 300 includes a supply control and partition chip generally designated by the reference character 302 in accordance with the preferred embodiment.
- power control structure 300 includes the supply control and partition chip 302 positioned between a functional chip 304 and a substrate carrier 306 .
- Supply control and partition chip 302 is electrically connected to the functional chip 304 , by a plurality of electrical connections generally designated by the reference character 308 on an upper surface 310 of the supply control and partition chip.
- Supply control and partition chip 302 is electrically connected to the substrate carrier 306 by a plurality of electrical connections generally designated by the reference character 312 on a lower surface 314 of the supply control and partition chip.
- the plurality of electrical connections 308 and 312 include, for example, solder bumps, such as solder bumps formed by controlled collapse chip connection (C4), and arranged, for example, as a ball grid array (BGA).
- the plurality of electrical connections 308 to the functional chip 304 has a substantially smaller or tighter pitch than the plurality of electrical connections 312 to the substrate carrier 306 .
- Power control structure 400 includes a supply control and partition chip generally designated by the reference character 402 in accordance with the preferred embodiment.
- Power control structure 400 includes a Multi-chip Module arrangement with the single supply control and partition chip 402 .
- power control structure 400 includes the supply control and partition chip 402 positioned between a pair of functional chips 404 A, 404 B and a substrate carrier 406 .
- Supply control and partition chip 402 is electrically connected to the functional chip chips 404 A, 404 B, by a respective plurality of electrical connections generally designated by the reference characters 408 A, 408 B on an upper surface 410 of the supply control and partition chip.
- Supply control and partition chip 402 is electrically connected to the substrate carrier 406 by a plurality of electrical connections generally designated by the reference character 412 on a lower surface 414 of the supply control and partition chip.
- the plurality of electrical connections 408 A, 408 B and 412 include, for example, solder bumps, such as solder bumps formed by controlled collapse chip connection (C4), and arranged, for example, as a ball grid array (BGA).
- the plurality of respective electrical connections 408 A, 408 B to the functional chips 404 A, 404 B has a substantially smaller or tighter pitch than the plurality of electrical connections 412 to the substrate carrier 406 .
- the present invention is not limited to the use of through hole silicon structures; for example, wire-bond, ball-bond, tab or other attach mechanisms can be used for electrical connections between respective functional chip 104 , 304 , functional chips 404 A, 404 B and the respective supply control and partition chip 102 , 302 , 402 . It should be understood that the present invention is not limited to just two layers, such as defined by the respective functional chip 104 , 304 , functional chips 404 A, 404 B and the supply control and partition chip 102 , 302 , 402 , and can be extended to more than two layers, for example, including more than one power-control silicon chip 102 , 302 , 402 .
Abstract
A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied to predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.
Description
- The present invention relates generally to the data processing field, and more particularly, relates to a method and power control structures for managing a plurality of voltage islands of a functional chip.
- Power dissipation today and as projected into the future is clearly one of the key limitations for electronic components and systems. Power dissipation issues with current and future silicon technologies include a significant leakage current component resulting from thinner oxides associated with smaller feature sizes of the ever-shrinking transistor sizes.
- Approaches to control power dissipation have generally included the stopping of clocks to a segment of the chip. As leakage current becomes such a large component of the total power dissipation, stopping the clocks is no longer an adequate solution to the problem.
- A need exists for an effective mechanism for minimizing leakage current and overall power dissipation.
- As used in the following description and claims the terms ball grid array (BGA) device and BGA connections are not limited to BGA solder connections and should be understood to include multiple various other chip carrier technologies including, for example, Land Grid Array (LGA), pin grid array, copper-copper thermal compression connections and similar devices.
- As used in the present specification and claims, the term substrate carrier should be understood to include a chip carrier, a module carrier, and a printed circuit board or PCB.
- As used in the present specification and claims, the term printed circuit board or PCB means a substrate or multiple layers (multi-layer) of substrates used to electrically attach electrical components and should be understood to generally include circuit cards, printed circuit cards, printed wiring cards, and printed wiring boards.
- Principal aspects of the present invention are to provide a power control method and power control structures for managing a plurality of voltage islands of a functional chip. Other important aspects of the present invention are to provide such power control method and power control structures substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
- In brief, a power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and the functional chip including the plurality of voltage islands. The supply control and partition chip is supported by the substrate carrier and carries the functional chip. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied by predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.
- In accordance with features of the invention, the supply control and partition chip selectively adjusts a local voltage coupled by a set of predetermined ones of the first electrical connections to the functional chip. More of the first electrical connections or interconnects at a tighter pitch are provided between the supply control and partition chip and the functional chip than the second electrical connections between the supply control and partition chip and the substrate carrier.
- The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
-
FIG. 1 is a side view not to scale illustrating an exemplary power control structure for managing a plurality of voltage islands in accordance with the preferred embodiment; -
FIG. 2 is a top view illustrating exemplary control functions of a supply control and partition chip in accordance with the preferred embodiment; -
FIG. 3 is a side view not to scale illustrating an exemplary power control structure for managing a plurality of voltage islands in accordance with another preferred embodiment; and -
FIG. 4 is a side view not to scale illustrating an exemplary power control structure for managing a plurality of voltage islands in accordance with yet another preferred embodiment. - In accordance with features of the preferred embodiments, a power control method and structures are provided for managing power to a plurality of voltage islands on a chip. The power control method and structures of the invention enables removing voltage from unused functions and macros on the chip and thus eliminate the leakage current component. The power control structures of the invention avoid the conventional challenge of increased complexity for routing and controlling the voltage islands on a PCB and through a chip carrier.
- In accordance with features of the preferred embodiments, a power control method and structures are provided for optimizing chip performance where certain functions may be the cycle limiting path. Power control structures of the invention are provided for selectively raising or lowering the voltage to selected functions, such as the floating point unit, or the processor, or arrays only when needed for maximizing performance of particular functions. Power control structures of the invention are provided for selectively lowering the voltage on selected segments of the chip in order to keep the total power dissipation of the given chip to an acceptable level and to better optimize performance of a system.
- In accordance with features of the preferred embodiments, a semiconductor device or sub-carrier chip with embedded power control circuits is placed between a conventional carrier and a functional chip or chips including a plurality of voltage islands. The voltage islands are selectively controlled either in an on-off fashion to reduce power dissipation or in an analog fashion to better optimize the use of the limited power dissipation and or cooling capabilities.
- Having reference now to the drawings, in
FIG. 1 , there is shown an exemplary power control structure for managing a plurality of voltage islands generally designated by thereference character 100 in accordance with the preferred embodiment.Power control structure 100 includes a supply control and partition chip generally designated by thereference character 102 in accordance with the preferred embodiment. - Supply control and
partition chip 102 of the present invention containing power capable switch and control devices for managing a plurality of voltage islands of a chip advantageously is used for coupling between a chip to chip carrier, a chip to PCB, and a multi-chip module to PCB. - As shown in
FIG. 1 ,power control structure 100 includes the supply control andpartition chip 102 positioned between afunctional chip 104 and asubstrate carrier 106. Supply control andpartition chip 102 is electrically connected to thefunctional chip 104, by a plurality of electrical connections generally designated by thereference character 108 on anupper surface 110 of the supply control and partition chip. Supply control andpartition chip 102 is electrically connected to thesubstrate carrier 106 by a plurality of electrical connections generally designated by thereference character 112 on alower surface 114 of the supply control and partition chip. The plurality ofelectrical connections - Supply control and
partition chip 102 contains switching elements, such as silicon controlled rectifiers (SCRs), or Darlington transistor pairs, or small regulator devices, Micro-Electronic-Mechanical Systems (MEMS) devices, or other switch capable device architectures. Supply control andpartition chip 102 advantageously contains also some amount of embedded capacitance to support the local supply transients caused by ramping up or down the voltage either in small increments or in a controlled turn-on/turn-off fashion. Supply control andpartition chip 102 typically contains also some amount of control logic which is managed by a controller with knowledge of what functions or portions of functions may be required versus what can be turned off, or have a supply voltage selectively adjusted or modified up or down. Supply control andpartition chip 102 is managed by either hardware or software which determines when, for example, a floating point engine would be used or could be shut down due to projected inactivity. - Referring to
FIG. 2 , supply control andpartition chip 102 includes a predefined pattern generally designated by thereference character 200 ofelectrical connections 108. Each power electrical connection orsolder bump 108 can be switched on and off by switch and control circuitry withinchip 102, or can be coupled to a linear control set of circuitry withinchip 102 to adjust a local voltage coupled by a particular electrical connection orsolder bump 108 to a particular functional island on thefunctional chip 104. - A plurality of selected
ones 202 of theelectrical connections 108 indicated by dotted lines represent, for example, selected connections that are selectively turned on and turned off. A plurality of selectedones 204 of theelectrical connections 108 indicated by shading represent, for example, a linear control set of for modifying a local supply voltage applied to a particular functional island on thefunctional chip 104. - In accordance with features of the preferred embodiments, the supply control and
partition chip 102 can be used to switch the solder bumps orconnections 108 between one voltage and another voltage. This could be a very important technique to allow for the migration of functions between different technologies. This approach could be used in its simplest form to connect an appropriate I/O supply, for example, fromsubstrate carrier 106 to a driver/receiver cell offunctional chip 104 to simplify the design of circuitry, which must be able to interoperate between the different supply voltages of different silicon technologies. - In the illustrated embodiment of
power control structure 100, the supply control andpartition chip 102 can include a regular grid arrangement for signal and power pass throughelectrical connections power structure connections 108, the supply control andpartition chip 102 includes a register accessible/controllable switch device to open and close theinterconnect 108 of power between the power structure of thefunctional chip 104 containing a given number of voltage islands and thesubstrate carrier 106. A particular supply control andpartition chip 102 can be used for different types offunctional chips 104, that is for more than one functional chip part number. The additional features over traditional packages include control signals which identify and switchcertain solder bumps 108 on and off between thefunctional chip 104 and thesubstrate carrier 106. These control signals could originate either in thefunctional chip 104 or in the system path between another card or board (not shown) and thesubstrate carrier 106. - In accordance with features of the preferred embodiments, signals from
substrate carrier 106 typically are routed directly through the supply control andpartition chip 102 to thefunctional chip 104, for example, essentially going in a straight-through path. Given the ability to make smaller micro-bumps on the silicon, it is also possible to build a coaxial like structure around a signal path to help compensate for the slightly longer path for the signals through the supply control andpartition chip 102 of the invention. - For example, as illustrated in
FIG. 2 , a coaxial like structure generally designated byreference character 210 is provided around a signal path orconnection 108 labeled S and include a grid ofelectrical connections 108 labeled G surrounding the particular signal connection S. Capacitance and additional power and ground wiring included in the supply control andpartition chip 102 is provided to compensate for and depending on the design could improve the power structure by having more decoupling. This added decoupling is used to offset any increase in inductance to on-module or on-card decoupling. - In accordance with features of other preferred embodiments, utilizing the ability to have more interconnects at a tighter pitch in the connection between a supply control and partition chip and a functional chip, enables finer control and partition on the functional chip than would otherwise be possible with conventional packaging approaches. For example, such an interconnection arrangement is illustrated and described with respect to power control structures of
FIGS. 3 and 4 . - Referring now to
FIG. 3 , there is shown another exemplary power control structure for managing a plurality of voltage islands generally designated by thereference character 300 in accordance with the preferred embodiment.Power control structure 300 includes a supply control and partition chip generally designated by thereference character 302 in accordance with the preferred embodiment. - As shown in
FIG. 3 ,power control structure 300 includes the supply control andpartition chip 302 positioned between afunctional chip 304 and asubstrate carrier 306. Supply control andpartition chip 302 is electrically connected to thefunctional chip 304, by a plurality of electrical connections generally designated by thereference character 308 on anupper surface 310 of the supply control and partition chip. Supply control andpartition chip 302 is electrically connected to thesubstrate carrier 306 by a plurality of electrical connections generally designated by thereference character 312 on alower surface 314 of the supply control and partition chip. The plurality ofelectrical connections - In the
power control structure 300, the plurality ofelectrical connections 308 to thefunctional chip 304 has a substantially smaller or tighter pitch than the plurality ofelectrical connections 312 to thesubstrate carrier 306. - Referring now to
FIG. 4 , there is shown another exemplary power control structure for managing a plurality of voltage islands generally designated by thereference character 400 in accordance with the preferred embodiment.Power control structure 400 includes a supply control and partition chip generally designated by thereference character 402 in accordance with the preferred embodiment.Power control structure 400 includes a Multi-chip Module arrangement with the single supply control andpartition chip 402. - As shown in
FIG. 4 ,power control structure 400 includes the supply control andpartition chip 402 positioned between a pair offunctional chips substrate carrier 406. Supply control andpartition chip 402 is electrically connected to thefunctional chip chips reference characters upper surface 410 of the supply control and partition chip. Supply control andpartition chip 402 is electrically connected to thesubstrate carrier 406 by a plurality of electrical connections generally designated by thereference character 412 on alower surface 414 of the supply control and partition chip. The plurality ofelectrical connections - In the
power control structure 400, the plurality of respectiveelectrical connections functional chips electrical connections 412 to thesubstrate carrier 406. - It should be understood that the present invention is not limited to the use of through hole silicon structures; for example, wire-bond, ball-bond, tab or other attach mechanisms can be used for electrical connections between respective
functional chip functional chips partition chip functional chip functional chips partition chip control silicon chip - While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
Claims (13)
1. A power control structure for managing a plurality of voltage islands of a functional chip comprising:
a substrate carrier;
a supply control and partition chip being positioned between said substrate carrier and the functional chip including a plurality of voltage islands;
said supply control and partition chip including a plurality of first electrical connections to the functional chip including the plurality of voltage islands;
said supply control and partition chip including a plurality of second electrical connections to the substrate carrier; and
said supply control and partition chip selectively switching on and off power applied to predefined ones of the first electrical connections to the functional chip.
2. The power control structure as recited in claim 1 wherein said supply control and partition chip selectively adjusts a local voltage coupled by a set of predetermined ones of said first electrical connections to said functional chip.
3. The power control structure as recited in claim 1 wherein said supply control and partition chip includes predefined ones of said first electrical connections being connected to respective ones of said second electrical connections for coupling signals between said substrate carrier and the functional chip.
4. The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip has a smaller pitch than said plurality of second electrical connections to said substrate carrier.
5. The power control structure as recited in claim 1 wherein said supply control and partition chip is positioned between said substrate carrier and a pair of the functional chips, wherein said supply control and partition chip including a plurality of first electrical connections to each of the functional chips.
6. The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip include a pattern of solder bumps.
7. The power control structure as recited in claim 6 wherein said pattern of solder bumps is formed by controlled collapse chip connection (C4).
8. The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip includes a ball grid array (BGA).
9. The power control structure as recited in claim 1 wherein said plurality of second electrical connections to said substrate carrier includes a pattern of solder bumps.
10. The power control structure as recited in claim 1 wherein said plurality of second electrical connections to said substrate carrier includes ball grid array (BGA).
11. The power control structure as recited in claim 1 wherein said plurality of first electrical connections to the functional chip include a coaxial signal structure.
12. The power control structure as recited in claim 11 wherein said coaxial signal structure includes a predefined signal first electrical connection coupling a signal; and a group of predefined first electrical connections surrounding said predefined signal first electrical connection coupled to ground potential.
13-15. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US12/101,826 US20080185734A1 (en) | 2005-12-15 | 2008-04-11 | Power control structure for managing a plurality of voltage islands |
Applications Claiming Priority (2)
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US11/304,138 US7402912B2 (en) | 2005-12-15 | 2005-12-15 | Method and power control structure for managing plurality of voltage islands |
US12/101,826 US20080185734A1 (en) | 2005-12-15 | 2008-04-11 | Power control structure for managing a plurality of voltage islands |
Related Parent Applications (1)
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US11/304,138 Continuation US7402912B2 (en) | 2005-12-15 | 2005-12-15 | Method and power control structure for managing plurality of voltage islands |
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US20080185734A1 true US20080185734A1 (en) | 2008-08-07 |
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US11/304,138 Expired - Fee Related US7402912B2 (en) | 2005-12-15 | 2005-12-15 | Method and power control structure for managing plurality of voltage islands |
US12/101,826 Abandoned US20080185734A1 (en) | 2005-12-15 | 2008-04-11 | Power control structure for managing a plurality of voltage islands |
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US11/304,138 Expired - Fee Related US7402912B2 (en) | 2005-12-15 | 2005-12-15 | Method and power control structure for managing plurality of voltage islands |
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Cited By (1)
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US20080024197A1 (en) * | 2006-03-31 | 2008-01-31 | Kerry Bernstein | Method and architecture for power management of an electronic device |
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US8110899B2 (en) * | 2006-12-20 | 2012-02-07 | Intel Corporation | Method for incorporating existing silicon die into 3D integrated stack |
US7667487B2 (en) * | 2008-01-10 | 2010-02-23 | International Business Machines Corporation | Techniques for providing switchable decoupling capacitors for an integrated circuit |
US8001394B2 (en) * | 2008-01-31 | 2011-08-16 | International Business Machines Corporation | Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes |
US8156287B2 (en) * | 2009-01-15 | 2012-04-10 | International Business Machines Corporation | Adaptive data prefetch |
US8212537B2 (en) * | 2009-07-23 | 2012-07-03 | International Business Machines Corporation | Integratable efficient switching down converter |
KR101286923B1 (en) | 2012-04-06 | 2013-07-16 | 박혜성 | Device for supplying direct current |
JP2015069333A (en) * | 2013-09-27 | 2015-04-13 | 富士通セミコンダクター株式会社 | Design method and design program |
CN106332499A (en) * | 2015-06-26 | 2017-01-11 | 台达电子工业股份有限公司 | Assembled structure for chip power supply, and electronic device |
KR20200145964A (en) * | 2019-06-21 | 2020-12-31 | 삼성디스플레이 주식회사 | Display device |
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Also Published As
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US7402912B2 (en) | 2008-07-22 |
US20070138653A1 (en) | 2007-06-21 |
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