US20080197495A1 - Structure for reducing lateral fringe capacitance in semiconductor devices - Google Patents
Structure for reducing lateral fringe capacitance in semiconductor devices Download PDFInfo
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- US20080197495A1 US20080197495A1 US12/106,396 US10639608A US2008197495A1 US 20080197495 A1 US20080197495 A1 US 20080197495A1 US 10639608 A US10639608 A US 10639608A US 2008197495 A1 US2008197495 A1 US 2008197495A1
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- conductive lines
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- cap layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to semiconductor device processing techniques, and, more particularly, to a structure for reducing lateral fringe capacitance in semiconductor devices and a method of forming the same.
- a typical dual-damascene structure is fabricated by depositing a dielectric material, defining the lines and vias through lithography and etching, then metallizing to fill the patterned lines and vias, the polishing the excess metal to completed lines. After chemical mechanical polishing (CMP), the surface is nearly flat and the current carrying lines are isolated from adjacent lines to complete the circuitry. At this point, the copper layer is typically capped and a subsequent dielectric layer is deposited.
- CMP chemical mechanical polishing
- one undesirable side effect of the increasing density of integrated circuits described above is a parasitic lateral capacitance between adjacent metal lines in a given metal layer. This unneeded capacitance slows circuit performance by causing too much buildup of charge where none is needed, thereby slowing the buildup of charge at circuit elements where it is needed.
- FIG. 1 illustrates a cross sectional view of partially formed, conventional integrated circuit device 100 .
- An interlevel dielectric (ILD) layer 102 such as silicon dioxide (SiO2) for example, has a plurality of conductive metal lines 104 formed therein.
- a dielectric cap layer 106 such as NBLoK (nitrogen-doped silicon carbide) is formed thereupon.
- the dielectric constant of the ILD layer 102 is on the order of about 2.5-3.0
- the dielectric constant of the NBLoK cap layer 106 is about 6 . 0 .
- the lateral capacitance (C) between adjacent metal lines 104 of the structure 100 is influenced by several factors, two of which are: (1) the capacitance due to the ILD material 102 between the lines 102 and (2) the fringe capacitance as a result of the overlaying NBLoK cap 106 .
- the capacitance contribution due to the ILD material 102 can be lowered by replacing silicon dioxide with a lower-k dielectric, it is much tougher to simply replace the NBLoK cap layer, as such a layer serves multiple functions that make it tough to replace as a material.
- the method includes defining a plurality of conductive lines within an interlevel dielectric (ILD) layer having a hardmask layer formed thereon, and recessing fill material of the conductive lines to a level below the top of the ILD layer.
- ILD interlevel dielectric
- a protective insulation layer is formed over the top of the recessed fill material, and a domed pattern is defined within the hardmask layer, thereby removing the protective insulation layer.
- the hardmask layer is removed so as to transfer the domed pattern into the top of the ILD layer, and a cap layer is formed over the ILD layer and the conductive lines, wherein the cap layer takes the form of the domed pattern.
- a semiconductor structure in another embodiment, includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
- ILD interlevel dielectric
- FIG. 1 is a cross sectional view of partially formed, conventional integrated circuit device
- FIG. 2 process flow diagram illustrating a method for reducing lateral fringe capacitance in semiconductor devices
- FIGS. 3( a ) through 3 ( g ) are cross sectional views of a semiconductor structure for reducing lateral fringe capacitance, in accordance with the method described in FIG. 2 .
- a domed cap structure is formed such that a higher-k cap layer is physically arched away from the top of the metal lines at the locations between the lines themselves, thereby decreasing the overall lateral capacitance of the device.
- a method of fabricating a domed capacitance structure is illustrated.
- a dual (or single) damascene structure is fabricated up through a CMP operation.
- the ILD layer 302 has a hardmask layer 303 formed thereon, followed by the patterning of lines 304 that are filled by the conductive material (e.g., copper).
- the conductive material e.g., copper.
- the particular CMP process used to planarize the copper fill may or may not need to be altered in order to preserve the hardmask layer 303 .
- the copper fill material is recessed past the bottom of the hardmask layer 303 to its final height below the top of ILD layer 302 .
- the recess step may be implemented through one or more of a variety of methods (such as wet etching, dry etching, CMP, etc.).
- a non-conformal or conformal deposition of a protective insulator material 306 e.g., SiO 2
- SiO 2 e.g., SiO 2
- a planarizing step is then carried out on the insulator material 306 , down to the top of the hardmask layer 303 , as shown in block 208 of FIG. 2 and in FIG. 3( d ).
- the U-shaped portions of the insulator material 306 provide a mechanism to protect the copper lines 304 during subsequent processing steps.
- an isotropic (non-directional) etch is carried so as to both remove the sacrificial insulator material portions 306 and to shape the corners of the hardmask layer 303 into rounded, domed patterns 308 .
- These domed patterns 308 are then transferred into the ILD layer 302 by an anisotropic (directional) etch, as shown in block 212 of FIG. 2 and in FIG. 3( f ).
- anisotropic transfer etch is depicted as a separate step in the Figures, the isotropic rounding etch and anisotropic transfer etches can be carried out in a single step.
- a cap layer 310 (e.g., NBLoK) is conformally deposited over the non-planar structure, thus retaining the domed pattern 308 .
- the portions of the cap layer 310 between the lines 304 are arched in an upward direction, thereby physically distancing the higher-k layer from the lines.
- the overall lateral capacitance of the lines is reduced by about 5% due to the dome height.
- the etch process it is desirable for the etch process to provide sharp comers during the fabrication of the single and dual damascene structure. Subsequent metallization on a rounded structure will tend to cause increased shorts as the burden is upon CMP to clear the liner residuals to the device manual tolerances.
- the Cu-to-Cu spacing is maintained to design rule specifications while achieving the fabrication of a domed insulator spacing.
Abstract
Description
- This non-provisional U.S. Patent Application is a divisional of pending U.S. patent application Ser. No. 11/420,253, which was filed May 25, 2006, and is assigned to the present assignee.
- The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a structure for reducing lateral fringe capacitance in semiconductor devices and a method of forming the same.
- The continuing trend in the semiconductor industry of forming more and more circuit devices into a given area has resulted in significant improvements in both the performance of individual integrated circuits and of electronic devices that employ integrated circuits. In a typical integrated circuit, individual circuit elements or groups of elements are generally electrically connected to one another by a metallization process, in which layers of metal are deposited and patterned to form metal lines which complete the circuit as designed. Individual metal lines formed within patterned metal layers are insulated from one another by layers referred to as interlevel dielectrics. These interlevel dielectrics insulate the metal lines from any undesired electrical contact with other metal lines (whether located in the same or another metal layer, and with other circuit elements.
- A typical dual-damascene structure is fabricated by depositing a dielectric material, defining the lines and vias through lithography and etching, then metallizing to fill the patterned lines and vias, the polishing the excess metal to completed lines. After chemical mechanical polishing (CMP), the surface is nearly flat and the current carrying lines are isolated from adjacent lines to complete the circuitry. At this point, the copper layer is typically capped and a subsequent dielectric layer is deposited.
- However, one undesirable side effect of the increasing density of integrated circuits described above is a parasitic lateral capacitance between adjacent metal lines in a given metal layer. This unneeded capacitance slows circuit performance by causing too much buildup of charge where none is needed, thereby slowing the buildup of charge at circuit elements where it is needed.
-
FIG. 1 illustrates a cross sectional view of partially formed, conventionalintegrated circuit device 100. An interlevel dielectric (ILD)layer 102, such as silicon dioxide (SiO2) for example, has a plurality ofconductive metal lines 104 formed therein. After a planarizing step used to polish themetal fill material 104 down to the top of theILD layer 102, adielectric cap layer 106 such as NBLoK (nitrogen-doped silicon carbide) is formed thereupon. Whereas the dielectric constant of theILD layer 102 is on the order of about 2.5-3.0, the dielectric constant of theNBLoK cap layer 106 is about 6.0. - The lateral capacitance (C) between
adjacent metal lines 104 of thestructure 100 is influenced by several factors, two of which are: (1) the capacitance due to theILD material 102 between thelines 102 and (2) the fringe capacitance as a result of theoverlaying NBLoK cap 106. Although the capacitance contribution due to theILD material 102 can be lowered by replacing silicon dioxide with a lower-k dielectric, it is much tougher to simply replace the NBLoK cap layer, as such a layer serves multiple functions that make it tough to replace as a material. - Accordingly, it would be desirable to be able to reduce the fringe contribution of lateral capacitance in metal lines in a manner that retains the benefits of using a higher dielectric constant capping layer.
- The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming a semiconductor structure. In an exemplary embodiment, the method includes defining a plurality of conductive lines within an interlevel dielectric (ILD) layer having a hardmask layer formed thereon, and recessing fill material of the conductive lines to a level below the top of the ILD layer. A protective insulation layer is formed over the top of the recessed fill material, and a domed pattern is defined within the hardmask layer, thereby removing the protective insulation layer. The hardmask layer is removed so as to transfer the domed pattern into the top of the ILD layer, and a cap layer is formed over the ILD layer and the conductive lines, wherein the cap layer takes the form of the domed pattern.
- In another embodiment, a semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
- Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
-
FIG. 1 is a cross sectional view of partially formed, conventional integrated circuit device; -
FIG. 2 process flow diagram illustrating a method for reducing lateral fringe capacitance in semiconductor devices; and -
FIGS. 3( a) through 3(g) are cross sectional views of a semiconductor structure for reducing lateral fringe capacitance, in accordance with the method described inFIG. 2 . - Disclosed herein is a method and structure for reducing the fringe component of lateral capacitance between metal lines of a semiconductor device. Briefly stated, a domed cap structure is formed such that a higher-k cap layer is physically arched away from the top of the metal lines at the locations between the lines themselves, thereby decreasing the overall lateral capacitance of the device.
- Referring now to both the flow diagram 200 of
FIG. 2 and the process sequence ofFIGS. 3( a) through 3(g), a method of fabricating a domed capacitance structure is illustrated. Beginning inblock 202 ofFIG. 2 andFIG. 3( a), a dual (or single) damascene structure is fabricated up through a CMP operation. In particular, the ILDlayer 302 has ahardmask layer 303 formed thereon, followed by the patterning oflines 304 that are filled by the conductive material (e.g., copper). The particular CMP process used to planarize the copper fill may or may not need to be altered in order to preserve thehardmask layer 303. - Then, as shown in
block 204 ofFIG. 2 and inFIG. 3( b), the copper fill material is recessed past the bottom of thehardmask layer 303 to its final height below the top ofILD layer 302. The recess step may be implemented through one or more of a variety of methods (such as wet etching, dry etching, CMP, etc.). At this stage, a non-conformal or conformal deposition of a protective insulator material 306 (e.g., SiO2) is implemented, as shown in block 206 ofFIG. 2 and inFIG. 3( c). A planarizing step is then carried out on theinsulator material 306, down to the top of thehardmask layer 303, as shown inblock 208 ofFIG. 2 and inFIG. 3( d). As a result, the U-shaped portions of theinsulator material 306 provide a mechanism to protect thecopper lines 304 during subsequent processing steps. - Referring next to
block 210 ofFIG. 2 and toFIG. 3( e), an isotropic (non-directional) etch is carried so as to both remove the sacrificial insulatormaterial portions 306 and to shape the corners of thehardmask layer 303 into rounded,domed patterns 308. Thesedomed patterns 308 are then transferred into theILD layer 302 by an anisotropic (directional) etch, as shown inblock 212 ofFIG. 2 and inFIG. 3( f). Although the anisotropic transfer etch is depicted as a separate step in the Figures, the isotropic rounding etch and anisotropic transfer etches can be carried out in a single step. - Finally, as shown in
block 214 ofFIG. 2 and inFIG. 3( g), a cap layer 310 (e.g., NBLoK) is conformally deposited over the non-planar structure, thus retaining thedomed pattern 308. As compared to the conventionalplanar structure 100 ofFIG. 1 , the portions of thecap layer 310 between thelines 304 are arched in an upward direction, thereby physically distancing the higher-k layer from the lines. In turn, the overall lateral capacitance of the lines is reduced by about 5% due to the dome height. - It is desirable for the etch process to provide sharp comers during the fabrication of the single and dual damascene structure. Subsequent metallization on a rounded structure will tend to cause increased shorts as the burden is upon CMP to clear the liner residuals to the device manual tolerances. By fabricating the structure in the manner described above, the Cu-to-Cu spacing is maintained to design rule specifications while achieving the fabrication of a domed insulator spacing.
- While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (3)
Priority Applications (1)
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US12/106,396 US20080197495A1 (en) | 2006-05-25 | 2008-04-21 | Structure for reducing lateral fringe capacitance in semiconductor devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/420,253 US7456099B2 (en) | 2006-05-25 | 2006-05-25 | Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices |
US12/106,396 US20080197495A1 (en) | 2006-05-25 | 2008-04-21 | Structure for reducing lateral fringe capacitance in semiconductor devices |
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US11/420,253 Division US7456099B2 (en) | 2006-05-25 | 2006-05-25 | Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices |
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US20080197495A1 true US20080197495A1 (en) | 2008-08-21 |
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US11/420,253 Expired - Fee Related US7456099B2 (en) | 2006-05-25 | 2006-05-25 | Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices |
US12/106,396 Abandoned US20080197495A1 (en) | 2006-05-25 | 2008-04-21 | Structure for reducing lateral fringe capacitance in semiconductor devices |
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US11/420,253 Expired - Fee Related US7456099B2 (en) | 2006-05-25 | 2006-05-25 | Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices |
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CN (1) | CN100483678C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130309871A1 (en) * | 2008-11-24 | 2013-11-21 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7470616B1 (en) | 2008-05-15 | 2008-12-30 | International Business Machines Corporation | Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention |
Citations (6)
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US6107183A (en) * | 1996-07-10 | 2000-08-22 | Micron Technology, Inc. | Method of forming an interlevel dielectric |
US6124176A (en) * | 1996-03-07 | 2000-09-26 | Nec Corporation | Method of producing a semiconductor device with reduced fringe capacitance and short channel effect |
US6593639B2 (en) * | 1998-12-23 | 2003-07-15 | Microchip Technology Incorporated | Layout technique for a capacitor array using continuous upper electrodes |
US20040097013A1 (en) * | 2002-11-15 | 2004-05-20 | Water Lur | Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device |
US6774421B2 (en) * | 1998-09-03 | 2004-08-10 | Micron Technology, Inc. | Gapped-plate capacitor |
US20070267730A1 (en) * | 2006-05-16 | 2007-11-22 | Tessera, Inc. | Wafer level semiconductor chip packages and methods of making the same |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6495917B1 (en) * | 2000-03-17 | 2002-12-17 | International Business Machines Corporation | Method and structure of column interconnect |
US20030134499A1 (en) * | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof |
US7241696B2 (en) * | 2002-12-11 | 2007-07-10 | International Business Machines Corporation | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer |
KR100583957B1 (en) * | 2003-12-03 | 2006-05-26 | 삼성전자주식회사 | Method of forming a dual damascene metal interconnection employing a sacrificial metal oxide layer |
-
2006
- 2006-05-25 US US11/420,253 patent/US7456099B2/en not_active Expired - Fee Related
-
2007
- 2007-04-17 CN CNB2007100970205A patent/CN100483678C/en not_active Expired - Fee Related
-
2008
- 2008-04-21 US US12/106,396 patent/US20080197495A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6124176A (en) * | 1996-03-07 | 2000-09-26 | Nec Corporation | Method of producing a semiconductor device with reduced fringe capacitance and short channel effect |
US6107183A (en) * | 1996-07-10 | 2000-08-22 | Micron Technology, Inc. | Method of forming an interlevel dielectric |
US6841463B1 (en) * | 1996-07-10 | 2005-01-11 | Micron Technology, Inc. | Interlevel dielectric structure and method of forming same |
US6774421B2 (en) * | 1998-09-03 | 2004-08-10 | Micron Technology, Inc. | Gapped-plate capacitor |
US6593639B2 (en) * | 1998-12-23 | 2003-07-15 | Microchip Technology Incorporated | Layout technique for a capacitor array using continuous upper electrodes |
US20040097013A1 (en) * | 2002-11-15 | 2004-05-20 | Water Lur | Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device |
US20070267730A1 (en) * | 2006-05-16 | 2007-11-22 | Tessera, Inc. | Wafer level semiconductor chip packages and methods of making the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130309871A1 (en) * | 2008-11-24 | 2013-11-21 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
US8871646B2 (en) * | 2008-11-24 | 2014-10-28 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
US20070275552A1 (en) | 2007-11-29 |
CN101079394A (en) | 2007-11-28 |
CN100483678C (en) | 2009-04-29 |
US7456099B2 (en) | 2008-11-25 |
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