US20080224093A1 - Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant - Google Patents
Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant Download PDFInfo
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- US20080224093A1 US20080224093A1 US12/106,023 US10602308A US2008224093A1 US 20080224093 A1 US20080224093 A1 US 20080224093A1 US 10602308 A US10602308 A US 10602308A US 2008224093 A1 US2008224093 A1 US 2008224093A1
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- 238000004519 manufacturing process Methods 0.000 title description 22
- 239000010409 thin film Substances 0.000 title description 6
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000003381 stabilizer Substances 0.000 claims abstract description 32
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 30
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 25
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims abstract description 24
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 15
- 239000008367 deionised water Substances 0.000 claims abstract description 13
- 229910021641 deionized water Inorganic materials 0.000 claims abstract description 13
- 229910013703 M(OH)x Inorganic materials 0.000 claims abstract description 12
- 125000000217 alkyl group Chemical group 0.000 claims abstract description 12
- 229910052788 barium Inorganic materials 0.000 claims abstract description 12
- 229910052796 boron Inorganic materials 0.000 claims abstract description 12
- 229910052804 chromium Inorganic materials 0.000 claims abstract description 12
- 229910052742 iron Inorganic materials 0.000 claims abstract description 12
- -1 oxy-hydride inorganic acid Chemical class 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 229910052718 tin Inorganic materials 0.000 claims abstract description 12
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 12
- 229910001868 water Inorganic materials 0.000 claims abstract description 12
- 229910052725 zinc Inorganic materials 0.000 claims abstract description 12
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims abstract description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 18
- 229910000838 Al alloy Inorganic materials 0.000 claims description 17
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 14
- 239000010410 layer Substances 0.000 description 133
- 239000004020 conductor Substances 0.000 description 48
- 239000010408 film Substances 0.000 description 45
- 239000004065 semiconductor Substances 0.000 description 38
- 229910021417 amorphous silicon Inorganic materials 0.000 description 36
- 238000003860 storage Methods 0.000 description 31
- 239000003990 capacitor Substances 0.000 description 21
- 238000002161 passivation Methods 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 239000000758 substrate Substances 0.000 description 17
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 239000011701 zinc Substances 0.000 description 9
- 229910000583 Nd alloy Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910001080 W alloy Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/20—Acidic compositions for etching aluminium or alloys thereof
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/26—Acidic compositions for etching refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Definitions
- the present invention relates to an etchant for a signal wire and a manufacturing method of a thin film transistor array panel using an etchant.
- LCDs are one of the most widely used flat panel displays.
- An LCD includes two panels provided with field-generating electrodes and a liquid crystal (LC) layer interposed therebetween.
- the LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer, which determines orientations of LC molecules in the LC layer to adjust polarization of incident light.
- a kind of LCDs provides a plurality of pixel electrodes arranged in a matrix at one panel and a common electrode covering an entire surface of the other panel.
- the image display of the LCD is accomplished by applying individual voltages to the respective pixel electrodes.
- a plurality of three-terminal thin film transistors (TFTs) are connected to the respective pixel electrodes, and a plurality of gate lines transmitting signals for controlling the TFTs and a plurality of data lines transmitting voltages to be applied to the pixel electrodes are provided on the panel.
- the panel for an LCD has a layered structure including several conductive layers and several insulating layers.
- the gate lines, the data lines, and the pixel electrodes are made from different conductive layers (referred to as “gate conductor,” “data conductor,” and “pixel conductor” hereinafter) preferably deposited in sequence and separated by insulating layers.
- a TFT includes three electrodes: a gate electrode made from the gate conductor and source and drain electrodes made from the data conductor.
- the source electrode and the drain electrode are connected by a semiconductor usually located thereunder, and the drain electrode is connected to the pixel electrode through a hole in an insulating layer.
- the gate conductor and the data conductor are preferably made of Al containing metal such as Al and Al alloy having low resistivity for reducing the signal delay in the gate lines and the data lines.
- the data conductor also includes a refractory metal for good contact with the semiconductor.
- the pixel electrodes are usually made of transparent conductive material such as indium tin oxide (ITO) for both the field generation upon voltage application and the light transmission.
- the conductors are patterned by dry etching or wet etching with an etchant.
- An etchant for patterning dual layers of Al (or Al—Nd alloy) and Mo is disclosed in Korean Patent Application Publication No. 2001-75932, an etchant for patterning triple layers of Mo, Al (or Al—Nd alloy), and Mo is disclosed in Korean Patent Application Publication Serial No. 2001-91799, and an etchant for patterning a layer of ITO is disclosed in Korean Patent Application Publication Serial No. 2002-33025.
- a method of manufacturing a thin film transistor array panel includes: forming a gate conductor on an insulating substrate; forming a gate insulating layer; forming a semiconductor member; forming a data conductor; and forming a pixel electrode connected to the drain electrode, wherein the gate conductor, the data conductor, and the pixel electrode are formed using a single etchant.
- the etchant preferably contains about 50-60% H 3 PO 4 , about 6-10% HNO 3 , about 15-25% CH 3 COOH, about 2-5% stabilizer, and deionized water.
- the stabilizer may contain oxy-hydride inorganic acid represented by M(OH) x L y , where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H 2 O, NH 3 , CN and NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- the gate conductor preferably includes a lower film of Al or Al alloy, more preferably Al—Nd, and an upper film of Mo or Mo alloy, more preferably MoW.
- the data conductor preferably includes Mo or Mo alloy, and the pixel electrode preferably includes IZO.
- the lower layer of the gate conductor, the upper layer of the gate conductor, the data conductor, and the pixel electrode may have thickness of about 1,500-3,000 ⁇ , about 300-600 ⁇ , about 1,500-3,000 ⁇ , and about 800-1,000 ⁇ , respectively.
- the etchant preferably contains about 65-75% H 3 PO 4 , about 0.5-4% HNO 3 , about 9-13% CH 3 COOH, about 2-5% stabilizer, and deionized water.
- the stabilizer may contain oxy-hydride inorganic acid represented by M(OH) x L y , where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H 2 O, NH 3 , CN and NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- the gate conductor preferably includes a lower film of Al or Al alloy, more preferably Al—Nd, and an upper film of Mo.
- the data conductor preferably includes a bottom layer of Mo, an intermediate layer of Al or Al alloy, and a top layer of Mo, and the pixel electrode preferably includes IZO.
- a method of manufacturing a thin film transistor array panel includes: forming a gate conductor on an insulating substrate; forming a gate insulating layer; forming a semiconductor member; forming a data conductor; and forming a pixel electrode connected to the drain electrode, wherein at least one of the gate conductor, the data conductor, and the pixel electrode are formed by using an etchant including a phosphoric acid of about 50-60%, a nitric acid of about 6-10%, an acetic acid of about 15-25%, a stabilizer of about 2-5% stabilizer, and deionized water, or an etchant including a phosphoric acid of about 65-75%, a nitric acid of about 0.5-4%, an acetic acid of about 9-13%, a stabilizer of about 2-5% stabilizer, and deionized water, where the stabilizer includes oxy-hydride inorganic acid represented by M(OH) x L y , where M includes at least one of Zn, S
- At least two of the gate conductor, the data conductor, and the pixel electrode preferably include at least one of Mo, Mo alloy, Al, Al alloy, and IZO, and furthermore, each of the gate conductor, the data conductor, and the pixel electrode may include at least one of Mo, Mo alloy, Al, Al alloy, and IZO.
- An etchant for a signal wire includes: a phosphoric acid of about 50-60%; a nitric acid of about 6-10%; an acetic acid of about 15-25%; a stabilizer of about 2-5% stabilizer; and deionized water, wherein the stabilizer. includes oxy-hydride inorganic acid represented by M(OH) x L y , where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H 2 O, NH. 3 , CN and NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- An etchant for a signal wire includes: a phosphoric acid of about 65-75%; a nitric acid of about 0.5-4%; an acetic acid of about 9-13%; a stabilizer of about 2-5% stabilizer; and deionized water, wherein the stabilizer includes oxy-hydride inorganic acid represented by M(OH) x L y , where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H 2 O, NH 3 , CN and NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- M(OH) x L y where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H 2 O, NH 3 , CN and NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- the etchant may be used for patterning an Al or Al alloy layer, a Mo or Mo alloy layer, and multiple layers including an Al or Al alloy layer and a Mo or Mo alloy layer, and it may also be used for patterning an IZO layer.
- the etchant may be used for patterning multiple layers including a Mo layer, an Al or Al alloy layer, and a Mo layer deposited in sequence.
- FIGS. 1-3 are photographs of sections of signal wires etched by a single etchant according to an embodiment of the present invention
- FIG. 4 is a layout view of an exemplary TFT array panel for an LCD according to an embodiment of the present invention.
- FIG. 5 is a sectional view of the TFT array panel shown in FIG. 4 taken along the line V-V′;
- FIGS. 6A , 7 A, 8 A and 9 A are layout views of the TFT array panel shown in FIGS. 4 and 5 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention
- FIGS. 6B , 7 B, 8 B and 9 B are sectional views of the TFT array panel shown in FIGS. 6A , 7 A, 8 A and 9 A taken along the lines VIB-VIB′, VIIB-VIIB′, VIIIB-VIIIB′, and IXB-IXB′, respectively;
- FIG. 10 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention.
- FIGS. 11 and 12 are sectional views of the TFT array panel shown in FIG. 10 taken along the line XI-XI′ and the line XII-XII′, respectively;
- FIG. 13A is a layout view of a TFT array panel shown in FIGS. 10-12 in the first step of a manufacturing method thereof according to an embodiment of the present invention
- FIGS. 13B and 13C are sectional views of the TFT array panel shown in FIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively;
- FIGS. 14A and 14B are sectional views of the TFT array panel shown in FIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively, and illustrate the step following the step shown in FIGS. 13B and 13C ;
- FIG. 15A is a layout view of the TFT array panel in the step following the step shown in FIGS. 14A and 14B ;
- FIGS. 15B and 15C are sectional views of the TFT array panel shown in FIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively;
- FIGS. 16A , 17 A and 18 A and FIGS. 16B , 17 B and 18 B are respective sectional views of the TFT array panel shown in FIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively, and illustrate the steps following the step shown in FIGS. 15B and 15C ;
- FIG. 19A is a layout view of a TFT array panel in the step following the step shown in FIGS. 18A and 18B ;
- FIGS. 19B and 19C are sectional views of the TFT array panel shown in FIG. 19A taken along the lines XIXB-XIXB′ and XIXC-XIXC′, respectively;
- FIG. 20 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention.
- FIG. 21 is a sectional view of the TFT array panel shown in FIG. 20 taken along the line XXI-XXI′;
- FIGS. 22A , 23 A, 24 A and 25 A are layout views of the TFT array panel shown in FIGS. 20 and 21 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention.
- FIGS. 22B , 23 B, 24 B and 25 B are sectional views of the TFT array panel shown in FIGS. 22A , 23 A, 24 A and 25 A taken along the lines XXIIB-XXIIB′, XXIIIB-XXIIIB′, XXIVB-XXIVB′, and XXV-XXV′, respectively.
- FIGS. 1-3 are photographs of sections of signal wires etched by a single etchant according to an embodiment of the present invention.
- a conductive layer was deposited on a substrate and etched using an etchant contains about 55% phosphoric acid (H 3 PO 4 ), about 8% nitric acid (HNO 3 ), about 19% acetic acid (CH 3 COOH), about 3% stabilizer, and deionized water.
- the stabilizer includes oxy-hydride inorganic acid represented by M(OH) x L y , where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H 2 O, NH 3 , CN or NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- the conductive layer includes a lower Al—Nd alloy layer having a thickness of about 2,500 ⁇ and an upper MoW alloy layer of about 500 ⁇ and the substrate was dipped into the etchant for etching the conductive layer.
- the photograph shows that the etched lateral side of the conductive layer has an inclination angle (or taper angle) of 40-50 degrees with respect to the surface of the substrate.
- the conductive layer is made of MoW alloy and has a thickness of about 2,000 ⁇ and the etchant was sprayed over the substrate for etching the conductive layer.
- the photograph shows that the etched lateral side of the conductive layer has an inclination angle of 30-40 degrees with respect to the surface of the substrate.
- the conductive layer is made of IZO and has a thickness of about 900 ⁇ and the etchant was sprayed over the substrate for etching the conductive layer.
- the photograph shows that the etched lateral side of the conductive layer has an inclination angle of 25-30 degrees with respect to the surface of the substrate.
- the conductive layers made of Al—Nd alloy, MoW alloy, and IZO are etched by a single etchant such that the inclination angles of the later sides of the conductive layers ranges from about 25 degrees to about 50 degrees.
- a TFT array panel for an LCD will be described in detail with reference to FIGS. 4 and 5 .
- FIG. 4 is an exemplary layout view of TFTs, pixel electrodes, portions of signal lines located on the display area and expansions of the signal lines located on the peripheral area of the exemplary TFT array panel shown in FIG. 2 according to an embodiment of the present invention
- FIG. 5 is a sectional view of the TFT array panel shown in FIG. 4 taken along the line V-V′.
- a plurality of gate lines 121 for transmitting gate signals are formed on an insulating substrate 110 .
- Each gate line 121 extends substantially in a transverse direction and a plurality of portions of each gate line 121 form a plurality of gate electrodes 123 .
- Each gate line 121 includes a plurality of projections 127 protruding downward and an expansion 125 having wider width for contact with another layer or an external device.
- the gate lines 121 include two films having different physical characteristics, a lower film 121 p and an upper film 121 q .
- the lower film 121 p is preferably made of low resistivity metal including Al containing metal such as Al and Al alloy for reducing signal delay or voltage drop in the gate lines 121 .
- the upper film 121 q is preferably made of material such as Mo and Mo alloy, which has good physical, chemical, and electrical contact characteristics with other materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).
- ITO indium tin oxide
- IZO indium zinc oxide
- a good exemplary combination of the lower film material and the upper film material is Al—Nd alloy and Mo—W alloy.
- the lower and the upper films of the gate electrodes 123 are indicated by reference numerals 123 p and 123 q , respectively, the lower and the upper films of the projections 127 are indicated by reference numerals 127 p and 127 q , and the lower and the upper films of the expansions 125 are indicated by reference numerals 125 p and 125 q , respectively.
- the expansions 125 of the gate lines 121 include only a lower film.
- the lateral sides of the upper film 121 q and the lower film 121 p are tapered, and the inclination angle of the lateral sides with respect to a surface of the substrate 110 ranges about 20-80 degrees.
- a gate insulating layer 140 preferably made of silicon nitride (SiNx) is formed on the gate lines 121 .
- a plurality of semiconductor stripes 151 preferably made of hydrogenated amorphous silicon (abbreviated to “a-Si”) are formed on the gate insulating layer 140 .
- Each semiconductor stripe 151 extends substantially in the longitudinal direction and has a plurality of projections 154 branched out toward the gate electrodes 123 .
- the width of each semiconductor stripe 151 becomes large near the gate lines 121 such that the semiconductor stripe 151 covers large areas of the gate lines 121 .
- a plurality of ohmic contact stripes and islands 161 and 165 preferably made of silicide or n+ hydrogenated a-Si heavily doped with n type impurity are formed on the semiconductor stripes 151 .
- Each ohmic contact stripe 161 has a plurality of projections 163 , and the projections 163 and the ohmic contact islands 165 are located in pairs on the projections 154 of the semiconductor stripes 151 .
- the lateral sides of the semiconductor stripes 151 and the ohmic contacts 161 and 165 are tapered, and the inclination angles thereof are preferably in a range between about 30-80 degrees.
- a plurality of data lines 171 , a plurality of drain electrodes 175 , and a plurality of storage capacitor conductors 177 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140 .
- the data lines 171 for transmitting data voltages extend substantially in the longitudinal direction and intersect the gate lines 121 .
- Each data line 171 includes an expansion 179 having wider width for contact with another layer or an external device.
- a plurality of branches of each data line 171 which project toward the drain electrodes 175 , form a plurality of source electrodes 173 .
- Each pair of the source electrodes 173 and the drain electrodes 175 are separated from each other and opposite each other with respect to a gate electrode 123 .
- a gate electrode 123 , a source electrode 173 , and a drain electrode 175 along with a projection 154 of a semiconductor stripe 151 form a TFT having a channel formed in the projection 154 disposed between the source electrode 173 and the drain electrode 175 .
- the storage capacitor conductors 177 overlap the projections 127 of the gate lines 121 .
- the data lines 171 , the drain electrodes 175 , and the storage capacitor conductors 177 is preferably made of Mo or Mo alloy, and more preferably, it is made of Mo—W alloy. They may include an upper film (not shown) preferably made of Mo, Mo alloy and an underlying lower film (not shown) preferably made of Al containing metal. In addition, they may further include a Mo or Mo alloy film disposed under the Al containing metal film.
- the data lines 171 , the drain electrodes 175 , and the storage capacitor conductors 177 have tapered lateral sides, and the inclination angles thereof range about 30-80 degrees.
- the ohmic contacts 161 and 165 are interposed only between the underlying semiconductor stripes 151 and the overlying data lines 171 and the overlying drain electrodes 175 thereon and reduce the contact resistance therebetween.
- the semiconductor stripes 151 include a plurality of exposed portions, which are not covered with the data lines 171 and the drain electrodes 175 , such as portions located between the source electrodes 173 and the drain electrodes 175 . Although the semiconductor stripes 151 are narrower than the data lines 171 at most places, the width of the semiconductor stripes 151 becomes large near the gate lines 121 as described above, to smooth the profile of the surface, thereby preventing the disconnection of the data lines 171 .
- a passivation layer 180 is formed on the data lines 171 , the drain electrodes 175 , the storage conductors 177 , and the exposed portions of the semiconductor stripes 151 .
- the passivation layer 180 is preferably made of photosensitive organic material having a good flatness characteristic, low dielectric insulating material having dielectric constant lower than 4.0 such as a-Si:C:O and a-Si:O:F formed by plasma enhanced chemical vapor deposition (PECVD), or inorganic material such as silicon nitride.
- PECVD plasma enhanced chemical vapor deposition
- the passivation layer 180 may have a dual layered structure including an inorganic lower layer preferably made of silicon nitride and an organic upper layer such that the exposed portions of the semiconductor stripes 151 is in contact with the inorganic layer.
- the thick organic insulating layer is removed in a peripheral area provided with the expansions 125 and 179 of the gate lines 121 and the data lines 179 for smooth contact between the expansions 125 and 179 and external driving circuits and this configuration is particularly advantageous for a COG (chip on glass) type mounting.
- the passivation layer 180 has a plurality of contact holes 185 , 187 and 189 exposing the lower films 175 p of the drain electrodes 175 , the lower films 177 p of the storage conductors 177 , and the expansions 179 of the data lines 171 , respectively.
- the passivation layer 180 and the gate insulating layer 140 have a plurality of contact holes 182 exposing the expansions 125 of the gate lines 121 .
- FIGS. 4 and 5 shows that the contact holes 182 , 185 , 187 and 189 have inclined sidewalls.
- the pixel electrodes 190 are physically and electrically connected to the drain electrodes 175 through the contact holes 185 and to the storage capacitor conductors 177 through the contact holes 187 such that the pixel electrodes 190 receive the data voltages from the drain electrodes 175 and transmit the received data voltages to the storage capacitor conductors 177 .
- the pixel electrodes 190 supplied with the data voltages generate electric fields in cooperation with a common electrode (not shown) on another panel (not shown), which reorient liquid crystal molecules in a liquid crystal layer (not shown) disposed therebetween.
- a pixel electrode 190 and a common electrode form a liquid crystal capacitor, which stores applied voltages after turn-off of the TFT.
- An additional capacitor called a “storage capacitor,” which is connected in parallel to the liquid crystal capacitor, is provided for enhancing the voltage storing capacity.
- the storage capacitors are implemented by overlapping the pixel electrodes 190 with the gate lines 121 adjacent thereto (called “previous gate lines”).
- the capacitances of the storage capacitors, i.e., the storage capacitances are increased by providing the projections 127 at the gate lines 121 for increasing overlapping areas and by providing the storage capacitor conductors 177 , which are connected to the pixel electrodes 190 and overlap the projections 127 , under the pixel electrodes 190 for decreasing the distance between the terminals.
- the pixel electrodes 190 overlap the gate lines 121 and the data lines 171 to increase aperture ratio but it is optional.
- the contact assistants 92 and 97 are connected to the exposed expansions 125 of the gate lines 121 and the exposed expansions 179 of the data lines 171 through the contact holes 182 and 189 , respectively.
- the contact assistants 92 and 97 are not requisites but preferred to protect the exposed portions 125 and 179 and to complement the adhesiveness of the exposed portions 125 and 179 and external devices.
- a plurality of metal islands are formed near the expansions 125 and 129 of the gate lines 121 and the data lines 179 and they are connected to the contact assistants 92 and 97 through a plurality of contact holes (not shown) are formed in the passivation layer 180 and/or the gate insulating layer 140 .
- FIGS. 4 and 5 A method of manufacturing the TFT array panel shown in FIGS. 4 and 5 according to an embodiment of the present invention will be now described in detail with reference to FIGS. 6A to 9B as well as FIGS. 4 and 5 .
- FIGS. 6A , 7 A, 8 A and 9 A are layout views of the TFT array panel shown in FIGS. 4 and 5 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention
- FIGS. 6B , 7 B, 8 B and 9 B are sectional views of the TFT array panel shown in FIGS. 6A , 7 A, 8 A and 9 A taken along the lines VIB-VIB′, VIIB-VIIB′, VIIIB-VIIIB′, and IXB-IXB′, respectively.
- the lower conductive film has a thickness of about 1,500-3,000 ⁇ , preferably 2,500 ⁇ , and is made of Al—Nd alloy, while the upper conductive film has a thickness of about 300-600 ⁇ , preferably 500 ⁇ , and is made of Mo—W alloy.
- the upper conductive film and the lower conductive film are simultaneously patterned by photolithography and wet etch with an etchant to form a plurality of gate lines 121 including a plurality of gate electrodes 123 , a plurality of projections 127 , and a plurality of expansions 125 .
- the etchant contains about 50-60% phosphoric acid (H 3 PO 4 ), about 6-10% nitric acid (HNO 3 ), about 15-25% acetic acid (CH 3 COOH), about 2-5% stabilizer, and deionized water.
- the stabilizer includes oxy-hydride inorganic acid represented by M(OH) x L y , where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H 2 O, NH 3 , CN or NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality of extrinsic semiconductor stripes 164 and a plurality of intrinsic semiconductor stripes 151 including a plurality of projections 154 on the gate insulating layer 140 .
- portions of the extrinsic semiconductor stripes 164 which are not covered with the data lines 171 , the drain electrodes 175 , and the storage capacitor conductors 177 , are removed to complete a plurality of ohmic contact stripes 161 including a plurality of projections 163 and a plurality of ohmic contact islands 165 and to expose portions of the intrinsic semiconductor stripes 151 .
- Oxygen plasma treatment preferably follows thereafter in order to stabilize the exposed surfaces of the semiconductor stripes 151 .
- a passivation layer 180 is formed by depositing silicon nitride, by PECVD of low dielectric material such as a-Si:C:O or a-Si:O:F, or by coating a photosensitive organic insulating material having a good planarization characteristic.
- the passivation layer 180 as well as the gate insulating layer 140 is photo-etched to form a plurality of contact holes 182 , 185 , 187 and 189 exposing the expansions 125 of the gate lines 121 , the drain electrodes 175 , the storage capacitor conductors 177 , and the expansions 179 of the data lines 171 .
- a plurality of pixel electrodes 190 and a plurality of contact assistants 92 and 97 are formed on the passivation layer 180 by sputtering and photo-etching an IZO layer having a thickness of about 800-1,000 ⁇ , preferably about 900 ⁇ with the etchant used for etching the gate lines 121 and the data lines 175 .
- the gate lines 121 , the data lines 171 , and the pixel electrodes 190 are etched by using a single etchant. Accordingly, the manufacturing method and apparatus are simplified, thereby reducing the manufacturing cost.
- a TFT array panel for an LCD according to another embodiment of the present invention will be described in detail with reference to FIGS. 10-12 .
- FIG. 10 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention
- FIGS. 11 and 12 are sectional views of the TFT array panel shown in FIG. 10 taken along the line XI-XI′ and the line XII-XII′, respectively.
- a layered structure of a TFT array panel of an LCD according to this embodiment is almost the same as that shown in FIGS. 4 and 5 . That is, a plurality of gate lines 121 including a plurality of gate electrodes 123 are formed on a substrate 110 , and a gate insulating layer 140 , a plurality of semiconductor stripes 151 including a plurality of projections 154 , and a plurality of ohmic contact stripes 161 including a plurality of projections 163 and a plurality of ohmic contact islands 165 are sequentially formed thereon.
- a plurality of data lines 171 including a plurality of source electrodes 173 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 , and a passivation layer 180 is formed thereon.
- a plurality of contact holes 182 , 185 and 189 are provided at the passivation layer 180 and/or the gate insulating layer 140 , and a plurality of pixel electrodes 190 and a plurality of contact assistants 92 and 97 are formed on the passivation layer 180 .
- the TFT array panel provides a plurality of storage electrode lines 131 , which are separated from the gate lines 121 and have a plurality of expansions 133 , on the same layer as the gate lines 121 without projections.
- the storage electrode lines 131 are supplied with a predetermined voltage such as the common voltage.
- the drain electrodes 175 extend to overlap the storage electrode lines 131 to form storage capacitors.
- the storage electrode lines 131 may be omitted if the storage capacitance generated by the overlapping of the gate lines 121 and the pixel electrodes 190 is sufficient.
- the positions of the storage electrode lines 131 may be changed, and, for example, the storage electrode lines 131 are disposed near the edges of the pixel electrodes 190 in consideration of the aperture ratio.
- gate lines 125 and the storage electrode lines 131 have a single layered structure.
- the semiconductor stripes 151 have almost the same planar shapes as the data lines 171 and the drain electrodes 175 as well as the underlying ohmic contacts 161 and 165 , except for the projections 154 where TFTs are provided. That is, the semiconductor stripes 151 include some exposed portions, which are not covered with the data lines 171 and the drain electrodes 175 , such as portions located between the source electrodes 173 and the drain electrodes 175 .
- FIGS. 10-12 a method of manufacturing the TFT array panel shown in FIGS. 10-12 according to an embodiment of the present invention will be described in detail with reference to FIGS. 13A-19C as well as FIGS. 10-12 .
- FIG. 13A is a layout view of a TFT array panel shown in FIGS. 10-12 in the first step of a manufacturing method thereof according to an embodiment of the present invention
- FIGS. 13B and 13C are sectional views of the TFT array panel shown in FIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively
- FIGS. 14A and 14B are sectional views of the TFT array panel shown in FIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively, and illustrate the step following the step shown in FIGS. 13B and 13C
- FIG. 15A is a layout view of the TFT array panel in the step following the step shown in FIGS.
- FIGS. 15B and 15C are sectional views of the TFT array panel shown in FIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively;
- FIGS. 16A , 17 A and 18 A and FIGS. 16B , 17 B and 18 B are respective sectional views of the TFT array panel shown in FIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively, and illustrate the steps following the step shown in FIGS. 15B and 15C ;
- FIG. 19A is a layout view of a TFT array panel in the step following the step shown in FIGS. 18A and 18B ;
- FIGS. 19B and 19C are sectional views of the TFT array panel shown in FIG. 19A taken along the lines XIXB-XIXB′ and XIXC-XIXC′, respectively.
- a plurality of gate lines 121 including a plurality of gate electrodes 123 and a plurality of storage electrode lines 131 are formed on a substrate 110 by photo etching using an etchant.
- the etchant about 50-60% H 3 PO 4 , about 6-10% HNO 3 , about 15-25% CH 3 COOH, about 2-5% stabilizer, and deionized water.
- the stabilizer includes oxy-hydride inorganic acid represented by M(OH) x L y , where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H 2 O, NH 3 , CN or NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- a gate insulating layer 140 , an intrinsic a-Si layer 150 , and an extrinsic a-Si layer 160 are sequentially deposited by CVD such that the layers 140 , 150 and 160 have thickness of about 1,500-5,000 ⁇ , about 500-2,000 ⁇ and about 300-600 ⁇ , respectively.
- a conductive layer 170 having a thickness of about 1,500-3,000 ⁇ and made of Mo or Mo alloy such as MoW is deposited by sputtering, and a photoresist film 210 with the thickness of about 1-2 microns is coated on the conductive layer 170 .
- the photoresist film 210 is exposed to light through an exposure mask (not shown), and developed such that the developed photoresist has a position dependent thickness.
- the photoresist shown in FIGS. 15B and 15C includes a plurality of first to third portions with decreased thickness.
- the first portions located on wire areas A and the second portions located on channel areas C are indicated by reference numerals 212 and 214 , respectively, and no reference numeral is assigned to the third portions located on remaining areas B since they have substantially zero thickness to expose underlying portions of the conductive layer 170 .
- the thickness ratio of the second portions 214 to the first portions 212 is adjusted depending upon the process conditions in the subsequent process steps. It is preferable that the thickness of the second portions 214 is equal to or less than half of the thickness of the first portions 212 , and in particular, equal to or less than 4,000 ⁇
- the position-dependent thickness of the photoresist is obtained by several techniques, for example, by providing translucent areas on the exposure mask 300 as well as transparent areas and light blocking opaque areas.
- the translucent areas may have a slit pattern, a lattice pattern, a thin film(s) with intermediate transmittance or intermediate thickness.
- a slit pattern it is preferable that the width of the slits or the distance between the slits is smaller than the resolution of a light exposer used for the photolithography.
- Another example is to use reflowable photoresist.
- a photoresist pattern made of a reflowable material is formed by using a normal exposure mask only with transparent areas and opaque areas, it is subject to reflow process to flow onto areas without the photoresist, thereby forming thin portions.
- a plurality of data lines 171 including a plurality of source electrodes 173 and a plurality of drain electrodes 175 as well as a plurality of ohmic contact stripes 161 including a plurality of projections 163 , a plurality of ohmic contact islands 165 and a plurality of semiconductor stripes 151 including a plurality of projections 154 are obtained by a series of etching steps.
- portions of the conductive layer 170 , the extrinsic a-Si layer 160 , and the intrinsic a-Si layer 150 on the wire areas A are called first portions
- portions of the conductive layer 170 , the extrinsic a-Si layer 160 , and the intrinsic a-Si layer 150 on the channel areas C are called second portions
- portions of the conductive layer 170 , the extrinsic a-Si layer 160 , and the intrinsic a-Si layer 150 on the remaining areas B are called third portions.
- the first example is described in detail.
- the exposed third portions of the conductive layer 170 on the remaining areas B are removed by wet etching with the etchant used for the gate lines 121 and the storage electrode lines 131 to expose the underlying third portions of the extrinsic a-Si layer 160 .
- Reference numeral 174 indicates portions of the conductive layer 170 including the data lines 171 and the drain electrode 175 connected to each other.
- the dry etching may etch out the top portions of the photoresist 212 and 214 .
- the third portions of the extrinsic a-Si layer 160 on the areas B and of the intrinsic a-Si layer 150 are removed preferably by dry etching and the second portions 214 of the photoresist are removed to expose the second portions of the conductors 174 .
- the removal of the second portions 214 of the photoresist are performed either simultaneously with or independent from the removal of the third portions of the extrinsic a-Si layer 160 and of the intrinsic a-Si layer 150 . Residue of the second portions 214 of the photoresist remained on the channel areas C is removed by ashing.
- reference numeral 164 indicates portions of the extrinsic a-Si layer 160 including the ohmic contact stripes and islands 161 and 165 connected to each other, which are called “extrinsic semiconductor stripes.”
- the second portions of the conductors 174 and the extrinsic a-Si stripes 164 on the channel areas C as well as the first portion 212 of the photoresist are removed.
- top portions of the projections 154 of the intrinsic semiconductor stripes 151 on the channel areas C may be removed to cause thickness reduction, and the first portions 212 of the photoresist are etched to a predetermined thickness.
- each conductor 174 is divided into a data line 171 and a plurality of drain electrodes 175 to be completed, and each extrinsic semiconductor stripe 164 is divided into an ohmic contact stripe 161 and a plurality of ohmic contact islands 165 to be completed.
- a passivation layer 180 is deposited and patterned to form a plurality of contact holes 182 , 185 and 189 exposing expansions 125 of the gate lines 121 , the drain electrodes 175 , and expansions of the data lines 171 .
- an IZO layer with a thickness in a range between about 500 ⁇ and about 1,000 ⁇ is sputtered and photo-etched using the etchant used for the gate lines 121 and the data lines 171 to form a plurality of pixel electrodes 190 and a plurality of contact assistants 92 and 97 .
- This embodiment simplifies the manufacturing process by forming the data lines 171 and the drain electrodes 175 as well as the ohmic contacts 161 and 165 and the semiconductor stripes 151 and using a single photolithography step.
- a TFT array panel for an LCD according to another embodiment of the present invention will be described in detail with reference to FIGS. 20 and 21 .
- FIG. 20 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention
- FIG. 21 is a sectional view of the TFT array panel shown in FIG. 20 taken along the line XXVII-XXVII′.
- a layered structure of a TFT array panel of an LCD according to this embodiment is almost the same as that shown in FIGS. 4 and 5 . That is, a plurality of gate lines 121 including a plurality of gate electrodes 123 are formed on a substrate 110 , and a gate insulating layer 140 , a plurality of semiconductor stripes 151 including a plurality of projections 154 , and a plurality of ohmic contact stripes 161 including a plurality of projections 163 and a plurality of ohmic contact islands 165 are sequentially formed thereon.
- a plurality of data lines 171 including a plurality of source electrodes 173 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 , and a passivation layer 180 is formed thereon.
- a plurality of contact holes 182 and 189 exposing expansions 125 and 179 of the gate lines 121 and the data lines 171 are provided at the passivation layer 180 and/or the gate insulating layer 140 , and a plurality of pixel electrodes 190 and a plurality of contact assistants 92 and 97 are formed thereon.
- the data lines 171 and the drain electrodes 175 includes a bottom layer 171 p preferably made of Mo or Mo alloy, an intermediate layer 171 q preferably made of Al or Al alloy, and a top layer 171 r preferably made of Mo or Mo alloy.
- FIGS. 20 and 21 a method of manufacturing the TFT array panel shown in FIGS. 20 and 21 according to an embodiment of the present invention will be described in detail with reference to FIGS. 22A-32 as well as FIGS. 20 and 21 .
- FIGS. 22A , 23 A, 24 A and 25 A are layout views of the TFT array panel shown in FIGS. 20 and 21 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention
- FIGS. 22B , 23 B, 24 B and 25 B are sectional views of the TFT array panel shown in FIGS. 22A , 23 A. 24 A and 25 A taken along the lines VIB-VIB′, VIIB-VIIB′, VIIIB-VIIIB′, and IXB-IXB′, respectively.
- the lower conductive film has a thickness of about 1,500-3,000 ⁇ , preferably 2,500 ⁇ and is made of Al—Nd alloy, while the upper conductive film has a thickness of about 300-600 ⁇ , preferably 500 ⁇ and is made of Mo.
- the upper conductive film and the lower conductive film are simultaneously patterned by photolithography and wet etch with an etchant to form a plurality of gate lines 121 including a plurality of gate electrodes 123 , a plurality of projections 127 , and a plurality of expansions 125 .
- the etchant contains about 65-75% H 3 PO 4 , about 0.5-4% HNO 3 , about 9-13% CH 3 COOH, about 2-5% stabilizer, and deionized water.
- the stabilizer includes oxy-hydride inorganic acid represented by M(OH) x L y , where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H 2 O, NH 3 , CN or NH 2 R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- M Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B
- L is H 2 O, NH 3 , CN or NH 2 R (where R is alkyl group)
- X is 2 or 3
- Y is 0, 1, 2 or 3.
- the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality of extrinsic semiconductor stripes 164 and a plurality of intrinsic semiconductor stripes 151 including a plurality of projections 154 on the gate insulating layer 140 .
- a bottom film made of Mo, an intermediate film made of Al—Nd alloy, and a top film made of Mo are sequentially deposited and wet-etched with the etchant used for patterning the gate lines 121 to form a plurality of data lines 171 including a plurality of source electrodes 173 and a plurality of expansions 179 , a plurality of drain electrodes 175 , and a plurality of storage capacitor conductors 177 .
- portions of the extrinsic semiconductor stripes 164 which are not covered with the data lines 171 , the drain electrodes 175 , and the storage capacitor conductors 177 , are removed to complete a plurality of ohmic contact stripes 161 including a plurality of projections 163 and a plurality of ohmic contact islands 165 and to expose portions of the intrinsic semiconductor stripes 151 .
- Oxygen plasma treatment preferably follows thereafter in order to stabilize the exposed surfaces of the semiconductor stripes 151 .
- a passivation layer 180 is deposited and the passivation layer 180 and the gate insulating layer 140 are photo-etched to form a plurality of contact holes 182 , 185 , 187 and 189 exposing the expansions 125 of the gate lines 121 , the drain electrodes 175 , the storage capacitor conductors 177 , and the expansions 179 of the data lines 171 .
- a plurality of pixel electrodes 190 and a plurality of contact assistants 92 and 97 are formed on the passivation layer 180 by sputtering and photo-etching an IZO layer having a thickness of about 800-1,000 ⁇ , preferably 900 ⁇ with the etchant used for etching the gate lines 121 and the data lines 175 .
- a plurality of color filters are provided under the pixel electrodes.
- the gate lines 121 , the data lines 171 , and the pixel electrodes 190 are etched by using a single etchant with elements having percentages depending on materials to be etched. Accordingly, the manufacturing method and apparatus are simplified, thereby reducing the manufacturing cost.
Abstract
Gate lines including a lower Al—Nd layer and an upper MoW layer, data lines including a MoW layer, and pixel electrodes including an IZO layer are patterned using a single etchant. The etchant contains a phosphoric acid of about 50-60%, a nitric acid of about 6-10%, an acetic acid of about 15-25%, a stabilizer of about 2-5% stabilizer, and deionized water. The stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
Description
- This application is a divisional of U.S. patent application Ser. No. 10/772,293, filed on Feb. 6, 2004, which in turn claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2003-03400 filed on May 28, 2003, the disclosures of which are each all incorporated herein by reference in their entirety.
- 1. Field of the Invention
- The present invention relates to an etchant for a signal wire and a manufacturing method of a thin film transistor array panel using an etchant.
- 2. Description of the Related Art
- Liquid crystal displays (LCDs) are one of the most widely used flat panel displays. An LCD includes two panels provided with field-generating electrodes and a liquid crystal (LC) layer interposed therebetween. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the LC layer, which determines orientations of LC molecules in the LC layer to adjust polarization of incident light.
- Among LCDs including field-generating electrodes on respective panels, a kind of LCDs provides a plurality of pixel electrodes arranged in a matrix at one panel and a common electrode covering an entire surface of the other panel. The image display of the LCD is accomplished by applying individual voltages to the respective pixel electrodes. For the application of the individual voltages, a plurality of three-terminal thin film transistors (TFTs) are connected to the respective pixel electrodes, and a plurality of gate lines transmitting signals for controlling the TFTs and a plurality of data lines transmitting voltages to be applied to the pixel electrodes are provided on the panel.
- The panel for an LCD has a layered structure including several conductive layers and several insulating layers. The gate lines, the data lines, and the pixel electrodes are made from different conductive layers (referred to as “gate conductor,” “data conductor,” and “pixel conductor” hereinafter) preferably deposited in sequence and separated by insulating layers. A TFT includes three electrodes: a gate electrode made from the gate conductor and source and drain electrodes made from the data conductor. The source electrode and the drain electrode are connected by a semiconductor usually located thereunder, and the drain electrode is connected to the pixel electrode through a hole in an insulating layer.
- The gate conductor and the data conductor are preferably made of Al containing metal such as Al and Al alloy having low resistivity for reducing the signal delay in the gate lines and the data lines. The data conductor also includes a refractory metal for good contact with the semiconductor. The pixel electrodes are usually made of transparent conductive material such as indium tin oxide (ITO) for both the field generation upon voltage application and the light transmission.
- In the meantime, the conductors are patterned by dry etching or wet etching with an etchant. An etchant for patterning dual layers of Al (or Al—Nd alloy) and Mo is disclosed in Korean Patent Application Publication No. 2001-75932, an etchant for patterning triple layers of Mo, Al (or Al—Nd alloy), and Mo is disclosed in Korean Patent Application Publication Serial No. 2001-91799, and an etchant for patterning a layer of ITO is disclosed in Korean Patent Application Publication Serial No. 2002-33025.
- Since different layers are etched using different etching conditions, the manufacturing process is complicated and the manufacturing cost is expensive.
- A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate conductor on an insulating substrate; forming a gate insulating layer; forming a semiconductor member; forming a data conductor; and forming a pixel electrode connected to the drain electrode, wherein the gate conductor, the data conductor, and the pixel electrode are formed using a single etchant.
- The etchant preferably contains about 50-60% H3PO4, about 6-10% HNO3, about 15-25% CH3COOH, about 2-5% stabilizer, and deionized water. The stabilizer may contain oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- The gate conductor preferably includes a lower film of Al or Al alloy, more preferably Al—Nd, and an upper film of Mo or Mo alloy, more preferably MoW.
- The data conductor preferably includes Mo or Mo alloy, and the pixel electrode preferably includes IZO.
- The lower layer of the gate conductor, the upper layer of the gate conductor, the data conductor, and the pixel electrode may have thickness of about 1,500-3,000 Å, about 300-600 Å, about 1,500-3,000 Å, and about 800-1,000 Å, respectively.
- The etchant preferably contains about 65-75% H3PO4, about 0.5-4% HNO3, about 9-13% CH3COOH, about 2-5% stabilizer, and deionized water. The stabilizer may contain oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- The gate conductor preferably includes a lower film of Al or Al alloy, more preferably Al—Nd, and an upper film of Mo.
- The data conductor preferably includes a bottom layer of Mo, an intermediate layer of Al or Al alloy, and a top layer of Mo, and the pixel electrode preferably includes IZO.
- A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate conductor on an insulating substrate; forming a gate insulating layer; forming a semiconductor member; forming a data conductor; and forming a pixel electrode connected to the drain electrode, wherein at least one of the gate conductor, the data conductor, and the pixel electrode are formed by using an etchant including a phosphoric acid of about 50-60%, a nitric acid of about 6-10%, an acetic acid of about 15-25%, a stabilizer of about 2-5% stabilizer, and deionized water, or an etchant including a phosphoric acid of about 65-75%, a nitric acid of about 0.5-4%, an acetic acid of about 9-13%, a stabilizer of about 2-5% stabilizer, and deionized water, where the stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH.3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- At least two of the gate conductor, the data conductor, and the pixel electrode preferably include at least one of Mo, Mo alloy, Al, Al alloy, and IZO, and furthermore, each of the gate conductor, the data conductor, and the pixel electrode may include at least one of Mo, Mo alloy, Al, Al alloy, and IZO.
- An etchant for a signal wire according to an embodiment of the present invention includes: a phosphoric acid of about 50-60%; a nitric acid of about 6-10%; an acetic acid of about 15-25%; a stabilizer of about 2-5% stabilizer; and deionized water, wherein the stabilizer. includes oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH.3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- An etchant for a signal wire according to another embodiment of the present invention includes: a phosphoric acid of about 65-75%; a nitric acid of about 0.5-4%; an acetic acid of about 9-13%; a stabilizer of about 2-5% stabilizer; and deionized water, wherein the stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- The etchant may be used for patterning an Al or Al alloy layer, a Mo or Mo alloy layer, and multiple layers including an Al or Al alloy layer and a Mo or Mo alloy layer, and it may also be used for patterning an IZO layer.
- The etchant may be used for patterning multiple layers including a Mo layer, an Al or Al alloy layer, and a Mo layer deposited in sequence.
- The present invention will become more apparent by describing embodiments thereof in detail with reference to the accompanying drawings in which:
-
FIGS. 1-3 are photographs of sections of signal wires etched by a single etchant according to an embodiment of the present invention; -
FIG. 4 is a layout view of an exemplary TFT array panel for an LCD according to an embodiment of the present invention; -
FIG. 5 is a sectional view of the TFT array panel shown inFIG. 4 taken along the line V-V′; -
FIGS. 6A , 7A, 8A and 9A are layout views of the TFT array panel shown inFIGS. 4 and 5 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention; -
FIGS. 6B , 7B, 8B and 9B are sectional views of the TFT array panel shown inFIGS. 6A , 7A, 8A and 9A taken along the lines VIB-VIB′, VIIB-VIIB′, VIIIB-VIIIB′, and IXB-IXB′, respectively; -
FIG. 10 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention; -
FIGS. 11 and 12 are sectional views of the TFT array panel shown inFIG. 10 taken along the line XI-XI′ and the line XII-XII′, respectively; -
FIG. 13A is a layout view of a TFT array panel shown inFIGS. 10-12 in the first step of a manufacturing method thereof according to an embodiment of the present invention; -
FIGS. 13B and 13C are sectional views of the TFT array panel shown inFIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively; -
FIGS. 14A and 14B are sectional views of the TFT array panel shown inFIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively, and illustrate the step following the step shown inFIGS. 13B and 13C ; -
FIG. 15A is a layout view of the TFT array panel in the step following the step shown inFIGS. 14A and 14B ; -
FIGS. 15B and 15C are sectional views of the TFT array panel shown inFIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively; -
FIGS. 16A , 17A and 18A andFIGS. 16B , 17B and 18B are respective sectional views of the TFT array panel shown inFIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively, and illustrate the steps following the step shown inFIGS. 15B and 15C ; -
FIG. 19A is a layout view of a TFT array panel in the step following the step shown inFIGS. 18A and 18B ; -
FIGS. 19B and 19C are sectional views of the TFT array panel shown inFIG. 19A taken along the lines XIXB-XIXB′ and XIXC-XIXC′, respectively; -
FIG. 20 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention; -
FIG. 21 is a sectional view of the TFT array panel shown inFIG. 20 taken along the line XXI-XXI′; -
FIGS. 22A , 23A, 24A and 25A are layout views of the TFT array panel shown inFIGS. 20 and 21 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention; and -
FIGS. 22B , 23B, 24B and 25B are sectional views of the TFT array panel shown inFIGS. 22A , 23A, 24A and 25A taken along the lines XXIIB-XXIIB′, XXIIIB-XXIIIB′, XXIVB-XXIVB′, and XXV-XXV′, respectively. - The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
- In the drawings, the thickness of layers, films and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
- Now, etchants for a wire, TFT array panels and manufacturing methods thereof according to embodiments of the present invention will be described with reference to the accompanying drawings.
-
FIGS. 1-3 are photographs of sections of signal wires etched by a single etchant according to an embodiment of the present invention. - A conductive layer was deposited on a substrate and etched using an etchant contains about 55% phosphoric acid (H3PO4), about 8% nitric acid (HNO3), about 19% acetic acid (CH3COOH), about 3% stabilizer, and deionized water. The stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H2O, NH3, CN or NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
- Referring to
FIG. 1 , the conductive layer includes a lower Al—Nd alloy layer having a thickness of about 2,500 Å and an upper MoW alloy layer of about 500 Å and the substrate was dipped into the etchant for etching the conductive layer. The photograph shows that the etched lateral side of the conductive layer has an inclination angle (or taper angle) of 40-50 degrees with respect to the surface of the substrate. - Referring to
FIG. 2 , the conductive layer is made of MoW alloy and has a thickness of about 2,000 Å and the etchant was sprayed over the substrate for etching the conductive layer. The photograph shows that the etched lateral side of the conductive layer has an inclination angle of 30-40 degrees with respect to the surface of the substrate. - Referring to
FIG. 3 , the conductive layer is made of IZO and has a thickness of about 900 Å and the etchant was sprayed over the substrate for etching the conductive layer. The photograph shows that the etched lateral side of the conductive layer has an inclination angle of 25-30 degrees with respect to the surface of the substrate. - Consequently, the conductive layers made of Al—Nd alloy, MoW alloy, and IZO are etched by a single etchant such that the inclination angles of the later sides of the conductive layers ranges from about 25 degrees to about 50 degrees.
- A TFT array panel for an LCD will be described in detail with reference to
FIGS. 4 and 5 . -
FIG. 4 is an exemplary layout view of TFTs, pixel electrodes, portions of signal lines located on the display area and expansions of the signal lines located on the peripheral area of the exemplary TFT array panel shown inFIG. 2 according to an embodiment of the present invention, andFIG. 5 is a sectional view of the TFT array panel shown inFIG. 4 taken along the line V-V′. - A plurality of
gate lines 121 for transmitting gate signals are formed on an insulatingsubstrate 110. Eachgate line 121 extends substantially in a transverse direction and a plurality of portions of eachgate line 121 form a plurality ofgate electrodes 123. Eachgate line 121 includes a plurality ofprojections 127 protruding downward and anexpansion 125 having wider width for contact with another layer or an external device. - The gate lines 121 include two films having different physical characteristics, a lower film 121 p and an upper film 121 q. The lower film 121 p is preferably made of low resistivity metal including Al containing metal such as Al and Al alloy for reducing signal delay or voltage drop in the gate lines 121. On the other hand, the upper film 121 q is preferably made of material such as Mo and Mo alloy, which has good physical, chemical, and electrical contact characteristics with other materials such as indium tin oxide (ITO) and indium zinc oxide (IZO). A good exemplary combination of the lower film material and the upper film material is Al—Nd alloy and Mo—W alloy. In
FIG. 5 , the lower and the upper films of thegate electrodes 123 are indicated byreference numerals projections 127 are indicated byreference numerals expansions 125 are indicated byreference numerals expansions 125 of thegate lines 121 include only a lower film. - In addition, the lateral sides of the upper film 121 q and the lower film 121 p are tapered, and the inclination angle of the lateral sides with respect to a surface of the
substrate 110 ranges about 20-80 degrees. - A
gate insulating layer 140 preferably made of silicon nitride (SiNx) is formed on the gate lines 121. - A plurality of
semiconductor stripes 151 preferably made of hydrogenated amorphous silicon (abbreviated to “a-Si”) are formed on thegate insulating layer 140. Eachsemiconductor stripe 151 extends substantially in the longitudinal direction and has a plurality ofprojections 154 branched out toward thegate electrodes 123. The width of eachsemiconductor stripe 151 becomes large near thegate lines 121 such that thesemiconductor stripe 151 covers large areas of the gate lines 121. - A plurality of ohmic contact stripes and
islands semiconductor stripes 151. Eachohmic contact stripe 161 has a plurality ofprojections 163, and theprojections 163 and theohmic contact islands 165 are located in pairs on theprojections 154 of thesemiconductor stripes 151. - The lateral sides of the
semiconductor stripes 151 and theohmic contacts - A plurality of
data lines 171, a plurality ofdrain electrodes 175, and a plurality ofstorage capacitor conductors 177 are formed on theohmic contacts gate insulating layer 140. - The data lines 171 for transmitting data voltages extend substantially in the longitudinal direction and intersect the gate lines 121. Each
data line 171 includes anexpansion 179 having wider width for contact with another layer or an external device. - A plurality of branches of each
data line 171, which project toward thedrain electrodes 175, form a plurality ofsource electrodes 173. Each pair of thesource electrodes 173 and thedrain electrodes 175 are separated from each other and opposite each other with respect to agate electrode 123. Agate electrode 123, asource electrode 173, and adrain electrode 175 along with aprojection 154 of asemiconductor stripe 151 form a TFT having a channel formed in theprojection 154 disposed between thesource electrode 173 and thedrain electrode 175. - The
storage capacitor conductors 177 overlap theprojections 127 of the gate lines 121. - The data lines 171, the
drain electrodes 175, and thestorage capacitor conductors 177 is preferably made of Mo or Mo alloy, and more preferably, it is made of Mo—W alloy. They may include an upper film (not shown) preferably made of Mo, Mo alloy and an underlying lower film (not shown) preferably made of Al containing metal. In addition, they may further include a Mo or Mo alloy film disposed under the Al containing metal film. - Like the
gate lines 121, thedata lines 171, thedrain electrodes 175, and thestorage capacitor conductors 177 have tapered lateral sides, and the inclination angles thereof range about 30-80 degrees. - The
ohmic contacts underlying semiconductor stripes 151 and theoverlying data lines 171 and theoverlying drain electrodes 175 thereon and reduce the contact resistance therebetween. Thesemiconductor stripes 151 include a plurality of exposed portions, which are not covered with thedata lines 171 and thedrain electrodes 175, such as portions located between thesource electrodes 173 and thedrain electrodes 175. Although thesemiconductor stripes 151 are narrower than thedata lines 171 at most places, the width of thesemiconductor stripes 151 becomes large near thegate lines 121 as described above, to smooth the profile of the surface, thereby preventing the disconnection of the data lines 171. - A
passivation layer 180 is formed on thedata lines 171, thedrain electrodes 175, thestorage conductors 177, and the exposed portions of thesemiconductor stripes 151. Thepassivation layer 180 is preferably made of photosensitive organic material having a good flatness characteristic, low dielectric insulating material having dielectric constant lower than 4.0 such as a-Si:C:O and a-Si:O:F formed by plasma enhanced chemical vapor deposition (PECVD), or inorganic material such as silicon nitride. Thepassivation layer 180 may have a dual layered structure including an inorganic lower layer preferably made of silicon nitride and an organic upper layer such that the exposed portions of thesemiconductor stripes 151 is in contact with the inorganic layer. Furthermore, the thick organic insulating layer is removed in a peripheral area provided with theexpansions gate lines 121 and thedata lines 179 for smooth contact between theexpansions - The
passivation layer 180 has a plurality of contact holes 185, 187 and 189 exposing thelower films 175 p of thedrain electrodes 175, thelower films 177 p of thestorage conductors 177, and theexpansions 179 of thedata lines 171, respectively. Thepassivation layer 180 and thegate insulating layer 140 have a plurality ofcontact holes 182 exposing theexpansions 125 of the gate lines 121.FIGS. 4 and 5 shows that the contact holes 182, 185, 187 and 189 have inclined sidewalls. - A plurality of
pixel electrodes 190 and a plurality ofcontact assistants passivation layer 180. - The
pixel electrodes 190 are physically and electrically connected to thedrain electrodes 175 through the contact holes 185 and to thestorage capacitor conductors 177 through the contact holes 187 such that thepixel electrodes 190 receive the data voltages from thedrain electrodes 175 and transmit the received data voltages to thestorage capacitor conductors 177. - The
pixel electrodes 190 supplied with the data voltages generate electric fields in cooperation with a common electrode (not shown) on another panel (not shown), which reorient liquid crystal molecules in a liquid crystal layer (not shown) disposed therebetween. - A
pixel electrode 190 and a common electrode form a liquid crystal capacitor, which stores applied voltages after turn-off of the TFT. An additional capacitor called a “storage capacitor,” which is connected in parallel to the liquid crystal capacitor, is provided for enhancing the voltage storing capacity. The storage capacitors are implemented by overlapping thepixel electrodes 190 with thegate lines 121 adjacent thereto (called “previous gate lines”). The capacitances of the storage capacitors, i.e., the storage capacitances are increased by providing theprojections 127 at thegate lines 121 for increasing overlapping areas and by providing thestorage capacitor conductors 177, which are connected to thepixel electrodes 190 and overlap theprojections 127, under thepixel electrodes 190 for decreasing the distance between the terminals. - The
pixel electrodes 190 overlap thegate lines 121 and thedata lines 171 to increase aperture ratio but it is optional. - The
contact assistants expansions 125 of thegate lines 121 and the exposedexpansions 179 of thedata lines 171 through the contact holes 182 and 189, respectively. Thecontact assistants portions portions - According to another embodiment of the present invention, a plurality of metal islands (not shown) are formed near the
expansions 125 and 129 of thegate lines 121 and thedata lines 179 and they are connected to thecontact assistants passivation layer 180 and/or thegate insulating layer 140. - A method of manufacturing the TFT array panel shown in
FIGS. 4 and 5 according to an embodiment of the present invention will be now described in detail with reference toFIGS. 6A to 9B as well asFIGS. 4 and 5 . -
FIGS. 6A , 7A, 8A and 9A are layout views of the TFT array panel shown inFIGS. 4 and 5 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention, andFIGS. 6B , 7B, 8B and 9B are sectional views of the TFT array panel shown inFIGS. 6A , 7A, 8A and 9A taken along the lines VIB-VIB′, VIIB-VIIB′, VIIIB-VIIIB′, and IXB-IXB′, respectively. - Two conductive films, a lower conductive film and an upper conductive film are sputtered in sequence on an insulating
substrate 110 such as transparent glass. The lower conductive film has a thickness of about 1,500-3,000 Å, preferably 2,500 Å, and is made of Al—Nd alloy, while the upper conductive film has a thickness of about 300-600 Å, preferably 500 Å, and is made of Mo—W alloy. - Referring to
FIGS. 6A and 6B , the upper conductive film and the lower conductive film are simultaneously patterned by photolithography and wet etch with an etchant to form a plurality ofgate lines 121 including a plurality ofgate electrodes 123, a plurality ofprojections 127, and a plurality ofexpansions 125. The etchant contains about 50-60% phosphoric acid (H3PO4), about 6-10% nitric acid (HNO3), about 15-25% acetic acid (CH3COOH), about 2-5% stabilizer, and deionized water. The stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H2O, NH3, CN or NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3. - Referring to
FIGS. 7A and 7B , after sequential deposition of agate insulating layer 140, an intrinsic a-Si layer, and an extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality ofextrinsic semiconductor stripes 164 and a plurality ofintrinsic semiconductor stripes 151 including a plurality ofprojections 154 on thegate insulating layer 140. - Referring to
FIGS. 8A and 8B , a conductive film made of Mo—W alloy and having a thickness of about 1,500-3,000 Å, preferably 2,000 Å, is deposited and wet-etched with the etchant used for patterning thegate lines 121 to form a plurality ofdata lines 171 including a plurality ofsource electrodes 173 and a plurality ofexpansions 179, a plurality ofdrain electrodes 175, and a plurality ofstorage capacitor conductors 177. - Thereafter, portions of the
extrinsic semiconductor stripes 164, which are not covered with thedata lines 171, thedrain electrodes 175, and thestorage capacitor conductors 177, are removed to complete a plurality ofohmic contact stripes 161 including a plurality ofprojections 163 and a plurality ofohmic contact islands 165 and to expose portions of theintrinsic semiconductor stripes 151. Oxygen plasma treatment preferably follows thereafter in order to stabilize the exposed surfaces of thesemiconductor stripes 151. - Next, a
passivation layer 180 is formed by depositing silicon nitride, by PECVD of low dielectric material such as a-Si:C:O or a-Si:O:F, or by coating a photosensitive organic insulating material having a good planarization characteristic. Referring to FIGS. 9A and 9B, thepassivation layer 180 as well as thegate insulating layer 140 is photo-etched to form a plurality of contact holes 182, 185, 187 and 189 exposing theexpansions 125 of thegate lines 121, thedrain electrodes 175, thestorage capacitor conductors 177, and theexpansions 179 of the data lines 171. - Finally, as shown in
FIGS. 4 and 5 , a plurality ofpixel electrodes 190 and a plurality ofcontact assistants passivation layer 180 by sputtering and photo-etching an IZO layer having a thickness of about 800-1,000 Å, preferably about 900 Å with the etchant used for etching thegate lines 121 and the data lines 175. - In the manufacturing method of the TFT array panel according to this embodiment, the
gate lines 121, thedata lines 171, and thepixel electrodes 190 are etched by using a single etchant. Accordingly, the manufacturing method and apparatus are simplified, thereby reducing the manufacturing cost. - A TFT array panel for an LCD according to another embodiment of the present invention will be described in detail with reference to
FIGS. 10-12 . -
FIG. 10 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention, andFIGS. 11 and 12 are sectional views of the TFT array panel shown inFIG. 10 taken along the line XI-XI′ and the line XII-XII′, respectively. - As shown in
FIGS. 10-12 , a layered structure of a TFT array panel of an LCD according to this embodiment is almost the same as that shown inFIGS. 4 and 5 . That is, a plurality ofgate lines 121 including a plurality ofgate electrodes 123 are formed on asubstrate 110, and agate insulating layer 140, a plurality ofsemiconductor stripes 151 including a plurality ofprojections 154, and a plurality ofohmic contact stripes 161 including a plurality ofprojections 163 and a plurality ofohmic contact islands 165 are sequentially formed thereon. A plurality ofdata lines 171 including a plurality ofsource electrodes 173 and a plurality ofdrain electrodes 175 are formed on theohmic contacts passivation layer 180 is formed thereon. A plurality of contact holes 182, 185 and 189 are provided at thepassivation layer 180 and/or thegate insulating layer 140, and a plurality ofpixel electrodes 190 and a plurality ofcontact assistants passivation layer 180. - Different from the TFT array panel shown in
FIGS. 4 and 5 , the TFT array panel according to this embodiment provides a plurality ofstorage electrode lines 131, which are separated from thegate lines 121 and have a plurality ofexpansions 133, on the same layer as thegate lines 121 without projections. Thestorage electrode lines 131 are supplied with a predetermined voltage such as the common voltage. Without providing thestorage capacitor conductors 177 shown inFIGS. 4 and 5 , thedrain electrodes 175 extend to overlap thestorage electrode lines 131 to form storage capacitors. Thestorage electrode lines 131 may be omitted if the storage capacitance generated by the overlapping of thegate lines 121 and thepixel electrodes 190 is sufficient. The positions of thestorage electrode lines 131 may be changed, and, for example, thestorage electrode lines 131 are disposed near the edges of thepixel electrodes 190 in consideration of the aperture ratio. - Furthermore, the
gate lines 125 and thestorage electrode lines 131 have a single layered structure. - The
semiconductor stripes 151 have almost the same planar shapes as thedata lines 171 and thedrain electrodes 175 as well as the underlyingohmic contacts projections 154 where TFTs are provided. That is, thesemiconductor stripes 151 include some exposed portions, which are not covered with thedata lines 171 and thedrain electrodes 175, such as portions located between thesource electrodes 173 and thedrain electrodes 175. - Now, a method of manufacturing the TFT array panel shown in
FIGS. 10-12 according to an embodiment of the present invention will be described in detail with reference toFIGS. 13A-19C as well asFIGS. 10-12 . -
FIG. 13A is a layout view of a TFT array panel shown inFIGS. 10-12 in the first step of a manufacturing method thereof according to an embodiment of the present invention;FIGS. 13B and 13C are sectional views of the TFT array panel shown inFIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively;FIGS. 14A and 14B are sectional views of the TFT array panel shown inFIG. 13A taken along the lines XIIIB-XIIIB′ and XIIIC-XIIIC′, respectively, and illustrate the step following the step shown inFIGS. 13B and 13C ;FIG. 15A is a layout view of the TFT array panel in the step following the step shown inFIGS. 14A and 14B ;FIGS. 15B and 15C are sectional views of the TFT array panel shown inFIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively;FIGS. 16A , 17A and 18A andFIGS. 16B , 17B and 18B are respective sectional views of the TFT array panel shown inFIG. 15A taken along the lines XVB-XVB′ and XVC-XVC′, respectively, and illustrate the steps following the step shown inFIGS. 15B and 15C ;FIG. 19A is a layout view of a TFT array panel in the step following the step shown inFIGS. 18A and 18B ; andFIGS. 19B and 19C are sectional views of the TFT array panel shown inFIG. 19A taken along the lines XIXB-XIXB′ and XIXC-XIXC′, respectively. - Referring to
FIGS. 13A-13C , a plurality ofgate lines 121 including a plurality ofgate electrodes 123 and a plurality ofstorage electrode lines 131 are formed on asubstrate 110 by photo etching using an etchant. The etchant about 50-60% H3PO4, about 6-10% HNO3, about 15-25% CH3COOH, about 2-5% stabilizer, and deionized water. The stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H2O, NH3, CN or NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3. - As shown in
FIGS. 14A and 14B , agate insulating layer 140, an intrinsica-Si layer 150, and an extrinsica-Si layer 160 are sequentially deposited by CVD such that thelayers conductive layer 170 having a thickness of about 1,500-3,000 Å and made of Mo or Mo alloy such as MoW is deposited by sputtering, and aphotoresist film 210 with the thickness of about 1-2 microns is coated on theconductive layer 170. - The
photoresist film 210 is exposed to light through an exposure mask (not shown), and developed such that the developed photoresist has a position dependent thickness. The photoresist shown inFIGS. 15B and 15C includes a plurality of first to third portions with decreased thickness. The first portions located on wire areas A and the second portions located on channel areas C are indicated byreference numerals conductive layer 170. The thickness ratio of thesecond portions 214 to thefirst portions 212 is adjusted depending upon the process conditions in the subsequent process steps. It is preferable that the thickness of thesecond portions 214 is equal to or less than half of the thickness of thefirst portions 212, and in particular, equal to or less than 4,000 Å - The position-dependent thickness of the photoresist is obtained by several techniques, for example, by providing translucent areas on the exposure mask 300 as well as transparent areas and light blocking opaque areas. The translucent areas may have a slit pattern, a lattice pattern, a thin film(s) with intermediate transmittance or intermediate thickness. When using a slit pattern, it is preferable that the width of the slits or the distance between the slits is smaller than the resolution of a light exposer used for the photolithography. Another example is to use reflowable photoresist. In detail, once a photoresist pattern made of a reflowable material is formed by using a normal exposure mask only with transparent areas and opaque areas, it is subject to reflow process to flow onto areas without the photoresist, thereby forming thin portions.
- The different thickness of the
photoresist data lines 171 including a plurality ofsource electrodes 173 and a plurality ofdrain electrodes 175 as well as a plurality ofohmic contact stripes 161 including a plurality ofprojections 163, a plurality ofohmic contact islands 165 and a plurality ofsemiconductor stripes 151 including a plurality ofprojections 154 are obtained by a series of etching steps. - For descriptive purpose, portions of the
conductive layer 170, theextrinsic a-Si layer 160, and theintrinsic a-Si layer 150 on the wire areas A are called first portions, portions of theconductive layer 170, theextrinsic a-Si layer 160, and theintrinsic a-Si layer 150 on the channel areas C are called second portions, and portions of theconductive layer 170, theextrinsic a-Si layer 160, and theintrinsic a-Si layer 150 on the remaining areas B are called third portions. - An exemplary sequence of forming such a structure is as follows:
- (1) Removal of third portions of the
conductive layer 170, theextrinsic a-Si layer 160 and theintrinsic a-Si layer 150 on the wire areas A; - (2) Removal of the
second portions 214 of the photoresist; - (3) Removal of the second portions of the
conductive layer 170 and theextrinsic a-Si layer 160 on the channel areas C; and - (4) Removal of the
first portions 212 of the photoresist. - Another exemplary sequence is as follows:
- (1) Removal of the third portions of the
conductive layer 170; - (2) Removal of the
second portions 214 of the photoresist; - (3) Removal of the third portions of the
extrinsic a-Si layer 160 and theintrinsic a-Si layer 150; - (4) Removal of the second portions of the
conductive layer 170; - (5) Removal of the
first portions 212 of the photoresist; and - (6) Removal of the second portions of the
extrinsic a-Si layer 160. - The first example is described in detail.
- As shown in
FIGS. 16A and 16B , the exposed third portions of theconductive layer 170 on the remaining areas B are removed by wet etching with the etchant used for thegate lines 121 and thestorage electrode lines 131 to expose the underlying third portions of theextrinsic a-Si layer 160. -
Reference numeral 174 indicates portions of theconductive layer 170 including thedata lines 171 and thedrain electrode 175 connected to each other. The dry etching may etch out the top portions of thephotoresist - Referring to
FIGS. 17A and 17B , the third portions of theextrinsic a-Si layer 160 on the areas B and of theintrinsic a-Si layer 150 are removed preferably by dry etching and thesecond portions 214 of the photoresist are removed to expose the second portions of theconductors 174. The removal of thesecond portions 214 of the photoresist are performed either simultaneously with or independent from the removal of the third portions of theextrinsic a-Si layer 160 and of theintrinsic a-Si layer 150. Residue of thesecond portions 214 of the photoresist remained on the channel areas C is removed by ashing. - The
semiconductor stripes 151 are completed in this step, andreference numeral 164 indicates portions of theextrinsic a-Si layer 160 including the ohmic contact stripes andislands - As shown in
FIGS. 18A and 18B , the second portions of theconductors 174 and theextrinsic a-Si stripes 164 on the channel areas C as well as thefirst portion 212 of the photoresist are removed. - As shown in
FIG. 18B , top portions of theprojections 154 of theintrinsic semiconductor stripes 151 on the channel areas C may be removed to cause thickness reduction, and thefirst portions 212 of the photoresist are etched to a predetermined thickness. - In this way, each
conductor 174 is divided into adata line 171 and a plurality ofdrain electrodes 175 to be completed, and eachextrinsic semiconductor stripe 164 is divided into anohmic contact stripe 161 and a plurality ofohmic contact islands 165 to be completed. - As shown in
FIGS. 19A-19C , apassivation layer 180 is deposited and patterned to form a plurality of contact holes 182, 185 and 189 exposingexpansions 125 of thegate lines 121, thedrain electrodes 175, and expansions of the data lines 171. - Finally, as shown in
FIGS. 10-12 , an IZO layer with a thickness in a range between about 500 Å and about 1,000 Å is sputtered and photo-etched using the etchant used for thegate lines 121 and thedata lines 171 to form a plurality ofpixel electrodes 190 and a plurality ofcontact assistants - This embodiment simplifies the manufacturing process by forming the
data lines 171 and thedrain electrodes 175 as well as theohmic contacts semiconductor stripes 151 and using a single photolithography step. - A TFT array panel for an LCD according to another embodiment of the present invention will be described in detail with reference to
FIGS. 20 and 21 . -
FIG. 20 is a layout view of an exemplary TFT array panel for an LCD according to another embodiment of the present invention, andFIG. 21 is a sectional view of the TFT array panel shown inFIG. 20 taken along the line XXVII-XXVII′. - As shown in
FIGS. 20 and 21 , a layered structure of a TFT array panel of an LCD according to this embodiment is almost the same as that shown inFIGS. 4 and 5 . That is, a plurality ofgate lines 121 including a plurality ofgate electrodes 123 are formed on asubstrate 110, and agate insulating layer 140, a plurality ofsemiconductor stripes 151 including a plurality ofprojections 154, and a plurality ofohmic contact stripes 161 including a plurality ofprojections 163 and a plurality ofohmic contact islands 165 are sequentially formed thereon. A plurality ofdata lines 171 including a plurality ofsource electrodes 173 and a plurality ofdrain electrodes 175 are formed on theohmic contacts passivation layer 180 is formed thereon. A plurality ofcontact holes expansions gate lines 121 and thedata lines 171 are provided at thepassivation layer 180 and/or thegate insulating layer 140, and a plurality ofpixel electrodes 190 and a plurality ofcontact assistants - Different from the TFT array panel shown in
FIGS. 4 and 5 , thedata lines 171 and thedrain electrodes 175 includes a bottom layer 171 p preferably made of Mo or Mo alloy, an intermediate layer 171 q preferably made of Al or Al alloy, and a top layer 171 r preferably made of Mo or Mo alloy. - Now, a method of manufacturing the TFT array panel shown in
FIGS. 20 and 21 according to an embodiment of the present invention will be described in detail with reference toFIGS. 22A-32 as well asFIGS. 20 and 21 . -
FIGS. 22A , 23A, 24A and 25A are layout views of the TFT array panel shown inFIGS. 20 and 21 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention, andFIGS. 22B , 23B, 24B and 25B are sectional views of the TFT array panel shown inFIGS. 22A , 23A. 24A and 25A taken along the lines VIB-VIB′, VIIB-VIIB′, VIIIB-VIIIB′, and IXB-IXB′, respectively. - Two conductive films, a lower conductive film and an upper conductive film are sputtered in sequence on an insulating
substrate 110 such as transparent glass. The lower conductive film has a thickness of about 1,500-3,000 Å, preferably 2,500 Å and is made of Al—Nd alloy, while the upper conductive film has a thickness of about 300-600 Å, preferably 500 Å and is made of Mo. - Referring to
FIGS. 22A and 22B , the upper conductive film and the lower conductive film are simultaneously patterned by photolithography and wet etch with an etchant to form a plurality ofgate lines 121 including a plurality ofgate electrodes 123, a plurality ofprojections 127, and a plurality ofexpansions 125. The etchant contains about 65-75% H3PO4, about 0.5-4% HNO3, about 9-13% CH3COOH, about 2-5% stabilizer, and deionized water. The stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, L is H2O, NH3, CN or NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3. Although the elements contained in the etchant are the same as those described with reference toFIGS. 6A and 6B, the percentages thereof are different since the materials forming thegate lines 121 are different. - Referring to
FIGS. 23A and 23B , after sequential deposition of agate insulating layer 140, an intrinsic a-Si layer, and an extrinsic a-Si layer, the extrinsic a-Si layer and the intrinsic a-Si layer are photo-etched to form a plurality ofextrinsic semiconductor stripes 164 and a plurality ofintrinsic semiconductor stripes 151 including a plurality ofprojections 154 on thegate insulating layer 140. - Referring to
FIGS. 24A and 24B , a bottom film made of Mo, an intermediate film made of Al—Nd alloy, and a top film made of Mo are sequentially deposited and wet-etched with the etchant used for patterning thegate lines 121 to form a plurality ofdata lines 171 including a plurality ofsource electrodes 173 and a plurality ofexpansions 179, a plurality ofdrain electrodes 175, and a plurality ofstorage capacitor conductors 177. - Thereafter, portions of the
extrinsic semiconductor stripes 164, which are not covered with thedata lines 171, thedrain electrodes 175, and thestorage capacitor conductors 177, are removed to complete a plurality ofohmic contact stripes 161 including a plurality ofprojections 163 and a plurality ofohmic contact islands 165 and to expose portions of theintrinsic semiconductor stripes 151. Oxygen plasma treatment preferably follows thereafter in order to stabilize the exposed surfaces of thesemiconductor stripes 151. - Referring to
FIGS. 25A and 25B , apassivation layer 180 is deposited and thepassivation layer 180 and thegate insulating layer 140 are photo-etched to form a plurality of contact holes 182, 185, 187 and 189 exposing theexpansions 125 of thegate lines 121, thedrain electrodes 175, thestorage capacitor conductors 177, and theexpansions 179 of the data lines 171. - Finally, as shown in
FIGS. 20 and 21 , a plurality ofpixel electrodes 190 and a plurality ofcontact assistants passivation layer 180 by sputtering and photo-etching an IZO layer having a thickness of about 800-1,000 Å, preferably 900 Å with the etchant used for etching thegate lines 121 and the data lines 175. - According to another embodiment of the present invention, a plurality of color filters (not shown) are provided under the pixel electrodes.
- As described above, the
gate lines 121, thedata lines 171, and thepixel electrodes 190 are etched by using a single etchant with elements having percentages depending on materials to be etched. Accordingly, the manufacturing method and apparatus are simplified, thereby reducing the manufacturing cost. - While the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications and substitutions can be made thereto without departing from the spirit and scope of the present invention as set forth in the appended claims.
Claims (8)
1. An etchant for a signal wire, the etchant comprising: a phosphoric acid of about 50-60%; a nitric acid of about 6-10%; an acetic acid of about 15-25%; a stabilizer of about 2-5% stabilizer; and deionized water, wherein the stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
2. An etchant of claim 1 , wherein the etchant is used for patterning an Al or Al alloy layer, a Mo or Mo alloy layer, and multiple layers including an Al or Al alloy layer and a Mo or Mo alloy layer.
3. An etchant of claim 1 , wherein the etchant is used for patterning an IZO layer.
4. An etchant for a signal wire, the etchant comprising: a phosphoric acid of about 65-75%; a nitric acid of about 0.5-4%; an acetic acid of about 9-13%; a stabilizer of about 2-5% stabilizer; and deionized water, wherein the stabilizer includes oxy-hydride inorganic acid represented by M(OH)xLy, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.
5. An etchant of claim 4 , wherein the etchant is used for patterning an Al or Al alloy layer, a Mo or Mo alloy layer, and multiple layers including an Al or Al alloy layer and a Mo or Mo alloy layer.
6. An etchant of claim 4 , wherein the etchant is used for patterning an IZO layer.
7. An etchant of claim 4 , wherein the etchant is used for patterning multiple layers including an Al or Al alloy layer, a Mo layer, and an IZO layer.
8. An etchant of claim 4 , wherein the etchant is used for patterning multiple layers including a Mo layer, an Al or Al alloy layer, and a Mo layer deposited in sequence.
Priority Applications (1)
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US12/106,023 US20080224093A1 (en) | 2003-05-28 | 2008-04-18 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant |
Applications Claiming Priority (4)
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KR2003-0034007 | 2003-05-28 | ||
KR1020030034007A KR100945583B1 (en) | 2002-08-07 | 2003-05-28 | Etchant for patterning a wiring and method for manufacturing a thin film transistor array panel using the etchant |
US10/772,293 US7371622B2 (en) | 2003-05-28 | 2004-02-06 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant |
US12/106,023 US20080224093A1 (en) | 2003-05-28 | 2008-04-18 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant |
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US10/772,293 Division US7371622B2 (en) | 2003-05-28 | 2004-02-06 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant |
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US20080224093A1 true US20080224093A1 (en) | 2008-09-18 |
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US10/772,293 Expired - Fee Related US7371622B2 (en) | 2003-05-28 | 2004-02-06 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant |
US12/106,023 Abandoned US20080224093A1 (en) | 2003-05-28 | 2008-04-18 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant |
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US10/772,293 Expired - Fee Related US7371622B2 (en) | 2003-05-28 | 2004-02-06 | Etchant for signal wire and method of manufacturing thin film transistor array panel using etchant |
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US (2) | US7371622B2 (en) |
JP (1) | JP2004356616A (en) |
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Cited By (1)
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US20150075850A1 (en) * | 2013-09-18 | 2015-03-19 | Kanto Kagaku Kabushiki Kaisha | Metal oxide etching solution and an etching method |
Families Citing this family (9)
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US7172913B2 (en) * | 2004-03-19 | 2007-02-06 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
KR101160829B1 (en) * | 2005-02-15 | 2012-06-29 | 삼성전자주식회사 | Etchant composition and method for thin film transistor array panel |
KR101124569B1 (en) * | 2005-06-09 | 2012-03-15 | 삼성전자주식회사 | Echant and method for fabricating interconnection line and method for fabricating thin film transistor substrate using the same |
KR101154244B1 (en) * | 2005-06-28 | 2012-06-18 | 주식회사 동진쎄미켐 | Etchant for etching Al, Mo and ITO |
KR20070017762A (en) * | 2005-08-08 | 2007-02-13 | 엘지.필립스 엘시디 주식회사 | Etchant composition, method of patterning electroconductive film using the same and method of fabricating flat panel display using the same |
JP2008166334A (en) * | 2006-12-27 | 2008-07-17 | Mitsubishi Electric Corp | Display device and its manufacturing method |
TWI328788B (en) * | 2008-03-11 | 2010-08-11 | Au Optronics Corp | Gate driver-on-array and method of making the same |
TWI461122B (en) * | 2013-01-07 | 2014-11-11 | Ecocera Optronics Co Ltd | Circuit board and method for manufacturing the same |
US20150069011A1 (en) * | 2013-09-11 | 2015-03-12 | Carestream Health, Inc. | Wet etching patterning compositions and methods |
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JP2004156070A (en) * | 2002-11-01 | 2004-06-03 | Kanto Chem Co Inc | Composition of etchant for multilayer film including transparent electroconductive film |
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- 2004-02-05 JP JP2004029921A patent/JP2004356616A/en active Pending
- 2004-02-06 US US10/772,293 patent/US7371622B2/en not_active Expired - Fee Related
- 2004-02-06 TW TW093102810A patent/TWI366066B/en not_active IP Right Cessation
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Also Published As
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US20040242017A1 (en) | 2004-12-02 |
US7371622B2 (en) | 2008-05-13 |
TWI366066B (en) | 2012-06-11 |
TW200426498A (en) | 2004-12-01 |
JP2004356616A (en) | 2004-12-16 |
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