US20080265234A1 - Method of Forming Phase Change Memory Cell With Reduced Switchable Volume - Google Patents
Method of Forming Phase Change Memory Cell With Reduced Switchable Volume Download PDFInfo
- Publication number
- US20080265234A1 US20080265234A1 US11/741,781 US74178107A US2008265234A1 US 20080265234 A1 US20080265234 A1 US 20080265234A1 US 74178107 A US74178107 A US 74178107A US 2008265234 A1 US2008265234 A1 US 2008265234A1
- Authority
- US
- United States
- Prior art keywords
- dielectric layer
- phase change
- memory cell
- hole
- catalytic material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000008859 change Effects 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims description 32
- 239000000463 material Substances 0.000 claims abstract description 35
- 230000003197 catalytic effect Effects 0.000 claims abstract description 29
- 239000000376 reactant Substances 0.000 claims abstract description 16
- 238000000059 patterning Methods 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- BLIQUJLAJXRXSG-UHFFFAOYSA-N 1-benzyl-3-(trifluoromethyl)pyrrolidin-1-ium-3-carboxylate Chemical compound C1C(C(=O)O)(C(F)(F)F)CCN1CC1=CC=CC=C1 BLIQUJLAJXRXSG-UHFFFAOYSA-N 0.000 claims description 6
- 239000012782 phase change material Substances 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000000737 periodic effect Effects 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 claims description 2
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 2
- 229910052787 antimony Inorganic materials 0.000 claims 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims 2
- 125000001153 fluoro group Chemical group F* 0.000 claims 2
- 229910052732 germanium Inorganic materials 0.000 claims 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 2
- 229910052714 tellurium Inorganic materials 0.000 claims 2
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims 1
- 125000001309 chloro group Chemical group Cl* 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 239000007788 liquid Substances 0.000 claims 1
- 125000004430 oxygen atom Chemical group O* 0.000 claims 1
- 230000004044 response Effects 0.000 claims 1
- 229910052711 selenium Inorganic materials 0.000 claims 1
- 239000011669 selenium Substances 0.000 claims 1
- 229910052717 sulfur Inorganic materials 0.000 claims 1
- 239000011593 sulfur Substances 0.000 claims 1
- 229910002058 ternary alloy Inorganic materials 0.000 claims 1
- 230000007704 transition Effects 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- -1 Ge2Sb2Te5 (GST) Inorganic materials 0.000 description 2
- 229910018321 SbTe Inorganic materials 0.000 description 2
- 150000004770 chalcogenides Chemical class 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910005872 GeSb Inorganic materials 0.000 description 1
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- 229910005855 NiOx Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 229910010252 TiO3 Inorganic materials 0.000 description 1
- 229910003087 TiOx Inorganic materials 0.000 description 1
- WGKMWBIFNQLOKM-UHFFFAOYSA-N [O].[Cl] Chemical compound [O].[Cl] WGKMWBIFNQLOKM-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- MRPWWVMHWSDJEH-UHFFFAOYSA-N antimony telluride Chemical compound [SbH3+3].[SbH3+3].[TeH2-2].[TeH2-2].[TeH2-2] MRPWWVMHWSDJEH-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910000473 manganese(VI) oxide Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910014031 strontium zirconium oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
Definitions
- This invention relates generally to memory cells in integrated circuits, and, more particularly, to memory cells comprising phase change materials for use in integrated circuits.
- phase change materials PCMs
- switching current pulse a pulse of electrical current
- the electrical resistance state of the given memory cell can be determined (i.e., read) by applying a low magnitude sensing voltage to the material in order to determine its electrical resistance.
- Embodiments of the present invention address the above-identified need by providing methods for reliably and reproducibly forming PCM-based memory cells with constricted PCM regions.
- a memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
- a memory cell comprises a dielectric layer comprising silicon dioxide.
- a hole is patterned in the dielectric layer by contacting the surface of the dielectric layer with a solid platinum catalytic feature in the presence of xenon difluoride (XeF 2 ) under temperature and pressure conditions selected to cause that region of the dielectric layer in contact with the catalytic feature to be selectively removed. The remainder of the dielectric layer remains substantially intact.
- PCM is deposited on the dielectric layer such that a portion of the PCM fills the hole. When a switching current pulse is applied to the memory cell, it must pass through this narrow region of PCM. As a result, high localized current densities are created in the PCM in this portion of the memory cell.
- the magnitude of the switching current pulse required to cause the PCM occupying the hole in the dielectric layer to make an electrical resistance state transition is substantially less than that which would be required to cause a transition in the remainder of the PCM volume.
- This memory cell design therefore, utilizes high localized switching current density to reduce the required magnitude of the switching current pulse.
- FIG. 1 shows a sectional view of a PCM-based memory cell in accordance with an illustrative embodiment of the invention.
- FIG. 2 shows a flow diagram of an illustrative method of forming the FIG. 1 memory cell.
- FIGS. 3A-3E show sectional views of the FIG. 1 memory cell during various stages of its formation.
- phase change material as used herein is intended to encompass any material displaying more than one programmable electrical resistance state for use in integrated circuits.
- PCMs comprise, for example, various chalcogenides and transition metal oxides and include, but are not limited to, doped or undoped GeSb, SbTe, Ge 2 Sb 2 Te 5 (GST), SrTiO 3 , BaTiO 3 , (Sr,Ba)TiO 3 , SrZrO 3 , Ca 2 Nb 2 O 7 , (Pr,Ca)MnO 3 , Ta 2 O 5 , NiO x and TiO x , as well as other suitable materials.
- FIG. 1 shows a memory cell 100 in accordance with an illustrative embodiment of the invention.
- the memory cell comprises a lower electrode 110 , a lower dielectric layer 120 , a PCM feature 130 , an upper electrode 140 , and an upper dielectric layer 150 .
- the lower electrode 110 comprises tungsten or titanium nitride while the upper electrode 1 40 comprises titanium nitride.
- Both the lower and upper dielectric layers 120 , 150 comprise silicon dioxide, and the PCM feature 130 comprises GST. Nonetheless, these material choices are merely illustrative and any other suitable materials may be used in the place of the ones described herein.
- One or both of the lower and upper electrodes may comprise tantalum nitride instead of titanium nitride or tungsten.
- one or both of the dielectric layers may comprise silicon nitride.
- the lower dielectric layer 110 comprises a hole 160 in which sits a portion of the PCM feature 130 .
- the formation of this hole will be described in greater detail below.
- the hole in the dielectric layer allows the PCM feature to electrically contact the lower electrode 110 .
- Access to the memory cell 100 is preferably controlled via two metallic lines (not explicitly shown in FIG. 1 ) in what is commonly referred to as a cross point memory array configuration.
- One metallic line operates as a bitline while the other operates as a wordline.
- the lower electrode 110 is preferably in series with some kind of isolation device which, in turn, is controlled by the wordline.
- isolation devices are conventionally used in random access memory technologies that use resistance to indicate memory state.
- the isolation device may, for example, comprise a metal-oxide-semiconductor (MOS) transistor in series with the memory cell with the transistor's gate coupled to the wordline.
- MOS metal-oxide-semiconductor
- the series MOS transistor allows the memory cell to be isolated from other memory cells when reading the memory cell.
- the upper electrode 140 is preferably electrically coupled to the bitline.
- Additional timing logic, pulse generation, sensing, and drive circuitry are coupled to the wordline and bitline, allowing data to be written to and read from the memory cell in the manner indicated below.
- This additional circuitry is also conventionally used in memory circuitry and therefore will be familiar to one skilled in the art.
- Writing data to the memory cell 100 comprises placing some portion of the total volume of the PCM feature 130 (the “switchable volume”) into either a lower electrical resistance polycrystalline state or a higher electrical resistance amorphous state. Transitions between these states are accomplished by heating the PCM feature through the application of a pulse of switching current between the lower electrode 110 and the upper electrode 140 .
- the placement of a portion of the PCM feature in the hole 160 in the lower dielectric layer 120 acts to force the switching current to pass through a constricted volume of PCM.
- a switching current pulse is applied between the lower electrode and upper electrode, the switching current pulse first passes through the lower electrode and into the portion of the PCM feature filling the hole. Subsequently, the current travels through the remainder of the PCM feature and into the upper electrode.
- the duration of the switching current pulse is preferably between about I and about 500 nanoseconds and has a fast falling edge (e.g., less than about ten nanoseconds), although the invention is not limited to any particular duration and/or rise or fall time of the switching current pulse.
- the fast falling edge acts to freeze the switchable volume of the PCM feature 130 in its current electrical resistance state without allowing additional time for the bonds within the material to continue to rearrange.
- Reading the state of the memory cell 100 may be accomplished by applying a sensing voltage to the memory cell, again via the lower and upper electrodes 110 , 140 .
- the ratio of the electrical resistances between the higher and lower electrical resistance states in a typical two-state PCM is between about 100:1 and 1,000:1.
- the sensing voltage is preferably of low enough magnitude to provide negligible ohmic heating in the PCM feature 130 . Accordingly, the electrical resistance state of the PCM feature may be determined in this manner without disturbing its written electrical resistance state. Data integrity is thereby maintained while reading the data.
- FIG. 2 shows a flow diagram of an illustrative method of forming the memory cell 100
- FIGS. 3A-3E show sectional views of the memory cell during various stages in its formation.
- a layer of electrode material for the lower electrode 110 e.g., titanium nitride or tungsten
- the lower dielectric layer 120 e.g., silicon dioxide
- Step 230 in FIG. 2 comprises patterning the hole 160 in the lower dielectric layer 120 .
- this is accomplished using a method for the selective removal of material similar to that described in U.S. Pat. No. 6,022,485 to Cheek, entitled “Method for Controlled Removal of Material From a Solid Surface,” which is incorporated by reference herein.
- the surface of the lower dielectric layer is contacted by a solid catalytic feature 310 in the presence of a reactant, as shown in FIG. 3B .
- Conditions are selected such that that the region of the lower dielectric layer in contact with the catalytic feature is selectively removed while the remainder of the lower dielectric layer remains substantially intact.
- the catalytic feature 310 is attached to an inert support 320 comprising, for example, a glass, a metal, or a polymer.
- the catalytic feature is preferably formed in the three-dimensional shape of the desired hole 160 in the lower dielectric layer 120 .
- the catalytic feature may be formed in this shape by first depositing a layer of the catalytic material on the inert support (e.g., using conventional sputter deposition or chemical vapor deposition) and then using patterning techniques well known to those skilled in the art.
- the inert substrate will typically comprise a plurality of catalytic features arranged in a repeating pattern when utilized to produce an actual integrated circuit.
- the catalytic feature 310 preferably comprises solid platinum, although other suitable materials or combinations of materials may be utilized.
- the reactant will preferably comprise xenon difluoride (XeF 2 ) gas or some other suitable fluorine-containing gas. Platinum catalytically etches silicon dioxide in the presence xenon difluoride. Conditions employed to effectively remove portions of the lower dielectric layer may vary over a wide range. Nevertheless, generally, temperature is from about 350° to about 450° Celsius and total pressure is from about 0.5 to 1 pounds-per-square-inch-gauge (psig). The reactant partial pressure is typically from about 0.005 to about 0.01 psig. Time for the reaction may be between about 1 and about 20 seconds depending on the thickness of the lower dielectric layer as well as the other reaction conditions.
- the proper choice of the catalytic material, reactant, and processing conditions will strongly depend on the composition of the lower dielectric layer 120 .
- materials or combinations of materials from Groups IVB, VB, VIB, and VIII of the Periodic Table of the Elements may be useful as catalytic features, while oxygen- and chlorine-containing molecules may be useful as reactants.
- the reactant may even be delivered in liquid phase.
- Effective combinations of catalytic materials, reactants, and processing conditions for different lower dielectric layer compositions will be known to one skilled in the art.
- several variations may be made to the selective removal process in step 230 in FIG. 2 and the results will still come within the scope of the invention.
- the hole 160 in the lower dielectric layer 120 may be of any desired shape in a plane parallel to the dielectric layer (e.g., square, rectangular, oval, or round).
- the hole will typically match the shape of the catalytic feature 310 .
- modifying the shape of the catalytic feature becomes a convenient way of tuning the power requirements of the memory cell 100 since the dimensions of the hole in the dielectric layer directly affect the switching current magnitude required to cause phase transitions in the PCM feature 130 .
- the use of the processing sequence just described allows the hole in the lower dielectric layer to have dimensions that are substantially smaller than those which can be formed by conventional photolithograpic techniques.
- the resultant film stack will appear as shown in FIG. 3C .
- the selective removal process may etch somewhat into the lower electrode 110 , as indicated in the figure.
- a layer of PCM for the PCM feature 130 e.g., GST
- the deposition preferably has good gap filling characteristics so that the PCM fully fills the hole.
- a layer of electrode material for the upper electrode 140 is deposited on the layer of PCM, resulting in the film stack shown in FIG. 3D .
- step 260 conventional photolithography and anisotropic etching (e.g., reactive ion etching) are utilized to pattern the layer of electrode material and the layer of PCM to form the upper electrode and the PCM feature as shown in FIG. 3E .
- developed photoresist may be utilized to pattern both the upper electrode and the PCM feature.
- the upper electrode may be etched first with the photoresist in place, the photoresist removed, and then the PCM feature etched using the upper electrode as a hard mask.
- step 270 of FIG. 2 a layer of dielectric material for the upper dielectric layer 150 (e.g., silicon dioxide) is conformally deposited on the film stack.
- step 270 chemical mechanical polishing is used to planarize this layer of dielectric material, removing any dielectric material from the top of the upper electrode and forming the upper dielectric layer as it appears in FIG. 1 .
- the PCM-based memory cell 100 described above is part of the design for an integrated circuit chip.
- the chip design may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly.
- the stored design is then converted into the appropriate format (e.g., GDSI) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are formed on a wafer.
- the photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- the resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (i.e., as a single wafer that has multiple unpackaged chips), as a bare die, or in packaged form.
- the chip is mounted in a single chip package (e.g., plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product (e.g., motherboard) or an end product.
- the end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Abstract
Description
- This invention relates generally to memory cells in integrated circuits, and, more particularly, to memory cells comprising phase change materials for use in integrated circuits.
- The possibility of using phase change materials (PCMs) in nonvolatile memory cells has recently gained momentum as more is learned about these materials and their integration into integrated circuits. When incorporated in a memory cell, these materials can be toggled between higher and lower electrical resistance states by applying a pulse of electrical current (“switching current pulse”) to the memory cell. After writing to a memory cell in this way, the electrical resistance state of the given memory cell can be determined (i.e., read) by applying a low magnitude sensing voltage to the material in order to determine its electrical resistance.
- Currently, binary and ternary chalcogenide alloys such as doped antimony telluride (SbTe) and germanium antimony telluride (Ge2Sb2Te5) (GST) are showing the greatest promise for use in practical PCM-based memory cells. However, the switching of a PCM-based memory cell requires that the switching current pulse produce enough heat in the PCM to cause at least some portion of the PCM to reproducibly change electrical resistance state. The required temperature may be as high 350 degrees Celsius. If the memory cell is not properly designed, the magnitude of the switching current pulse necessary to create these required temperatures can easily exceed that which can be tolerated by modern integrated circuits.
- It has been recognized that the magnitude of the required switching current pulse can be reduced by forcing the current pulse to pass through an extremely narrow region of PCM. The confinement of the switching current to this narrow region results in high localized current density, and, in turn, in high localized ohmic heating. Nevertheless, it remains challenging to reliably and reproducibly form constricted regions of PCM with suitably narrow dimensions. Frequently, for example, such processing requires the formation of features that are smaller than those that can be formed using conventional photolithographic techniques. There remains, as a result, a need for methods of reliably and reproducibly forming constricted regions of PCM in PCM-based memory cells.
- Embodiments of the present invention address the above-identified need by providing methods for reliably and reproducibly forming PCM-based memory cells with constricted PCM regions.
- In accordance with an aspect of the invention, a memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
- In one of the above-identified embodiments, a memory cell comprises a dielectric layer comprising silicon dioxide. A hole is patterned in the dielectric layer by contacting the surface of the dielectric layer with a solid platinum catalytic feature in the presence of xenon difluoride (XeF2) under temperature and pressure conditions selected to cause that region of the dielectric layer in contact with the catalytic feature to be selectively removed. The remainder of the dielectric layer remains substantially intact. Once the hole is formed in the dielectric layer, PCM is deposited on the dielectric layer such that a portion of the PCM fills the hole. When a switching current pulse is applied to the memory cell, it must pass through this narrow region of PCM. As a result, high localized current densities are created in the PCM in this portion of the memory cell.
- Advantageously, the magnitude of the switching current pulse required to cause the PCM occupying the hole in the dielectric layer to make an electrical resistance state transition is substantially less than that which would be required to cause a transition in the remainder of the PCM volume. This memory cell design, therefore, utilizes high localized switching current density to reduce the required magnitude of the switching current pulse.
- These and other features and advantages of the present invention will become apparent from the following detailed description which is to be read in conjunction with the accompanying figures.
-
FIG. 1 shows a sectional view of a PCM-based memory cell in accordance with an illustrative embodiment of the invention. -
FIG. 2 shows a flow diagram of an illustrative method of forming theFIG. 1 memory cell. -
FIGS. 3A-3E show sectional views of theFIG. 1 memory cell during various stages of its formation. - This invention will be illustrated herein in conjunction with exemplary memory cells for use in integrated circuits and methods for forming such memory cells. It should be understood, however, that the invention is not limited to the particular materials, features, and processing steps shown and described herein. Modifications to the illustrative embodiments will become apparent to those skilled in the art.
- Particularly with respect to processing steps, it is emphasized that the descriptions provided herein are not intended to encompass all of the processing steps which may be required to successfully form a functional integrated circuit device. Rather, certain processing steps which are conventionally used in forming integrated circuit devices, such as, for example, wet cleaning and annealing steps, are purposefully not described for economy of description. However one skilled in the art will readily recognize those processing steps omitted from these generalized descriptions. Moreover, many details of the processing steps used to fabricate such integrated circuit devices may be found in a number of publications, for example, S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Volume 1, Lattice Press, 1986 and S. M. Sze, VLSI Technology, Second Edition, McGraw-Hill, 1988, both of which are incorporated herein by reference.
- The term “phase change material” (PCM) as used herein is intended to encompass any material displaying more than one programmable electrical resistance state for use in integrated circuits. PCMs comprise, for example, various chalcogenides and transition metal oxides and include, but are not limited to, doped or undoped GeSb, SbTe, Ge2Sb2Te5 (GST), SrTiO3, BaTiO3, (Sr,Ba)TiO3, SrZrO3, Ca2Nb2O7, (Pr,Ca)MnO3, Ta2O5, NiOx and TiOx, as well as other suitable materials.
- It should also be understood that the various layers and/or regions shown in the accompanying figures are not drawn to scale, and that one or more layers and/or regions of a type commonly used in integrated circuits may not be explicitly shown in a given figure. For example, those integrated circuit features associated with what is commonly referred to as the front-end-of-line and middle-of-line are not described herein. This does not imply that the layers and/or regions not explicitly shown are omitted from the actual integrated circuit.
- For ease of understanding, the design and operating characteristics of a PCM-based memory cell in accordance with an illustrative embodiment of the invention will be described first. Subsequently, methods for forming the illustrative memory cell embodiment in an integrated circuit will be addressed.
-
FIG. 1 shows amemory cell 100 in accordance with an illustrative embodiment of the invention. The memory cell comprises alower electrode 110, a lowerdielectric layer 120, a PCM feature 130, anupper electrode 140, and an upperdielectric layer 150. - The
lower electrode 110 comprises tungsten or titanium nitride while the upper electrode 1 40comprises titanium nitride. Both the lower and upperdielectric layers PCM feature 130 comprises GST. Nonetheless, these material choices are merely illustrative and any other suitable materials may be used in the place of the ones described herein. One or both of the lower and upper electrodes, for example, may comprise tantalum nitride instead of titanium nitride or tungsten. Additionally or alternatively, one or both of the dielectric layers may comprise silicon nitride. One skilled in the art will recognize the various advantages and disadvantages of making such substitutions. - Referring again to
FIG. 1 , it will be observed that the lowerdielectric layer 110 comprises ahole 160 in which sits a portion of thePCM feature 130. The formation of this hole will be described in greater detail below. The hole in the dielectric layer allows the PCM feature to electrically contact thelower electrode 110. - Access to the
memory cell 100 is preferably controlled via two metallic lines (not explicitly shown inFIG. 1 ) in what is commonly referred to as a cross point memory array configuration. One metallic line operates as a bitline while the other operates as a wordline. Thelower electrode 110 is preferably in series with some kind of isolation device which, in turn, is controlled by the wordline. Such isolation devices are conventionally used in random access memory technologies that use resistance to indicate memory state. The isolation device may, for example, comprise a metal-oxide-semiconductor (MOS) transistor in series with the memory cell with the transistor's gate coupled to the wordline. The series MOS transistor allows the memory cell to be isolated from other memory cells when reading the memory cell. In contrast, theupper electrode 140 is preferably electrically coupled to the bitline. Additional timing logic, pulse generation, sensing, and drive circuitry are coupled to the wordline and bitline, allowing data to be written to and read from the memory cell in the manner indicated below. This additional circuitry is also conventionally used in memory circuitry and therefore will be familiar to one skilled in the art. - Writing data to the
memory cell 100 comprises placing some portion of the total volume of the PCM feature 130 (the “switchable volume”) into either a lower electrical resistance polycrystalline state or a higher electrical resistance amorphous state. Transitions between these states are accomplished by heating the PCM feature through the application of a pulse of switching current between thelower electrode 110 and theupper electrode 140. Advantageously, the placement of a portion of the PCM feature in thehole 160 in the lowerdielectric layer 120 acts to force the switching current to pass through a constricted volume of PCM. When, for example, a switching current pulse is applied between the lower electrode and upper electrode, the switching current pulse first passes through the lower electrode and into the portion of the PCM feature filling the hole. Subsequently, the current travels through the remainder of the PCM feature and into the upper electrode. - The forcing of the switching current through the constricted region of the PCM feature 130 in the
hole 160 in the lowerdielectric layer 120 results in a high localized current density in this region of the PCM, and, in turn, in high ohmic heating. For this reason, the switchable volume of the PCM can be found in this region of the PCM feature (as indicated onFIG. 1 ). Outside of the hole in the lower dielectric layer, the current density in the PCM feature is insufficient to cause the transition between electrical resistance states. Accordingly, the magnitude of the required switching current pulse is substantially less than that which would be required to cause a state transition in the entire PCM feature. What is more, this memory cell design allows the magnitude of the switching current pulse to be readily tuned by adjusting the dimensions of the hole in the dielectric layer. The narrower the hole, the more constricted a region of PCM through which the switching current must pass. Through this kind of tuning, the magnitude of the switching current pulse may be readily adjusted to a value that is compatible with modern integrated circuits. - The duration of the switching current pulse is preferably between about I and about 500 nanoseconds and has a fast falling edge (e.g., less than about ten nanoseconds), although the invention is not limited to any particular duration and/or rise or fall time of the switching current pulse. The fast falling edge acts to freeze the switchable volume of the PCM feature 130 in its current electrical resistance state without allowing additional time for the bonds within the material to continue to rearrange.
- Reading the state of the
memory cell 100 may be accomplished by applying a sensing voltage to the memory cell, again via the lower andupper electrodes PCM feature 130. Accordingly, the electrical resistance state of the PCM feature may be determined in this manner without disturbing its written electrical resistance state. Data integrity is thereby maintained while reading the data. -
FIG. 2 shows a flow diagram of an illustrative method of forming thememory cell 100, whileFIGS. 3A-3E show sectional views of the memory cell during various stages in its formation. Initially, instep 210, a layer of electrode material for the lower electrode 110 (e.g., titanium nitride or tungsten) is deposited on whatever structures underlie the memory cell and then patterned to form the lower electrode. Subsequently, instep 220 the lower dielectric layer 120 (e.g., silicon dioxide) is deposited on the lower electrode. The resultant film stack in shown inFIG. 3A . - Step 230 in
FIG. 2 comprises patterning thehole 160 in the lowerdielectric layer 120. In accordance with an aspect of the invention, this is accomplished using a method for the selective removal of material similar to that described in U.S. Pat. No. 6,022,485 to Cheek, entitled “Method for Controlled Removal of Material From a Solid Surface,” which is incorporated by reference herein. In this selective removal process, the surface of the lower dielectric layer is contacted by a solidcatalytic feature 310 in the presence of a reactant, as shown inFIG. 3B . Conditions are selected such that that the region of the lower dielectric layer in contact with the catalytic feature is selectively removed while the remainder of the lower dielectric layer remains substantially intact. - Reference to
FIG. 3B indicates that thecatalytic feature 310 is attached to aninert support 320 comprising, for example, a glass, a metal, or a polymer. The catalytic feature is preferably formed in the three-dimensional shape of the desiredhole 160 in the lowerdielectric layer 120. The catalytic feature may be formed in this shape by first depositing a layer of the catalytic material on the inert support (e.g., using conventional sputter deposition or chemical vapor deposition) and then using patterning techniques well known to those skilled in the art. Of course, it is recognized that the inert substrate will typically comprise a plurality of catalytic features arranged in a repeating pattern when utilized to produce an actual integrated circuit. - If the lower
dielectric layer 120 comprises silicon dioxide, thecatalytic feature 310 preferably comprises solid platinum, although other suitable materials or combinations of materials may be utilized. The reactant, on the other hand, will preferably comprise xenon difluoride (XeF2) gas or some other suitable fluorine-containing gas. Platinum catalytically etches silicon dioxide in the presence xenon difluoride. Conditions employed to effectively remove portions of the lower dielectric layer may vary over a wide range. Nevertheless, generally, temperature is from about 350° to about 450° Celsius and total pressure is from about 0.5 to 1 pounds-per-square-inch-gauge (psig). The reactant partial pressure is typically from about 0.005 to about 0.01 psig. Time for the reaction may be between about 1 and about 20 seconds depending on the thickness of the lower dielectric layer as well as the other reaction conditions. - One skilled in the art will recognize that the proper choice of the catalytic material, reactant, and processing conditions will strongly depend on the composition of the lower
dielectric layer 120. For example, depending on the material to be selectively removed, several materials or combinations of materials from Groups IVB, VB, VIB, and VIII of the Periodic Table of the Elements may be useful as catalytic features, while oxygen- and chlorine-containing molecules may be useful as reactants. The reactant may even be delivered in liquid phase. Effective combinations of catalytic materials, reactants, and processing conditions for different lower dielectric layer compositions will be known to one skilled in the art. As a result, several variations may be made to the selective removal process instep 230 inFIG. 2 and the results will still come within the scope of the invention. - It should be noted that the
hole 160 in the lowerdielectric layer 120 may be of any desired shape in a plane parallel to the dielectric layer (e.g., square, rectangular, oval, or round). The hole will typically match the shape of thecatalytic feature 310. As a result, modifying the shape of the catalytic feature becomes a convenient way of tuning the power requirements of thememory cell 100 since the dimensions of the hole in the dielectric layer directly affect the switching current magnitude required to cause phase transitions in thePCM feature 130. Moreover, the use of the processing sequence just described allows the hole in the lower dielectric layer to have dimensions that are substantially smaller than those which can be formed by conventional photolithograpic techniques. - After performing the patterning of the
hole 160 in the lowerdielectric layer 120, the resultant film stack will appear as shown inFIG. 3C . The selective removal process may etch somewhat into thelower electrode 110, as indicated in the figure. A layer of PCM for the PCM feature 130 (e.g., GST) is then deposited on the lower dielectric layer instep 240 by, for example, sputter deposition. The deposition preferably has good gap filling characteristics so that the PCM fully fills the hole. Subsequently, instep 250, a layer of electrode material for theupper electrode 140 is deposited on the layer of PCM, resulting in the film stack shown inFIG. 3D . Instep 260, conventional photolithography and anisotropic etching (e.g., reactive ion etching) are utilized to pattern the layer of electrode material and the layer of PCM to form the upper electrode and the PCM feature as shown inFIG. 3E . During this patterning process, developed photoresist may be utilized to pattern both the upper electrode and the PCM feature. Alternatively, the upper electrode may be etched first with the photoresist in place, the photoresist removed, and then the PCM feature etched using the upper electrode as a hard mask. One skilled in the art will recognize the relative merits of both patterning techniques. - Once the film stack appears as shown in
FIG. 3E , only a few processing steps remain to convert the film stack into thememory cell 100 shown inFIG. 1 . Instep 270 ofFIG. 2 , a layer of dielectric material for the upper dielectric layer 150 (e.g., silicon dioxide) is conformally deposited on the film stack. Instep 270, chemical mechanical polishing is used to planarize this layer of dielectric material, removing any dielectric material from the top of the upper electrode and forming the upper dielectric layer as it appears inFIG. 1 . - The PCM-based
memory cell 100 described above is part of the design for an integrated circuit chip. The chip design may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSI) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. - The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (i.e., as a single wafer that has multiple unpackaged chips), as a bare die, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product (e.g., motherboard) or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- Although illustrative embodiments of the present invention have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments. For example, the materials utilized in the illustrative embodiments and the particular sequence of processing steps used to fabricate the illustrative embodiments may be changed without departing from the scope of the appended claims. These changes and various other modifications will be evident to one skilled in the art.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/741,781 US20080265234A1 (en) | 2007-04-30 | 2007-04-30 | Method of Forming Phase Change Memory Cell With Reduced Switchable Volume |
US12/498,840 US8115186B2 (en) | 2007-04-30 | 2009-07-07 | Phase change memory cell with reduced switchable volume |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/741,781 US20080265234A1 (en) | 2007-04-30 | 2007-04-30 | Method of Forming Phase Change Memory Cell With Reduced Switchable Volume |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/498,840 Division US8115186B2 (en) | 2007-04-30 | 2009-07-07 | Phase change memory cell with reduced switchable volume |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080265234A1 true US20080265234A1 (en) | 2008-10-30 |
Family
ID=39885872
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/741,781 Abandoned US20080265234A1 (en) | 2007-04-30 | 2007-04-30 | Method of Forming Phase Change Memory Cell With Reduced Switchable Volume |
US12/498,840 Expired - Fee Related US8115186B2 (en) | 2007-04-30 | 2009-07-07 | Phase change memory cell with reduced switchable volume |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/498,840 Expired - Fee Related US8115186B2 (en) | 2007-04-30 | 2009-07-07 | Phase change memory cell with reduced switchable volume |
Country Status (1)
Country | Link |
---|---|
US (2) | US20080265234A1 (en) |
Cited By (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7688619B2 (en) | 2005-11-28 | 2010-03-30 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US20100080036A1 (en) * | 2008-09-30 | 2010-04-01 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure |
US20100080048A1 (en) * | 2008-09-30 | 2010-04-01 | Micron Technology, Inc. | Stt-mram cell structure incorporating piezoelectric stress material |
US20100080047A1 (en) * | 2008-09-30 | 2010-04-01 | Micron Technology, Inc. | Spin current generator for stt-mram or other spintronics applications |
US20100110783A1 (en) * | 2008-11-05 | 2010-05-06 | Micron Technology, Inc. | Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling |
US7719913B2 (en) | 2008-09-12 | 2010-05-18 | Macronix International Co., Ltd. | Sensing circuit for PCRAM applications |
US7749854B2 (en) | 2006-12-06 | 2010-07-06 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US7786460B2 (en) | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7786461B2 (en) | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US7785920B2 (en) | 2006-07-12 | 2010-08-31 | Macronix International Co., Ltd. | Method for making a pillar-type phase change memory element |
US7869270B2 (en) | 2008-12-29 | 2011-01-11 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US7894254B2 (en) | 2009-07-15 | 2011-02-22 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US7903457B2 (en) | 2008-08-19 | 2011-03-08 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US7903447B2 (en) | 2006-12-13 | 2011-03-08 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on programmable resistive memory cell |
US7910906B2 (en) | 2006-10-04 | 2011-03-22 | Macronix International Co., Ltd. | Memory cell device with circumferentially-extending memory element |
US7919766B2 (en) | 2007-10-22 | 2011-04-05 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US7932506B2 (en) | 2008-07-22 | 2011-04-26 | Macronix International Co., Ltd. | Fully self-aligned pore-type memory cell having diode access device |
US7933139B2 (en) | 2009-05-15 | 2011-04-26 | Macronix International Co., Ltd. | One-transistor, one-resistor, one-capacitor phase change memory |
US20110121252A1 (en) * | 2009-11-25 | 2011-05-26 | International Business Machines Corporation | Single mask adder phase change memory element |
US7957182B2 (en) | 2009-01-12 | 2011-06-07 | Micron Technology, Inc. | Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same |
US7968876B2 (en) | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US7978509B2 (en) | 2007-08-02 | 2011-07-12 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
US7993962B2 (en) | 2005-11-15 | 2011-08-09 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US20110210307A1 (en) * | 2009-08-28 | 2011-09-01 | International Business Machines Corporation | Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |
US8030635B2 (en) | 2009-01-13 | 2011-10-04 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8036014B2 (en) | 2008-11-06 | 2011-10-11 | Macronix International Co., Ltd. | Phase change memory program method without over-reset |
US8064248B2 (en) | 2009-09-17 | 2011-11-22 | Macronix International Co., Ltd. | 2T2R-1T1R mix mode phase change memory array |
US8064247B2 (en) | 2009-01-14 | 2011-11-22 | Macronix International Co., Ltd. | Rewritable memory device based on segregation/re-absorption |
US8077505B2 (en) | 2008-05-07 | 2011-12-13 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US8084760B2 (en) | 2009-04-20 | 2011-12-27 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
US8089137B2 (en) | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
US8097871B2 (en) | 2009-04-30 | 2012-01-17 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US8107283B2 (en) | 2009-01-12 | 2012-01-31 | Macronix International Co., Ltd. | Method for setting PCRAM devices |
US8110430B2 (en) | 2005-11-21 | 2012-02-07 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US8110822B2 (en) | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
US8134857B2 (en) | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US8173987B2 (en) | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US20120113541A1 (en) * | 2005-11-02 | 2012-05-10 | Seagate Technology Llc | Magneto-Elastic Anisotropy Assisted Thin Film Structure |
US8178387B2 (en) | 2009-10-23 | 2012-05-15 | Macronix International Co., Ltd. | Methods for reducing recrystallization time for a phase change material |
US8178405B2 (en) | 2006-12-28 | 2012-05-15 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US8198619B2 (en) | 2009-07-15 | 2012-06-12 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8238149B2 (en) | 2009-06-25 | 2012-08-07 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
US8310864B2 (en) | 2010-06-15 | 2012-11-13 | Macronix International Co., Ltd. | Self-aligned bit line under word line memory array |
US8324605B2 (en) | 2008-10-02 | 2012-12-04 | Macronix International Co., Ltd. | Dielectric mesh isolated phase change structure for phase change memory |
US8350316B2 (en) | 2009-05-22 | 2013-01-08 | Macronix International Co., Ltd. | Phase change memory cells having vertical channel access transistor and memory plane |
US8363463B2 (en) | 2009-06-25 | 2013-01-29 | Macronix International Co., Ltd. | Phase change memory having one or more non-constant doping profiles |
US8395935B2 (en) | 2010-10-06 | 2013-03-12 | Macronix International Co., Ltd. | Cross-point self-aligned reduced cell size phase change memory |
US8406033B2 (en) | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
US8415653B2 (en) | 2009-08-28 | 2013-04-09 | International Business Machines Corporation | Single mask adder phase change memory element |
US8467238B2 (en) | 2010-11-15 | 2013-06-18 | Macronix International Co., Ltd. | Dynamic pulse operation for phase change memory |
US8471236B2 (en) | 2009-08-28 | 2013-06-25 | International Business Machines Corporation | Flat lower bottom electrode for phase change memory cell |
US8497705B2 (en) | 2010-11-09 | 2013-07-30 | Macronix International Co., Ltd. | Phase change device for interconnection of programmable logic device |
US8553449B2 (en) | 2009-01-09 | 2013-10-08 | Micron Technology, Inc. | STT-MRAM cell structures |
US8729521B2 (en) | 2010-05-12 | 2014-05-20 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8809829B2 (en) | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8933536B2 (en) | 2009-01-22 | 2015-01-13 | Macronix International Co., Ltd. | Polysilicon pillar bipolar transistor with self-aligned memory element |
US9059394B2 (en) | 2009-11-16 | 2015-06-16 | International Business Machines Corporation | Self-aligned lower bottom electrode |
CN105633279A (en) * | 2016-01-29 | 2016-06-01 | 中国科学院上海微系统与信息技术研究所 | Phase-change memory unit comprising partially defined phase-change material structures and fabrication method |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090263934A1 (en) * | 2008-04-22 | 2009-10-22 | Samsung Electronics Co., Ltd. | Methods of forming chalcogenide films and methods of manufacturing memory devices using the same |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6022485A (en) * | 1997-10-17 | 2000-02-08 | International Business Machines Corporation | Method for controlled removal of material from a solid surface |
US20030127007A1 (en) * | 2001-11-22 | 2003-07-10 | Kabushiki Kaisha Toshiba | Nano-imprinting method, magnetic printing method and recording medium |
US20040251551A1 (en) * | 2003-06-11 | 2004-12-16 | Horii Hideki | Phase changeable memory devices including carbon nano tubes and methods for forming the same |
US20050018526A1 (en) * | 2003-07-21 | 2005-01-27 | Heon Lee | Phase-change memory device and manufacturing method thereof |
US20050079283A1 (en) * | 2001-05-09 | 2005-04-14 | Masatoshi Sakurai | Recording medium, method of manufacturing recording medium and recording-reproducing apparatus |
US20050112901A1 (en) * | 2003-09-30 | 2005-05-26 | Bing Ji | Removal of transition metal ternary and/or quaternary barrier materials from a substrate |
US20050250316A1 (en) * | 2003-12-12 | 2005-11-10 | Suk-Hun Choi | Methods for fabricating memory devices using sacrifical layers and memory devices fabricated by same |
US20050265072A1 (en) * | 2004-05-28 | 2005-12-01 | Hart Mark W | Indirect switching and sensing of phase change memory cells |
US7034332B2 (en) * | 2004-01-27 | 2006-04-25 | Hewlett-Packard Development Company, L.P. | Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making |
US7157304B2 (en) * | 2000-09-29 | 2007-01-02 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US7214958B2 (en) * | 2005-02-10 | 2007-05-08 | Infineon Technologies Ag | Phase change memory cell with high read margin at low power operation |
US7378347B2 (en) * | 2002-10-28 | 2008-05-27 | Hewlett-Packard Development Company, L.P. | Method of forming catalyst nanoparticles for nanowire growth and other applications |
US20080142776A1 (en) * | 2006-12-15 | 2008-06-19 | Harald Seidl | Phase change random access memory device with transistor, and method for fabricating a memory device |
US7465675B2 (en) * | 2004-08-31 | 2008-12-16 | Samsung Electronics Co., Ltd. | Method of forming a phase change memory device having a small area of contact |
-
2007
- 2007-04-30 US US11/741,781 patent/US20080265234A1/en not_active Abandoned
-
2009
- 2009-07-07 US US12/498,840 patent/US8115186B2/en not_active Expired - Fee Related
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6254719B1 (en) * | 1997-10-17 | 2001-07-03 | International Business Machines Corporation | Method for controlled removal of material from a solid surface |
US6022485A (en) * | 1997-10-17 | 2000-02-08 | International Business Machines Corporation | Method for controlled removal of material from a solid surface |
US7157304B2 (en) * | 2000-09-29 | 2007-01-02 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US20050079283A1 (en) * | 2001-05-09 | 2005-04-14 | Masatoshi Sakurai | Recording medium, method of manufacturing recording medium and recording-reproducing apparatus |
US20030127007A1 (en) * | 2001-11-22 | 2003-07-10 | Kabushiki Kaisha Toshiba | Nano-imprinting method, magnetic printing method and recording medium |
US7378347B2 (en) * | 2002-10-28 | 2008-05-27 | Hewlett-Packard Development Company, L.P. | Method of forming catalyst nanoparticles for nanowire growth and other applications |
US20040251551A1 (en) * | 2003-06-11 | 2004-12-16 | Horii Hideki | Phase changeable memory devices including carbon nano tubes and methods for forming the same |
US20050018526A1 (en) * | 2003-07-21 | 2005-01-27 | Heon Lee | Phase-change memory device and manufacturing method thereof |
US20050112901A1 (en) * | 2003-09-30 | 2005-05-26 | Bing Ji | Removal of transition metal ternary and/or quaternary barrier materials from a substrate |
US20050250316A1 (en) * | 2003-12-12 | 2005-11-10 | Suk-Hun Choi | Methods for fabricating memory devices using sacrifical layers and memory devices fabricated by same |
US7034332B2 (en) * | 2004-01-27 | 2006-04-25 | Hewlett-Packard Development Company, L.P. | Nanometer-scale memory device utilizing self-aligned rectifying elements and method of making |
US20050265072A1 (en) * | 2004-05-28 | 2005-12-01 | Hart Mark W | Indirect switching and sensing of phase change memory cells |
US7465675B2 (en) * | 2004-08-31 | 2008-12-16 | Samsung Electronics Co., Ltd. | Method of forming a phase change memory device having a small area of contact |
US7214958B2 (en) * | 2005-02-10 | 2007-05-08 | Infineon Technologies Ag | Phase change memory cell with high read margin at low power operation |
US20080142776A1 (en) * | 2006-12-15 | 2008-06-19 | Harald Seidl | Phase change random access memory device with transistor, and method for fabricating a memory device |
Cited By (86)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8503126B2 (en) * | 2005-11-02 | 2013-08-06 | Seagate Technology Llc | Magneto-elastic anisotropy assisted thin film structure |
US20120113541A1 (en) * | 2005-11-02 | 2012-05-10 | Seagate Technology Llc | Magneto-Elastic Anisotropy Assisted Thin Film Structure |
US8008114B2 (en) | 2005-11-15 | 2011-08-30 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7786460B2 (en) | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7993962B2 (en) | 2005-11-15 | 2011-08-09 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US8110430B2 (en) | 2005-11-21 | 2012-02-07 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7688619B2 (en) | 2005-11-28 | 2010-03-30 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7929340B2 (en) | 2005-11-28 | 2011-04-19 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7785920B2 (en) | 2006-07-12 | 2010-08-31 | Macronix International Co., Ltd. | Method for making a pillar-type phase change memory element |
US7910906B2 (en) | 2006-10-04 | 2011-03-22 | Macronix International Co., Ltd. | Memory cell device with circumferentially-extending memory element |
US7749854B2 (en) | 2006-12-06 | 2010-07-06 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US7903447B2 (en) | 2006-12-13 | 2011-03-08 | Macronix International Co., Ltd. | Method, apparatus and computer program product for read before programming process on programmable resistive memory cell |
US8178405B2 (en) | 2006-12-28 | 2012-05-15 | Macronix International Co., Ltd. | Resistor random access memory cell device |
US7875493B2 (en) | 2007-04-03 | 2011-01-25 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US7786461B2 (en) | 2007-04-03 | 2010-08-31 | Macronix International Co., Ltd. | Memory structure with reduced-size memory element between memory material portions |
US7978509B2 (en) | 2007-08-02 | 2011-07-12 | Macronix International Co., Ltd. | Phase change memory with dual word lines and source lines and method of operating same |
US7919766B2 (en) | 2007-10-22 | 2011-04-05 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US8222071B2 (en) | 2007-10-22 | 2012-07-17 | Macronix International Co., Ltd. | Method for making self aligning pillar memory cell device |
US8077505B2 (en) | 2008-05-07 | 2011-12-13 | Macronix International Co., Ltd. | Bipolar switching of phase change device |
US8134857B2 (en) | 2008-06-27 | 2012-03-13 | Macronix International Co., Ltd. | Methods for high speed reading operation of phase change memory and device employing same |
US7932506B2 (en) | 2008-07-22 | 2011-04-26 | Macronix International Co., Ltd. | Fully self-aligned pore-type memory cell having diode access device |
US7903457B2 (en) | 2008-08-19 | 2011-03-08 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US8315088B2 (en) | 2008-08-19 | 2012-11-20 | Macronix International Co., Ltd. | Multiple phase change materials in an integrated circuit for system on a chip application |
US7719913B2 (en) | 2008-09-12 | 2010-05-18 | Macronix International Co., Ltd. | Sensing circuit for PCRAM applications |
US9552858B2 (en) | 2008-09-30 | 2017-01-24 | Micron Technology. Inc. | STT-MRAM cell structure incorporating piezoelectric stress material |
US9589618B2 (en) | 2008-09-30 | 2017-03-07 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure |
US7876603B2 (en) | 2008-09-30 | 2011-01-25 | Micron Technology, Inc. | Spin current generator for STT-MRAM or other spintronics applications |
US10573366B2 (en) | 2008-09-30 | 2020-02-25 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure and methods of programming the same |
US10127962B2 (en) | 2008-09-30 | 2018-11-13 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure |
US20100080047A1 (en) * | 2008-09-30 | 2010-04-01 | Micron Technology, Inc. | Spin current generator for stt-mram or other spintronics applications |
US20100080036A1 (en) * | 2008-09-30 | 2010-04-01 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure |
US8917542B2 (en) | 2008-09-30 | 2014-12-23 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure |
US20100080048A1 (en) * | 2008-09-30 | 2010-04-01 | Micron Technology, Inc. | Stt-mram cell structure incorporating piezoelectric stress material |
US8102700B2 (en) | 2008-09-30 | 2012-01-24 | Micron Technology, Inc. | Unidirectional spin torque transfer magnetic memory cell structure |
US8310861B2 (en) | 2008-09-30 | 2012-11-13 | Micron Technology, Inc. | STT-MRAM cell structure incorporating piezoelectric stress material |
US8324605B2 (en) | 2008-10-02 | 2012-12-04 | Macronix International Co., Ltd. | Dielectric mesh isolated phase change structure for phase change memory |
US8218357B2 (en) | 2008-11-05 | 2012-07-10 | Micron Technology, Inc. | Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling |
US7944738B2 (en) | 2008-11-05 | 2011-05-17 | Micron Technology, Inc. | Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling |
US8665640B2 (en) | 2008-11-05 | 2014-03-04 | Micron Technologies, Inc. | Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling |
US20110216581A1 (en) * | 2008-11-05 | 2011-09-08 | Micron Technology, Inc. | Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling |
US20100110783A1 (en) * | 2008-11-05 | 2010-05-06 | Micron Technology, Inc. | Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling |
US8036014B2 (en) | 2008-11-06 | 2011-10-11 | Macronix International Co., Ltd. | Phase change memory program method without over-reset |
US7869270B2 (en) | 2008-12-29 | 2011-01-11 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US8094488B2 (en) | 2008-12-29 | 2012-01-10 | Macronix International Co., Ltd. | Set algorithm for phase change memory cell |
US8089137B2 (en) | 2009-01-07 | 2012-01-03 | Macronix International Co., Ltd. | Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method |
US8553449B2 (en) | 2009-01-09 | 2013-10-08 | Micron Technology, Inc. | STT-MRAM cell structures |
US7957182B2 (en) | 2009-01-12 | 2011-06-07 | Micron Technology, Inc. | Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same |
US8107283B2 (en) | 2009-01-12 | 2012-01-31 | Macronix International Co., Ltd. | Method for setting PCRAM devices |
US8237144B2 (en) | 2009-01-13 | 2012-08-07 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8030635B2 (en) | 2009-01-13 | 2011-10-04 | Macronix International Co., Ltd. | Polysilicon plug bipolar transistor for phase change memory |
US8064247B2 (en) | 2009-01-14 | 2011-11-22 | Macronix International Co., Ltd. | Rewritable memory device based on segregation/re-absorption |
US8933536B2 (en) | 2009-01-22 | 2015-01-13 | Macronix International Co., Ltd. | Polysilicon pillar bipolar transistor with self-aligned memory element |
US8084760B2 (en) | 2009-04-20 | 2011-12-27 | Macronix International Co., Ltd. | Ring-shaped electrode and manufacturing method for same |
US8173987B2 (en) | 2009-04-27 | 2012-05-08 | Macronix International Co., Ltd. | Integrated circuit 3D phase change memory array and manufacturing method |
US8097871B2 (en) | 2009-04-30 | 2012-01-17 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US8916845B2 (en) | 2009-04-30 | 2014-12-23 | Macronix International Co., Ltd. | Low operational current phase change memory structures |
US7933139B2 (en) | 2009-05-15 | 2011-04-26 | Macronix International Co., Ltd. | One-transistor, one-resistor, one-capacitor phase change memory |
US8350316B2 (en) | 2009-05-22 | 2013-01-08 | Macronix International Co., Ltd. | Phase change memory cells having vertical channel access transistor and memory plane |
US8624236B2 (en) | 2009-05-22 | 2014-01-07 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US7968876B2 (en) | 2009-05-22 | 2011-06-28 | Macronix International Co., Ltd. | Phase change memory cell having vertical channel access transistor |
US8809829B2 (en) | 2009-06-15 | 2014-08-19 | Macronix International Co., Ltd. | Phase change memory having stabilized microstructure and manufacturing method |
US8406033B2 (en) | 2009-06-22 | 2013-03-26 | Macronix International Co., Ltd. | Memory device and method for sensing and fixing margin cells |
US8238149B2 (en) | 2009-06-25 | 2012-08-07 | Macronix International Co., Ltd. | Methods and apparatus for reducing defect bits in phase change memory |
US8363463B2 (en) | 2009-06-25 | 2013-01-29 | Macronix International Co., Ltd. | Phase change memory having one or more non-constant doping profiles |
US7894254B2 (en) | 2009-07-15 | 2011-02-22 | Macronix International Co., Ltd. | Refresh circuitry for phase change memory |
US8198619B2 (en) | 2009-07-15 | 2012-06-12 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8110822B2 (en) | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
US8779408B2 (en) | 2009-07-15 | 2014-07-15 | Macronix International Co., Ltd. | Phase change memory cell structure |
US8415653B2 (en) | 2009-08-28 | 2013-04-09 | International Business Machines Corporation | Single mask adder phase change memory element |
US20110210307A1 (en) * | 2009-08-28 | 2011-09-01 | International Business Machines Corporation | Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |
US8471236B2 (en) | 2009-08-28 | 2013-06-25 | International Business Machines Corporation | Flat lower bottom electrode for phase change memory cell |
US8492194B2 (en) * | 2009-08-28 | 2013-07-23 | International Business Machines Corporation | Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |
US8064248B2 (en) | 2009-09-17 | 2011-11-22 | Macronix International Co., Ltd. | 2T2R-1T1R mix mode phase change memory array |
US8178387B2 (en) | 2009-10-23 | 2012-05-15 | Macronix International Co., Ltd. | Methods for reducing recrystallization time for a phase change material |
US9059394B2 (en) | 2009-11-16 | 2015-06-16 | International Business Machines Corporation | Self-aligned lower bottom electrode |
US8395192B2 (en) | 2009-11-25 | 2013-03-12 | International Business Machines Corporation | Single mask adder phase change memory element |
US20110121252A1 (en) * | 2009-11-25 | 2011-05-26 | International Business Machines Corporation | Single mask adder phase change memory element |
US8853047B2 (en) | 2010-05-12 | 2014-10-07 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8729521B2 (en) | 2010-05-12 | 2014-05-20 | Macronix International Co., Ltd. | Self aligned fin-type programmable memory cell |
US8310864B2 (en) | 2010-06-15 | 2012-11-13 | Macronix International Co., Ltd. | Self-aligned bit line under word line memory array |
US8395935B2 (en) | 2010-10-06 | 2013-03-12 | Macronix International Co., Ltd. | Cross-point self-aligned reduced cell size phase change memory |
US8497705B2 (en) | 2010-11-09 | 2013-07-30 | Macronix International Co., Ltd. | Phase change device for interconnection of programmable logic device |
US8467238B2 (en) | 2010-11-15 | 2013-06-18 | Macronix International Co., Ltd. | Dynamic pulse operation for phase change memory |
US9559113B2 (en) | 2014-05-01 | 2017-01-31 | Macronix International Co., Ltd. | SSL/GSL gate oxide in 3D vertical channel NAND |
US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
CN105633279A (en) * | 2016-01-29 | 2016-06-01 | 中国科学院上海微系统与信息技术研究所 | Phase-change memory unit comprising partially defined phase-change material structures and fabrication method |
Also Published As
Publication number | Publication date |
---|---|
US8115186B2 (en) | 2012-02-14 |
US20090294748A1 (en) | 2009-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8115186B2 (en) | Phase change memory cell with reduced switchable volume | |
US7514705B2 (en) | Phase change memory cell with limited switchable volume | |
US7989796B2 (en) | Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement | |
US7932167B2 (en) | Phase change memory cell with vertical transistor | |
US7220983B2 (en) | Self-aligned small contact phase-change memory method and device | |
US10756265B2 (en) | Methods for forming narrow vertical pillars and integrated circuit devices having the same | |
US7718989B2 (en) | Resistor random access memory cell device | |
US7479671B2 (en) | Thin film phase change memory cell formed on silicon-on-insulator substrate | |
KR100687750B1 (en) | Phase change type memory device using sb-se metal alloy and method of manufacturing the same | |
US8008114B2 (en) | Phase change memory device and manufacturing method | |
US7728352B2 (en) | Damascene conductive line for contacting an underlying memory element | |
US7642125B2 (en) | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing | |
US20080165569A1 (en) | Resistance Limited Phase Change Memory Material | |
TWI419322B (en) | Phase change memory device for multibit storage | |
JP5431701B2 (en) | Multi-level memory device and operation method thereof | |
US20120298946A1 (en) | Shaping a Phase Change Layer in a Phase Change Memory Cell | |
US20040211953A1 (en) | Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof | |
US20080164452A1 (en) | Scaled-Down Phase Change Memory Cell in Recessed Heater | |
US20090194758A1 (en) | Heating center pcram structure and methods for making | |
CN113169272B (en) | Multi-level phase change memory cell and method of manufacturing the same | |
US20090101885A1 (en) | Method of producing phase change memory device | |
US7985693B2 (en) | Method of producing phase change memory device | |
US7525176B2 (en) | Phase change memory cell design with adjusted seam location | |
CN115210812A (en) | Multi-terminal phase change memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUNG, HSIANG-LAN;REEL/FRAME:019225/0489 Effective date: 20070419 Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BREITWISCH, MATTHEW J.;CHEEK, ROGER W.;JOSEPH, ERIC ANDREW;AND OTHERS;REEL/FRAME:019225/0485;SIGNING DATES FROM 20070419 TO 20070420 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |