US20080277153A1 - System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards - Google Patents
System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards Download PDFInfo
- Publication number
- US20080277153A1 US20080277153A1 US11/931,698 US93169807A US2008277153A1 US 20080277153 A1 US20080277153 A1 US 20080277153A1 US 93169807 A US93169807 A US 93169807A US 2008277153 A1 US2008277153 A1 US 2008277153A1
- Authority
- US
- United States
- Prior art keywords
- power
- information handling
- handling system
- socket
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0776—Resistance and impedance
- H05K2201/0792—Means against parasitic impedance; Means against eddy currents
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
Definitions
- the present invention relates in general to the field of information handling system circuit boards, and more particularly to a system and method for capacitive coupled via structures between circuit board ground, power and circuit planes.
- An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information.
- information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated.
- the variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications.
- information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
- BGA ball grid array
- parasitic inductance is associated with the physical structure of integrated circuits.
- the parasitic inductance tends to disrupt power supply to the integrated circuit, especially at current flows having lower voltages and greater transient surges to meet the demands of powerful modern processors.
- Small parasitic effects have more pronounced effects on power delivery to processors, especially in transient conditions, as operating voltages decrease.
- Discrete component solutions are typically employed to reduce the undesired impact on power supply and delivery, such as associating capacitance with a power supply circuit board wire line to smooth, current flow during transient power demands.
- the ability of discrete component, solutions to compensate for power delivery, decoupling and processor package parasitic effects has fallen behind as processor density has increased and supply voltage decreased, especially in highly utilized areas of a circuit board such as near BGA socket connectors.
- a system and method are provided which substantially reduce the disadvantages and problems associated with previous methods and systems for power supply to information handling system components through a circuit board.
- Power, ground and signal vias connecting with the component are configured according to one or more factors to create a desired level of parasitic capacitance.
- the parasitic capacitance offsets the impact of parasitic inductance associated with the component on the supply of power to the component, such as impacts relating to parasitic inductance that arise during power transients.
- an information handling system circuit board has a ball grid array processor socket disposed on its surface plane to interface processor connectors with circuit board signal wirelines through socket connectors.
- Power is provided to the processor from a power plane through a socket connector by a power via having a barrel length extending from the power plane to the socket.
- Ground is provided to the processor from a ground plane through a socket connector by a ground via having a barrel length extending from the ground plane to the socket.
- Application of power to the processor faces the parasitic inductance that disrupts power delivery, signal compensation and high speed decoupling.
- the power, ground and signal vias are configured to create a desired parasitic capacitance to offset the parasitic inductance.
- the desired parasitic capacitance is created by consideration of one or more factors including, the radius associated with the power via equivalent line charge, the distance associated with the line charges between capacitively coupled vias and the via barrel length.
- the present invention provides a number of important technical advantages.
- One example of an important technical advantage is that coupled via structures reduce the impact of package parasitics, such as inductance, with the presence of greater parasitic capacitance.
- the increased parasitic capacitance reduces or eliminates the need for discrete component solutions and provides improved signal compensation, power delivery and high speed decoupling.
- greater parasitic capacitance of between 0.1 pF and 0.4 pF may be generated for each capacitively coupled via structure in highly utilized areas of a circuit board design, such as BGA locals, depending upon the spatial geometry of the coupled via structure.
- FIG. 1 an information handling system 10 having a circuit board and processor
- FIG. 2 depicts a cutaway view of a circuit board configured to create a predetermined parasitic capacitance that compensates for parasitic inductance;
- FIG. 3 depicts non-uniform charge distribution and equivalent line charge offset of a power and ground via
- FIG. 4 depicts parasitic capacitance associated with plural ground vias configured proximate a power via.
- an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes,
- an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price.
- the information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.
- RAM random access memory
- processing resources such as a central processing unit (CPU) or hardware or software control logic
- ROM read-only memory
- Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display.
- I/O input and output
- the information handling system may also include one or more buses operable to transmit communications between the various hardware components.
- an information handling system 10 having processing components disposed on a circuit board 12 to process information.
- a processor 14 couples to a socket 16 , the socket physically securing the processor to circuit board 12 and electronically interfacing the processor with other processing components.
- Socket 16 has ball grid array contacts 18 that interface with wirelines integrated along the surface of circuit board 12 , such as a memory bus 20 connected to memory 22 or an external bus 24 that communicates with processing components external to circuit board 12 .
- the wirelines are etched along the surface plane of circuit board 12 and protected by a covering insulating layer, although signal wires may extend through various layers of circuit board 12 .
- Signal vias connect the wirelines with the socket contacts 18 by extending vertically through the insulating layer.
- a power supply 26 provides power to one or more socket contacts 18 through a power plane 28 of circuit board 12 .
- a power via extends vertically between power plane 28 and a socket contact 18 to provide power to processor 14 .
- the ground of information handling system 10 is the chassis 30 which connects to a ground plane 32 of circuit board 12 .
- a ground via extends vertically between ground plane 32 and a socket contact 18 to provide ground to processor 14 .
- parasitic inductance and parasitic capacitance are intensified impact on power delivery, high speed decoupling and signal compensation with increased processor speed, increased circuit board wiring density and reduced power voltages.
- parasitic inductance adversely impacts power delivery during transient conditions, especially where processors power demands increase more instantaneously with relatively low supply voltages.
- parasitic capacitance tends to aid power delivery by reducing the impact of parasitic inductance during transient conditions. Inter via spatial relationships define the amount of parasitic capacitance with strong dependencies on via structure within circuit board 12 .
- a range of between 0.1 pF and 0.4 pF of capacitance are available per via structure depending on the spatial via geometry.
- Configuring power, ground and signal vias according to factors associated with parasitic capacitance allows the integration of a desired parasitic capacitance to a power delivery solution to the effects of parasitic inductance.
- the radius associated with the equivalent line charge of a power via, the distance associated with the line charges between associated power and ground vias and the via barrel length are used as factors to build a model and simulation of the circuit board that calculates the parasitic capacitance, such as the Q3D and Etch Spies modeling systems.
- the increase and locality of the capacitive parasitics through via configuration offsets package inductance, appearing as distributed capacitance that provides local high speed decoupling at the socket contacts of an electronic component.
- FIG. 2 a side cutaway view is depicted of a circuit board 12 configured to create a predetermined parasitic capacitance that compensates for processor 14 packaging parasitic inductance.
- Power via 34 is positioned in a predetermined proximity to ground via 36 to create a desired capacitance 38 related to current flow from application of power to processor 14 .
- a buried ground via extends from ground plane 32 to a position proximate to one or more signal wirelines 20 to create a desired capacitance associated with communication of signals through the signal wireline 20 .
- Vias are capacitively coupled in this manner to create a desired distributed capacitance by modeling and simulating circuit board configurations to identify via positions having the desired parasitic capacitance.
- power or signal vias are paired with one or more ground vias or buried ground vias to form a structure having a desired parasitic capacitance.
- multiple structures, each having multiple vias are defined to provide capacitance that offsets the effects of parasitic inductance in combination with conventional discrete component solutions.
- the buried ground vias may be routed throughout the proximity of processor 14 in various shapes and may encase or partially encase power or signal vias in a cylinder shape that surrounds the power or signal via.
- processor 14 socket connection definitions are defined to increase the utility of capacitively coupled via structures that create capacitance by application of power to the processor.
- signal, ground and power connections of the processor are positioned on the processor to support creation of desired capacitance by vias connecting to the signal, ground and power connections through the circuit board.
- FIGS. 3 and 4 top views of various configurations of power and ground vias are depicted to illustrate factors associated with creation of desired parasitic capacitance.
- FIG. 3 depicts a non uniform charge distribution and equivalent line charge offset of a single pair of a power via 34 and ground via 36 .
- One factor applied to increase parasitic capacitance to a desired level is the radius 42 of power via 34 and the radius 44 associated with the power via equivalent line charge.
- the equivalent line charge radius 44 is offset from the physical via radius 42 due to the non-uniformity of charge distribution from the proximity of the single ground via 36 .
- the equivalent line charge radius and physical radius of FIG. 4 overlap due to the uniform charge distribution provided by plural ground vias.
- Another factor applied to increase parasitic capacitance to a desired level is the distance associated with the line charges between capacitively coupled vias, depicted by numeral 46 of FIG. 3 and measured as the separation between the equivalent line charge radii 44 of power via 34 and ground via 36 .
- Another factor is the via barrel length of the power and ground vias, measured as the vertical distance from a socket connection to termination in the power or ground planes.
Abstract
Power supplied to an information handling system electronic component through a circuit board has component package inductance parasitic effects compensated by configuring connections to the electronic component to have increased parasitic capacitance. For instance, power and ground vias that connect a processor to power and ground planes of the circuit board are aligned to create a desired parasitic capacitance that reduces the impact of parasitic inductance relating to signal compensation, power delivery and high speed decoupling. The desired distributed capacitance is modeled by altering the radius associated with the equivalent line charge of the power via, the distance associated with the line charges between power and ground vias, and the via barrel length.
Description
- 1. Field of the Invention
- The present invention relates in general to the field of information handling system circuit boards, and more particularly to a system and method for capacitive coupled via structures between circuit board ground, power and circuit planes.
- 2. Description of the Related Art
- As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
- Over the past several decades, information handling systems have steadily increased their capacity to process and store information in designs having compact footprints. These improvements have been largely based on the availability of processors to handle greater numbers of computations with increased speed by fabricating increased numbers of circuits within a given size of semiconductor material. The processor designs have improved by increasing the number of cycles performed in a given time frame and decreasing the operating voltages. Improved processors allow more rapid execution of application instructions for interaction with an information handling system user as well as improved communication of information through busses that interface various components of an information handling system, such as memory, network interfaces and graphic display interfaces. Information handling system designers face a substantial challenge in interfacing the various components through a circuit board. For instance, design challenges include arranging components in a compact footprint with ease of assembly and adequate cooling. One type of circuit board-to-processor interface that has become increasingly common is the ball grid array (BGA) connector and socket. BGA sockets provide high density, high input/output count packaging with reduced pin-to-pin trace gaps by distributing the ball and grid connections between the processor and the circuit board.
- One difficulty often faced in the design of information handling system circuit boards is that the speed, density and power requirements of powerful processors tend to generate undesired electromagnetic effects and interference. For instance, parasitic inductance is associated with the physical structure of integrated circuits. The parasitic inductance tends to disrupt power supply to the integrated circuit, especially at current flows having lower voltages and greater transient surges to meet the demands of powerful modern processors. Small parasitic effects have more pronounced effects on power delivery to processors, especially in transient conditions, as operating voltages decrease. Discrete component solutions are typically employed to reduce the undesired impact on power supply and delivery, such as associating capacitance with a power supply circuit board wire line to smooth, current flow during transient power demands. However, the ability of discrete component, solutions to compensate for power delivery, decoupling and processor package parasitic effects has fallen behind as processor density has increased and supply voltage decreased, especially in highly utilized areas of a circuit board such as near BGA socket connectors.
- Therefore a need has arisen for a system and method which reduces power delivery, decoupling and package parasitic effects on information handling system circuit board designs.
- In accordance with the present invention, a system and method are provided which substantially reduce the disadvantages and problems associated with previous methods and systems for power supply to information handling system components through a circuit board. Power, ground and signal vias connecting with the component are configured according to one or more factors to create a desired level of parasitic capacitance. The parasitic capacitance offsets the impact of parasitic inductance associated with the component on the supply of power to the component, such as impacts relating to parasitic inductance that arise during power transients.
- More specifically, an information handling system circuit board has a ball grid array processor socket disposed on its surface plane to interface processor connectors with circuit board signal wirelines through socket connectors. Power is provided to the processor from a power plane through a socket connector by a power via having a barrel length extending from the power plane to the socket. Ground is provided to the processor from a ground plane through a socket connector by a ground via having a barrel length extending from the ground plane to the socket. Application of power to the processor faces the parasitic inductance that disrupts power delivery, signal compensation and high speed decoupling. The power, ground and signal vias are configured to create a desired parasitic capacitance to offset the parasitic inductance. The desired parasitic capacitance is created by consideration of one or more factors including, the radius associated with the power via equivalent line charge, the distance associated with the line charges between capacitively coupled vias and the via barrel length.
- The present invention provides a number of important technical advantages. One example of an important technical advantage is that coupled via structures reduce the impact of package parasitics, such as inductance, with the presence of greater parasitic capacitance. The increased parasitic capacitance reduces or eliminates the need for discrete component solutions and provides improved signal compensation, power delivery and high speed decoupling. For instance, greater parasitic capacitance of between 0.1 pF and 0.4 pF may be generated for each capacitively coupled via structure in highly utilized areas of a circuit board design, such as BGA locals, depending upon the spatial geometry of the coupled via structure.
- The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.
-
FIG. 1 aninformation handling system 10 having a circuit board and processor; -
FIG. 2 depicts a cutaway view of a circuit board configured to create a predetermined parasitic capacitance that compensates for parasitic inductance; -
FIG. 3 depicts non-uniform charge distribution and equivalent line charge offset of a power and ground via; and -
FIG. 4 depicts parasitic capacitance associated with plural ground vias configured proximate a power via. - Information handling system power supply to low voltage electronic components has the effect of parasitic inductance during power transients reduced by configuring power and ground vias associated with the electronic component to have a desired parasitic conductance. For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes, For example, an information handling system may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory. Additional components of the information handling system may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communications between the various hardware components.
- Referring now to
FIG. 1 , aninformation handling system 10 is depicted having processing components disposed on acircuit board 12 to process information. For instance, aprocessor 14 couples to asocket 16, the socket physically securing the processor tocircuit board 12 and electronically interfacing the processor with other processing components.Socket 16 has ballgrid array contacts 18 that interface with wirelines integrated along the surface ofcircuit board 12, such as amemory bus 20 connected tomemory 22 or an external bus 24 that communicates with processing components external tocircuit board 12. The wirelines are etched along the surface plane ofcircuit board 12 and protected by a covering insulating layer, although signal wires may extend through various layers ofcircuit board 12. Signal vias connect the wirelines with thesocket contacts 18 by extending vertically through the insulating layer. Apower supply 26 provides power to one ormore socket contacts 18 through apower plane 28 ofcircuit board 12. A power via extends vertically betweenpower plane 28 and asocket contact 18 to provide power toprocessor 14. The ground ofinformation handling system 10 is thechassis 30 which connects to aground plane 32 ofcircuit board 12. A ground via extends vertically betweenground plane 32 and asocket contact 18 to provide ground toprocessor 14. - Application of power to
processor 14 results in package parasitic effects, such as parasitic inductance and parasitic capacitance, that have intensified impact on power delivery, high speed decoupling and signal compensation with increased processor speed, increased circuit board wiring density and reduced power voltages. In particular, parasitic inductance adversely impacts power delivery during transient conditions, especially where processors power demands increase more instantaneously with relatively low supply voltages. In contrast, parasitic capacitance tends to aid power delivery by reducing the impact of parasitic inductance during transient conditions. Inter via spatial relationships define the amount of parasitic capacitance with strong dependencies on via structure withincircuit board 12. For instance, in a typical circuit board design, a range of between 0.1 pF and 0.4 pF of capacitance are available per via structure depending on the spatial via geometry. Configuring power, ground and signal vias according to factors associated with parasitic capacitance allows the integration of a desired parasitic capacitance to a power delivery solution to the effects of parasitic inductance. For instance, the radius associated with the equivalent line charge of a power via, the distance associated with the line charges between associated power and ground vias and the via barrel length are used as factors to build a model and simulation of the circuit board that calculates the parasitic capacitance, such as the Q3D and Etch Spies modeling systems. The increase and locality of the capacitive parasitics through via configuration offsets package inductance, appearing as distributed capacitance that provides local high speed decoupling at the socket contacts of an electronic component. - Referring now to
FIG. 2 , a side cutaway view is depicted of acircuit board 12 configured to create a predetermined parasitic capacitance that compensates forprocessor 14 packaging parasitic inductance. Power via 34 is positioned in a predetermined proximity to ground via 36 to create a desiredcapacitance 38 related to current flow from application of power toprocessor 14. Similarly, a buried ground via extends fromground plane 32 to a position proximate to one ormore signal wirelines 20 to create a desired capacitance associated with communication of signals through thesignal wireline 20. Vias are capacitively coupled in this manner to create a desired distributed capacitance by modeling and simulating circuit board configurations to identify via positions having the desired parasitic capacitance. For instance, power or signal vias are paired with one or more ground vias or buried ground vias to form a structure having a desired parasitic capacitance. With more complex modeling, multiple structures, each having multiple vias, are defined to provide capacitance that offsets the effects of parasitic inductance in combination with conventional discrete component solutions. The buried ground vias may be routed throughout the proximity ofprocessor 14 in various shapes and may encase or partially encase power or signal vias in a cylinder shape that surrounds the power or signal via. In one embodiment,processor 14 socket connection definitions are defined to increase the utility of capacitively coupled via structures that create capacitance by application of power to the processor. For instance, signal, ground and power connections of the processor are positioned on the processor to support creation of desired capacitance by vias connecting to the signal, ground and power connections through the circuit board. - Referring now to
FIGS. 3 and 4 , top views of various configurations of power and ground vias are depicted to illustrate factors associated with creation of desired parasitic capacitance.FIG. 3 depicts a non uniform charge distribution and equivalent line charge offset of a single pair of a power via 34 and ground via 36. One factor applied to increase parasitic capacitance to a desired level is the radius 42 of power via 34 and the radius 44 associated with the power via equivalent line charge. InFIG. 3 , the equivalent line charge radius 44 is offset from the physical via radius 42 due to the non-uniformity of charge distribution from the proximity of the single ground via 36. By comparison, the equivalent line charge radius and physical radius ofFIG. 4 overlap due to the uniform charge distribution provided by plural ground vias. Another factor applied to increase parasitic capacitance to a desired level is the distance associated with the line charges between capacitively coupled vias, depicted bynumeral 46 ofFIG. 3 and measured as the separation between the equivalent line charge radii 44 of power via 34 and ground via 36. Another factor is the via barrel length of the power and ground vias, measured as the vertical distance from a socket connection to termination in the power or ground planes. - Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1.-8. (canceled)
9. An information handling system comprising:
a circuit board operable to support electronic components, the circuit board having a surface plane, a power plane and a ground plane;
an electronic component socket coupled to the circuit board surface plane;
plural wirelines disposed in the circuit board and interfaced with the socket, the wirelines operable to communicate signals with the socket;
an electronic component coupled to the socket and operable to process information for communication as signals through the socket and wirelines, the electronic component operating with parasitic inductance and capacitance;
one or more power vias interfacing the socket to the power plane; and
one or more ground vias interfacing the socket to the ground plane;
wherein the power vias and ground vias are configured according to one or more factors associated with increased parasitic capacitance that offsets the effects of the parasitic inductance.
10. The information handling system of claim 9 wherein the one or more factors comprise the radius associated with the equivalent line charge of the power via.
11. The information handling system of claim 9 wherein the one or more factors comprise the distance associated with the line charges between a power via and a ground via.
12. The information handling system of claim 9 wherein the one or more factors comprise the length of one or more of the vias.
13. The information handling system of claim 9 wherein the electronic component comprises a processor packaged with ball grid array connectors and the socket comprises a ball grid array socket configured to accept the processor.
14. The information handling system of claim 9 further comprising one or more buried vias integrated within the circuit board and interfaced with the ground plane, the buried via disposed to according to the one or more factors to increase parasitic capacitance.
15. The information handling system of claim 14 wherein the buried via at least partially encircles a power via.
16. The information handling system of claim 14 wherein the buried via at least partially encircles a via associated with communication of a signal.
17.-20. (canceled)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/931,698 US20080277153A1 (en) | 2004-08-24 | 2007-10-31 | System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/924,629 US7305760B2 (en) | 2004-08-24 | 2004-08-24 | System and method for capacitive coupled via structures in information handling system circuit boards |
US11/931,698 US20080277153A1 (en) | 2004-08-24 | 2007-10-31 | System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/924,629 Continuation US7305760B2 (en) | 2004-08-24 | 2004-08-24 | System and method for capacitive coupled via structures in information handling system circuit boards |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080277153A1 true US20080277153A1 (en) | 2008-11-13 |
Family
ID=35942832
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/924,629 Active 2025-08-23 US7305760B2 (en) | 2004-08-24 | 2004-08-24 | System and method for capacitive coupled via structures in information handling system circuit boards |
US11/931,698 Abandoned US20080277153A1 (en) | 2004-08-24 | 2007-10-31 | System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/924,629 Active 2025-08-23 US7305760B2 (en) | 2004-08-24 | 2004-08-24 | System and method for capacitive coupled via structures in information handling system circuit boards |
Country Status (1)
Country | Link |
---|---|
US (2) | US7305760B2 (en) |
Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090243756A1 (en) * | 2008-03-20 | 2009-10-01 | Greatbatch Ltd. | Shielded three-terminal flat-through emi/energy dissipating filter |
US20100185263A1 (en) * | 2008-03-20 | 2010-07-22 | Greatbatch Ltd. | Rf activated aimd telemetry transceiver |
US8095224B2 (en) | 2009-03-19 | 2012-01-10 | Greatbatch Ltd. | EMI shielded conduit assembly for an active implantable medical device |
US20120325530A1 (en) * | 2011-06-24 | 2012-12-27 | Hon Hai Precision Industry Co., Ltd. | Circuit board with even current distribution |
US9093974B2 (en) | 2012-09-05 | 2015-07-28 | Avx Corporation | Electromagnetic interference filter for implanted electronics |
US20150216046A1 (en) * | 2014-01-24 | 2015-07-30 | Dell Products, Lp | Structure to Dampen Barrel Resonance of Unused Portion of Printed Circuit Board Via |
US9101782B2 (en) | 2011-08-19 | 2015-08-11 | Greatbatch Ltd. | Implantable cardioverter defibrillator designed for use in a magnetic resonance imaging environment |
US9427596B2 (en) | 2013-01-16 | 2016-08-30 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
US9463329B2 (en) | 2008-03-20 | 2016-10-11 | Greatbatch Ltd. | Shielded three-terminal flat-through EMI/energy dissipating filter with co-fired hermetically sealed feedthrough |
US9504843B2 (en) | 2011-08-19 | 2016-11-29 | Greatbach Ltd. | Implantable cardioverter defibrillator designed for use in a magnetic resonance imaging environment |
USRE46699E1 (en) | 2013-01-16 | 2018-02-06 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
US9931514B2 (en) | 2013-06-30 | 2018-04-03 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
US10080889B2 (en) | 2009-03-19 | 2018-09-25 | Greatbatch Ltd. | Low inductance and low resistance hermetically sealed filtered feedthrough for an AIMD |
US10350421B2 (en) | 2013-06-30 | 2019-07-16 | Greatbatch Ltd. | Metallurgically bonded gold pocket pad for grounding an EMI filter to a hermetic terminal for an active implantable medical device |
US10559409B2 (en) | 2017-01-06 | 2020-02-11 | Greatbatch Ltd. | Process for manufacturing a leadless feedthrough for an active implantable medical device |
US10561837B2 (en) | 2011-03-01 | 2020-02-18 | Greatbatch Ltd. | Low equivalent series resistance RF filter for an active implantable medical device utilizing a ceramic reinforced metal composite filled via |
US10589107B2 (en) | 2016-11-08 | 2020-03-17 | Greatbatch Ltd. | Circuit board mounted filtered feedthrough assembly having a composite conductive lead for an AIMD |
US10629543B2 (en) | 2018-06-26 | 2020-04-21 | SK Hynix Inc. | Package substrates having an electromagnetic bandgap structure and semiconductor packages employing the package substrates |
US10707600B1 (en) * | 2019-06-28 | 2020-07-07 | Arista Networks, Inc. | Systems with electrical isolation between signal and power domains |
US10905888B2 (en) | 2018-03-22 | 2021-02-02 | Greatbatch Ltd. | Electrical connection for an AIMD EMI filter utilizing an anisotropic conductive layer |
US10912945B2 (en) | 2018-03-22 | 2021-02-09 | Greatbatch Ltd. | Hermetic terminal for an active implantable medical device having a feedthrough capacitor partially overhanging a ferrule for high effective capacitance area |
US11147977B2 (en) | 2008-03-20 | 2021-10-19 | Greatbatch Ltd. | MLCC filter on an aimd circuit board conductively connected to a ground pin attached to a hermetic feedthrough ferrule |
US11198014B2 (en) | 2011-03-01 | 2021-12-14 | Greatbatch Ltd. | Hermetically sealed filtered feedthrough assembly having a capacitor with an oxide resistant electrical connection to an active implantable medical device housing |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5636099A (en) * | 1994-05-31 | 1997-06-03 | Matsushita Electric Industrial Co., Ltd. | Variable capacitor formed by multilayer circuit board |
US5973929A (en) * | 1994-04-21 | 1999-10-26 | Canon Kabushiki Kaisha | Printed circuit board having an embedded capacitor |
US6661316B2 (en) * | 1999-02-25 | 2003-12-09 | Formfactor, Inc. | High frequency printed circuit board via |
US6791429B2 (en) * | 2000-10-04 | 2004-09-14 | Hewlett-Packard Development Company, L.P. | Transmission line parasitic element discontinuity cancellation |
US6961231B1 (en) * | 2002-12-06 | 2005-11-01 | Xilinx, Inc. | Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761049A (en) * | 1994-09-19 | 1998-06-02 | Hitachi, Ltd. | Inductance cancelled condenser implemented apparatus |
US6252177B1 (en) * | 1998-02-18 | 2001-06-26 | Compaq Computer Corporation | Low inductance capacitor mounting structure for capacitors of a printed circuit board |
US6563299B1 (en) * | 2000-08-30 | 2003-05-13 | Micron Technology, Inc. | Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer |
US7075185B2 (en) * | 2004-09-14 | 2006-07-11 | Hewlett-Packard Development Company, L.P. | Routing vias in a substrate from bypass capacitor pads |
-
2004
- 2004-08-24 US US10/924,629 patent/US7305760B2/en active Active
-
2007
- 2007-10-31 US US11/931,698 patent/US20080277153A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5973929A (en) * | 1994-04-21 | 1999-10-26 | Canon Kabushiki Kaisha | Printed circuit board having an embedded capacitor |
US5636099A (en) * | 1994-05-31 | 1997-06-03 | Matsushita Electric Industrial Co., Ltd. | Variable capacitor formed by multilayer circuit board |
US6661316B2 (en) * | 1999-02-25 | 2003-12-09 | Formfactor, Inc. | High frequency printed circuit board via |
US6791429B2 (en) * | 2000-10-04 | 2004-09-14 | Hewlett-Packard Development Company, L.P. | Transmission line parasitic element discontinuity cancellation |
US6961231B1 (en) * | 2002-12-06 | 2005-11-01 | Xilinx, Inc. | Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit |
Cited By (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11241581B2 (en) | 2008-03-20 | 2022-02-08 | Greatbatch Ltd. | Feedthrough terminal assembly with an electrically conductive pad conductively connected to a terminal pin |
US10016596B2 (en) | 2008-03-20 | 2018-07-10 | Greatbatch Ltd. | MLCC filter on an AIMD circuit board having an external ground plate adjacent to the hermetic seal insulator |
US9463329B2 (en) | 2008-03-20 | 2016-10-11 | Greatbatch Ltd. | Shielded three-terminal flat-through EMI/energy dissipating filter with co-fired hermetically sealed feedthrough |
US7957806B2 (en) | 2008-03-20 | 2011-06-07 | Greatbatch Ltd. | Shielded three-terminal flat-through EMI/energy dissipating filter |
US10857369B2 (en) | 2008-03-20 | 2020-12-08 | Greatbatch Ltd. | Ground electrical path from an MLCC filter capacitor on an AIMD circuit board to the ferrule of a hermetic feedthrough |
US8195295B2 (en) | 2008-03-20 | 2012-06-05 | Greatbatch Ltd. | Shielded three-terminal flat-through EMI/energy dissipating filter |
US10874866B2 (en) | 2008-03-20 | 2020-12-29 | Greatbatch Ltd. | Flat-through capacitor mounted in a tombstone position on a hermetic feedthrough for an active implantable medical device |
US8433410B2 (en) | 2008-03-20 | 2013-04-30 | Greetbatch Ltd. | Shielded three-terminal flat-through EMI/energy dissipating filter |
US11013928B2 (en) | 2008-03-20 | 2021-05-25 | Greatbatch Ltd. | Ground electrical path from an MLCC filter capacitor on an AIMD circuit board to the ferrule of a hermetic feedthrough |
US8761895B2 (en) | 2008-03-20 | 2014-06-24 | Greatbatch Ltd. | RF activated AIMD telemetry transceiver |
US8868189B2 (en) | 2008-03-20 | 2014-10-21 | Greatbatch Ltd. | Internally grounded flat through filter with hermetically sealed insulative body with internal ground plates |
US20090243756A1 (en) * | 2008-03-20 | 2009-10-01 | Greatbatch Ltd. | Shielded three-terminal flat-through emi/energy dissipating filter |
US11648409B2 (en) | 2008-03-20 | 2023-05-16 | Greatbatch Ltd. | Ground electrical path from an MLCC filter capacitor on an AIMD circuit board to the ferrule of a hermetic feedthrough |
US10124164B2 (en) | 2008-03-20 | 2018-11-13 | Greatbatch Ltd. | MLCC filter on an AIMD circuit board with conductive ground pin attached to a hermetic feedthrough ferrule |
US20110004283A1 (en) * | 2008-03-20 | 2011-01-06 | Greatbatch Ltd. | Shielded three-terminal flat-through emi/energy dissipating filter |
US10722706B2 (en) | 2008-03-20 | 2020-07-28 | Greatbatch Ltd. | Filtered feedthrough assembly having an MLCC filter capacitor on an AIMD circuit board attached to the ferrule of a hermetic feedthrough |
US20100185263A1 (en) * | 2008-03-20 | 2010-07-22 | Greatbatch Ltd. | Rf activated aimd telemetry transceiver |
US10099051B2 (en) | 2008-03-20 | 2018-10-16 | Greatbatch Ltd. | MLCC filter on an AIMD circuit board with direct connect to the gold braze hermetically sealing a feed through insulator to a ferrule |
US9895534B2 (en) | 2008-03-20 | 2018-02-20 | Greatbatch Ltd. | MLCC filter on an AIMD circuit board with conductive ground pin attached to a hermetic feedthrough ferrule |
US11147977B2 (en) | 2008-03-20 | 2021-10-19 | Greatbatch Ltd. | MLCC filter on an aimd circuit board conductively connected to a ground pin attached to a hermetic feedthrough ferrule |
US10016595B2 (en) | 2008-03-20 | 2018-07-10 | Greatbatch Ltd. | MLCC filter on an AIMD circuit board with ground electrical connection to a gold braze between a hermetic feedthrough ferrule and insulator |
US10080889B2 (en) | 2009-03-19 | 2018-09-25 | Greatbatch Ltd. | Low inductance and low resistance hermetically sealed filtered feedthrough for an AIMD |
US8095224B2 (en) | 2009-03-19 | 2012-01-10 | Greatbatch Ltd. | EMI shielded conduit assembly for an active implantable medical device |
US11071858B2 (en) | 2011-03-01 | 2021-07-27 | Greatbatch Ltd. | Hermetically sealed filtered feedthrough having platinum sealed directly to the insulator in a via hole |
US11198014B2 (en) | 2011-03-01 | 2021-12-14 | Greatbatch Ltd. | Hermetically sealed filtered feedthrough assembly having a capacitor with an oxide resistant electrical connection to an active implantable medical device housing |
US10561837B2 (en) | 2011-03-01 | 2020-02-18 | Greatbatch Ltd. | Low equivalent series resistance RF filter for an active implantable medical device utilizing a ceramic reinforced metal composite filled via |
US10596369B2 (en) | 2011-03-01 | 2020-03-24 | Greatbatch Ltd. | Low equivalent series resistance RF filter for an active implantable medical device |
US8625299B2 (en) * | 2011-06-24 | 2014-01-07 | Hon Hai Precision Industry Co., Ltd. | Circuit board with even current distribution |
US20120325530A1 (en) * | 2011-06-24 | 2012-12-27 | Hon Hai Precision Industry Co., Ltd. | Circuit board with even current distribution |
US9504843B2 (en) | 2011-08-19 | 2016-11-29 | Greatbach Ltd. | Implantable cardioverter defibrillator designed for use in a magnetic resonance imaging environment |
US9101782B2 (en) | 2011-08-19 | 2015-08-11 | Greatbatch Ltd. | Implantable cardioverter defibrillator designed for use in a magnetic resonance imaging environment |
US9093974B2 (en) | 2012-09-05 | 2015-07-28 | Avx Corporation | Electromagnetic interference filter for implanted electronics |
US10154616B2 (en) | 2012-09-05 | 2018-12-11 | Avx Corporation | Electromagnetic interference filter for implanted electronics |
US9427596B2 (en) | 2013-01-16 | 2016-08-30 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
USRE46699E1 (en) | 2013-01-16 | 2018-02-06 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
US10350421B2 (en) | 2013-06-30 | 2019-07-16 | Greatbatch Ltd. | Metallurgically bonded gold pocket pad for grounding an EMI filter to a hermetic terminal for an active implantable medical device |
US9931514B2 (en) | 2013-06-30 | 2018-04-03 | Greatbatch Ltd. | Low impedance oxide resistant grounded capacitor for an AIMD |
US9955568B2 (en) * | 2014-01-24 | 2018-04-24 | Dell Products, Lp | Structure to dampen barrel resonance of unused portion of printed circuit board via |
US10595397B2 (en) | 2014-01-24 | 2020-03-17 | Dell Products, L.P. | Structure to dampen barrel resonance of unused portion of printed circuit board via |
US20150216046A1 (en) * | 2014-01-24 | 2015-07-30 | Dell Products, Lp | Structure to Dampen Barrel Resonance of Unused Portion of Printed Circuit Board Via |
US10589107B2 (en) | 2016-11-08 | 2020-03-17 | Greatbatch Ltd. | Circuit board mounted filtered feedthrough assembly having a composite conductive lead for an AIMD |
US10559409B2 (en) | 2017-01-06 | 2020-02-11 | Greatbatch Ltd. | Process for manufacturing a leadless feedthrough for an active implantable medical device |
US10905888B2 (en) | 2018-03-22 | 2021-02-02 | Greatbatch Ltd. | Electrical connection for an AIMD EMI filter utilizing an anisotropic conductive layer |
US10912945B2 (en) | 2018-03-22 | 2021-02-09 | Greatbatch Ltd. | Hermetic terminal for an active implantable medical device having a feedthrough capacitor partially overhanging a ferrule for high effective capacitance area |
US11712571B2 (en) | 2018-03-22 | 2023-08-01 | Greatbatch Ltd. | Electrical connection for a hermetic terminal for an active implantable medical device utilizing a ferrule pocket |
US10629543B2 (en) | 2018-06-26 | 2020-04-21 | SK Hynix Inc. | Package substrates having an electromagnetic bandgap structure and semiconductor packages employing the package substrates |
US10707600B1 (en) * | 2019-06-28 | 2020-07-07 | Arista Networks, Inc. | Systems with electrical isolation between signal and power domains |
Also Published As
Publication number | Publication date |
---|---|
US7305760B2 (en) | 2007-12-11 |
US20060044895A1 (en) | 2006-03-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20080277153A1 (en) | System and Method for Capacitive Coupled VIA Structures in Information Handling System Circuit Boards | |
US20140374877A1 (en) | Integrated Circuits With On-Die Decoupling Capacitors | |
US10963024B2 (en) | Combination parallel path heatsink and EMI shield | |
US20050024840A1 (en) | Power distribution system with a dedicated power structure and a high performance voltage regulator | |
KR100911784B1 (en) | Split thin film capacitor for multiple voltages | |
US9691437B2 (en) | Compact microelectronic assembly having reduced spacing between controller and memory packages | |
CN101960934A (en) | Multilayer printed wiring board | |
CN101360394A (en) | Printed wiring board structure and electronic apparatus | |
CN105279124B (en) | Integrated circuit with interface circuitry and interface unit for interface circuitry | |
US6794581B2 (en) | Method and apparatus for distributing power to integrated circuits | |
CN109691241A (en) | The circuit and method of mutual capacitance are provided in vertical electrical connector | |
US7667320B2 (en) | Integrated circuit package with improved power signal connection | |
US20070244684A1 (en) | Method to model 3-D PCB PTH via | |
US11294435B2 (en) | Information handling system high density motherboard | |
US20110169173A1 (en) | Wiring substrate for a semiconductor chip and semiconducotor package having the wiring substrate | |
US8282406B2 (en) | Connector with electrostatic discharge protection | |
US7173804B2 (en) | Array capacitor with IC contacts and applications | |
US20070144767A1 (en) | Layout structure of a conduction region of a cpu socket | |
US7677902B2 (en) | Extended package substrate | |
US7365428B2 (en) | Array capacitor with resistive structure | |
US20190057938A1 (en) | Chip on glass package assembly | |
US20080112142A1 (en) | Memory module comprising memory devices | |
CN215298264U (en) | Fingerprint identification module and electronic equipment | |
US11259403B1 (en) | Printed circuit board structure for solid state drives | |
TW201631727A (en) | Electrical interconnect for an electronic package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |