US20090007086A1 - Compiler Optimization - Google Patents
Compiler Optimization Download PDFInfo
- Publication number
- US20090007086A1 US20090007086A1 US12/167,421 US16742108A US2009007086A1 US 20090007086 A1 US20090007086 A1 US 20090007086A1 US 16742108 A US16742108 A US 16742108A US 2009007086 A1 US2009007086 A1 US 2009007086A1
- Authority
- US
- United States
- Prior art keywords
- partial program
- pattern
- instruction
- program
- optimized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/443—Optimisation
- G06F8/4434—Reducing the memory space required by the program code
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
Provides effective use of architecture-specific instructions. There is provided a compiler including: a target partial program detecting unit for detecting, from among a partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced as a partial program to be optimized; an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced, so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced; an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with a target instruction sequence determined in accordance with the pattern to be replaced.
Description
- The present invention relates to a compiler, an optimization method, a compiler program, and a recording medium. In particular, the present invention relates to a compiler, an optimization method, a compiler program, and a recording medium that replace an instruction arrangement pattern that is known to be optimizable with a target instruction sequence corresponding to the arrangement pattern.
- There has been proposed a technique of detecting an instruction sequence matching a predetermined pattern from a program to be optimized and replacing the instruction sequence with another instruction sequence determined in advance in accordance with the pattern. This technique can optimize a program, for example, by replacing a sequence of instructions for performing a certain kind of processing with a single instruction producing the same processing result as the processing performed by the sequence of instructions. The instruction which replaces the sequence of instructions is, for example, a TRT instruction in the S/390 architecture provided by IBM Corporation.
- The following are documents are referred to and/or considered with respect to an embodiment:
-
- [Non-Patent Document 1]
- Jianghai Fu. Directed graph pattern matching and topological embedding. Journal of Algorithms, 22(2):372-391, February 1997.
- [Non-Patent Document 2]
- S. S. Muchnick. Advanced compiler design and implementation, Morgan Kaufmann Publishers, Inc., 1997.
- [Non-Patent Document 3]
- Arvind Gupta and Naomi Nishimura. Finding Largest Subtrees and Smallest Supertrees, Algorithmica, Vol. 21, No. 2, pp. 183-210, 1998
- [Non-Patent Document 4]
- http://publibz.boulder.ibm.com/epubs/pdf/dz9zr002.pdf, pp. 7-180
- A TRT instruction is an instruction to scan a predetermined storage area in order from the top and output an address or the like at which a value satisfying a predetermined condition is stored (see Non-Patent Document 4).
FIG. 16 is a control flow graph corresponding to processing according to a TRT instruction. The processing by means of the TRT instruction corresponds to a sequence of processing steps by which values stored in a storage area byte array are read out in order from the top of the storage area to a variable ch, and which ends when one of conditions cond1 to condN is satisfied. A compiler may replace such a processing sequence with a single TRT instruction to optimize a program. - However, it is rare that a program to be optimized completely matches a predetermined pattern. If such a match does not occur, optimization is abandoned in the conventional art. Therefore there has been a possibility of failure to effectively utilize an instruction such as a TRT instruction specific to an architecture.
- It is, therefore, an object of the present invention to provide a compiler, an optimization method, a compiler program, and a recording medium as a solution to the above-described problem. This object can be attained by a combination of features described in the independent claims in the appended claims. In the dependent claims, further advantageous examples of the present invention are specified.
- To solve the above-described problem, according to a first aspect of the present invention, there is provided a compiler detecting a pattern that is to be replaced. The compiler includes multiple predetermined instructions in a program to be optimized, and replaces the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced.
- The compiler has: a target partial program detecting unit for detecting, from among partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced, as a partial program to be optimized; an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced; and an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with the target instruction sequence determined in accordance with the pattern to be replaced. Thus, the present invention allows architecture-specific instructions to be used effectively.
- The foregoing and other aspects of these teachings are made more evident in the following detailed description of the invention, when read in conjunction with the attached drawing figures, wherein:
-
FIG. 1 is a functional block diagram of acompiler 10; -
FIG. 2 shows a concrete example of apattern 20 to be replaced and apartial program 40 to be optimized; -
FIG. 3 shows a concrete example of thepartial program 40 to be optimized and apartial program 50 to be optimized corresponding toFIG. 2( e); -
FIG. 4 is a flowchart showing a process in which thecompiler 10 optimizes the program to be optimized; -
FIG. 5 shows a first example of thepattern 20 to be replaced and atarget instruction template 30; -
FIG. 6 shows a first example of thepartial pattern 40 to be optimized by thecompiler 10; -
FIG. 7 shows a resultantpartial program 60 in the first example; -
FIG. 8 shows a second example of thepartial pattern 40 to be optimized by thecompiler 10; -
FIG. 9 shows the resultantpartial program 60 in the second example; -
FIG. 10 shows a third example of thepartial pattern 40 to be optimized by thecompiler 10; -
FIG. 11 shows the resultantpartial program 60 in the third example; -
FIG. 12 shows a fourth example of thepartial pattern 40 to be optimized by thecompiler 10; -
FIG. 13 shows the resultantpartial program 60 in the fourth example; -
FIG. 14 is a diagram for explaining the effect of the embodiment; -
FIG. 15 shows an example of the hardware configuration of acomputer 500 which functions as thecompiler 10; and -
FIG. 16 is a control flow graph corresponding to processing according to a TRT instruction. -
-
- 10 . . . Compiler
- 20 . . . Pattern to be replaced
- 30 . . . Target instruction template
- 40 . . . Partial program to be optimized
- 50 . . . Partial program to be optimized
- 60 . . . Resultant partial program
- 100 . . . Optimization candidate detecting unit
- 110 . . . Target partial program detecting unit
- 120 . . . Instruction sequence transforming unit
- 130 . . . Instruction sequence replacing unit
- The present invention provides a compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized, and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, the compiler having a target partial program detecting unit for detecting, from among partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced, as a partial program to be optimized, an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced, and an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with the target instruction sequence determined in accordance with the pattern to be replaced.
- It is noted that not all the necessary features of the invention are listed. Subcombinations of the features can also constitute the present invention. The present invention allows architecture-specific instructions to be used effectively.
- The present invention will be described with respect to embodiments thereof. The embodiment described below, however, is not limited the invention set forth in the appended claims, and all combinations of features described in the description of the embodiment are not necessarily indispensable to the solution according to the present invention.
-
FIG. 1 is a functional block diagram of acompiler 10. Thecompiler 10 detects a pattern which is to be replaced and which has multiple predetermined instructions, and replaces the detected pattern to be replaced with a target instruction sequence determined in accordance with the pattern to be replaced. The target instruction sequence is an instruction sequence that is executed more efficiently than the pattern to be replaced and includes, for example, an architecture-specific high-speed instruction. That is, the purpose is to optimize the program to be optimized into an instruction sequence which is executed more efficiently. - The
compiler 10 has an optimizationcandidate detecting unit 100, a target partialprogram detecting unit 110, an instructionsequence transforming unit 120, and an instructionsequence replacing unit 130. The optimizationcandidate detecting unit 100 detects a candidate for a partial program which is an object to be optimized. For example, the optimizationcandidate detecting unit 100 detects, in a program to be optimized, a partial program including a memory access instruction to access the same type of data as data to be accessed according to a memory access instruction included in the pattern to be replaced. The partial program may be a processing unit of the program called a method, a function or a procedure, or may be an instruction sequence such as loop processing determined on the basis of a characteristic of a control flow. - The partial
program detecting unit 110 detects as apartial program 40 to be optimized a partial program similar to apattern 20 to be replaced in multiple partial programs detected by the optimizationcandidate detecting unit 100. For example, the partialprogram detecting unit 110 detects as partial program 40 a partial program including instructions corresponding to all instructions included in thepattern 20. More specifically, the partialprogram detecting unit 110 determines, with respect to two instructions, that the instructions correspond to each other if the processing details according to the instructions are identical to each other, if the number of control flows output from the instructions are equal to each other, and if instructions at transition destinations of the control flows are identical to each other. - The instruction
sequence transforming unit 120 transforms, in thepartial program 40, instructions other than those instructions corresponding to instructions included in thepattern 20 and those instructions having execution dependencies different from the pattern to be replaced so that dependencies between instructions included in thepartial program 40 match thepattern 20. The instructionsequence transforming unit 120 may transform other instructions if necessary. The transformed partial program to be optimized is set as apartial program 50 to be optimized. - The instruction
sequence replacing unit 130 replaces thepartial program 50 transformed by the instructionsequence transforming unit 120 with a target instruction sequence determined in accordance with thepattern 20. For example, thecompiler 10 generates a target instruction sequence by replacing each variable in atarget instruction template 30 showing the structure of the target instruction sequence with a corresponding variable in thepartial program 50. As a result, thecompiler 10 outputs as a resultantpartial program 60 the program to be optimized including the target instruction sequence. -
FIG. 2( a) shows a concrete example of thepattern 20. Thepattern 20 has an instruction A, an instruction B, an instruction C and an instruction D. Thepattern 20 determines execution dependencies between the instruction A, instruction B, instruction C and instruction D. The execution dependencies between the instructions are, for example, control flows between the instructions. According to the control flows, the instruction B is executed after execution of the instruction A, the instruction C is executed after execution of the instruction B, and the instruction D is executed after execution of the instruction C. The instruction A is again executed after execution of the instruction D. - The
pattern 20 may alternatively determine control dependences or data dependences between instructions. Also, thepattern 20 may be a PDG (program dependence graph) which is a dependence graph determining both control dependences and data dependences. That is, thepattern 20 may be a dependence graph having as a node each of multiple instructions included in thepattern 20 and having directed edges representing execution dependences between multiple instructions. -
FIG. 2( b) shows a first example of thepartial program 40. This partial program includes instruction A, instruction B, instruction C, instruction D and instruction A. Accordingly, this partial program includes instructions corresponding to all the instructions included in thepattern 20. The target partialprogram detecting unit 110 therefore detects this partial program as thepartial program 40. Thus, in a case where thepattern 20 determines recurring dependences between instructions, the target partialprogram detecting unit 110 can detect, as thepartial program 40, an instruction sequence having dependencies which are the same as those determined by the pattern to be replaced 20 but differ in recurrence phase. - In this case, the instruction
sequence replacing unit 130 replaces thepartial program 40 with the target instruction sequence, without thepartial program 40 being transformed by the instructionsequence transforming unit 120. The target partialprogram detecting unit 110 may detect, as well as this example of instruction sequence, as thepartial program 40 to be optimized, an instruction sequence having dependences which are the same as those determined by thepattern 20 and which appear in the same recurrence phase (a completely matching sequence). Also in this case, the instructionsequence replacing unit 130 replaces thepartial program 40 with the target instruction sequence, without thepartial program 40 being transformed by the instructionsequence transforming unit 120. -
FIG. 2( c) shows a second example of thepartial program 40. This partial program includes instruction A, instruction B, instruction C and instruction D. Accordingly, this partial program includes instructions corresponding to all the instructions included in thepattern 20. The target partialprogram detecting unit 110 therefore detects this partial program as thepartial program 40. Thus, the target partialprogram detecting unit 110 can detect, as thepartial program 40, a partial program including an instruction sequence executed in a certain order different from that of the execution dependences in thepattern 20. - In this case, the instruction
sequence transforming unit 120 changes the order of execution of the instructions in thepartial program 40 on the basis of the dependences on condition that the results of processing by thepartial program 40 are not changed after changing the order of execution of the instructions in thepartial program 40. More specifically, the instructionsequence transforming unit 120 interchanges the positions of the instruction B and the instruction C in the execution order if the instruction B does not depend on the result of processing according to the instruction C. Thepartial program 50 is thereby produced. The instructionsequence replacing unit 130 replaces thepartial program 50 changed in instruction execution order, with the target instruction sequence. -
FIG. 2( d) shows a third example of thepartial program 40. This partial program includes instruction A, instruction B, instruction C, instruction D and instruction E. Accordingly, this partial program includes instructions corresponding to all the instructions included in thepattern 20. The target partialprogram detecting unit 110 therefore detects this partial program as thepartial program 40. Thus, the target partialprogram detecting unit 110 can detect, as thepartial program 40, a partial program including in loop processing an additional instruction E which does not correspond to any of the an instructions included in thepattern 20. - In this case, the instruction
sequence transforming unit 120 makes a transformation such that the additional instruction is executed out of the loop processing, on condition that the result of execution of the additional instruction included in the loop processing of thepartial program 40 is constant independently of repetition of the loop processing. Alternatively, the instructionsequence transforming unit 120 may divide the loop processing of thepartial program 40 into two loop processings in which the additional instruction and the instruction sequence other than the additional instruction are respectively executed. Division of loop processing will not be described since it is well known fromNon-Patent Document 2. The instructionsequence replacing unit 130 replaces the loop processing from which the additional instruction has been removed with the target instruction sequence. -
FIG. 2 shows a fourth example of thepartial program 40. This partial program includes instruction A, instruction B and instruction D. This partial program lacks some of the instructions included in the pattern 20 (i.e., instruction C). In this case, the target partialprogram detecting unit 110 first computes the proportion of the instructions in the partial program corresponding to the other instructions included in thepattern 20 in all the instructions included in thepattern 20. The target partialprogram detecting unit 110 then detects the partial program as thepartial program 40, on condition that the computed proportion is higher than a predetermined reference proportion. Processing in this case will be described with reference toFIG. 3 . -
FIG. 3 shows a concrete example of thepartial program 40 and thepartial program 50 corresponding toFIG. 2( e). The instructionsequence transforming unit 120 adds to thepartial program 40 the instruction C which is the absent instruction absent in the instructions in thepartial program 40 corresponding to all the instructions included in thepattern 20. The instructionsequence transforming unit 120 generates a cancel instruction to return the result of processing of thepartial program 40 changed by the addition of the absent instruction to the processing result obtained in the case where the absent instruction is not added. Instruction C−1 represents this cancel instruction. The instructionsequence transforming unit 120 may generate a set of two instructions respectively executed before and after the instruction C to cancel out the effect of the addition. Instruction C−1 before and instruction C−1 after represent these instructions. - For example, the instruction
sequence transforming unit 120 generates as instruction C−1 before a save instruction to save, before the instruction C, the value in a storage area in which the result of processing according to the instruction C is stored. The instructionsequence transforming unit 120 also generates as instruction C−1 after a recovery instruction to recover the value in the storage area after execution of the instruction C.FIG. 3( a) shows the generatedpartial program 50. The instructionsequence transforming unit 120 makes a transformation such that the save instruction and the recovery instruction are executed out of the generatedpartial program 50 to be optimized.FIG. 3( b) shows the transformedpartial program 50. In this case, the instructionsequence replacing unit 130 replaces thepartial program 50 including the instruction C with the target instruction sequence. - Preferably, the target partial
program detecting unit 110 computes, with respect to each of partial programs, an estimate of the processing time increased in a case where an absent instruction and a save instruction or the like to the partial program. The target partialprogram detecting unit 110 also computes an estimate of the reduced processing time in a case where the partial program is replaced with the target instruction sequence by the instructionsequence replacing unit 130. The target partialprogram detecting unit 110 then detects the partial program as the partial program to be optimized, if the increased processing time is shorter than the reduced processing time, thus optimizing only the portion transformable to improve the efficiency. - Further, for example, in a case where a comparison instruction included in the
pattern 20 and a comparison instruction included in thepartial program 40 differ only in a variable to be compared, the instructionsequence transforming unit 120 may change only a constant, with which the variable is to be compared, in the comparison instruction included in thepartial program 40. For example, in a case where thepattern 20 includes an instruction “switch(ch)” and thepartial program 40 includes an instruction “switch(ch+1)”, the instructionsequence transforming unit 120 makes a transformation by reducing 1 from a constant of a case statement in thepartial program 40. The instructionsequence transforming unit 120 transforms the instruction “switch(ch+1)” in thepartial program 40 into the instruction “switch(ch)”. Consequently, the instructionsequence replacing unit 130 can match the instruction included in thepartial program 40 to thepattern 20. -
FIG. 4 is a flowchart showing a process in which thecompiler 10 optimizes a program to be optimized. The optimizationcandidate detecting unit 100 detects a partial program as a candidate to be optimized (S400). Description will be made of a concrete example. For example, the optimizationcandidate detecting unit 100 first detects, as a candidate to be optimized, a partial program including a memory access instruction to access the same type of data as data to be accessed according to a memory access instruction included in thepattern 20. - For example, in a case where the
pattern 20 includes a load instruction, the optimizationcandidate detecting unit 100 determines that a partial program is a candidate to be optimized, on condition that the partial program includes the load instruction. Similarly, in a case where thepattern 20 includes a store instruction, the optimizationcandidate detecting unit 100 determines that a partial program is a candidate to be optimized, on condition that the partial program includes the store instruction. Types of data to be accessed include types indicating kinds of data (an array variable, an instance variable, and a class variable) as well as “byte”, “int”, “float” and “double” which are types indicating ranges of data expression. - In a case where the
pattern 20 includes loop processing, the optimizationcandidate detecting unit 100 detects a partial program including loop processing as a candidate for a partial program to be optimized. The loop processing is an instruction sequence corresponding to strongly connected components in a case where the program is expressed as a control flow graph. Also, the optimizationcandidate detecting unit 100 detects a partial program as a candidate to be optimized, further on condition that the partial program includes loop processing having the same increment in a loop induction variable as that in the loop processing included in thepattern 20. - Also, the optimization
candidate detecting unit 100 may detect a partial program as a candidate to be optimized, further on condition that the loop processing is repeated a number of times equal to or larger than a predetermined reference number of times. The above-described processing narrows down the range in which optimization is tried, thus reducing the processing time required for compilation. As a result, the facility with which the technique described with respect to this embodiment is applied to a dynamic compiler such as a just-in-time compiler. - Preferably, in a case where an optimization level indicating the degree of optimization needed by a user is set, the optimization
candidate detecting unit 100 changes, according to the optimization level, a criterion for detection of a candidate to be optimized. For example, in a case where a higher optimization level is set, the optimizationcandidate detecting unit 100 detects a larger number of partial programs as a candidate to be optimized in comparison with that in a case where a lower optimization level is set. Further, the optimizationcandidate detecting unit 100 may omit processing in S400, for example, depending on a setting made by the user. - Subsequently, the target partial
program detecting unit 110 detects, as a partial program to be optimized, a partial program including instructions corresponding to all the instructions included in thepattern 20 in the partial programs detected as a candidate to be optimized (S410). A concrete example of this processing will be described with respect to a case where thepattern 20 includes loop processing. The target partialprogram detecting unit 110 determines the correspondence between instructions with respect to instructions in the loop processing and makes no determination as to coincidence between dependences. On the other hand, the target partialprogram detecting unit 110 determines not only the correspondence between instructions but also the coincidence between dependences with respect to instructions out of the loop processing. - That is, if the target partial
program detecting unit 110 determines, with respect to each of the partial programs, that the partial program includes in the loop processing the instructions corresponding to all the instructions included in the loop processing, and that all the instructions out of the loop processing in the partial program conform to the dependences determined by thepattern 20, it detects the partial program as a program to be optimized. In this way, loops etc. having the same dependences but differing in recurrence phase can be suitably detected. - Description will be made of further details. The target partial
program detecting unit 110 first generates a dependence graph in which each of multiple instructions included in each of the partial programs is set as a node and execution dependences between multiple instructions are represented by directed edges. The target partialprogram detecting unit 110 then makes a determination as to correspondence in the form between the generated dependence graph and the dependence graph indicating thepattern 20, by means of an algorithm for determination as to graph form correspondence. - The target partial
program detecting unit 110 may detect the same type of dependence graph as thepattern 20, for example, by the topological embedding technique described inNon-Patent Document 1. Alternatively, the target partialprogram detecting unit 110 may detect the dependence graph corresponding in form to thepattern 20, by detecting a piece of program having the largest common portion in common with thepattern 20 on the basis of the method described inNon-Patent Document 2. Each of these techniques allows determination of correspondence in the form even in a case where an arbitrary node is included between the nodes in the dependence graph of thepattern 20. Therefore, the instruction sequence shown inFIG. 2( d) can be detected as a partial program to be optimized. - Also, the dependence graph with respect to loop processing is handled as a tree structure extending infinitely. Then, with respect to (b), A->B->C->D->A->B->C-> . . . is determined to find correspondence in the form. With respect to (c), the loop is developed to obtain A->C->B->D->A->C->B->D->A . . . . This algorithm allows an arbitrary node to be included between the nodes, as mentioned above. Thus, the underlined portions are connected to A->B->C->D. Therefore, correspondence in the form to the pattern is also determined with respect to this structure.
- Thus, when the target partial
program detecting unit 110 determines, with respect each of the partial programs, that the instructions in the partial program corresponding to all the instructions included in thepattern 20 are executed in the execution order designated by the execution dependences between the instructions in thepattern 20, it can detect the partial program as a partial program to be optimized. In this way, each of the instruction sequences shown inFIGS. 2( b), 2(c), and 2(d), for example, can be detected as a partial program to be optimized. - The topological embedding technique may be extended by a method described below to enable the target partial
program detecting unit 110 to detect the instruction sequence shown inFIG. 2( d) as a partial program to be optimized. More specifically, in the topological embedding algorithm, a portion which determines that a partial program lacks a node corresponding to one of the nodes in thepattern 20 is changed so that it determines that the node has been detected regardless of the actual lack of the node. - Each time the absence of one of the nodes is detected, the target partial
program detecting unit 110 records information for identification of the node to obtain a set of absent nodes. As a result, the target partialprogram detecting unit 110 can compute the proportion of the instructions in the partial program corresponding to the other instructions included in thepattern 20 in all the instructions included in thepattern 20. Further, by means of this algorithm, the target partialprogram detecting unit 110 can detect an instruction sequence having two or more of the characteristics shown inFIGS. 2( b) to 2(e). - Subsequently, the instruction
sequence transforming unit 120 transforms, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in thepattern 20 and those instructions having execution dependencies different from thepattern 20 so that dependencies between instructions included in thepartial program 40 match thepattern 20 S420). The instructionsequence replacing unit 130 replaces the transformedpartial pattern 50 with the target instruction sequence determined in accordance with the pattern to be replaced (S430). It is not necessarily possible that all instruction sequences detected by the target partialprogram detecting unit 110 will be replaced with target instruction sequences. That is, in some cases, the instructionsequence transforming unit 120 fails to transform thepartial program 40 and the instructionsequence replacing unit 130 fails to replace the instruction sequence. - Four examples of a process in which the
compiler 10 is supplied with a program to be optimized and optimizes the program will be described successively. -
FIG. 5( a) shows thepattern 20 to be replaced in the first example. - The
pattern 20 is a pattern to be replaced for detection of an instruction sequence shown inFIG. 16 . In the instruction sequence shown inFIG. 16 , the destination of branching from a switch instruction (2) is variable among numbers from 2 to 256. It is, therefore, thought that there is a need to generate 255patterns 20 having the corresponding number of branchingdestinations 2 to 256 in order to suitably detect the switch instruction. However, it is inefficient to compare the large number ofpatterns 20 and partial programs because a long processing time is required for the comparison there between. - Then, the target partial
program detecting unit 110 detects partial programs to be optimized by using the illustratedpattern 20. Thispattern 20 has, with respect to a multiple-branch instruction (e.g., switch instruction (2)) to hand over control to an external instruction out of thepattern 20 in a case where one of multiple conditions is satisfied, a representative edge representative of multiple control flows through which control is handed over from the multiple-branch instruction to the external instruction. - The target partial
program detecting unit 110 determines that a partial program includes the corresponding multiple-branch instruction, if the dependence graph showing control flows of the partial program has an edge corresponding to the representative edge. That is, the target partialprogram detecting unit 110 determines that the multiple-branch instructions correspond to each other, on condition that the number of edges of the multiple-branch instruction of the partial program is larger than the number of edges of the multiple-branch instruction of thepattern 20. -
FIG. 5( b) shows a targetinstruction sequence template 30 in the first example. This figure shows a program source code indicating details of processing according to instructions included in the targetinstruction sequence template 30. In actuality, the targetinstruction sequence template 30 may be described by means of a predetermined intermediate code or a machine language. - In the target
instruction sequence template 30, a variable “bytearray” represents an address in a storage area in which a value with which comparison is made is stored by a TRT instruction. A variable “i” represents an index for scanning the storage area. The instructionsequence replacing unit 130 secures the storage area for storing a number of values equal to the value of the variable “bytearray”, and stores in a variable “table” the address stored in the storage area. For example, when the value of index i in the “bytearray” storage area satisfies a condition for termination of the loop, the value of index i in the “table” storage area is a non-zero value. -
FIG. 6 shows a first example of thepartial program 40 to be optimized by thecompiler 10. The program shown inFIG. 6( a) is a source program representing details of processing in accordance with thepartial program 40.FIG. 6( b) is a control flow graph of thepartial program 40. According to thepartial program 40, a storage area determined by a variable “data” is scanned in order and loop processing is terminated when a constant “GREATERTHAN” or a constant 0 is detected. When the constant 0 is detected, a return from a method call is made. - As is apparent from comparison between this figure and
FIG. 5( a), thepattern 20 and thepartial program 40 have different orders of processing according to instructions to read out the value from the storage area. More specifically, while the value is read out from the storage area by instruction (1) according to thepattern 20, the value is read out from the storage area by instruction (a) and instruction (e) according to thepartial program 40. According to the conventional art, correspondence in the form between programs can be determined without considering a difference in variable name for example, but correspondence in form between programs cannot be determined if the placement of instructions is changed. That is, thepartial program 40 shown in this figure cannot be detected as a program to be optimized. - In contrast, the
compiler 10 in this embodiment is capable of detecting correspondence between instruction (1) inFIG. 5( a) and the instruction (a) inFIG. 6( b) and correspondence between instruction (1) and the instruction (e) inFIG. 6( b). Thecompiler 10 is also capable of detecting correspondence between instruction (2) inFIG. 5( a) and the instruction (b) inFIG. 6( b) and correspondence between instruction (2) and the instruction (c) inFIG. 6( b). Further, thecompiler 10 is capable of detecting correspondence between instruction (3) inFIG. 5( a) and the instruction (d) inFIG. 6( b). - The instruction
sequence transforming unit 120 obtains a detection result showing that instruction (b) and instruction (c) are successively executed and that instructions (b) and (c) are transformable into instruction (2) inFIG. 5( a). The instructionsequence transforming unit 120 also obtains a detection result showing that thepattern 20 and thepartial program 40 have the same dependence of the variable ch. The instructionsequence transforming unit 120 further obtains a detection result showing that thepattern 20 and thepartial program 40 have the same dependence with respect to the index variable in the storage area. The instructionsequence transforming unit 120 further obtains a detection result showing that thepartial program 40 does not include an additional instruction in comparison with thepattern 20. If all the above-described conditions are satisfied, the instructionsequence replacing unit 130 replaces thepartial program 40 with the target instruction sequence based on thepattern 20. -
FIG. 7 shows the resultantpartial program 60 in the first example. The instructionsequence replacing unit 130 generates a storage area indicated by the variable “table” when a target instruction sequence is generated. For example, if the value of index i in the variable “data” storage area is GREATERTHAN or 0, the value of index i in the “table” storage area is an on-zero value. The instructionsequence replacing unit 130 initializes other values in the “table” storage area to 0. - As is apparent from this processing, the instruction
sequence replacing unit 130 can optimize the instruction sequence if determination as to whether or not the loop processing is terminated is made on the basis of the value of index i. Therefore, the target partialprogram detecting unit 110 may detect a partial program as thepartial program 40, on condition that determination as to whether or not the loop processing is terminated is made on the basis of the value of index i, even in a case where the partial program and thepattern 20 have different switch instruction references. For example, in a case where a partial program includes an instruction “switch” (map1 [ch]), the target partialprogram detecting unit 110 may detect the partial program as thepartial program 40, on condition that the array variable map1 corresponds to a constant array. - Processing in accordance with the resultant
partial program 60 will be described. According to a while instruction (3) and a TRT instruction (5) in the resultantpartial program 60, the computer scans on a 256 byte basis the storage area determined by the variable “data”. The TRT instruction (5) can be executed at an extremely high speed in comparison with the process in which loop processing is repeated 256 times. Therefore, the speed of scanning of the storage area determined by the variable “data” can be increased. For example, in a case where 0 or GREATERTHAN is stored within initial 256 bytes in the storage area, instructions (1) to (9) are executed in this order. Thus, loop processing is not executed and, therefore, the efficiency is markedly high. - According to the first example, as described above, the instruction
sequence replacing unit 130 can replace processing realized by two or more instructions such as a while instruction and a switch instruction with a TRT instruction which is one instruction for performing the same processing as that performed by multiple instructions. - As a modification of the first example, a case is conceivable in which the
pattern 20 includes a nullcheck instruction for determining whether or not the value of the variable “bytearray” is null. For example, the nullcheck instruction is ordinarily used immediately before execution of instruction (1) each time instruction (1) is executed. The nullcheck instruction is used for the purpose of preventing readout of the value from an invalid address by instruction (1). - The value of byte array is constant independently of repetition of the loop. Therefore the result of execution of the nullcheck instruction is the same independently of repetition of the loop. In such a case, the instruction
sequence transforming unit 120 executes the nullcheck instruction out of the loop processing and, therefore, the instructionsequence replacing unit 130 can replace the loop processing from which the nullcheck instruction has been removed with a target instruction sequence. -
FIG. 8 shows a second example of thepartial program 40 by thecompiler 10. The program shown inFIG. 8( a) is a source program representing details of processing in accordance with thepartial program 40 is shown.FIG. 8( b) is a control flow graph of thepartial program 40 is shown. According to thepartial program 40, the computer scans in order a storage area determined by a variable “bytes”, with respect to the index indicated by a variable “offset”. Loop processing is terminated when a negative value is detected. - In the
partial program 40, loop processing has two induction variables: the variable “offset” and a variable “count”. That is, thepartial program 40 and thepattern 20 shown inFIG. 5( a) apparently differ in program structure from each other. Therefore, the conventional compiler cannot recognize thepartial program 40 as a program to be optimized. - According to the
compiler 10 in this embodiment, the target partialprogram detecting unit 110 can detect a partial program as thepartial program 40 even if the partial program has an additional instruction in comparison with thepattern 20. More specifically, the target partialprogram detecting unit 10 can obtain a detection result showing that instruction (1) inFIG. 5( b) corresponds to instruction (a) inFIG. 8( b), a detection result showing that instruction (2) inFIG. 5( b) corresponds to instruction (b) inFIG. 8( b), and a detection result showing that instruction (3) inFIG. 5( b) corresponds to instruction (c) inFIG. 6( b). - In this case, the instruction
sequence transforming unit 120 generates new loop processing to execute an additional instruction. Consequently, the instructionsequence replacing unit 130 can replace instructions other than the additional instruction in the program to be optimized with a target instruction sequence. Thecompiler 10 may further optimize the newly generated loop processing. That is, thecompiler 10 can optimize the newly generated loop processing into processing for computing the value of the variable “count” from the value of the variable “offset”. -
FIG. 9 shows the resultantpartial program 60 in the second example. The instructionsequence replacing unit 130 generates a storage area indicated by the variable “table” when a target instruction sequence is generated. For example, if the value of index i in the variable “bytes” storage area is a negative value, the value of index i in the “table” storage area is an on-zero value. The instructionsequence replacing unit 130 initializes other values in the “table” storage area to 0. - Processing in accordance with the resultant
partial program 60 will be described. According to a while instruction (3) and a TRT instruction (5) in the resultantpartial program 60, the computer scans on a 256 byte basis the storage area determined by the variable “bytes”. The TRT instruction (5) can be executed at an extremely high speed in comparison with the process in which loop processing is repeated 256 times. Therefore, the speed of scanning of the storage area determined by the variable “bytes” can be increased. For example, in a case where a negative value is stored within initial 256 bytes in the storage area, instructions (1) to (9) are executed in this order. Thus, loop processing is not executed and, therefore, the efficiency is markedly high. -
FIG. 10 shows a third example of thepartial program 40 by thecompiler 10. This figure shows a source program representing details of processing in accordance with thepartial program 40. According to thepartial program 40, the computer scans in order a storage area determined by a variable “bytes” with respect to the index indicated by a variable “offset”. Loop processing is terminated when a negative value is detected. In this loop processing, a storage area determined by a variable “a” is initialized in order from the top. - In the
partial program 40, loop processing has two induction variables: the variable “offset” and a variable “count”. That is, thepartial program 40 and thepattern 20 shown inFIG. 5( a) apparently differ in program structure from each other. In this case, the conventional compiler cannot recognize thepartial program 40 as a program to be optimized. - According to the
compiler 10 in this embodiment, the target partialprogram detecting unit 110 can detect a partial program as thepartial program 40 even if the partial program has an additional instruction in comparison with thepattern 20. Accordingly, the instructionsequence transforming unit 120 divides the loop processing of thepartial program 40 into two loop processings in which the additional instruction and the instruction sequence other than the additional instruction are respectively executed. -
FIG. 11 shows the resultantpartial program 60 in the third example. The program shown inFIG. 11( a) is the resultantpartial program 60 including a target instruction sequence substituted by the instructionsequence replacing unit 130. A while instruction and a conditional branch instruction are replaced with a TRT instruction, as are those shown inFIG. 9 . The additional instruction to initialize the storage area determined by the variable “a” is executed in loop processings (2) and (3) newly generated. -
FIG. 11( b) shows the resultantpartial program 60 further optimized by thecompiler 10. As shown in this figure, thecompiler 10 may optimize the loop processing that initializes the storage area determined by the variable “a” into an XC instruction. According to the XC instruction, a storage area of a predetermined size can be initialized by a predetermined value. The XC instruction is executed at an extremely high speed in comparison with the processing that initializes in order a 256 byte storage area in a loop processing manner. Therefore, the program to be optimized can be optimized further effectively. - The XC instruction is capable of initializing a storage area of a size designated by a constant operand. For example, instruction (1) is an XC instruction for initializing a storage area of a constant size of 256 bytes. Further, according to the EXECUTE instruction in accordance with S/390 provided by IBM Corporation, a value designated by a constant operand can be changed during execution of a program (see pp. 7-108 of Non-Patent Document 4). Thus, the XC instruction is substantially capable of initializing a storage area of a size designated by a register. For example, instruction (3) in this figure represents an XC instruction such that a constant operand which designates the size of a storage area to be initialized is changed to the value of a variable T_inccount by the EXECUTE instruction.
-
FIG. 12 shows a fourth example of thepartial program 40 by thecompiler 10. The program shown inFIG. 12( a) is a source program representing details of processing in accordance with thepartial program 40.FIG. 12( b) is a control flow graph of thepartial program 40. According to thepartial program 40, the computer counts the number ofbits 1 in data stored in a variable “input” and stores the count value in a variable “output”. This program is not efficient since the processing time is increased in proportion to the number of bits in the variable “input”. -
FIG. 13 shows the resultantpartial program 60 in the fourth example. The instructionsequence replacing unit 130 replaces thepartial program 40 shown inFIG. 12 with the resultantpartial program 60 shown inFIG. 13 . According to the resultantpartial program 60, the computer can execute the number ofbits 1 in the variable “input” at a higher speed in comparison with thepartial program 40. In this way, the instructionsequence replacing unit 130 may perform not only processing for replacement with a particular instruction but also processing for replacing an algorithm. That is, the instructionsequence replacing unit 130 may replace an instruction sequence for processing based on an algorithm requiring a longer processing time with an instruction sequence for processing based on a different algorithm requiring a shorter processing time. -
FIG. 14 is a diagram for explaining the effect of this embodiment. Comparison between the speed of thepartial program 40 shown inFIG. 6 and the speed of the resultantpartial program 60 shown inFIG. 7 was made. The table inFIG. 14 shows the rate at which the speed of the resultantpartial program 60 is increased relative to that of thepartial program 40. While the increase rate with respect to 256 data items are shown in this figure, it has also been confirmed that the increase rate is further improved with respect to a number of data items exceeding 256. - It can be understood that, as shown in the figure, the efficiency of execution of the program can be improved by optimization in a case where eight or more data items on average are scanned. That is, for example, the
compiler 10 may select and optimize only loop processing highly probable to scan eight or more data items to improve the efficiency of execution of the entire program. -
FIG. 15 shows an example of a hardware configuration of acomputer 500 which functions as thecompiler 10. Thecomputer 500 has a CPU peripheral section having aCPU 1000, aRAM 1020 and agraphic controller 1075 connected to each other by ahost controller 1082, an input/output section having acommunication interface 1030, ahard disk drive 1040 and a CD-ROM drive 1060 connected to thehost controller 1082 by an input/output controller 1084, and a legacy input/output section having aBIOS 1010, aflexible disk drive 1050 and an input/output chip 1070 connected to the input/output controller 1084. - The
host controller 1082 connects theRAM 1020, and theCPU 1000 and thegraphic controller 1075, which access theRAM 1020 at a high transfer rate. TheCPU 1000 operates on the basis of programs stored in theBIOS 1010 and theRAM 1020, and controls each component. Thegraphic controller 1075 obtains image data generated, for example, by theCPU 1000 on a frame buffer provided in theRAM 1020, and displays the image data on adisplay device 1080. Alternatively, thegraphic controller 1075 may contain therein a frame buffer for storing image data generated by theCPU 1000 for example. - The input/
output controller 1084 connects thehost controller 1082, thecommunication interface 1030, which is an input/output device of a comparatively high speed, thehard disk drive 1040 and the CD-ROM drive 1060. Thecommunication interface 1030 performs communication with an external unit via a network. Thehard disk drive 1040 stores programs and data used by thecomputer 500. The CD-ROM drive 1060 reads a program or data from a CD-ROM 1095 and provides the read program or data to the input/output chip 1070 via theRAM 1020. - To the input/
output controller 1084, theBIOS 1010 and input/output devices of a comparatively low speed, i.e., theflexible disk drive 1050 and the input/output chip 1070 or the like are also connected. TheBIOS 1010 stores programs including a boot program executed by theCPU 1000 at the time of startup of thecomputer 500 and programs dependent on the hardware of thecomputer 500. Theflexible disk drive 1050 reads a program or data from aflexible disk 1090 and provides the read program or data to the input/output chip 1070 via theRAM 1020. The input/output chip 1070 connects theflexible disk 1090 and various input/output devices, for example, through a parallel port, a serial port, a keyboard port, a mouse port, etc. - A program provided to the
computer 500 is provided by a user in a state of being stored on a recording medium, such as theflexible disk 1090, the CD-ROM 1095, or an IC card. The program is read out from the recording medium, installed in thecomputer 500 via the input/output chip 1070 and/or the input/output controller 1084, and executed in thecomputer 500. Operations which thecomputer 500 is made by the this program, e.g., the compiler program to perform are the same as the operations in thecomputer 500 described above with reference toFIGS. 1 to 14 . Therefore, description of the operations will not be repeated. - The above-described program may be stored on an external storage medium. As the recording medium, an optical recording medium such as a DVD or a PD, a magneto-optic recording medium such as an MD, a tape medium, a semiconductor memory such as an IC card, or the like can be used as well the
flexible disk 1090 and the CD-ROM 1095. Also, a storage device such as a hard disk, a RAM or the like provided in a server system connected to a special-purpose communication network or the Internet may be used as the recording medium to provide the program to thecomputer 500 via the network. - While the present invention has been described with respect to the embodiment thereof, the technical scope of the present invention is not limited to the scope described above with respect to the embodiment. It is apparent to those skilled in the art that various changes and medications can be made in the above-described embodiment. It is apparent from the description in the appended claims that other embodiments of the invention provided by making such changes and modifications are also included in the technical scope of the present invention.
- Variations described for the present invention can be realized in any combination desirable for each particular application. Thus particular limitations, and/or embodiment enhancements described herein, which may have particular advantages to a particular application need not be used for all applications. Also, not all limitations need be implemented in methods, systems and/or apparatus including one or more concepts of the present invention.
- The present invention can be realized in hardware, software, or a combination of hardware and software. A visualization tool according to the present invention can be realized in a centralized fashion in one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system—or other apparatus adapted for carrying out the methods and/or functions described herein—is suitable. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which—when loaded in a computer system—is able to carry out these methods.
- Computer program means or computer program in the present context include any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after conversion to another language, code or notation, and/or reproduction in a different material form.
- Thus the invention includes an article of manufacture which comprises a computer usable medium having computer readable program code means embodied therein for causing a function described above. The computer readable program code means in the article of manufacture comprises computer readable program code means for causing a computer to effect the steps of a method of this invention. Similarly, the present invention may be implemented as a computer program product comprising a computer usable medium having computer readable program code means embodied therein for causing a function described above. The computer readable program code means in the computer program product comprising computer readable program code means for causing a computer to effect one or more functions of this invention. Furthermore, the present invention may be implemented as a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for causing one or more functions of this invention.
- It is noted that the foregoing has outlined some of the more pertinent objects and embodiments of the present invention. This invention may be used for many applications. Thus, although the description is made for particular arrangements and methods, the intent and concept of the invention is suitable and applicable to other arrangements and applications. It will be clear to those skilled in the art that modifications to the disclosed embodiments can be effected without departing from the spirit and scope of the invention. The described embodiments ought to be construed to be merely illustrative of some of the more prominent features and applications of the invention. Other beneficial results can be realized by applying the disclosed invention in a different manner or modifying the invention in ways known to those familiar with the art.
Claims (25)
1) An optimizing compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the pattern to be replaced, comprising:
a target partial program detecting unit for detecting, from among a partial programs of said program to be optimized, a partial program including instructions corresponding to all instructions included in said pattern to be replaced as a partial program to be optimized;
an instruction sequence transforming unit for transforming, in said partial program to be optimized, instructions other than those instructions corresponding to instructions included in said pattern to be replaced and those instructions having execution dependencies different from said pattern to be replaced, so that dependencies between instructions included in said partial program to be optimized match said pattern to be replaced; and
an instruction sequence replacing unit for replacing said partial program to be optimized transformed by said instruction sequence transforming unit with a target instruction sequence determined in accordance with said pattern to be replaced.
2) The compiler according to claim 1 , wherein said target partial program detecting unit detects each of the partial programs as the partial program to be optimized, if the instructions in the partial program corresponding to all the instructions included in said pattern to be replaced are executed in the order designated by the execution dependencies between the instructions in said pattern to be replaced.
3) The compiler according to claim 2 , wherein in a case where said pattern to be replaced includes loop processing, said target partial program detecting unit detects each of the partial programs as the partial program to be optimized, if the partial program includes in loop processing the instructions corresponding to all the instructions included in said loop processing, and if all the instructions out of the loop processing in the partial program conform to the dependencies determined by said pattern to be replaced.
4) The compiler according to claim 1 , wherein said pattern to be replaced is a dependence graph having as a node each of multiple instructions included in the said pattern to be replaced and having directed edges representing the execution dependencies between multiple instructions, and
wherein said target partial program detecting unit generates, with respect to each of the partial programs, a dependence graph having as a node each of multiple instructions included in the partial program and having directed edges representing the execution dependencies between multiple instructions, and makes a determination on the basis of the dependence graph and a dependence graph representing said pattern to be replaced as to whether or not the partial program should be detected as the partial program to be optimized.
5) The compiler according to claim 4 , wherein said pattern to be replaced indicate control flows between the instructions,
wherein the dependence graph of said pattern to be replaced has, with respect to a multiple-branch instruction to hand over control to an external instruction out of said pattern to be replaced in a case where one of multiple conditions is satisfied, a representative edge representative of multiple control flows through which control is handed over from the multiple-branch instruction to the external instruction, and
wherein said target partial program detecting unit determines, with respect to each of multiple partial programs, that the partial program includes the corresponding multiple-branch instruction, if the dependence graph showing control flows of the partial program has an edge corresponding to the representative edge.
6) The compiler according to claim 1 , further comprising an optimization candidate detecting unit which detects, in the program to be optimized, as a candidate for the partial program to be optimized, the partial program including a memory access instruction to access the same type of data as data to be accessed according to a memory access instruction included in said pattern to be replaced,
wherein said target partial program detecting unit detects the partial program to be optimized in the partial programs detected by said optimization candidate detecting unit.
7) The compiler according to claim 1 , further comprising an optimization candidate detecting unit which detects, in the program to be optimized, as a candidate for the partial program to be optimized, the partial program including loop processing having the same increment in a loop induction variable as that in loop processing included in said pattern to be replaced,
wherein said target partial program detecting unit detects the partial program to be optimized in the partial programs detected by said optimization candidate detecting unit.
8) The compiler according to claim 1 , further comprising an
optimization candidate detecting unit which detects, in the program to be optimized, as a candidate for the partial program to be optimized, the partial program including loop processing repeatedly performed a number of times equal to or larger than a predetermined reference number of times,
wherein said target partial program detecting unit detects the partial program to be optimized in the partial programs detected by said optimization candidate detecting unit.
9) The compiler according to claim 1 , wherein said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including in loop processing an additional instruction which does not correspond to any of the instructions included in said pattern to be replaced,
wherein said instruction sequence transforming unit executes the additional instruction out of the loop processing of the partial program to be optimized, on condition that the result of execution of the additional instruction included in the loop processing is constant independently of repetition of the loop processing, and
wherein said instruction sequence replacing unit replaces the loop processing from which the additional instruction has been removed with the target instruction sequence.
10) The compiler according to claim 1 , wherein said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including in loop processing an additional instruction which does not correspond to any of the instructions included in said pattern to be replaced,
wherein said instruction sequence transforming unit divides the loop processing of the partial program to be optimized into two loop processes in which the additional instruction and the instruction sequence other than the additional instruction are respectively executed, and
wherein said instruction sequence replacing unit replaces the instruction sequence other than the additional instruction with the target instruction sequence.
11) The compiler according to claim 1 , wherein said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including an instruction sequence executed in an order different from that of the execution dependencies in said pattern to be replaced,
wherein said instruction sequence transforming unit changes, on the basis of the execution dependencies, the order of execution of the instruction in the partial program to be optimized, on condition that the result of processing of the partial program to be optimized is not changed even if the order of execution of the instructions in the partial program to be optimized is changed, and
wherein said instruction sequence replacing unit replaces the partial program to be optimized in which the instruction execution order has been changed with the target instruction sequence.
12) The compiler according to claim 1 , wherein if one of the partial programs lacks some of the instructions included in said pattern to be replaced, said target partial program detecting unit detects the partial program as the partial program to be optimized, on condition that the proportion of the instructions in the partial program corresponding to the other instructions included in said pattern to be replaced in all the instructions included in said pattern to be replaced is equal to or higher than a predetermined reference proportion.
13) The compiler according to claim 12 , wherein said instruction sequence transforming unit adds to the partial program to be optimized the absent instruction absent in the instructions in the partial program to be optimized corresponding to all the instructions included in said pattern to be replaced, generates a cancel instruction to return the result of processing of the program to be optimized changed by the addition of the absent instruction to the processing result obtained in the case where the absent instruction is not added, and executes the cancel instruction out of the partial program to be optimized, and
wherein said instruction sequence replacing unit replaces the partial program to be optimized including the added instruction that has been absent with the target instruction sequence.
14) The compiler according to claim 13 , wherein said instruction sequence transforming unit generates as the cancel instruction a save instruction to save, before the absent instruction, the value in a storage area in which the result of processing according to the absent instruction is stored, and a recovery instruction to recover the value saved in the storage area after execution of the absent instruction, and executes the save instruction and the recovery instruction out of the partial program to be optimized.
15) The compiler according to claim 12 , wherein said target partial program detecting unit detects each of the partial programs as the partial program to be optimized, if the processing time increased in a case where the instruction absent in the partial program in comparison with said pattern to be replaced is added to the partial program is shorter than the reduced processing time in a case where the partial program is replaced with the target instruction sequence by said instruction sequence transforming unit.
16) The compiler according to claim 1 , wherein said instruction sequence replacing unit comprises a limitation selected from a group of limitations consisting of:
said instruction sequence replacing unit generates the target instruction sequence by replacing each of variables in the target instruction template showing the structure of the target instruction with a variable in the partial program to be optimized corresponding to the variable in the target instruction template;
said instruction sequence replacing unit replaces two or more of the instructions of the partial program to be optimized with one instruction for performing the same processing as that according to the two or more instructions;
said instruction sequence replacing unit replaces an instruction sequence for processing based on an algorithm requiring a longer processing time with an instruction sequence for processing based on a different algorithm requiring a shorter processing time; and
any combination of these limitations.
17) A computer program product comprising a computer usable medium having computer readable program code means embodied therein for causing functions of an optimizing compiler, the computer readable program code means in said computer program product comprising computer readable program code means for causing a computer to effect the functions of claim 1 .
18) An optimization method for optimizing a program to be optimized detecting, from a program to be optimized, a pattern that is to be replaced and includes multiple predetermined instructions and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with said instruction sequence to be replaced, comprising:
a target partial program detecting step of detecting a partial program as said target partial program to be optimized if it is determined that instructions in said partial program that correspond to all instructions included in said pattern to be replaced are executed in an execution order indicated by execution dependencies between instructions in said pattern to be replaced; and
an instruction sequence replacing step of replacing said partial program to be optimized with a target instruction sequence determined in accordance with said pattern to be replaced.
19) A compiler detecting, from a program to be optimized, a pattern that is to be replaced and includes multiple predetermined instructions and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with said pattern to be replaced, comprising:
a target partial program detecting unit for detecting a partial program as said target partial program to be optimized if it is determined that instructions in said partial program that correspond to all instructions included in said pattern to be replaced are executed in an execution order indicated by execution dependencies between instructions in said pattern to be replaced; and
an instruction sequence replacing unit for replacing said partial program to be optimized with a target instruction sequence determined in accordance with said pattern to be replaced.
20) The compiler according to claim 19 , wherein in a case where said pattern to be replaced determines dependencies recurring among the instructions, said target partial program detecting unit detects, as the partial program to be optimized, one of the partial programs including an instruction sequence having the same dependencies as those determined by said pattern to be replaced but differing in recurrence phase, and
wherein said instruction sequence replacing unit replaces the partial program to be optimized with the target instruction sequence.
21) An optimization method for detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, comprising:
a target partial program detecting step of detecting, from among a partial programs of said program to be optimized, a partial program including instructions corresponding to all instructions included in said pattern to be replaced as a partial program to be optimized;
an instruction sequence transforming step of transforming, in said partial program to be optimized, instructions other than those instructions corresponding to instructions included in said pattern to be replaced and those instructions having execution dependencies different from said pattern to be replaced, so that dependencies between instructions included in said partial program to be optimized match said pattern to be replaced;
an instruction replacing step of replacing said partial program to be optimized transformed by said instruction sequence transforming unit with a target instruction sequence determined in accordance with said pattern to be replaced.
22) An article of manufacture comprising a computer usable medium having computer readable program code means embodied therein for causing detection by a compiler, the computer readable program code means in said article of manufacture comprising computer readable program code means for causing a computer to effect the steps of claim 19 .
23) A compiler program for causing a computer to function as a compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, said compiler program causing said computer as:
a target partial program detecting unit for detecting, from among a partial programs of said program to be optimized, a partial program including instructions corresponding to all instructions included in said pattern to be replaced as a partial program to be optimized;
an instruction sequence transforming unit for transforming, in said partial program to be optimized, instructions other than those instructions corresponding to instructions included in said pattern to be replaced and those instructions having execution dependencies different from said pattern to be replaced, so that dependencies between instructions included in said partial program to be optimized match said pattern to be replaced;
an instruction sequence replacing unit for replacing said partial program to be optimized transformed by said instruction sequence transforming unit with a target instruction sequence determined in accordance with said pattern to be replaced.
24) A compiler program for causing a computer to function as a compiler detecting a pattern that is to be replaced and includes multiple predetermined instructions in a program to be optimized and replacing the detected pattern to be replaced with a target instruction sequence determined in accordance with the instruction sequence to be replaced, said compiler program causing said computer as:
a target partial program detecting unit for detecting a partial program as said target partial program to be optimized if it is determined that instructions in said partial program that correspond to all instructions included in said pattern to be replaced are executed in an execution order indicated by execution dependencies between instructions in said pattern to be replaced; and
an instruction sequence replacing unit for replacing said partial program to be optimized with a target instruction sequence determined in accordance with said pattern to be replaced.
25) A recording medium on which the compiler program according to claim 23 is recorded.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004154794A JP4178278B2 (en) | 2004-05-25 | 2004-05-25 | Compiler device, optimization method, compiler program, and recording medium |
JP2004-154794 | 2004-05-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
US20090007086A1 true US20090007086A1 (en) | 2009-01-01 |
Family
ID=35426897
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/133,897 Expired - Fee Related US7707568B2 (en) | 2004-05-25 | 2005-05-20 | Compiler optimization |
US12/167,421 Abandoned US20090007086A1 (en) | 2004-05-25 | 2008-07-03 | Compiler Optimization |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/133,897 Expired - Fee Related US7707568B2 (en) | 2004-05-25 | 2005-05-20 | Compiler optimization |
Country Status (2)
Country | Link |
---|---|
US (2) | US7707568B2 (en) |
JP (1) | JP4178278B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060200811A1 (en) * | 2005-03-07 | 2006-09-07 | Cheng Stephen M | Method of generating optimised stack code |
US20080091926A1 (en) * | 2006-10-11 | 2008-04-17 | Motohiro Kawahito | Optimization of a target program |
US20110214110A1 (en) * | 2010-02-26 | 2011-09-01 | Red Hat, Inc. | Compiler Mechanism for Handling Conditional Statements |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008059279A (en) * | 2006-08-31 | 2008-03-13 | Internatl Business Mach Corp <Ibm> | Technique for optimizing character string output processing |
US8656381B2 (en) * | 2006-12-07 | 2014-02-18 | International Business Machines Corporation | Presenting machine instructions in a machine-independent tree form suitable for post-link optimizations |
US7430733B1 (en) * | 2007-11-15 | 2008-09-30 | International Business Machines Corporation | Method for validation of binary code transformations |
JP2009205264A (en) * | 2008-02-26 | 2009-09-10 | Nippon Telegr & Teleph Corp <Ntt> | Web service request processing apparatus, web service request processing method, and web service request processing system |
FR2960988B1 (en) * | 2010-06-03 | 2013-03-15 | Invia | METHOD OF COMPRESSION AND DECOMPRESSION OF AN EXECUTABLE OR INTERPRETABLE PROGRAM |
GB2514618B (en) * | 2013-05-31 | 2020-11-11 | Advanced Risc Mach Ltd | Data processing systems |
GB2521367A (en) * | 2013-12-17 | 2015-06-24 | Ibm | Adaptable and extensible runtime and system for heterogeneous computer systems |
CN107003861B (en) * | 2014-08-29 | 2020-07-24 | 华为技术有限公司 | Method for compiling source code |
JP6547477B2 (en) * | 2015-07-15 | 2019-07-24 | 富士通株式会社 | Source code optimization apparatus, source code optimization program and object code generation method |
US10776087B2 (en) * | 2018-06-25 | 2020-09-15 | Intel Corporation | Sequence optimizations in a high-performance computing environment |
US10970073B2 (en) * | 2018-10-02 | 2021-04-06 | International Business Machines Corporation | Branch optimization during loading |
US11379200B2 (en) * | 2020-01-30 | 2022-07-05 | Oracle International Corporation | Method for applying graph-specific compiler optimizations to graph analysis programs |
CN112947999B (en) * | 2021-03-10 | 2022-06-28 | 超睿科技(上海)有限公司 | Method and device for expanding instruction function of reduced instruction set computer |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5828886A (en) * | 1994-02-23 | 1998-10-27 | Fujitsu Limited | Compiling apparatus and method for promoting an optimization effect of a program |
US6349384B1 (en) * | 1999-01-23 | 2002-02-19 | International Business Machines Corporation | System, apparatus and method for processing instructions |
US20020120923A1 (en) * | 1999-12-30 | 2002-08-29 | Granston Elana D. | Method for software pipelining of irregular conditional control loops |
US20020147969A1 (en) * | 1998-10-21 | 2002-10-10 | Richard A. Lethin | Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method |
US6546550B1 (en) * | 1999-01-28 | 2003-04-08 | International Business Machines Corporation | Method to determine dynamic compilation time and to select bytecode execution mode |
US20050108695A1 (en) * | 2003-11-14 | 2005-05-19 | Long Li | Apparatus and method for an automatic thread-partition compiler |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0721032A (en) | 1993-07-01 | 1995-01-24 | Mitsubishi Electric Corp | Program optimization processing system |
US6343375B1 (en) * | 1998-04-24 | 2002-01-29 | International Business Machines Corporation | Method for optimizing array bounds checks in programs |
JP2000284970A (en) | 1999-03-29 | 2000-10-13 | Matsushita Electric Ind Co Ltd | Program converting device and processor |
US6507947B1 (en) * | 1999-08-20 | 2003-01-14 | Hewlett-Packard Company | Programmatic synthesis of processor element arrays |
US7386839B1 (en) * | 2002-11-06 | 2008-06-10 | Valery Golender | System and method for troubleshooting software configuration problems using application tracing |
-
2004
- 2004-05-25 JP JP2004154794A patent/JP4178278B2/en not_active Expired - Fee Related
-
2005
- 2005-05-20 US US11/133,897 patent/US7707568B2/en not_active Expired - Fee Related
-
2008
- 2008-07-03 US US12/167,421 patent/US20090007086A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5828886A (en) * | 1994-02-23 | 1998-10-27 | Fujitsu Limited | Compiling apparatus and method for promoting an optimization effect of a program |
US20020147969A1 (en) * | 1998-10-21 | 2002-10-10 | Richard A. Lethin | Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method |
US6349384B1 (en) * | 1999-01-23 | 2002-02-19 | International Business Machines Corporation | System, apparatus and method for processing instructions |
US6546550B1 (en) * | 1999-01-28 | 2003-04-08 | International Business Machines Corporation | Method to determine dynamic compilation time and to select bytecode execution mode |
US20020120923A1 (en) * | 1999-12-30 | 2002-08-29 | Granston Elana D. | Method for software pipelining of irregular conditional control loops |
US20050108695A1 (en) * | 2003-11-14 | 2005-05-19 | Long Li | Apparatus and method for an automatic thread-partition compiler |
Non-Patent Citations (4)
Title |
---|
Cooper, K. D. and McIntosh, N., Enhanced Code Compression for Embedded RISC Processors, PLDI'99 (1999) * |
Hoover, R., Zadeck, K., Generating Machine Specific Optimizing Compilers, ACM (1996). * |
J.W. Davidson and D.B. Whalley, Quick Compilers Using Peephole Optimization, Software Practice and Experience, Vol. 19, No. 1 (Jan. 1989). * |
Kennedy, K. and McKinley, K. S., Maximizing Loop Parallelism and Improving Data Locality via Loop Fusion and Distribution (1993). * |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060200811A1 (en) * | 2005-03-07 | 2006-09-07 | Cheng Stephen M | Method of generating optimised stack code |
US20080091926A1 (en) * | 2006-10-11 | 2008-04-17 | Motohiro Kawahito | Optimization of a target program |
US8296750B2 (en) | 2006-10-11 | 2012-10-23 | International Business Machines Corporation | Optimization of a target program |
US20110214110A1 (en) * | 2010-02-26 | 2011-09-01 | Red Hat, Inc. | Compiler Mechanism for Handling Conditional Statements |
US9134977B2 (en) * | 2010-02-26 | 2015-09-15 | Red Hat, Inc. | Compiler operation for handling conditional statements |
Also Published As
Publication number | Publication date |
---|---|
US20050268293A1 (en) | 2005-12-01 |
JP2005339021A (en) | 2005-12-08 |
JP4178278B2 (en) | 2008-11-12 |
US7707568B2 (en) | 2010-04-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7707568B2 (en) | Compiler optimization | |
US8104026B2 (en) | Compiler register allocation and compilation | |
US6983458B1 (en) | System for optimizing data type definition in program language processing, method and computer readable recording medium therefor | |
US20050166195A1 (en) | Compiler, compilation and storage | |
US20070038987A1 (en) | Preprocessor to improve the performance of message-passing-based parallel programs on virtualized multi-core processors | |
US8291398B2 (en) | Compiler for optimizing program | |
WO2000042518A9 (en) | Parallelizing applications of script-driven tools | |
US9256437B2 (en) | Code generation method, and information processing apparatus | |
US11016778B2 (en) | Method for vectorizing Heapsort using horizontal aggregation SIMD instructions | |
US8296750B2 (en) | Optimization of a target program | |
US8117604B2 (en) | Architecture cloning for power PC processors | |
US8037464B2 (en) | Generating optimized SIMD code in the presence of data dependences | |
US5889995A (en) | Using constant selectors for method identification | |
US7523448B2 (en) | Optimizing compiler | |
US20080184213A1 (en) | Compiler device, method, program and recording medium | |
US7526761B2 (en) | Exception handling compiler apparatus, program, recording medium, and compiling method | |
US6077314A (en) | Method of, system for, and computer program product for providing improved code motion and code redundancy removal using extended global value numbering | |
US6035124A (en) | Method of, system for, and computer program product for providing extended global value numbering | |
US6163882A (en) | Language processing apparatus for converting source program into object program | |
US6944852B2 (en) | Compiler | |
US20090119632A1 (en) | Method for supporting determination of design process order | |
US11144288B1 (en) | System and method for compiling rules set into bytecode using switch and class hierarchies | |
US20030171873A1 (en) | Method and apparatus for grouping proteomic and genomic samples | |
Wolfe | New program restructuring technology | |
CN117493169A (en) | Method, device, equipment and medium for detecting API (application program interface) behavior incompatibility among Java dependency library versions |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWAHITO, MOTOHIRO;KOMATSU, HIDEAKI;REEL/FRAME:021467/0448;SIGNING DATES FROM 20050606 TO 20050616 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |