US20090020763A1 - Poly silicon layer and structure for forming the same - Google Patents

Poly silicon layer and structure for forming the same Download PDF

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Publication number
US20090020763A1
US20090020763A1 US12/242,876 US24287608A US2009020763A1 US 20090020763 A1 US20090020763 A1 US 20090020763A1 US 24287608 A US24287608 A US 24287608A US 2009020763 A1 US2009020763 A1 US 2009020763A1
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Prior art keywords
silicon layer
layer
amorphous silicon
poly silicon
patterned metal
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US12/242,876
Inventor
Chiung-Wei Lin
Sheng-Chi Lee
Yi-Liang Chen
Rui-Cheng Huang
Te-Hua Teng
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Chunghwa Picture Tubes Ltd
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Chunghwa Picture Tubes Ltd
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Priority to US12/242,876 priority Critical patent/US20090020763A1/en
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Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters

Definitions

  • the present invention generally relates to a film and a structure for forming the same, and more particularly, to a polysilicon layer and a structure for forming the same.
  • a display serves as a communication interface for human to acquire information from a device
  • the flat panel display is the current trend in the display market.
  • the FPD can be classified into various types including an organic electro-luminescence display (OLED), a plasma display panel (PDP), a liquid crystal display (LCD), a light emitting diode (LED) and so on.
  • OLED organic electro-luminescence display
  • PDP plasma display panel
  • LCD liquid crystal display
  • LED light emitting diode
  • the above-mentioned display usually employs the thin film transistor (TFT) as the switch of the display.
  • TFT thin film transistor
  • the TFT may be classified into mainly two types including an amorphous silicon TFT and a low-temperature poly silicon thin film transistor (LTPS TFT).
  • LTPS TFT low-temperature poly silicon thin film transistor
  • the poly silicon layer serving as the channel layer of the LTPS TFT may be fabricated by the following methods.
  • MILC Metal induced lateral crystallization
  • Rapid energy transfer annealing (RETA) process the disadvantage of this method lies in that the process adopts a wafer as a heating plate, and therefore this method may not be applied to the large-sized substrate.
  • the present invention is also directed to a polysilicon layer having comparatively larger grains size.
  • the present invention is directed to a method of fabricating a polysilicon layer comprising the following steps. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing (PRTA) process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, and the patterned metal layer and the metal silicide are adapted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed.
  • PRTA pulsed rapid thermal annealing
  • a material of the patterned metal layer comprises nickel, cobalt, copper, tantalum, iron or platinum.
  • an operation temperature of the pulsed rapid thermal annealing process is between 550° C. and 900° C.
  • the present invention also provides a polysilicon layer formed according to the above-mentioned fabrication method.
  • the grains of the poly silicon layer are spherical in shape.
  • the grain size is larger than 4000 angstrom.
  • the surface roughness of the poly silicon layer is smaller than 10 angstrom.
  • the present invention employs the pulsed rapid thermal annealing process for forming the metal silicide and the patterned metal layer and the amorphous silicon layer may conduct thermal energy to the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer.
  • the fabrication method provided by present invention may manufacture poly silicon layers with comparatively larger gain size.
  • FIGS. 1A to 1F are schematic, cross-sectional diagrams illustrating the process flow for fabricating a poly silicon layer according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing a heating curve of the PRTA process according to an embodiment of the present invention.
  • FIG. 3 is a spectrum diagram of the poly silicon layer measured by an energy dispersive X-ray spectrometer.
  • FIGS. 1A to 1F are schematic cross-sectional diagrams illustrating the process flow for fabricating a poly silicon layer according to an embodiment of the present invention.
  • the method of fabricating a polysilicon layer according to an embodiment of the present invention comprises the following steps. First, a substrate 110 is provided, and the substrate 110 may be a glass substrate or a quartz substrate. Next, an amorphous silicon layer 120 is formed on the substrate 110 .
  • the amorphous silicon layer 120 may be formed using, for example, a chemical vapor deposition (CVD) process or a plasma enhanced CVD (PECVD) process.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced CVD
  • a metal layer 130 is formed on the amorphous silicon layer 120 , and the metal layer 130 may be comprised of nickel, cobalt, copper, tantalum, iron, platinum or any other metallic material and may be formed by using, for example, a sputtering process.
  • a portion of the metal layer 130 is removed to form a patterned metal layer 132 .
  • a portion of the metal layer 130 may be removed by using, for example, a photolithography process and an etching process.
  • a PRTA process is performed to form a metal silicide 140 between the patterned metal layer 132 and the amorphous silicon layer 120 .
  • the patterned metal layer 132 and the metal silicide 140 conduct thermal energy to the amorphous silicon layer 120 such that the amorphous silicon layer 120 is transformed into a polysilicon layer 150 as shown in FIG. 1E .
  • FIG. 2 is a diagram showing a heating curve of the PRTA process according to an embodiment of the present invention.
  • the horizontal coordinate represents time, wherein a unit of time is one second
  • the vertical coordinate represents temperature, wherein centigrade represents the units used for the degrees of temperature.
  • the operation temperature of the PRTA process is between 550° C. and 900° C.
  • the high temperature (900° C.) lasts for 5 seconds
  • the slope for heating is 70° C./second
  • the slope for cooling is 35° C./second.
  • a seed metal silicide 140 serving as crystal seed may be formed in advance.
  • infra red energy generated from the PRTA process is converted to heat by the metal silicide 140 and the patterned metal layer 132 , and then heat is conducted to the amorphous silicon layer 120 to make it crystallize.
  • the mechanism of re-crystallization is a kind of SPC-like method.
  • the patterned metal layer 132 is removed, and the patterned metal layer 132 may be removed by an etching process.
  • the method of fabricating the polysilicon layer 150 according to an embodiment of the present invention is complete.
  • the conventional MILC process utilizes the lateral migration of the metal silicide to induce the amorphous silicon layer to re-crystallize, and therefore the lateral crystallization region (a region which is not covered by the patterned metal layer 132 shown in FIG. 1D ) may have metal contamination.
  • the poly silicon layer is analyzed by an energy dispersive X-ray spectrometer (EDS), and the result is shown as follows.
  • FIG. 3 is a spectrum diagram of the poly silicon layer measured by an energy dispersive X-ray spectrometer.
  • the horizontal coordinate represents energy, wherein a unit of energy is one kiloelectron volt (KeV), and the vertical coordinate represents counts per second (cps).
  • the metal silicide of the present invention may not migrate laterally, and therefore the signal of nickel within the lateral crystallization region is not obvious (such as the dotted line region in FIG. 3 ). In other words, the lateral crystallization region has negligible amount of nickel.
  • the grains of the poly silicon layer formed by the conventional ELA process are arborization.
  • the grains of the poly silicon layer 150 formed according to the above-mentioned processes are substantially spherical in shape. Since the metal silicide makes the generation of a portion of the nucleation sites earlier, therefore the nucleation density is significantly reduced and the polysilicon layer 150 has larger grains size.
  • the size of the grains of the polysilicon layer formed according to the above-mentioned processes may be larger than 4000 angstrom.
  • the surface roughness of the poly silicon layer formed by the conventional ELA process is between dozens to hundreds of nanometers, but the surface roughness of the polysilicon layer formed by the above-mentioned process may be smaller than 10 angstrom.
  • the present invention has at least the following advantages.
  • the present invention is faster (less than 2 minutes).
  • the present invention employs the PRTA process, and accordingly it is suitable for forming a polysilicon layer on every kind of substrate.
  • the equipment required by the present invention is cheaper and the processing time thereof is faster (less than 2 minutes). Additionally, the planarity of the polysilicon layer formed according to the present invention is better, which is less than 10 angstrom.
  • the metal contamination of the present invention may not migrate laterally, and therefore the metal contamination may be effectively avoided.

Abstract

A method of fabricating a poly silicon layer comprising the following steps is provided. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, wherein the patterned metal layer and the amorphous silicon layer are adopted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed. A polysilicon layer formed according to the above-mentioned fabrication method is also provided. The grains of the poly silicon layer are spherical in shape.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional of an application Ser. No. 11/308,961, filed on May 30, 2006. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a film and a structure for forming the same, and more particularly, to a polysilicon layer and a structure for forming the same.
  • 2. Description of Related Art
  • A display serves as a communication interface for human to acquire information from a device, and the flat panel display (FPD) is the current trend in the display market. The FPD can be classified into various types including an organic electro-luminescence display (OLED), a plasma display panel (PDP), a liquid crystal display (LCD), a light emitting diode (LED) and so on.
  • The above-mentioned display usually employs the thin film transistor (TFT) as the switch of the display. Generally speaking, the TFT may be classified into mainly two types including an amorphous silicon TFT and a low-temperature poly silicon thin film transistor (LTPS TFT). Compared with the conventional amorphous silicon TFT, since the electron mobility of the LTPS TFT may exceed 200 cm2/V-sec, the area of the LTPS TFT is smaller to meet the requirement of high aperture ratio.
  • The poly silicon layer serving as the channel layer of the LTPS TFT may be fabricated by the following methods.
  • 1. Furnace annealing (FA) process combining with solid phase crystallization (SPC)-the disadvantage of this method lies in that the operation temperature is too high (more than 600° C.) and the required time for the thermal process is too long (more than 15 hours). Besides, when using a glass substrate, the glass substrate is likely to become deformed due to the high temperature.
  • 2. Excimer laser crystallization (ELA) process-the disadvantage of this method lies in that the equipment is more expensive, the processing time is longer and the surface roughness of the poly silicon layer is poor.
  • 3. Metal induced lateral crystallization (MILC) process-the disadvantage of this method lies in that the poly silicon film has metal contamination. Besides, since the individual grain size is too small, the size of the grain can only be represented by the range value.
  • 4. Rapid energy transfer annealing (RETA) process-the disadvantage of this method lies in that the process adopts a wafer as a heating plate, and therefore this method may not be applied to the large-sized substrate.
    • SUMMARY OF THE INVENTION
  • The present invention is also directed to a polysilicon layer having comparatively larger grains size.
  • As embodied and broadly described herein, the present invention is directed to a method of fabricating a polysilicon layer comprising the following steps. First, a substrate is provided and an amorphous silicon layer is formed on the substrate. A patterned metal layer is formed on the amorphous silicon layer. Next, a pulsed rapid thermal annealing (PRTA) process is performed to form a metal silicide between the patterned metal layer and the amorphous silicon layer, and the patterned metal layer and the metal silicide are adapted for conducting thermal energy to the amorphous silicon layer such that the amorphous silicon layer is converted into a polysilicon layer. Finally, the patterned metal layer is removed.
  • According to an embodiment of the present invention, a material of the patterned metal layer comprises nickel, cobalt, copper, tantalum, iron or platinum.
  • According to an embodiment of the present invention, an operation temperature of the pulsed rapid thermal annealing process is between 550° C. and 900° C.
  • As embodied and broadly described herein, the present invention also provides a polysilicon layer formed according to the above-mentioned fabrication method. The grains of the poly silicon layer are spherical in shape.
  • According to an embodiment of the present invention, the grain size is larger than 4000 angstrom.
  • According to an embodiment of the present invention, the surface roughness of the poly silicon layer is smaller than 10 angstrom.
  • In accordance with the foregoing descriptions, the present invention employs the pulsed rapid thermal annealing process for forming the metal silicide and the patterned metal layer and the amorphous silicon layer may conduct thermal energy to the amorphous silicon layer to transform the amorphous silicon layer into a polysilicon layer. Compared with the conventional MILC, since the metal silicide of the present invention is not likely to laterally migrate, the occurrence of the metal contamination may be effectively reduced. In addition, compared with the conventional ELA process, the fabrication method provided by present invention may manufacture poly silicon layers with comparatively larger gain size.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIGS. 1A to 1F are schematic, cross-sectional diagrams illustrating the process flow for fabricating a poly silicon layer according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing a heating curve of the PRTA process according to an embodiment of the present invention.
  • FIG. 3 is a spectrum diagram of the poly silicon layer measured by an energy dispersive X-ray spectrometer.
    •  DESCRIPTION OF THE EMBODIMENTS
  • Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
  • FIGS. 1A to 1F are schematic cross-sectional diagrams illustrating the process flow for fabricating a poly silicon layer according to an embodiment of the present invention. Referring to FIG. 1A, the method of fabricating a polysilicon layer according to an embodiment of the present invention comprises the following steps. First, a substrate 110 is provided, and the substrate 110 may be a glass substrate or a quartz substrate. Next, an amorphous silicon layer 120 is formed on the substrate 110. The amorphous silicon layer 120 may be formed using, for example, a chemical vapor deposition (CVD) process or a plasma enhanced CVD (PECVD) process.
  • Referring to FIG. 1B, a metal layer 130 is formed on the amorphous silicon layer 120, and the metal layer 130 may be comprised of nickel, cobalt, copper, tantalum, iron, platinum or any other metallic material and may be formed by using, for example, a sputtering process.
  • Referring to FIG. 1C, a portion of the metal layer 130 is removed to form a patterned metal layer 132. A portion of the metal layer 130 may be removed by using, for example, a photolithography process and an etching process.
  • Referring to FIG. 1D, a PRTA process is performed to form a metal silicide 140 between the patterned metal layer 132 and the amorphous silicon layer 120. Next, during the PRTA process, the patterned metal layer 132 and the metal silicide 140 conduct thermal energy to the amorphous silicon layer 120 such that the amorphous silicon layer 120 is transformed into a polysilicon layer 150 as shown in FIG. 1E.
  • FIG. 2 is a diagram showing a heating curve of the PRTA process according to an embodiment of the present invention. Referring to FIGS. 1D and 2, the horizontal coordinate represents time, wherein a unit of time is one second, and the vertical coordinate represents temperature, wherein centigrade represents the units used for the degrees of temperature. For example, the operation temperature of the PRTA process is between 550° C. and 900° C. In addition, for each cycle, the high temperature (900° C.) lasts for 5 seconds, the slope for heating is 70° C./second and the slope for cooling is 35° C./second. More specifically, a seed metal silicide 140 serving as crystal seed may be formed in advance. Next, infra red energy generated from the PRTA process is converted to heat by the metal silicide 140 and the patterned metal layer 132, and then heat is conducted to the amorphous silicon layer 120 to make it crystallize. In other words, the mechanism of re-crystallization is a kind of SPC-like method.
  • Referring to FIG. 1F, the patterned metal layer 132 is removed, and the patterned metal layer 132 may be removed by an etching process. Thus, the method of fabricating the polysilicon layer 150 according to an embodiment of the present invention is complete.
  • Since the conventional MILC process utilizes the lateral migration of the metal silicide to induce the amorphous silicon layer to re-crystallize, and therefore the lateral crystallization region (a region which is not covered by the patterned metal layer 132 shown in FIG. 1D) may have metal contamination. The poly silicon layer is analyzed by an energy dispersive X-ray spectrometer (EDS), and the result is shown as follows.
  • FIG. 3 is a spectrum diagram of the poly silicon layer measured by an energy dispersive X-ray spectrometer. Referring to FIG. 3, the horizontal coordinate represents energy, wherein a unit of energy is one kiloelectron volt (KeV), and the vertical coordinate represents counts per second (cps). The metal silicide of the present invention may not migrate laterally, and therefore the signal of nickel within the lateral crystallization region is not obvious (such as the dotted line region in FIG. 3). In other words, the lateral crystallization region has negligible amount of nickel.
  • Referring to FIG. 1F, the grains of the poly silicon layer formed by the conventional ELA process, are arborization. However, the grains of the poly silicon layer 150 formed according to the above-mentioned processes are substantially spherical in shape. Since the metal silicide makes the generation of a portion of the nucleation sites earlier, therefore the nucleation density is significantly reduced and the polysilicon layer 150 has larger grains size. Compared to the size of the grains of the poly silicon layer formed by the conventional ELA process, which is about 3000 angstrom to 4000 angstrom, the size of the grains of the polysilicon layer formed according to the above-mentioned processes may be larger than 4000 angstrom. Besides, compared to the surface roughness of the poly silicon layer formed by the conventional ELA process is between dozens to hundreds of nanometers, but the surface roughness of the polysilicon layer formed by the above-mentioned process may be smaller than 10 angstrom.
  • In summary, the present invention has at least the following advantages.
  • 1. Compared to the conventional SPC process, the present invention is faster (less than 2 minutes). The present invention employs the PRTA process, and accordingly it is suitable for forming a polysilicon layer on every kind of substrate.
  • 2. Compared to the conventional ELA process, the equipment required by the present invention is cheaper and the processing time thereof is faster (less than 2 minutes). Additionally, the planarity of the polysilicon layer formed according to the present invention is better, which is less than 10 angstrom.
  • 3. Compared with the conventional MILC process, the metal contamination of the present invention may not migrate laterally, and therefore the metal contamination may be effectively avoided.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (8)

1. A poly silicon layer, comprising;
a substrate; and
a poly silicon layer on the substrate, wherein grains of the polysilicon layer are spherical in shape.
2. The poly silicon layer according to claim 1, wherein a size of the grain is larger than 4000 angstrom.
3. The poly silicon layer according to claim 1, wherein a surface roughness of the poly silicon layer is smaller than 10 angstrom.
4. The poly silicon layer according to claim 1, further comprising a patterned metal layer on the poly silicon layer.
5. The poly silicon layer according to claim 4, wherein a material of the patterned metal layer comprises nickel, cobalt, copper, tantalum, iron or platinum.
6. A structure for forming a poly silicon layer, comprising;
a substrate;
an amorphous silicon layer on the substrate;
a patterned metal layer on the amorphous silicon layer; and
a metal silicide between the patterned metal layer and the amorphous silicon layer.
7. The structure according to claim 6, wherein a material of the patterned metal layer comprises nickel, cobalt, copper, tantalum, iron or platinum.
8. The structure according to claim 6, wherein the metal silicide is formed on the surface of the amorphous silicon layer and does not pass through the amorphous silicon layer.
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